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hat_i86.c
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hat_i86.c
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/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* or http://www.opensolaris.org/os/licensing.
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
*/
/*
* Copyright (c) 2010, Intel Corporation.
* All rights reserved.
*/
/*
* Copyright 2011 Nexenta Systems, Inc. All rights reserved.
*/
/*
* VM - Hardware Address Translation management for i386 and amd64
*
* Implementation of the interfaces described in <common/vm/hat.h>
*
* Nearly all the details of how the hardware is managed should not be
* visible outside this layer except for misc. machine specific functions
* that work in conjunction with this code.
*
* Routines used only inside of i86pc/vm start with hati_ for HAT Internal.
*/
#include <sys/machparam.h>
#include <sys/machsystm.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/systm.h>
#include <sys/cpuvar.h>
#include <sys/thread.h>
#include <sys/proc.h>
#include <sys/cpu.h>
#include <sys/kmem.h>
#include <sys/disp.h>
#include <sys/shm.h>
#include <sys/sysmacros.h>
#include <sys/machparam.h>
#include <sys/vmem.h>
#include <sys/vmsystm.h>
#include <sys/promif.h>
#include <sys/var.h>
#include <sys/x86_archext.h>
#include <sys/atomic.h>
#include <sys/bitmap.h>
#include <sys/controlregs.h>
#include <sys/bootconf.h>
#include <sys/bootsvcs.h>
#include <sys/bootinfo.h>
#include <sys/archsystm.h>
#include <vm/seg_kmem.h>
#include <vm/hat_i86.h>
#include <vm/as.h>
#include <vm/seg.h>
#include <vm/page.h>
#include <vm/seg_kp.h>
#include <vm/seg_kpm.h>
#include <vm/vm_dep.h>
#ifdef __xpv
#include <sys/hypervisor.h>
#endif
#include <vm/kboot_mmu.h>
#include <vm/seg_spt.h>
#include <sys/cmn_err.h>
/*
* Basic parameters for hat operation.
*/
struct hat_mmu_info mmu;
/*
* The page that is the kernel's top level pagetable.
*
* For 32 bit PAE support on i86pc, the kernel hat will use the 1st 4 entries
* on this 4K page for its top level page table. The remaining groups of
* 4 entries are used for per processor copies of user VLP pagetables for
* running threads. See hat_switch() and reload_pae32() for details.
*
* vlp_page[0..3] - level==2 PTEs for kernel HAT
* vlp_page[4..7] - level==2 PTEs for user thread on cpu 0
* vlp_page[8..11] - level==2 PTE for user thread on cpu 1
* etc...
*/
static x86pte_t *vlp_page;
/*
* forward declaration of internal utility routines
*/
static x86pte_t hati_update_pte(htable_t *ht, uint_t entry, x86pte_t expected,
x86pte_t new);
/*
* The kernel address space exists in all HATs. To implement this the
* kernel reserves a fixed number of entries in the topmost level(s) of page
* tables. The values are setup during startup and then copied to every user
* hat created by hat_alloc(). This means that kernelbase must be:
*
* 4Meg aligned for 32 bit kernels
* 512Gig aligned for x86_64 64 bit kernel
*
* The hat_kernel_range_ts describe what needs to be copied from kernel hat
* to each user hat.
*/
typedef struct hat_kernel_range {
level_t hkr_level;
uintptr_t hkr_start_va;
uintptr_t hkr_end_va; /* zero means to end of memory */
} hat_kernel_range_t;
#define NUM_KERNEL_RANGE 2
static hat_kernel_range_t kernel_ranges[NUM_KERNEL_RANGE];
static int num_kernel_ranges;
uint_t use_boot_reserve = 1; /* cleared after early boot process */
uint_t can_steal_post_boot = 0; /* set late in boot to enable stealing */
/*
* enable_1gpg: controls 1g page support for user applications.
* By default, 1g pages are exported to user applications. enable_1gpg can
* be set to 0 to not export.
*/
int enable_1gpg = 1;
/*
* AMD shanghai processors provide better management of 1gb ptes in its tlb.
* By default, 1g page support will be disabled for pre-shanghai AMD
* processors that don't have optimal tlb support for the 1g page size.
* chk_optimal_1gtlb can be set to 0 to force 1g page support on sub-optimal
* processors.
*/
int chk_optimal_1gtlb = 1;
#ifdef DEBUG
uint_t map1gcnt;
#endif
/*
* A cpuset for all cpus. This is used for kernel address cross calls, since
* the kernel addresses apply to all cpus.
*/
cpuset_t khat_cpuset;
/*
* management stuff for hat structures
*/
kmutex_t hat_list_lock;
kcondvar_t hat_list_cv;
kmem_cache_t *hat_cache;
kmem_cache_t *hat_hash_cache;
kmem_cache_t *vlp_hash_cache;
/*
* Simple statistics
*/
struct hatstats hatstat;
/*
* Some earlier hypervisor versions do not emulate cmpxchg of PTEs
* correctly. For such hypervisors we must set PT_USER for kernel
* entries ourselves (normally the emulation would set PT_USER for
* kernel entries and PT_USER|PT_GLOBAL for user entries). pt_kern is
* thus set appropriately. Note that dboot/kbm is OK, as only the full
* HAT uses cmpxchg() and the other paths (hypercall etc.) were never
* incorrect.
*/
int pt_kern;
/*
* useful stuff for atomic access/clearing/setting REF/MOD/RO bits in page_t's.
*/
extern void atomic_orb(uchar_t *addr, uchar_t val);
extern void atomic_andb(uchar_t *addr, uchar_t val);
#ifndef __xpv
extern pfn_t memseg_get_start(struct memseg *);
#endif
#define PP_GETRM(pp, rmmask) (pp->p_nrm & rmmask)
#define PP_ISMOD(pp) PP_GETRM(pp, P_MOD)
#define PP_ISREF(pp) PP_GETRM(pp, P_REF)
#define PP_ISRO(pp) PP_GETRM(pp, P_RO)
#define PP_SETRM(pp, rm) atomic_orb(&(pp->p_nrm), rm)
#define PP_SETMOD(pp) PP_SETRM(pp, P_MOD)
#define PP_SETREF(pp) PP_SETRM(pp, P_REF)
#define PP_SETRO(pp) PP_SETRM(pp, P_RO)
#define PP_CLRRM(pp, rm) atomic_andb(&(pp->p_nrm), ~(rm))
#define PP_CLRMOD(pp) PP_CLRRM(pp, P_MOD)
#define PP_CLRREF(pp) PP_CLRRM(pp, P_REF)
#define PP_CLRRO(pp) PP_CLRRM(pp, P_RO)
#define PP_CLRALL(pp) PP_CLRRM(pp, P_MOD | P_REF | P_RO)
/*
* kmem cache constructor for struct hat
*/
/*ARGSUSED*/
static int
hati_constructor(void *buf, void *handle, int kmflags)
{
hat_t *hat = buf;
mutex_init(&hat->hat_mutex, NULL, MUTEX_DEFAULT, NULL);
bzero(hat->hat_pages_mapped,
sizeof (pgcnt_t) * (mmu.max_page_level + 1));
hat->hat_ism_pgcnt = 0;
hat->hat_stats = 0;
hat->hat_flags = 0;
CPUSET_ZERO(hat->hat_cpus);
hat->hat_htable = NULL;
hat->hat_ht_hash = NULL;
return (0);
}
/*
* Allocate a hat structure for as. We also create the top level
* htable and initialize it to contain the kernel hat entries.
*/
hat_t *
hat_alloc(struct as *as)
{
hat_t *hat;
htable_t *ht; /* top level htable */
uint_t use_vlp;
uint_t r;
hat_kernel_range_t *rp;
uintptr_t va;
uintptr_t eva;
uint_t start;
uint_t cnt;
htable_t *src;
/*
* Once we start creating user process HATs we can enable
* the htable_steal() code.
*/
if (can_steal_post_boot == 0)
can_steal_post_boot = 1;
ASSERT(AS_WRITE_HELD(as, &as->a_lock));
hat = kmem_cache_alloc(hat_cache, KM_SLEEP);
hat->hat_as = as;
mutex_init(&hat->hat_mutex, NULL, MUTEX_DEFAULT, NULL);
ASSERT(hat->hat_flags == 0);
#if defined(__xpv)
/*
* No VLP stuff on the hypervisor due to the 64-bit split top level
* page tables. On 32-bit it's not needed as the hypervisor takes
* care of copying the top level PTEs to a below 4Gig page.
*/
use_vlp = 0;
#else /* __xpv */
/* 32 bit processes uses a VLP style hat when running with PAE */
#if defined(__amd64)
use_vlp = (ttoproc(curthread)->p_model == DATAMODEL_ILP32);
#elif defined(__i386)
use_vlp = mmu.pae_hat;
#endif
#endif /* __xpv */
if (use_vlp) {
hat->hat_flags = HAT_VLP;
bzero(hat->hat_vlp_ptes, VLP_SIZE);
}
/*
* Allocate the htable hash
*/
if ((hat->hat_flags & HAT_VLP)) {
hat->hat_num_hash = mmu.vlp_hash_cnt;
hat->hat_ht_hash = kmem_cache_alloc(vlp_hash_cache, KM_SLEEP);
} else {
hat->hat_num_hash = mmu.hash_cnt;
hat->hat_ht_hash = kmem_cache_alloc(hat_hash_cache, KM_SLEEP);
}
bzero(hat->hat_ht_hash, hat->hat_num_hash * sizeof (htable_t *));
/*
* Initialize Kernel HAT entries at the top of the top level page
* tables for the new hat.
*/
hat->hat_htable = NULL;
hat->hat_ht_cached = NULL;
XPV_DISALLOW_MIGRATE();
ht = htable_create(hat, (uintptr_t)0, TOP_LEVEL(hat), NULL);
hat->hat_htable = ht;
#if defined(__amd64)
if (hat->hat_flags & HAT_VLP)
goto init_done;
#endif
for (r = 0; r < num_kernel_ranges; ++r) {
rp = &kernel_ranges[r];
for (va = rp->hkr_start_va; va != rp->hkr_end_va;
va += cnt * LEVEL_SIZE(rp->hkr_level)) {
if (rp->hkr_level == TOP_LEVEL(hat))
ht = hat->hat_htable;
else
ht = htable_create(hat, va, rp->hkr_level,
NULL);
start = htable_va2entry(va, ht);
cnt = HTABLE_NUM_PTES(ht) - start;
eva = va +
((uintptr_t)cnt << LEVEL_SHIFT(rp->hkr_level));
if (rp->hkr_end_va != 0 &&
(eva > rp->hkr_end_va || eva == 0))
cnt = htable_va2entry(rp->hkr_end_va, ht) -
start;
#if defined(__i386) && !defined(__xpv)
if (ht->ht_flags & HTABLE_VLP) {
bcopy(&vlp_page[start],
&hat->hat_vlp_ptes[start],
cnt * sizeof (x86pte_t));
continue;
}
#endif
src = htable_lookup(kas.a_hat, va, rp->hkr_level);
ASSERT(src != NULL);
x86pte_copy(src, ht, start, cnt);
htable_release(src);
}
}
init_done:
#if defined(__xpv)
/*
* Pin top level page tables after initializing them
*/
xen_pin(hat->hat_htable->ht_pfn, mmu.max_level);
#if defined(__amd64)
xen_pin(hat->hat_user_ptable, mmu.max_level);
#endif
#endif
XPV_ALLOW_MIGRATE();
/*
* Put it at the start of the global list of all hats (used by stealing)
*
* kas.a_hat is not in the list but is instead used to find the
* first and last items in the list.
*
* - kas.a_hat->hat_next points to the start of the user hats.
* The list ends where hat->hat_next == NULL
*
* - kas.a_hat->hat_prev points to the last of the user hats.
* The list begins where hat->hat_prev == NULL
*/
mutex_enter(&hat_list_lock);
hat->hat_prev = NULL;
hat->hat_next = kas.a_hat->hat_next;
if (hat->hat_next)
hat->hat_next->hat_prev = hat;
else
kas.a_hat->hat_prev = hat;
kas.a_hat->hat_next = hat;
mutex_exit(&hat_list_lock);
return (hat);
}
/*
* process has finished executing but as has not been cleaned up yet.
*/
/*ARGSUSED*/
void
hat_free_start(hat_t *hat)
{
ASSERT(AS_WRITE_HELD(hat->hat_as, &hat->hat_as->a_lock));
/*
* If the hat is currently a stealing victim, wait for the stealing
* to finish. Once we mark it as HAT_FREEING, htable_steal()
* won't look at its pagetables anymore.
*/
mutex_enter(&hat_list_lock);
while (hat->hat_flags & HAT_VICTIM)
cv_wait(&hat_list_cv, &hat_list_lock);
hat->hat_flags |= HAT_FREEING;
mutex_exit(&hat_list_lock);
}
/*
* An address space is being destroyed, so we destroy the associated hat.
*/
void
hat_free_end(hat_t *hat)
{
kmem_cache_t *cache;
ASSERT(hat->hat_flags & HAT_FREEING);
/*
* must not be running on the given hat
*/
ASSERT(CPU->cpu_current_hat != hat);
/*
* Remove it from the list of HATs
*/
mutex_enter(&hat_list_lock);
if (hat->hat_prev)
hat->hat_prev->hat_next = hat->hat_next;
else
kas.a_hat->hat_next = hat->hat_next;
if (hat->hat_next)
hat->hat_next->hat_prev = hat->hat_prev;
else
kas.a_hat->hat_prev = hat->hat_prev;
mutex_exit(&hat_list_lock);
hat->hat_next = hat->hat_prev = NULL;
#if defined(__xpv)
/*
* On the hypervisor, unpin top level page table(s)
*/
xen_unpin(hat->hat_htable->ht_pfn);
#if defined(__amd64)
xen_unpin(hat->hat_user_ptable);
#endif
#endif
/*
* Make a pass through the htables freeing them all up.
*/
htable_purge_hat(hat);
/*
* Decide which kmem cache the hash table came from, then free it.
*/
if (hat->hat_flags & HAT_VLP)
cache = vlp_hash_cache;
else
cache = hat_hash_cache;
kmem_cache_free(cache, hat->hat_ht_hash);
hat->hat_ht_hash = NULL;
hat->hat_flags = 0;
kmem_cache_free(hat_cache, hat);
}
/*
* round kernelbase down to a supported value to use for _userlimit
*
* userlimit must be aligned down to an entry in the top level htable.
* The one exception is for 32 bit HAT's running PAE.
*/
uintptr_t
hat_kernelbase(uintptr_t va)
{
#if defined(__i386)
va &= LEVEL_MASK(1);
#endif
if (IN_VA_HOLE(va))
panic("_userlimit %p will fall in VA hole\n", (void *)va);
return (va);
}
/*
*
*/
static void
set_max_page_level()
{
level_t lvl;
if (!kbm_largepage_support) {
lvl = 0;
} else {
if (is_x86_feature(x86_featureset, X86FSET_1GPG)) {
lvl = 2;
if (chk_optimal_1gtlb &&
cpuid_opteron_erratum(CPU, 6671130)) {
lvl = 1;
}
if (plat_mnode_xcheck(LEVEL_SIZE(2) >>
LEVEL_SHIFT(0))) {
lvl = 1;
}
} else {
lvl = 1;
}
}
mmu.max_page_level = lvl;
if ((lvl == 2) && (enable_1gpg == 0))
mmu.umax_page_level = 1;
else
mmu.umax_page_level = lvl;
}
/*
* Initialize hat data structures based on processor MMU information.
*/
void
mmu_init(void)
{
uint_t max_htables;
uint_t pa_bits;
uint_t va_bits;
int i;
/*
* If CPU enabled the page table global bit, use it for the kernel
* This is bit 7 in CR4 (PGE - Page Global Enable).
*/
if (is_x86_feature(x86_featureset, X86FSET_PGE) &&
(getcr4() & CR4_PGE) != 0)
mmu.pt_global = PT_GLOBAL;
/*
* Detect NX and PAE usage.
*/
mmu.pae_hat = kbm_pae_support;
if (kbm_nx_support)
mmu.pt_nx = PT_NX;
else
mmu.pt_nx = 0;
/*
* Use CPU info to set various MMU parameters
*/
cpuid_get_addrsize(CPU, &pa_bits, &va_bits);
if (va_bits < sizeof (void *) * NBBY) {
mmu.hole_start = (1ul << (va_bits - 1));
mmu.hole_end = 0ul - mmu.hole_start - 1;
} else {
mmu.hole_end = 0;
mmu.hole_start = mmu.hole_end - 1;
}
#if defined(OPTERON_ERRATUM_121)
/*
* If erratum 121 has already been detected at this time, hole_start
* contains the value to be subtracted from mmu.hole_start.
*/
ASSERT(hole_start == 0 || opteron_erratum_121 != 0);
hole_start = mmu.hole_start - hole_start;
#else
hole_start = mmu.hole_start;
#endif
hole_end = mmu.hole_end;
mmu.highest_pfn = mmu_btop((1ull << pa_bits) - 1);
if (mmu.pae_hat == 0 && pa_bits > 32)
mmu.highest_pfn = PFN_4G - 1;
if (mmu.pae_hat) {
mmu.pte_size = 8; /* 8 byte PTEs */
mmu.pte_size_shift = 3;
} else {
mmu.pte_size = 4; /* 4 byte PTEs */
mmu.pte_size_shift = 2;
}
if (mmu.pae_hat && !is_x86_feature(x86_featureset, X86FSET_PAE))
panic("Processor does not support PAE");
if (!is_x86_feature(x86_featureset, X86FSET_CX8))
panic("Processor does not support cmpxchg8b instruction");
#if defined(__amd64)
mmu.num_level = 4;
mmu.max_level = 3;
mmu.ptes_per_table = 512;
mmu.top_level_count = 512;
mmu.level_shift[0] = 12;
mmu.level_shift[1] = 21;
mmu.level_shift[2] = 30;
mmu.level_shift[3] = 39;
#elif defined(__i386)
if (mmu.pae_hat) {
mmu.num_level = 3;
mmu.max_level = 2;
mmu.ptes_per_table = 512;
mmu.top_level_count = 4;
mmu.level_shift[0] = 12;
mmu.level_shift[1] = 21;
mmu.level_shift[2] = 30;
} else {
mmu.num_level = 2;
mmu.max_level = 1;
mmu.ptes_per_table = 1024;
mmu.top_level_count = 1024;
mmu.level_shift[0] = 12;
mmu.level_shift[1] = 22;
}
#endif /* __i386 */
for (i = 0; i < mmu.num_level; ++i) {
mmu.level_size[i] = 1UL << mmu.level_shift[i];
mmu.level_offset[i] = mmu.level_size[i] - 1;
mmu.level_mask[i] = ~mmu.level_offset[i];
}
set_max_page_level();
mmu_page_sizes = mmu.max_page_level + 1;
mmu_exported_page_sizes = mmu.umax_page_level + 1;
/* restrict legacy applications from using pagesizes 1g and above */
mmu_legacy_page_sizes =
(mmu_exported_page_sizes > 2) ? 2 : mmu_exported_page_sizes;
for (i = 0; i <= mmu.max_page_level; ++i) {
mmu.pte_bits[i] = PT_VALID | pt_kern;
if (i > 0)
mmu.pte_bits[i] |= PT_PAGESIZE;
}
/*
* NOTE Legacy 32 bit PAE mode only has the P_VALID bit at top level.
*/
for (i = 1; i < mmu.num_level; ++i)
mmu.ptp_bits[i] = PT_PTPBITS;
#if defined(__i386)
mmu.ptp_bits[2] = PT_VALID;
#endif
/*
* Compute how many hash table entries to have per process for htables.
* We start with 1 page's worth of entries.
*
* If physical memory is small, reduce the amount need to cover it.
*/
max_htables = physmax / mmu.ptes_per_table;
mmu.hash_cnt = MMU_PAGESIZE / sizeof (htable_t *);
while (mmu.hash_cnt > 16 && mmu.hash_cnt >= max_htables)
mmu.hash_cnt >>= 1;
mmu.vlp_hash_cnt = mmu.hash_cnt;
#if defined(__amd64)
/*
* If running in 64 bits and physical memory is large,
* increase the size of the cache to cover all of memory for
* a 64 bit process.
*/
#define HASH_MAX_LENGTH 4
while (mmu.hash_cnt * HASH_MAX_LENGTH < max_htables)
mmu.hash_cnt <<= 1;
#endif
}
/*
* initialize hat data structures
*/
void
hat_init()
{
#if defined(__i386)
/*
* _userlimit must be aligned correctly
*/
if ((_userlimit & LEVEL_MASK(1)) != _userlimit) {
prom_printf("hat_init(): _userlimit=%p, not aligned at %p\n",
(void *)_userlimit, (void *)LEVEL_SIZE(1));
halt("hat_init(): Unable to continue");
}
#endif
cv_init(&hat_list_cv, NULL, CV_DEFAULT, NULL);
/*
* initialize kmem caches
*/
htable_init();
hment_init();
hat_cache = kmem_cache_create("hat_t",
sizeof (hat_t), 0, hati_constructor, NULL, NULL,
NULL, 0, 0);
hat_hash_cache = kmem_cache_create("HatHash",
mmu.hash_cnt * sizeof (htable_t *), 0, NULL, NULL, NULL,
NULL, 0, 0);
/*
* VLP hats can use a smaller hash table size on large memroy machines
*/
if (mmu.hash_cnt == mmu.vlp_hash_cnt) {
vlp_hash_cache = hat_hash_cache;
} else {
vlp_hash_cache = kmem_cache_create("HatVlpHash",
mmu.vlp_hash_cnt * sizeof (htable_t *), 0, NULL, NULL, NULL,
NULL, 0, 0);
}
/*
* Set up the kernel's hat
*/
AS_LOCK_ENTER(&kas, &kas.a_lock, RW_WRITER);
kas.a_hat = kmem_cache_alloc(hat_cache, KM_NOSLEEP);
mutex_init(&kas.a_hat->hat_mutex, NULL, MUTEX_DEFAULT, NULL);
kas.a_hat->hat_as = &kas;
kas.a_hat->hat_flags = 0;
AS_LOCK_EXIT(&kas, &kas.a_lock);
CPUSET_ZERO(khat_cpuset);
CPUSET_ADD(khat_cpuset, CPU->cpu_id);
/*
* The kernel hat's next pointer serves as the head of the hat list .
* The kernel hat's prev pointer tracks the last hat on the list for
* htable_steal() to use.
*/
kas.a_hat->hat_next = NULL;
kas.a_hat->hat_prev = NULL;
/*
* Allocate an htable hash bucket for the kernel
* XX64 - tune for 64 bit procs
*/
kas.a_hat->hat_num_hash = mmu.hash_cnt;
kas.a_hat->hat_ht_hash = kmem_cache_alloc(hat_hash_cache, KM_NOSLEEP);
bzero(kas.a_hat->hat_ht_hash, mmu.hash_cnt * sizeof (htable_t *));
/*
* zero out the top level and cached htable pointers
*/
kas.a_hat->hat_ht_cached = NULL;
kas.a_hat->hat_htable = NULL;
/*
* Pre-allocate hrm_hashtab before enabling the collection of
* refmod statistics. Allocating on the fly would mean us
* running the risk of suffering recursive mutex enters or
* deadlocks.
*/
hrm_hashtab = kmem_zalloc(HRM_HASHSIZE * sizeof (struct hrmstat *),
KM_SLEEP);
}
/*
* Prepare CPU specific pagetables for VLP processes on 64 bit kernels.
*
* Each CPU has a set of 2 pagetables that are reused for any 32 bit
* process it runs. They are the top level pagetable, hci_vlp_l3ptes, and
* the next to top level table for the bottom 512 Gig, hci_vlp_l2ptes.
*/
/*ARGSUSED*/
static void
hat_vlp_setup(struct cpu *cpu)
{
#if defined(__amd64) && !defined(__xpv)
struct hat_cpu_info *hci = cpu->cpu_hat_info;
pfn_t pfn;
/*
* allocate the level==2 page table for the bottom most
* 512Gig of address space (this is where 32 bit apps live)
*/
ASSERT(hci != NULL);
hci->hci_vlp_l2ptes = kmem_zalloc(MMU_PAGESIZE, KM_SLEEP);
/*
* Allocate a top level pagetable and copy the kernel's
* entries into it. Then link in hci_vlp_l2ptes in the 1st entry.
*/
hci->hci_vlp_l3ptes = kmem_zalloc(MMU_PAGESIZE, KM_SLEEP);
hci->hci_vlp_pfn =
hat_getpfnum(kas.a_hat, (caddr_t)hci->hci_vlp_l3ptes);
ASSERT(hci->hci_vlp_pfn != PFN_INVALID);
bcopy(vlp_page, hci->hci_vlp_l3ptes, MMU_PAGESIZE);
pfn = hat_getpfnum(kas.a_hat, (caddr_t)hci->hci_vlp_l2ptes);
ASSERT(pfn != PFN_INVALID);
hci->hci_vlp_l3ptes[0] = MAKEPTP(pfn, 2);
#endif /* __amd64 && !__xpv */
}
/*ARGSUSED*/
static void
hat_vlp_teardown(cpu_t *cpu)
{
#if defined(__amd64) && !defined(__xpv)
struct hat_cpu_info *hci;
if ((hci = cpu->cpu_hat_info) == NULL)
return;
if (hci->hci_vlp_l2ptes)
kmem_free(hci->hci_vlp_l2ptes, MMU_PAGESIZE);
if (hci->hci_vlp_l3ptes)
kmem_free(hci->hci_vlp_l3ptes, MMU_PAGESIZE);
#endif
}
#define NEXT_HKR(r, l, s, e) { \
kernel_ranges[r].hkr_level = l; \
kernel_ranges[r].hkr_start_va = s; \
kernel_ranges[r].hkr_end_va = e; \
++r; \
}
/*
* Finish filling in the kernel hat.
* Pre fill in all top level kernel page table entries for the kernel's
* part of the address range. From this point on we can't use any new
* kernel large pages if they need PTE's at max_level
*
* create the kmap mappings.
*/
void
hat_init_finish(void)
{
size_t size;
uint_t r = 0;
uintptr_t va;
hat_kernel_range_t *rp;
/*
* We are now effectively running on the kernel hat.
* Clearing use_boot_reserve shuts off using the pre-allocated boot
* reserve for all HAT allocations. From here on, the reserves are
* only used when avoiding recursion in kmem_alloc().
*/
use_boot_reserve = 0;
htable_adjust_reserve();
/*
* User HATs are initialized with copies of all kernel mappings in
* higher level page tables. Ensure that those entries exist.
*/
#if defined(__amd64)
NEXT_HKR(r, 3, kernelbase, 0);
#if defined(__xpv)
NEXT_HKR(r, 3, HYPERVISOR_VIRT_START, HYPERVISOR_VIRT_END);
#endif
#elif defined(__i386)
#if !defined(__xpv)
if (mmu.pae_hat) {
va = kernelbase;
if ((va & LEVEL_MASK(2)) != va) {
va = P2ROUNDUP(va, LEVEL_SIZE(2));
NEXT_HKR(r, 1, kernelbase, va);
}
if (va != 0)
NEXT_HKR(r, 2, va, 0);
} else
#endif /* __xpv */
NEXT_HKR(r, 1, kernelbase, 0);
#endif /* __i386 */
num_kernel_ranges = r;
/*
* Create all the kernel pagetables that will have entries
* shared to user HATs.
*/
for (r = 0; r < num_kernel_ranges; ++r) {
rp = &kernel_ranges[r];
for (va = rp->hkr_start_va; va != rp->hkr_end_va;
va += LEVEL_SIZE(rp->hkr_level)) {
htable_t *ht;
if (IN_HYPERVISOR_VA(va))
continue;
/* can/must skip if a page mapping already exists */
if (rp->hkr_level <= mmu.max_page_level &&
(ht = htable_getpage(kas.a_hat, va, NULL)) !=
NULL) {
htable_release(ht);
continue;
}
(void) htable_create(kas.a_hat, va, rp->hkr_level - 1,
NULL);
}
}
/*
* 32 bit PAE metal kernels use only 4 of the 512 entries in the
* page holding the top level pagetable. We use the remainder for
* the "per CPU" page tables for VLP processes.
* Map the top level kernel pagetable into the kernel to make
* it easy to use bcopy access these tables.
*/
if (mmu.pae_hat) {
vlp_page = vmem_alloc(heap_arena, MMU_PAGESIZE, VM_SLEEP);
hat_devload(kas.a_hat, (caddr_t)vlp_page, MMU_PAGESIZE,
kas.a_hat->hat_htable->ht_pfn,
#if !defined(__xpv)
PROT_WRITE |
#endif
PROT_READ | HAT_NOSYNC | HAT_UNORDERED_OK,
HAT_LOAD | HAT_LOAD_NOCONSIST);
}
hat_vlp_setup(CPU);
/*
* Create kmap (cached mappings of kernel PTEs)
* for 32 bit we map from segmap_start .. ekernelheap
* for 64 bit we map from segmap_start .. segmap_start + segmapsize;
*/
#if defined(__i386)
size = (uintptr_t)ekernelheap - segmap_start;
#elif defined(__amd64)
size = segmapsize;
#endif
hat_kmap_init((uintptr_t)segmap_start, size);
}
/*
* On 32 bit PAE mode, PTE's are 64 bits, but ordinary atomic memory references
* are 32 bit, so for safety we must use atomic_cas_64() to install these.
*/
#ifdef __i386
static void
reload_pae32(hat_t *hat, cpu_t *cpu)
{
x86pte_t *src;
x86pte_t *dest;
x86pte_t pte;
int i;
/*
* Load the 4 entries of the level 2 page table into this
* cpu's range of the vlp_page and point cr3 at them.
*/
ASSERT(mmu.pae_hat);
src = hat->hat_vlp_ptes;
dest = vlp_page + (cpu->cpu_id + 1) * VLP_NUM_PTES;
for (i = 0; i < VLP_NUM_PTES; ++i) {
for (;;) {
pte = dest[i];
if (pte == src[i])
break;
if (atomic_cas_64(dest + i, pte, src[i]) != src[i])
break;
}
}
}
#endif
/*
* Switch to a new active hat, maintaining bit masks to track active CPUs.
*
* On the 32-bit PAE hypervisor, %cr3 is a 64-bit value, on metal it
* remains a 32-bit value.
*/
void
hat_switch(hat_t *hat)
{
uint64_t newcr3;
cpu_t *cpu = CPU;
hat_t *old = cpu->cpu_current_hat;
/*
* set up this information first, so we don't miss any cross calls
*/
if (old != NULL) {
if (old == hat)
return;
if (old != kas.a_hat)
CPUSET_ATOMIC_DEL(old->hat_cpus, cpu->cpu_id);
}
/*