Skip to content
FPGA USB stack written in LiteX
Python C Other
Branch: master
Clone or download
xobs travis: move git-clone into individual test body
Signed-off-by: Sean Cross <>
Latest commit a0526ad Jan 2, 2020
Type Name Latest commit message Commit time
Failed to load latest commit information.
docs docs: don't let sphinx reorder our classes Sep 26, 2019
sim sim: test-eptri: fix build with new setup behavior Nov 1, 2019
src src: add simple responder library Jul 26, 2019
test-suite/conf travis: check out test-suite submodules as part of test suite Jan 2, 2020
valentyusb eptri: use EventSourceProcess to signal usb reset Nov 29, 2019
.gitignore gitignore: ignore .vscode files Aug 27, 2019
.travis.yml travis: move git-clone into individual test body Jan 2, 2020
LICENSE Initial commit Oct 15, 2018 README: add documentation showing how to use it Jul 26, 2019
pytest.ini Trying to get travis to run. Jan 23, 2019
requirements.txt Trying to get travis to run. Jan 23, 2019


USB Full-Speed core written in Migen/LiteX. This core has been tested and is known to work on various incarnations of Fomu. It requires you to have a 48 MHz clock and a 12 MHz clock. It optionally comes with a debug bridge for debugging Wishbone.


To use this in your project, instantiate one of the CPU instances. The epfifo instances is the most widely-tested API, however dummyusb can be used for designs without a CPU.

  • DummyUsb: A wishbone device with no CPU interface that simply enumerates and can act as a Wishbone bridge
  • PerEndpointFifoInterface: Requires a CPU to configure and manage the device.
_io = [
    ("usb", 0,
        Subsignal("d_p", Pins("34")),
        Subsignal("d_n", Pins("37")),
        Subsignal("pullup", Pins("35")),

class BaseSoC(SoCCore):
    def __init__(self, platform, **kwargs):
        clk_freq = int(12e6)
        SoCCore.__init__(self, platform, clk_freq, with_uart=False, **kwargs)

        from valentyusb.usbcore.cpu import epfifo, dummyusb
        usb_pads = platform.request("usb")
        usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)

        # If a CPU is present, add a per-endpoint interface.  Otherwise, add a dummy
        # interface that simply acts as a Wishbone bridge.
        # Note that the dummy interface only really makes sense when doing a debug build.
        # Also note that you can add a dummyusb interface to a CPU if you only care
        # about the wishbone bridge.
        if hasattr(self, "cpu"):
            self.submodules.usb = epfifo.PerEndpointFifoInterface(usb_iobuf, debug=usb_debug)
            self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=usb_debug)
        if usb_debug:
            self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100)

platform = LatticePlatform("ice40-up5k-sg48", _io, [], toolchain="icestorm")
soc = BaseSoC(platform, cpu_type="vexriscv", cpu_variant="min+debug") # set cpu_type=None to build without a CPU
builder = Builder(soc)

Debug tools

You can use the litex_server built into the litex distribution to communicate with the device:

$ litex_server --usb --usb-pid 0x70bl

Alternately, you can use wishbone-tool:

$ wishbone-tool 0
INFO [wishbone_tool::usb_bridge] opened USB device device 017 on bus 001
Value at 00000000: 6f80106f

GDB server

You can use wishbone-tool to run a GDB server:

$ wishbone-tool -s gdb
INFO [wishbone_tool::usb_bridge] opened USB device device 017 on bus 001
INFO [wishbone_tool] accepting connections on
You can’t perform that action at this time.