{"payload":{"header_redesign_enabled":false,"results":[{"id":"178610858","archived":false,"color":"#b2b7f8","followers":8,"has_funding_file":false,"hl_name":"imaoca/dl166","hl_trunc_description":"4 BIT Original CPU","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":178610858,"name":"dl166","owner_id":3948328,"owner_login":"imaoca","updated_at":"2023-12-26T00:46:33.289Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":67,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aimaoca%252Fdl166%2B%2Blanguage%253AVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/imaoca/dl166/star":{"post":"Shu1G5oobKlWt0bwHVQ5qHXCbsBHZY6pAnvdsiDEQ7CrFqjS2C8BaP5OOteHkKq3Ss__X-ozwbWGOaxynw2WPA"},"/imaoca/dl166/unstar":{"post":"s6t81wMdc2GkGOuTfAm1RzwJID7qsDQvv6jWtEMfL6VVFlDolO-W1NJUSuwDc-w2agA-Wm0L_WJtFO-IC55qDA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"nMTAoEkCjgsIR_qzUN4MXe8h_cxQlcXciCulnz7NR6HjPJkgzl9yiXxwUstK7vl2rP-bry8wK0-C_Ha5Y6fqaA"}}},"title":"Repository search results"}