From 25c74a866b5b555699520552caeccb1e8426d86b Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Sat, 18 Apr 2015 15:00:45 -0400 Subject: [PATCH] nv50/ir: fix spilling of 3-wide texture results There is no 96-bit store to lmem operation, so we have to split it up into a 64-bit and 32-bit store. Signed-off-by: Ilia Mirkin --- .../drivers/nouveau/codegen/nv50_ir_ra.cpp | 28 +++++++++++++++++-- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp index 898653c9953..102cf9c1b50 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp @@ -1496,10 +1496,32 @@ SpillCodeInserter::spill(Instruction *defi, Value *slot, LValue *lval) Instruction *st; if (slot->reg.file == FILE_MEMORY_LOCAL) { - st = new_Instruction(func, OP_STORE, ty); - st->setSrc(0, slot); - st->setSrc(1, lval); + bool split = !func->getProgram()->getTarget()->isAccessSupported( + slot->reg.file, ty); lval->noSpill = 1; + if (split) { + Instruction *split = new_Instruction(func, OP_SPLIT, ty); + split->setSrc(0, lval); + for (int d = 0; d < lval->reg.size / 4; ++d) { + split->setDef(d, new_LValue(func, FILE_GPR)); + } + defi->bb->insertAfter(defi, split); + for (int d = 0; d < lval->reg.size / 4; ++d) { + Value *tmp = cloneShallow(func, slot); + tmp->reg.size = 4; + tmp->reg.data.offset += 4 * d; + + st = new_Instruction(func, OP_STORE, TYPE_U32); + st->setSrc(0, tmp); + st->setSrc(1, split->getDef(d)); + split->bb->insertAfter(split, st); + } + return; + } else { + st = new_Instruction(func, OP_STORE, ty); + st->setSrc(0, slot); + st->setSrc(1, lval); + } } else { st = new_Instruction(func, OP_CVT, ty); st->setDef(0, slot);