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initial mmu support for sq remaps
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| Original file line number | Diff line number | Diff line change |
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@@ -36,6 +36,11 @@ struct sh4_dtr { | |
| int size; | ||
| }; | ||
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| struct sh4_tlb_entry { | ||
| union pteh hi; | ||
| union ptel lo; | ||
| }; | ||
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| struct sh4 { | ||
| struct device; | ||
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@@ -61,6 +66,10 @@ struct sh4 { | |
| uint64_t requested_interrupts; | ||
| /* pending interrupts moved to context for fast jit access */ | ||
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| /* mmu */ | ||
| uint32_t utlb_sq_map[64]; | ||
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| struct sh4_tlb_entry utlb[64]; | ||
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| /* tmu */ | ||
| struct timer *tmu_timers[3]; | ||
| }; | ||
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@@ -71,14 +80,24 @@ DECLARE_COUNTER(sh4_instrs); | |
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| AM_DECLARE(sh4_data_map); | ||
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| /* ccn */ | ||
| void sh4_ccn_sq_prefetch(void *data, uint32_t addr); | ||
| uint32_t sh4_ccn_cache_read(struct sh4 *sh4, uint32_t addr, uint32_t data_mask); | ||
| void sh4_ccn_cache_write(struct sh4 *sh4, uint32_t addr, uint32_t data, | ||
| uint32_t data_mask); | ||
| uint32_t sh4_ccn_sq_read(struct sh4 *sh4, uint32_t addr, uint32_t data_mask); | ||
| void sh4_ccn_sq_write(struct sh4 *sh4, uint32_t addr, uint32_t data, | ||
| uint32_t data_mask); | ||
| uint32_t sh4_ccn_icache_read(struct sh4 *sh4, uint32_t addr, | ||
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| uint32_t data_mask); | ||
| void sh4_ccn_icache_write(struct sh4 *sh4, uint32_t addr, uint32_t data, | ||
| uint32_t data_mask); | ||
| uint32_t sh4_ccn_ocache_read(struct sh4 *sh4, uint32_t addr, | ||
| uint32_t data_mask); | ||
| void sh4_ccn_ocache_write(struct sh4 *sh4, uint32_t addr, uint32_t data, | ||
| uint32_t data_mask); | ||
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| /* dbg */ | ||
| int sh4_dbg_num_registers(struct device *dev); | ||
| void sh4_dbg_step(struct device *dev); | ||
| void sh4_dbg_add_breakpoint(struct device *dev, int type, uint32_t addr); | ||
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@@ -91,10 +110,20 @@ int sh4_dbg_invalid_instr(struct sh4 *sh4); | |
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| void sh4_dmac_ddt(struct sh4 *sh, struct sh4_dtr *dtr); | ||
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| /* intc */ | ||
| void sh4_intc_update_pending(struct sh4 *sh4); | ||
| void sh4_intc_check_pending(void *data); | ||
| void sh4_intc_reprioritize(struct sh4 *sh4); | ||
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| /* mmu */ | ||
| void sh4_mmu_load_tlb(void *data); | ||
| uint32_t sh4_mmu_itlb_read(struct sh4 *sh4, uint32_t addr, uint32_t data_mask); | ||
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| uint32_t sh4_mmu_utlb_read(struct sh4 *sh4, uint32_t addr, uint32_t data_mask); | ||
| void sh4_mmu_itlb_write(struct sh4 *sh4, uint32_t addr, uint32_t data, | ||
| uint32_t data_mask); | ||
| void sh4_mmu_utlb_write(struct sh4 *sh4, uint32_t addr, uint32_t data, | ||
| uint32_t data_mask); | ||
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| struct sh4 *sh4_create(struct dreamcast *dc); | ||
| void sh4_destroy(struct sh4 *sh4); | ||
| void sh4_debug_menu(struct sh4 *sh4); | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,6 +1,12 @@ | ||
| #include "guest/sh4/sh4.h" | ||
| #include "jit/jit.h" | ||
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| #if 0 | ||
| #define LOG_CCN LOG_INFO | ||
| #else | ||
| #define LOG_CCN(...) | ||
| #endif | ||
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| /* with OIX, bit 25, rather than bit 13, determines which 4kb bank to use */ | ||
| #define CACHE_OFFSET(addr, OIX) \ | ||
| ((OIX ? ((addr & 0x2000000) >> 13) : ((addr & 0x2000) >> 1)) | (addr & 0xfff)) | ||
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@@ -29,12 +35,27 @@ void sh4_ccn_sq_prefetch(void *data, uint32_t addr) { | |
| DCHECK(addr >= 0xe0000000 && addr <= 0xe3ffffff); | ||
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| struct sh4 *sh4 = data; | ||
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| uint32_t dst = 0x0; | ||
| uint32_t sqi = (addr & 0x20) >> 5; | ||
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| if (sh4->MMUCR->AT) { | ||
| /* get upper 12 bits from UTLB */ | ||
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| uint32_t vpn = addr >> 20; | ||
| dst = sh4->utlb_sq_map[vpn & 0x3f]; | ||
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| /* get lower 20 bits from original address */ | ||
| dst |= addr & 0xfffe0; | ||
| } else { | ||
| /* get upper 6 bits from QACR* registers */ | ||
| if (sqi) { | ||
| dst = (*sh4->QACR1 & 0x1c) << 24; | ||
| } else { | ||
| dst = (*sh4->QACR0 & 0x1c) << 24; | ||
| } | ||
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| /* get lower 26 bits from original address */ | ||
| dst |= addr & 0x3ffffe0; | ||
| } | ||
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| as_memcpy_to_guest(sh4->memory_if->space, dst, sh4->ctx.sq[sqi], 32); | ||
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@@ -69,10 +90,43 @@ void sh4_ccn_sq_write(struct sh4 *sh4, uint32_t addr, uint32_t data, | |
| sh4->ctx.sq[sqi][idx] = data; | ||
| } | ||
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| uint32_t sh4_ccn_icache_read(struct sh4 *sh4, uint32_t addr, | ||
| uint32_t data_mask) { | ||
| LOG_CCN("sh4_ccn_icache_read 0x%08x", addr); | ||
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| /* return an invalid entry */ | ||
| return 0; | ||
| } | ||
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| void sh4_ccn_icache_write(struct sh4 *sh4, uint32_t addr, uint32_t data, | ||
| uint32_t data_mask) { | ||
| LOG_CCN("sh4_ccn_icache_write 0x%08x", addr); | ||
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| /* ignore */ | ||
| } | ||
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| uint32_t sh4_ccn_ocache_read(struct sh4 *sh4, uint32_t addr, | ||
| uint32_t data_mask) { | ||
| LOG_CCN("sh4_ccn_ocache_read 0x%08x", addr); | ||
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| /* return an invalid entry */ | ||
| return 0; | ||
| } | ||
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| void sh4_ccn_ocache_write(struct sh4 *sh4, uint32_t addr, uint32_t data, | ||
| uint32_t data_mask) { | ||
| LOG_CCN("sh4_ccn_ocache_write 0x%08x", addr); | ||
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| /* ignore */ | ||
| } | ||
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| REG_W32(sh4_cb, MMUCR) { | ||
| struct sh4 *sh4 = dc->sh4; | ||
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| sh4->MMUCR->full = value; | ||
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| if (sh4->MMUCR->AT) { | ||
| LOG_WARNING("MMU not fully supported"); | ||
| } | ||
| } | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,123 @@ | ||
| #include "guest/sh4/sh4.h" | ||
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| #if 0 | ||
| #define LOG_MMU LOG_INFO | ||
| #else | ||
| #define LOG_MMU(...) | ||
| #endif | ||
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| #define TLB_INDEX(addr) (((addr) >> 8) & 0x3f) | ||
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| #define PAGE_SIZE(entry) (((entry)->lo.SZ1 << 1) | (entry)->lo.SZ0) | ||
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| enum { | ||
| PAGE_SIZE_1KB, | ||
| PAGE_SIZE_4KB, | ||
| PAGE_SIZE_64KB, | ||
| PAGE_SIZE_1MB, | ||
| }; | ||
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| static void sh4_mmu_utlb_sync(struct sh4 *sh4, struct sh4_tlb_entry *entry) { | ||
| int n = entry - sh4->utlb; | ||
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| /* check if entry maps to sq region [0xe0000000, 0xe3ffffff] */ | ||
| if ((entry->hi.VPN & (0xfc000000 >> 10)) == (0xe0000000 >> 10)) { | ||
| /* assume page size is 1MB | ||
| FIXME support all page sizes */ | ||
| uint32_t vpn = entry->hi.VPN >> 10; | ||
| uint32_t ppn = entry->lo.PPN << 10; | ||
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| sh4->utlb_sq_map[vpn & 0x3f] = ppn; | ||
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| LOG_INFO("sh4_mmu_utlb_sync sq map (%d) 0x%x -> 0x%x", n, vpn, ppn); | ||
| } else { | ||
| LOG_FATAL("sh4_mmu_utlb_sync memory mapping not supported"); | ||
| } | ||
| } | ||
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| static void sh4_mmu_translate(struct sh4 *sh4, uint32_t addr) {} | ||
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| void sh4_mmu_load_tlb(void *data) { | ||
| struct sh4 *sh4 = data; | ||
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| uint32_t n = sh4->MMUCR->URC; | ||
| struct sh4_tlb_entry *entry = &sh4->utlb[n]; | ||
| entry->lo = *sh4->PTEL; | ||
| entry->hi = *sh4->PTEH; | ||
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| sh4_mmu_utlb_sync(sh4, entry); | ||
| } | ||
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| uint32_t sh4_mmu_itlb_read(struct sh4 *sh4, uint32_t addr, uint32_t data_mask) { | ||
| if (addr < 0x01000000) { | ||
| LOG_MMU("sh4_mmu_itlb_read address array %08x", addr); | ||
| } else { | ||
| LOG_MMU("sh4_mmu_itlb_read data array %08x", addr); | ||
| } | ||
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| /* return an invalid entry */ | ||
| return 0; | ||
| } | ||
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| uint32_t sh4_mmu_utlb_read(struct sh4 *sh4, uint32_t addr, uint32_t data_mask) { | ||
| if (addr < 0x01000000) { | ||
| LOG_MMU("sh4_mmu_utlb_read address array %08x", addr); | ||
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| struct sh4_tlb_entry *entry = &sh4->utlb[TLB_INDEX(addr)]; | ||
| uint32_t data = entry->hi.full; | ||
| data |= entry->lo.D << 9; | ||
| data |= entry->lo.V << 8; | ||
| return data; | ||
| } else { | ||
| if (addr & 0x800000) { | ||
| LOG_FATAL("sh4_mmu_utlb_read data array 2 %08x", addr); | ||
| } else { | ||
| LOG_MMU("sh4_mmu_utlb_read data array 1 %08x", addr); | ||
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| struct sh4_tlb_entry *entry = &sh4->utlb[TLB_INDEX(addr)]; | ||
| uint32_t data = entry->lo.full; | ||
| return data; | ||
| } | ||
| } | ||
| } | ||
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| void sh4_mmu_itlb_write(struct sh4 *sh4, uint32_t addr, uint32_t data, | ||
| uint32_t data_mask) { | ||
| if (addr < 0x01000000) { | ||
| LOG_MMU("sh4_mmu_itlb_write address array %08x %08x", addr, data); | ||
| } else { | ||
| LOG_MMU("sh4_mmu_itlb_write data array %08x %08x", addr, data); | ||
| } | ||
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| /* ignore */ | ||
| } | ||
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| void sh4_mmu_utlb_write(struct sh4 *sh4, uint32_t addr, uint32_t data, | ||
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|
||
| uint32_t data_mask) { | ||
| if (addr < 0x01000000) { | ||
| if (addr & 0x80) { | ||
| LOG_FATAL("sh4_mmu_utlb_write address array (associative) %08x %08x", | ||
| addr, data); | ||
| } else { | ||
| LOG_MMU("sh4_mmu_utlb_write address array %08x %08x", addr, data); | ||
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| struct sh4_tlb_entry *entry = &sh4->utlb[TLB_INDEX(addr)]; | ||
| entry->hi.full = data & 0xfffffcff; | ||
| entry->lo.D = (data >> 9) & 1; | ||
| entry->lo.V = (data >> 8) & 1; | ||
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| sh4_mmu_utlb_sync(sh4, entry); | ||
| } | ||
| } else { | ||
| if (addr & 0x800000) { | ||
| LOG_FATAL("sh4_mmu_utlb_write data array 2 %08x %08x", addr, data); | ||
| } else { | ||
| LOG_MMU("sh4_mmu_utlb_write data array 1 %08x %08x", addr, data); | ||
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| struct sh4_tlb_entry *entry = &sh4->utlb[TLB_INDEX(addr)]; | ||
| entry->lo.full = data; | ||
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| sh4_mmu_utlb_sync(sh4, entry); | ||
| } | ||
| } | ||
| } | ||
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I think this is not P4, it is somehow the end of P3. I have no idea how it works on the hardware. I think if the cache index* mode is disabled, then this directs to area7?
(I guess something more to test)