diff --git a/AIB_Intel_Specification 1_1.pdf b/AIB_Intel_Specification 1_1.pdf deleted file mode 100644 index 3f27280..0000000 Binary files a/AIB_Intel_Specification 1_1.pdf and /dev/null differ diff --git a/README.txt b/README.txt index fd7b5ed..dddcfdd 100644 --- a/README.txt +++ b/README.txt @@ -5,9 +5,11 @@ FEB 4, 2019 ============================================================ Included in this package are: -1. c3aib rtl (RTL implementation of AIB interface) +1. c3aib rtl (RTL implementation of AIB interface with no timing constrain file supplied) 2. CHIP AIB model. Based on AIB spec 1.0. -3. Test bench +3. Slave FPGA AIB model +4. Base Test bench master c3aib connect to FPGA AIB or AIB model +5. Test examples with different configurations =========================================================== Revision history: Version 1.0: Initial release @@ -35,18 +37,21 @@ aib_lib: c3aib files |-- c3aibadapt_wrap |--aibcr3_lib, aibcr3pnr_lib, c3aibadapt, c3dfx, and c3lib. They are related library and rtl. +maib_rtl: FPGA AIB models if user want to interop c3aib with FPGA through AIB interface. + ndsimslv: simulation test bench and file list |-top.sv - Test bench file. |-multidie.f - Simulation file list, include test bench and all AIB model files. + See README.txt for detail in this directory. how2use: example design and testbench |-README.txt |-sim_aib_top - Test bench show 24 channel external loopback test. |-sim_aib_top_ncsim - Test bench show 24 channel external loopback test with ncsim. |-sim_phasecom - Test one channel loopback simulation of enabling phase compensation fifo |-sim_dcc - This test show how DCC works and can correct the duty cycle to almost 50/50 from 40/60 - |-sim_modelsim - 1 channel connects with AIB model simulated with modelsim simulator + |-sim_sl2ms_lpbk - 1 channel connects with FPGA AIB model loopback test. See README.txt in this directory for detail. |-sim_mod2mod - Model to Model test. This test show how master model works with slave model - +maib_rtl: Stratix 10 MAIB rtl ============================================================ How to compile and run simulation (VCS) ============================================================ diff --git a/Stratix 10 Chiplet AIB Profile_v1_0.pdf b/Stratix 10 Chiplet AIB Profile_v1_0.pdf deleted file mode 100644 index 55a4066..0000000 Binary files a/Stratix 10 Chiplet AIB Profile_v1_0.pdf and /dev/null differ diff --git a/aib_lib/c3aibadapt/rtl/c3aibadapt.v b/aib_lib/c3aibadapt/rtl/c3aibadapt.v index a4f1534..638865e 100644 --- a/aib_lib/c3aibadapt/rtl/c3aibadapt.v +++ b/aib_lib/c3aibadapt/rtl/c3aibadapt.v @@ -22,6 +22,8 @@ // // //----------------------------------------------------------------------------- + + module c3aibadapt ( // AIB @@ -864,7 +866,7 @@ assign fpll_shared_direct_async[2] = tb_direct_async[1]; assign fpll_shared_direct_async[1] = tb_direct_async[0]; assign fpll_shared_direct_async[0] = tb_direct_async[0]; -assign sl_sideband = {rx_ssr_parity_checker_in[35:32], rx_ssr_parity_checker_in[30],tx_ssr_parity_checker_in[35:32], rx_ssr_parity_checker_in[31], rx_ssr_parity_checker_in[29:0], tx_ssr_parity_checker_in[31:0]}; +assign sl_sideband = {avmm_hrdrst_fabric_osc_transfer_en_ssr_data, rx_ssr_parity_checker_in[35:32], rx_ssr_parity_checker_in[30],tx_ssr_parity_checker_in[35:32], rx_ssr_parity_checker_in[31], rx_ssr_parity_checker_in[29:0], tx_ssr_parity_checker_in[31:0]}; c3aibadapt_txchnl adapt_txchnl (/*AUTOINST*/ // Outputs diff --git a/aib_lib/c3aibadapt_wrap/rtl/aib_top.v b/aib_lib/c3aibadapt_wrap/rtl/aib_top.v index 51202f1..3a2eef4 100644 --- a/aib_lib/c3aibadapt_wrap/rtl/aib_top.v +++ b/aib_lib/c3aibadapt_wrap/rtl/aib_top.v @@ -115,11 +115,11 @@ module aib_top input [31:0] i_aibaux_ctrl_bus0, //1st set of register bits from register file input [31:0] i_aibaux_ctrl_bus1, //2nd set of register bits from register file input [31:0] i_aibaux_ctrl_bus2, //3rd set of register bits from register file - input [9:0] i_aibaux_osc_fuse_trim, //control by Fuse/OTP from Jariet + input [9:0] i_aibaux_osc_fuse_trim, //control by Fuse/OTP from User // - input i_osc_bypclk, // test clock from c4 bump, may tie low for Jariet if not used - output o_aibaux_osc_clk, // osc clk output to test C4 bump to characterize the oscillator, Jariet may use this clock to connect with i_test_clk_1g + input i_osc_bypclk, // test clock from c4 bump, may tie low for User if not used + output o_aibaux_osc_clk, // osc clk output to test C4 bump to characterize the oscillator, User may use this clock to connect with i_test_clk_1g //====================================================================================== // DFT signals input i_scan_clk, //ATPG Scan shifting clock from Test Pad. @@ -150,12 +150,12 @@ module aib_top input [2:0] i_aibdft2osc, //To AIB osc.[2] force reset [1] force enable [0] 33 MHz JTAG output [12:0] o_aibdft2osc, //Observability of osc and DLL/DCC status - //this signal go through C4 bump, Jariet may muxed it out with their test signals + //this signal go through C4 bump, User may muxed it out with their test signals //output TCB output o_last_bs_out, //last boundary scan chain output, TDO - output o_por, // S10 POR to Jariet, can be left unconnected for Jariet + output o_por, // S10 POR to User, can be left unconnected for User output o_osc_monitor, //Output from oscillator, go to pinmux block before go to C4 test bump diff --git a/aib_lib/c3aibadapt_wrap/rtl/aib_top_master.sv b/aib_lib/c3aibadapt_wrap/rtl/aib_top_master.sv index a7a404e..897005f 100644 --- a/aib_lib/c3aibadapt_wrap/rtl/aib_top_master.sv +++ b/aib_lib/c3aibadapt_wrap/rtl/aib_top_master.sv @@ -69,10 +69,10 @@ module aib_top_master inout [TOTAL_CHNL_NUM-1:0] iopad_fs_fwd_clk, inout [TOTAL_CHNL_NUM-1:0] iopad_fs_mac_rdy, inout [TOTAL_CHNL_NUM-1:0] iopad_ns_mac_rdy, - inout [TOTAL_CHNL_NUM-1:0] iopad_ns_adapt_rstn, + inout [TOTAL_CHNL_NUM-1:0] iopad_ns_adapter_rstn, inout [TOTAL_CHNL_NUM-1:0] iopad_fs_rcv_clk, inout [TOTAL_CHNL_NUM-1:0] iopad_fs_rcv_clkb, - inout [TOTAL_CHNL_NUM-1:0] iopad_fs_adapt_rstn, + inout [TOTAL_CHNL_NUM-1:0] iopad_fs_adapter_rstn, inout [TOTAL_CHNL_NUM-1:0] iopad_fs_sr_clkb, inout [TOTAL_CHNL_NUM-1:0] iopad_fs_sr_clk, inout [TOTAL_CHNL_NUM-1:0] iopad_ns_sr_clk, @@ -85,9 +85,49 @@ module aib_top_master inout [TOTAL_CHNL_NUM-1:0] iopad_fs_sr_data, inout [TOTAL_CHNL_NUM-1:0] iopad_ns_sr_load, inout [TOTAL_CHNL_NUM-1:0] iopad_ns_sr_data, - - inout [95:0] io_aib_aux, - + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib45, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib46, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib47, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib50, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib51, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib52, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib58, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib60, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib61, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib62, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib63, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib64, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib66, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib67, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib68, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib69, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib70, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib71, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib72, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib73, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib74, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib75, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib76, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib77, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib78, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib79, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib80, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib81, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib88, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib89, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib90, + inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib91, + + +// inout [95:0] io_aib_aux, + inout [7:0] iopad_unused_aux95_88, + inout iopad_power_on_reset_r, //iopad_aib_aux[87] power on redundency from slave + inout iopad_unused_aux86, + inout iopad_power_on_reset, //iopad_aib_aux[85] power on from slave. + inout [8:0] iopad_unused_aux84_76, + inout iopad_device_detect_r, //iopad_aib_aux[75] device detect redundency to slave + inout iopad_device_detect, //iopad_aib_aux[74] device detect to slave + inout [73:0] iopad_unused_aux73_0, inout io_aux_bg_ext_2k, //connect to external 2k resistor, C4 bump //====================================================================================== @@ -101,11 +141,11 @@ module aib_top_master input [31:0] i_aibaux_ctrl_bus0, //1st set of register bits from register file input [31:0] i_aibaux_ctrl_bus1, //2nd set of register bits from register file input [31:0] i_aibaux_ctrl_bus2, //3rd set of register bits from register file - input [9:0] i_aibaux_osc_fuse_trim, //control by Fuse/OTP from Jariet + input [9:0] i_aibaux_osc_fuse_trim, //control by Fuse/OTP from User // - input i_osc_bypclk, // test clock from c4 bump, may tie low for Jariet if not used - output o_aibaux_osc_clk, // osc clk output to test C4 bump to characterize the oscillator, Jariet may use this clock to connect with i_test_clk_1g + input i_osc_bypclk, // test clock from c4 bump, may tie low for User if not used + output o_aibaux_osc_clk, // osc clk output to test C4 bump to characterize the oscillator, User may use this clock to connect with i_test_clk_1g //====================================================================================== // DFT signals input i_scan_clk, //ATPG Scan shifting clock from Test Pad. @@ -136,12 +176,13 @@ module aib_top_master input [2:0] i_aibdft2osc, //To AIB osc.[2] force reset [1] force enable [0] 33 MHz JTAG output [12:0] o_aibdft2osc, //Observability of osc and DLL/DCC status - //this signal go through C4 bump, Jariet may muxed it out with their test signals + //this signal go through C4 bump, User may muxed it out with their test signals //output TCB output o_last_bs_out, //last boundary scan chain output, TDO - output o_por, // S10 POR to Jariet, can be left unconnected for Jariet + output m_power_on_reset, // S10 POR to User, can be left unconnected for User. In theory, MAc on master side + // should look at this signal to determine if "slave" is there and slave complete power up seq. output o_osc_monitor, //Output from oscillator, go to pinmux block before go to C4 test bump @@ -153,7 +194,6 @@ module aib_top_master input i_aux_atpg_scan_in, //scan chain in input i_aux_atpg_scan_shift_n, //~scan_enable output o_aux_atpg_scan_out //scan chain out - ); wire [TOTAL_CHNL_NUM-1:0] i_rx_pma_clk; @@ -164,25 +204,6 @@ wire [TOTAL_CHNL_NUM-1:0] o_tx_transfer_clk; wire [TOTAL_CHNL_NUM-1:0] o_tx_transfer_div2_clk; wire [TOTAL_CHNL_NUM*40-1:0] o_tx_pma_data; wire [TOTAL_CHNL_NUM-1:0] o_rx_xcvrif_rst_n; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib46; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib47; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib49; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib50; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib51; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib52; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib60; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib62; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib66; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib68; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib69; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib70; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib71; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib75; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib76; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib77; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib84; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib90; -wire [TOTAL_CHNL_NUM-1:0] iopad_unused_aib91; wire HI, LO; assign HI = 1'b1; assign LO = 1'b0; @@ -224,409 +245,395 @@ assign fs_mac_rdy = o_rx_xcvrif_rst_n; .ms_sideband (ms_sideband), .sl_sideband (sl_sideband), - .io_aib_ch0 ({ iopad_ns_sr_data[0], iopad_ns_sr_load[0], iopad_fs_sr_data[0], iopad_fs_sr_load[0], - iopad_unused_aib91[0], iopad_unused_aib90[0], LO, LO, - iopad_ns_rcv_clk[0], iopad_ns_rcv_clkb[0], iopad_ns_sr_clkb[0], iopad_ns_sr_clk[0], - iopad_fs_sr_clk[0], iopad_fs_sr_clkb[0], LO, LO, - LO, LO, iopad_unused_aib77[0], iopad_unused_aib76[0], - iopad_unused_aib75[0], LO, LO, LO, - iopad_unused_aib71[0], iopad_unused_aib70[0], iopad_unused_aib69[0], iopad_unused_aib68[0], - LO, iopad_unused_aib66[0], iopad_fs_adapt_rstn[0], LO, - LO, iopad_unused_aib62[0], HI, iopad_unused_aib60[0], - iopad_fs_rcv_clkb[0], LO, iopad_fs_rcv_clk[0], iopad_ns_adapt_rstn[0], - iopad_ns_rcv_div2_clkb[0], iopad_ns_fwd_div2_clkb[0], iopad_ns_fwd_div2_clk[0], iopad_unused_aib52[0], - iopad_unused_aib51[0], iopad_unused_aib50[0], iopad_fs_mac_rdy[0], iopad_ns_rcv_div2_clk[0], - iopad_unused_aib47[0], iopad_unused_aib46[0], HI, iopad_fs_mac_rdy[0], - iopad_fs_fwd_clk[0], iopad_fs_fwd_clkb[0], iopad_ns_fwd_clk[0], iopad_ns_fwd_clkb[0], - iopad_rx[19:0], iopad_tx[19:0]}), - .io_aib_ch1 ({ iopad_ns_sr_data[1], iopad_ns_sr_load[1], iopad_fs_sr_data[1], iopad_fs_sr_load[1], - iopad_unused_aib91[1], iopad_unused_aib90[1], LO, LO, - iopad_ns_rcv_clk[1], iopad_ns_rcv_clkb[1], iopad_ns_sr_clkb[1], iopad_ns_sr_clk[1], - iopad_fs_sr_clk[1], iopad_fs_sr_clkb[1], LO, LO, - LO, LO, iopad_unused_aib77[1], iopad_unused_aib76[1], - iopad_unused_aib75[1], LO, LO, LO, - iopad_unused_aib71[1], iopad_unused_aib70[1], iopad_unused_aib69[1], iopad_unused_aib68[1], - LO, iopad_unused_aib66[1], iopad_fs_adapt_rstn[1], LO, - LO, iopad_unused_aib62[1], HI, iopad_unused_aib60[1], - iopad_fs_rcv_clkb[1], LO, iopad_fs_rcv_clk[1], iopad_ns_adapt_rstn[1], - iopad_ns_rcv_div2_clkb[1], iopad_ns_fwd_div2_clkb[1], iopad_ns_fwd_div2_clk[1], iopad_unused_aib52[1], - iopad_unused_aib51[1], iopad_unused_aib50[1], iopad_fs_mac_rdy[1], iopad_ns_rcv_div2_clk[1], - iopad_unused_aib47[1], iopad_unused_aib46[1], HI, iopad_fs_mac_rdy[1], - iopad_fs_fwd_clk[1], iopad_fs_fwd_clkb[1], iopad_ns_fwd_clk[1], iopad_ns_fwd_clkb[1], - iopad_rx[39:20], iopad_tx[39:20]}), + .io_aib_ch0 ({ iopad_ns_sr_data[0], iopad_ns_sr_load[0], iopad_fs_sr_data[0], iopad_fs_sr_load[0], + iopad_unused_aib91[0], iopad_unused_aib90[0], iopad_unused_aib89[0], iopad_unused_aib88[0], + iopad_ns_rcv_clk[0], iopad_ns_rcv_clkb[0], iopad_ns_sr_clkb[0], iopad_ns_sr_clk[0], + iopad_fs_sr_clk[0], iopad_fs_sr_clkb[0], iopad_unused_aib81[0], iopad_unused_aib80[0], + iopad_unused_aib79[0], iopad_unused_aib78[0], iopad_unused_aib77[0], iopad_unused_aib76[0], + iopad_unused_aib75[0], iopad_unused_aib74[0], iopad_unused_aib73[0], iopad_unused_aib72[0], + iopad_unused_aib71[0], iopad_unused_aib70[0], iopad_unused_aib69[0], iopad_unused_aib68[0], + iopad_unused_aib67[0], iopad_unused_aib66[0], iopad_fs_adapter_rstn[0], iopad_unused_aib64[0], + iopad_unused_aib63[0], iopad_unused_aib62[0], iopad_unused_aib61[0], iopad_unused_aib60[0], + iopad_fs_rcv_clkb[0], iopad_unused_aib58[0], iopad_fs_rcv_clk[0], iopad_ns_adapter_rstn[0], + iopad_ns_rcv_div2_clkb[0], iopad_ns_fwd_div2_clkb[0], iopad_ns_fwd_div2_clk[0], iopad_unused_aib52[0], + iopad_unused_aib51[0], iopad_unused_aib50[0], iopad_fs_mac_rdy[0], iopad_ns_rcv_div2_clk[0], + iopad_unused_aib47[0], iopad_unused_aib46[0], iopad_unused_aib45[0], iopad_fs_mac_rdy[0], + iopad_fs_fwd_clk[0], iopad_fs_fwd_clkb[0], iopad_ns_fwd_clk[0], iopad_ns_fwd_clkb[0], + iopad_rx[19:0], iopad_tx[19:0]}), + + .io_aib_ch1 ({ iopad_ns_sr_data[1], iopad_ns_sr_load[1], iopad_fs_sr_data[1], iopad_fs_sr_load[1], + iopad_unused_aib91[1], iopad_unused_aib90[1], iopad_unused_aib89[1], iopad_unused_aib88[1], + iopad_ns_rcv_clk[1], iopad_ns_rcv_clkb[1], iopad_ns_sr_clkb[1], iopad_ns_sr_clk[1], + iopad_fs_sr_clk[1], iopad_fs_sr_clkb[1], iopad_unused_aib81[1], iopad_unused_aib80[1], + iopad_unused_aib79[1], iopad_unused_aib78[1], iopad_unused_aib77[1], iopad_unused_aib76[1], + iopad_unused_aib75[1], iopad_unused_aib74[1], iopad_unused_aib73[1], iopad_unused_aib72[1], + iopad_unused_aib71[1], iopad_unused_aib70[1], iopad_unused_aib69[1], iopad_unused_aib68[1], + iopad_unused_aib67[1], iopad_unused_aib66[1], iopad_fs_adapter_rstn[1], iopad_unused_aib64[1], + iopad_unused_aib63[1], iopad_unused_aib62[1], iopad_unused_aib61[1], iopad_unused_aib60[1], + iopad_fs_rcv_clkb[1], iopad_unused_aib58[1], iopad_fs_rcv_clk[1], iopad_ns_adapter_rstn[1], + iopad_ns_rcv_div2_clkb[1], iopad_ns_fwd_div2_clkb[1], iopad_ns_fwd_div2_clk[1], iopad_unused_aib52[1], + iopad_unused_aib51[1], iopad_unused_aib50[1], iopad_fs_mac_rdy[1], iopad_ns_rcv_div2_clk[1], + iopad_unused_aib47[1], iopad_unused_aib46[1], iopad_unused_aib45[1], iopad_fs_mac_rdy[1], + iopad_fs_fwd_clk[1], iopad_fs_fwd_clkb[1], iopad_ns_fwd_clk[1], iopad_ns_fwd_clkb[1], + iopad_rx[39:20], iopad_tx[39:20]}), - .io_aib_ch2 ({ iopad_ns_sr_data[2], iopad_ns_sr_load[2], iopad_fs_sr_data[2], iopad_fs_sr_load[2], - iopad_unused_aib91[2], iopad_unused_aib90[2], LO, LO, - iopad_ns_rcv_clk[2], iopad_ns_rcv_clkb[2], iopad_ns_sr_clkb[2], iopad_ns_sr_clk[2], - iopad_fs_sr_clk[2], iopad_fs_sr_clkb[2], LO, LO, - LO, LO, iopad_unused_aib77[2], iopad_unused_aib76[2], - iopad_unused_aib75[2], LO, LO, LO, - iopad_unused_aib71[2], iopad_unused_aib70[2], iopad_unused_aib69[2], iopad_unused_aib68[2], - LO, iopad_unused_aib66[2], iopad_fs_adapt_rstn[2], LO, - LO, iopad_unused_aib62[2], HI, iopad_unused_aib60[2], - iopad_fs_rcv_clkb[2], LO, iopad_fs_rcv_clk[2], iopad_ns_adapt_rstn[2], - iopad_ns_rcv_div2_clkb[2], iopad_ns_fwd_div2_clkb[2], iopad_ns_fwd_div2_clk[2], iopad_unused_aib52[2], - iopad_unused_aib51[2], iopad_unused_aib50[2], iopad_fs_mac_rdy[2], iopad_ns_rcv_div2_clk[2], - iopad_unused_aib47[2], iopad_unused_aib46[2], HI, iopad_fs_mac_rdy[2], - iopad_fs_fwd_clk[2], iopad_fs_fwd_clkb[2], iopad_ns_fwd_clk[2], iopad_ns_fwd_clkb[2], - iopad_rx[59:40], iopad_tx[59:40]}), - - .io_aib_ch3 ({ iopad_ns_sr_data[3], iopad_ns_sr_load[3], iopad_fs_sr_data[3], iopad_fs_sr_load[3], - iopad_unused_aib91[3], iopad_unused_aib90[3], LO, LO, - iopad_ns_rcv_clk[3], iopad_ns_rcv_clkb[3], iopad_ns_sr_clkb[3], iopad_ns_sr_clk[3], - iopad_fs_sr_clk[3], iopad_fs_sr_clkb[3], LO, LO, - LO, LO, iopad_unused_aib77[3], iopad_unused_aib76[3], - iopad_unused_aib75[3], LO, LO, LO, - iopad_unused_aib71[3], iopad_unused_aib70[3], iopad_unused_aib69[3], iopad_unused_aib68[3], - LO, iopad_unused_aib66[3], iopad_fs_adapt_rstn[3], LO, - LO, iopad_unused_aib62[3], HI, iopad_unused_aib60[3], - iopad_fs_rcv_clkb[3], LO, iopad_fs_rcv_clk[3], iopad_ns_adapt_rstn[3], - iopad_ns_rcv_div2_clkb[3], iopad_ns_fwd_div2_clkb[3], iopad_ns_fwd_div2_clk[3], iopad_unused_aib52[3], - iopad_unused_aib51[3], iopad_unused_aib50[3], iopad_fs_mac_rdy[3], iopad_ns_rcv_div2_clk[3], - iopad_unused_aib47[3], iopad_unused_aib46[3], HI, iopad_fs_mac_rdy[3], - iopad_fs_fwd_clk[3], iopad_fs_fwd_clkb[3], iopad_ns_fwd_clk[3], iopad_ns_fwd_clkb[3], - iopad_rx[79:60], iopad_tx[79:60]}), - - .io_aib_ch4 ({ iopad_ns_sr_data[4], iopad_ns_sr_load[4], iopad_fs_sr_data[4], iopad_fs_sr_load[4], - iopad_unused_aib91[4], iopad_unused_aib90[4], LO, LO, - iopad_ns_rcv_clk[4], iopad_ns_rcv_clkb[4], iopad_ns_sr_clkb[4], iopad_ns_sr_clk[4], - iopad_fs_sr_clk[4], iopad_fs_sr_clkb[4], LO, LO, - LO, LO, iopad_unused_aib77[4], iopad_unused_aib76[4], - iopad_unused_aib75[4], LO, LO, LO, - iopad_unused_aib71[4], iopad_unused_aib70[4], iopad_unused_aib69[4], iopad_unused_aib68[4], - LO, iopad_unused_aib66[4], iopad_fs_adapt_rstn[4], LO, - LO, iopad_unused_aib62[4], HI, iopad_unused_aib60[4], - iopad_fs_rcv_clkb[4], LO, iopad_fs_rcv_clk[4], iopad_ns_adapt_rstn[4], - iopad_ns_rcv_div2_clkb[4], iopad_ns_fwd_div2_clkb[4], iopad_ns_fwd_div2_clk[4], iopad_unused_aib52[4], - iopad_unused_aib51[4], iopad_unused_aib50[4], iopad_fs_mac_rdy[4], iopad_ns_rcv_div2_clk[4], - iopad_unused_aib47[4], iopad_unused_aib46[4], HI, iopad_fs_mac_rdy[4], - iopad_fs_fwd_clk[4], iopad_fs_fwd_clkb[4], iopad_ns_fwd_clk[4], iopad_ns_fwd_clkb[4], + .io_aib_ch2 ({ iopad_ns_sr_data[2], iopad_ns_sr_load[2], iopad_fs_sr_data[2], iopad_fs_sr_load[2], + iopad_unused_aib91[2], iopad_unused_aib90[2], iopad_unused_aib89[2], iopad_unused_aib88[2], + iopad_ns_rcv_clk[2], iopad_ns_rcv_clkb[2], iopad_ns_sr_clkb[2], iopad_ns_sr_clk[2], + iopad_fs_sr_clk[2], iopad_fs_sr_clkb[2], iopad_unused_aib81[2], iopad_unused_aib80[2], + iopad_unused_aib79[2], iopad_unused_aib78[2], iopad_unused_aib77[2], iopad_unused_aib76[2], + iopad_unused_aib75[2], iopad_unused_aib74[2], iopad_unused_aib73[2], iopad_unused_aib72[2], + iopad_unused_aib71[2], iopad_unused_aib70[2], iopad_unused_aib69[2], iopad_unused_aib68[2], + iopad_unused_aib67[2], iopad_unused_aib66[2], iopad_fs_adapter_rstn[2], iopad_unused_aib64[2], + iopad_unused_aib63[2], iopad_unused_aib62[2], iopad_unused_aib61[2], iopad_unused_aib60[2], + iopad_fs_rcv_clkb[2], iopad_unused_aib58[2], iopad_fs_rcv_clk[2], iopad_ns_adapter_rstn[2], + iopad_ns_rcv_div2_clkb[2], iopad_ns_fwd_div2_clkb[2], iopad_ns_fwd_div2_clk[2], iopad_unused_aib52[2], + iopad_unused_aib51[2], iopad_unused_aib50[2], iopad_fs_mac_rdy[2], iopad_ns_rcv_div2_clk[2], + iopad_unused_aib47[2], iopad_unused_aib46[2], iopad_unused_aib45[2], iopad_fs_mac_rdy[2], + iopad_fs_fwd_clk[2], iopad_fs_fwd_clkb[2], iopad_ns_fwd_clk[2], iopad_ns_fwd_clkb[2], + iopad_rx[59:40], iopad_tx[59:40]}), + + .io_aib_ch3 ({ iopad_ns_sr_data[3], iopad_ns_sr_load[3], iopad_fs_sr_data[3], iopad_fs_sr_load[3], + iopad_unused_aib91[3], iopad_unused_aib90[3], iopad_unused_aib89[3], iopad_unused_aib88[3], + iopad_ns_rcv_clk[3], iopad_ns_rcv_clkb[3], iopad_ns_sr_clkb[3], iopad_ns_sr_clk[3], + iopad_fs_sr_clk[3], iopad_fs_sr_clkb[3], iopad_unused_aib81[3], iopad_unused_aib80[3], + iopad_unused_aib79[3], iopad_unused_aib78[3], iopad_unused_aib77[3], iopad_unused_aib76[3], + iopad_unused_aib75[3], iopad_unused_aib74[3], iopad_unused_aib73[3], iopad_unused_aib72[3], + iopad_unused_aib71[3], iopad_unused_aib70[3], iopad_unused_aib69[3], iopad_unused_aib68[3], + iopad_unused_aib67[3], iopad_unused_aib66[3], iopad_fs_adapter_rstn[3], iopad_unused_aib64[3], + iopad_unused_aib63[3], iopad_unused_aib62[3], iopad_unused_aib61[3], iopad_unused_aib60[3], + iopad_fs_rcv_clkb[3], iopad_unused_aib58[3], iopad_fs_rcv_clk[3], iopad_ns_adapter_rstn[3], + iopad_ns_rcv_div2_clkb[3], iopad_ns_fwd_div2_clkb[3], iopad_ns_fwd_div2_clk[3], iopad_unused_aib52[3], + iopad_unused_aib51[3], iopad_unused_aib50[3], iopad_fs_mac_rdy[3], iopad_ns_rcv_div2_clk[3], + iopad_unused_aib47[3], iopad_unused_aib46[3], iopad_unused_aib45[3], iopad_fs_mac_rdy[3], + iopad_fs_fwd_clk[3], iopad_fs_fwd_clkb[3], iopad_ns_fwd_clk[3], iopad_ns_fwd_clkb[3], + iopad_rx[79:60], iopad_tx[79:60]}), + + .io_aib_ch4 ({ iopad_ns_sr_data[4], iopad_ns_sr_load[4], iopad_fs_sr_data[4], iopad_fs_sr_load[4], + iopad_unused_aib91[4], iopad_unused_aib90[4], iopad_unused_aib89[4], iopad_unused_aib88[4], + iopad_ns_rcv_clk[4], iopad_ns_rcv_clkb[4], iopad_ns_sr_clkb[4], iopad_ns_sr_clk[4], + iopad_fs_sr_clk[4], iopad_fs_sr_clkb[4], iopad_unused_aib81[4], iopad_unused_aib80[4], + iopad_unused_aib79[4], iopad_unused_aib78[4], iopad_unused_aib77[4], iopad_unused_aib76[4], + iopad_unused_aib75[4], iopad_unused_aib74[4], iopad_unused_aib73[4], iopad_unused_aib72[4], + iopad_unused_aib71[4], iopad_unused_aib70[4], iopad_unused_aib69[4], iopad_unused_aib68[4], + iopad_unused_aib67[4], iopad_unused_aib66[4], iopad_fs_adapter_rstn[4], iopad_unused_aib64[4], + iopad_unused_aib63[4], iopad_unused_aib62[4], iopad_unused_aib61[4], iopad_unused_aib60[4], + iopad_fs_rcv_clkb[4], iopad_unused_aib58[4], iopad_fs_rcv_clk[4], iopad_ns_adapter_rstn[4], + iopad_ns_rcv_div2_clkb[4], iopad_ns_fwd_div2_clkb[4], iopad_ns_fwd_div2_clk[4], iopad_unused_aib52[4], + iopad_unused_aib51[4], iopad_unused_aib50[4], iopad_fs_mac_rdy[4], iopad_ns_rcv_div2_clk[4], + iopad_unused_aib47[4], iopad_unused_aib46[4], iopad_unused_aib45[4], iopad_fs_mac_rdy[4], + iopad_fs_fwd_clk[4], iopad_fs_fwd_clkb[4], iopad_ns_fwd_clk[4], iopad_ns_fwd_clkb[4], iopad_rx[99:80], iopad_tx[99:80]}), - - .io_aib_ch5 ({ iopad_ns_sr_data[5], iopad_ns_sr_load[5], iopad_fs_sr_data[5], iopad_fs_sr_load[5], - iopad_unused_aib91[5], iopad_unused_aib90[5], LO, LO, - iopad_ns_rcv_clk[5], iopad_ns_rcv_clkb[5], iopad_ns_sr_clkb[5], iopad_ns_sr_clk[5], - iopad_fs_sr_clk[5], iopad_fs_sr_clkb[5], LO, LO, - LO, LO, iopad_unused_aib77[5], iopad_unused_aib76[5], - iopad_unused_aib75[5], LO, LO, LO, - iopad_unused_aib71[5], iopad_unused_aib70[5], iopad_unused_aib69[5], iopad_unused_aib68[5], - LO, iopad_unused_aib66[5], iopad_fs_adapt_rstn[5], LO, - LO, iopad_unused_aib62[5], HI, iopad_unused_aib60[5], - iopad_fs_rcv_clkb[5], LO, iopad_fs_rcv_clk[5], iopad_ns_adapt_rstn[5], - iopad_ns_rcv_div2_clkb[5], iopad_ns_fwd_div2_clkb[5], iopad_ns_fwd_div2_clk[5], iopad_unused_aib52[5], - iopad_unused_aib51[5], iopad_unused_aib50[5], iopad_fs_mac_rdy[5], iopad_ns_rcv_div2_clk[5], - iopad_unused_aib47[5], iopad_unused_aib46[5], HI, iopad_fs_mac_rdy[5], - iopad_fs_fwd_clk[5], iopad_fs_fwd_clkb[5], iopad_ns_fwd_clk[5], iopad_ns_fwd_clkb[5], + .io_aib_ch5 ({ iopad_ns_sr_data[5], iopad_ns_sr_load[5], iopad_fs_sr_data[5], iopad_fs_sr_load[5], + iopad_unused_aib91[5], iopad_unused_aib90[5], iopad_unused_aib89[5], iopad_unused_aib88[5], + iopad_ns_rcv_clk[5], iopad_ns_rcv_clkb[5], iopad_ns_sr_clkb[5], iopad_ns_sr_clk[5], + iopad_fs_sr_clk[5], iopad_fs_sr_clkb[5], iopad_unused_aib81[5], iopad_unused_aib80[5], + iopad_unused_aib79[5], iopad_unused_aib78[5], iopad_unused_aib77[5], iopad_unused_aib76[5], + iopad_unused_aib75[5], iopad_unused_aib74[5], iopad_unused_aib73[5], iopad_unused_aib72[5], + iopad_unused_aib71[5], iopad_unused_aib70[5], iopad_unused_aib69[5], iopad_unused_aib68[5], + iopad_unused_aib67[5], iopad_unused_aib66[5], iopad_fs_adapter_rstn[5], iopad_unused_aib64[5], + iopad_unused_aib63[5], iopad_unused_aib62[5], iopad_unused_aib61[5], iopad_unused_aib60[5], + iopad_fs_rcv_clkb[5], iopad_unused_aib58[5], iopad_fs_rcv_clk[5], iopad_ns_adapter_rstn[5], + iopad_ns_rcv_div2_clkb[5], iopad_ns_fwd_div2_clkb[5], iopad_ns_fwd_div2_clk[5], iopad_unused_aib52[5], + iopad_unused_aib51[5], iopad_unused_aib50[5], iopad_fs_mac_rdy[5], iopad_ns_rcv_div2_clk[5], + iopad_unused_aib47[5], iopad_unused_aib46[5], iopad_unused_aib45[5], iopad_fs_mac_rdy[5], + iopad_fs_fwd_clk[5], iopad_fs_fwd_clkb[5], iopad_ns_fwd_clk[5], iopad_ns_fwd_clkb[5], iopad_rx[119:100], iopad_tx[119:100]}), - - .io_aib_ch6 ({ iopad_ns_sr_data[6], iopad_ns_sr_load[6], iopad_fs_sr_data[6], iopad_fs_sr_load[6], - iopad_unused_aib91[6], iopad_unused_aib90[6], LO, LO, - iopad_ns_rcv_clk[6], iopad_ns_rcv_clkb[6], iopad_ns_sr_clkb[6], iopad_ns_sr_clk[6], - iopad_fs_sr_clk[6], iopad_fs_sr_clkb[6], LO, LO, - LO, LO, iopad_unused_aib77[6], iopad_unused_aib76[6], - iopad_unused_aib75[6], LO, LO, LO, - iopad_unused_aib71[6], iopad_unused_aib70[6], iopad_unused_aib69[6], iopad_unused_aib68[6], - LO, iopad_unused_aib66[6], iopad_fs_adapt_rstn[6], LO, - LO, iopad_unused_aib62[6], HI, iopad_unused_aib60[6], - iopad_fs_rcv_clkb[6], LO, iopad_fs_rcv_clk[6], iopad_ns_adapt_rstn[6], - iopad_ns_rcv_div2_clkb[6], iopad_ns_fwd_div2_clkb[6], iopad_ns_fwd_div2_clk[6], iopad_unused_aib52[6], - iopad_unused_aib51[6], iopad_unused_aib50[6], iopad_fs_mac_rdy[6], iopad_ns_rcv_div2_clk[6], - iopad_unused_aib47[6], iopad_unused_aib46[6], HI, iopad_fs_mac_rdy[6], - iopad_fs_fwd_clk[6], iopad_fs_fwd_clkb[6], iopad_ns_fwd_clk[6], iopad_ns_fwd_clkb[6], + .io_aib_ch6 ({ iopad_ns_sr_data[6], iopad_ns_sr_load[6], iopad_fs_sr_data[6], iopad_fs_sr_load[6], + iopad_unused_aib91[6], iopad_unused_aib90[6], iopad_unused_aib89[6], iopad_unused_aib88[6], + iopad_ns_rcv_clk[6], iopad_ns_rcv_clkb[6], iopad_ns_sr_clkb[6], iopad_ns_sr_clk[6], + iopad_fs_sr_clk[6], iopad_fs_sr_clkb[6], iopad_unused_aib81[6], iopad_unused_aib80[6], + iopad_unused_aib79[6], iopad_unused_aib78[6], iopad_unused_aib77[6], iopad_unused_aib76[6], + iopad_unused_aib75[6], iopad_unused_aib74[6], iopad_unused_aib73[6], iopad_unused_aib72[6], + iopad_unused_aib71[6], iopad_unused_aib70[6], iopad_unused_aib69[6], iopad_unused_aib68[6], + iopad_unused_aib67[6], iopad_unused_aib66[6], iopad_fs_adapter_rstn[6], iopad_unused_aib64[6], + iopad_unused_aib63[6], iopad_unused_aib62[6], iopad_unused_aib61[6], iopad_unused_aib60[6], + iopad_fs_rcv_clkb[6], iopad_unused_aib58[6], iopad_fs_rcv_clk[6], iopad_ns_adapter_rstn[6], + iopad_ns_rcv_div2_clkb[6], iopad_ns_fwd_div2_clkb[6], iopad_ns_fwd_div2_clk[6], iopad_unused_aib52[6], + iopad_unused_aib51[6], iopad_unused_aib50[6], iopad_fs_mac_rdy[6], iopad_ns_rcv_div2_clk[6], + iopad_unused_aib47[6], iopad_unused_aib46[6], iopad_unused_aib45[6], iopad_fs_mac_rdy[6], + iopad_fs_fwd_clk[6], iopad_fs_fwd_clkb[6], iopad_ns_fwd_clk[6], iopad_ns_fwd_clkb[6], iopad_rx[139:120], iopad_tx[139:120]}), - - .io_aib_ch7 ({ iopad_ns_sr_data[7], iopad_ns_sr_load[7], iopad_fs_sr_data[7], iopad_fs_sr_load[7], - iopad_unused_aib91[7], iopad_unused_aib90[7], LO, LO, - iopad_ns_rcv_clk[7], iopad_ns_rcv_clkb[7], iopad_ns_sr_clkb[7], iopad_ns_sr_clk[7], - iopad_fs_sr_clk[7], iopad_fs_sr_clkb[7], LO, LO, - LO, LO, iopad_unused_aib77[7], iopad_unused_aib76[7], - iopad_unused_aib75[7], LO, LO, LO, - iopad_unused_aib71[7], iopad_unused_aib70[7], iopad_unused_aib69[7], iopad_unused_aib68[7], - LO, iopad_unused_aib66[7], iopad_fs_adapt_rstn[7], LO, - LO, iopad_unused_aib62[7], HI, iopad_unused_aib60[7], - iopad_fs_rcv_clkb[7], LO, iopad_fs_rcv_clk[7], iopad_ns_adapt_rstn[7], - iopad_ns_rcv_div2_clkb[7], iopad_ns_fwd_div2_clkb[7], iopad_ns_fwd_div2_clk[7], iopad_unused_aib52[7], - iopad_unused_aib51[7], iopad_unused_aib50[7], iopad_fs_mac_rdy[7], iopad_ns_rcv_div2_clk[7], - iopad_unused_aib47[7], iopad_unused_aib46[7], HI, iopad_fs_mac_rdy[7], - iopad_fs_fwd_clk[7], iopad_fs_fwd_clkb[7], iopad_ns_fwd_clk[7], iopad_ns_fwd_clkb[7], + .io_aib_ch7 ({ iopad_ns_sr_data[7], iopad_ns_sr_load[7], iopad_fs_sr_data[7], iopad_fs_sr_load[7], + iopad_unused_aib91[7], iopad_unused_aib90[7], iopad_unused_aib89[7], iopad_unused_aib88[7], + iopad_ns_rcv_clk[7], iopad_ns_rcv_clkb[7], iopad_ns_sr_clkb[7], iopad_ns_sr_clk[7], + iopad_fs_sr_clk[7], iopad_fs_sr_clkb[7], iopad_unused_aib81[7], iopad_unused_aib80[7], + iopad_unused_aib79[7], iopad_unused_aib78[7], iopad_unused_aib77[7], iopad_unused_aib76[7], + iopad_unused_aib75[7], iopad_unused_aib74[7], iopad_unused_aib73[7], iopad_unused_aib72[7], + iopad_unused_aib71[7], iopad_unused_aib70[7], iopad_unused_aib69[7], iopad_unused_aib68[7], + iopad_unused_aib67[7], iopad_unused_aib66[7], iopad_fs_adapter_rstn[7], iopad_unused_aib64[7], + iopad_unused_aib63[7], iopad_unused_aib62[7], iopad_unused_aib61[7], iopad_unused_aib60[7], + iopad_fs_rcv_clkb[7], iopad_unused_aib58[7], iopad_fs_rcv_clk[7], iopad_ns_adapter_rstn[7], + iopad_ns_rcv_div2_clkb[7], iopad_ns_fwd_div2_clkb[7], iopad_ns_fwd_div2_clk[7], iopad_unused_aib52[7], + iopad_unused_aib51[7], iopad_unused_aib50[7], iopad_fs_mac_rdy[7], iopad_ns_rcv_div2_clk[7], + iopad_unused_aib47[7], iopad_unused_aib46[7], iopad_unused_aib45[7], iopad_fs_mac_rdy[7], + iopad_fs_fwd_clk[7], iopad_fs_fwd_clkb[7], iopad_ns_fwd_clk[7], iopad_ns_fwd_clkb[7], iopad_rx[159:140], iopad_tx[159:140]}), - - .io_aib_ch8 ({ iopad_ns_sr_data[8], iopad_ns_sr_load[8], iopad_fs_sr_data[8], iopad_fs_sr_load[8], - iopad_unused_aib91[8], iopad_unused_aib90[8], LO, LO, - iopad_ns_rcv_clk[8], iopad_ns_rcv_clkb[8], iopad_ns_sr_clkb[8], iopad_ns_sr_clk[8], - iopad_fs_sr_clk[8], iopad_fs_sr_clkb[8], LO, LO, - LO, LO, iopad_unused_aib77[8], iopad_unused_aib76[8], - iopad_unused_aib75[8], LO, LO, LO, - iopad_unused_aib71[8], iopad_unused_aib70[8], iopad_unused_aib69[8], iopad_unused_aib68[8], - LO, iopad_unused_aib66[8], iopad_fs_adapt_rstn[8], LO, - LO, iopad_unused_aib62[8], HI, iopad_unused_aib60[8], - iopad_fs_rcv_clkb[8], LO, iopad_fs_rcv_clk[8], iopad_ns_adapt_rstn[8], - iopad_ns_rcv_div2_clkb[8], iopad_ns_fwd_div2_clkb[8], iopad_ns_fwd_div2_clk[8], iopad_unused_aib52[8], - iopad_unused_aib51[8], iopad_unused_aib50[8], iopad_fs_mac_rdy[8], iopad_ns_rcv_div2_clk[8], - iopad_unused_aib47[8], iopad_unused_aib46[8], HI, iopad_fs_mac_rdy[8], - iopad_fs_fwd_clk[8], iopad_fs_fwd_clkb[8], iopad_ns_fwd_clk[8], iopad_ns_fwd_clkb[8], + .io_aib_ch8 ({ iopad_ns_sr_data[8], iopad_ns_sr_load[8], iopad_fs_sr_data[8], iopad_fs_sr_load[8], + iopad_unused_aib91[8], iopad_unused_aib90[8], iopad_unused_aib89[8], iopad_unused_aib88[8], + iopad_ns_rcv_clk[8], iopad_ns_rcv_clkb[8], iopad_ns_sr_clkb[8], iopad_ns_sr_clk[8], + iopad_fs_sr_clk[8], iopad_fs_sr_clkb[8], iopad_unused_aib81[8], iopad_unused_aib80[8], + iopad_unused_aib79[8], iopad_unused_aib78[8], iopad_unused_aib77[8], iopad_unused_aib76[8], + iopad_unused_aib75[8], iopad_unused_aib74[8], iopad_unused_aib73[8], iopad_unused_aib72[8], + iopad_unused_aib71[8], iopad_unused_aib70[8], iopad_unused_aib69[8], iopad_unused_aib68[8], + iopad_unused_aib67[8], iopad_unused_aib66[8], iopad_fs_adapter_rstn[8], iopad_unused_aib64[8], + iopad_unused_aib63[8], iopad_unused_aib62[8], iopad_unused_aib61[8], iopad_unused_aib60[8], + iopad_fs_rcv_clkb[8], iopad_unused_aib58[8], iopad_fs_rcv_clk[8], iopad_ns_adapter_rstn[8], + iopad_ns_rcv_div2_clkb[8], iopad_ns_fwd_div2_clkb[8], iopad_ns_fwd_div2_clk[8], iopad_unused_aib52[8], + iopad_unused_aib51[8], iopad_unused_aib50[8], iopad_fs_mac_rdy[8], iopad_ns_rcv_div2_clk[8], + iopad_unused_aib47[8], iopad_unused_aib46[8], iopad_unused_aib45[8], iopad_fs_mac_rdy[8], + iopad_fs_fwd_clk[8], iopad_fs_fwd_clkb[8], iopad_ns_fwd_clk[8], iopad_ns_fwd_clkb[8], iopad_rx[179:160], iopad_tx[179:160]}), - - .io_aib_ch9 ({ iopad_ns_sr_data[9], iopad_ns_sr_load[9], iopad_fs_sr_data[9], iopad_fs_sr_load[9], - iopad_unused_aib91[9], iopad_unused_aib90[9], LO, LO, - iopad_ns_rcv_clk[9], iopad_ns_rcv_clkb[9], iopad_ns_sr_clkb[9], iopad_ns_sr_clk[9], - iopad_fs_sr_clk[9], iopad_fs_sr_clkb[9], LO, LO, - LO, LO, iopad_unused_aib77[9], iopad_unused_aib76[9], - iopad_unused_aib75[9], LO, LO, LO, - iopad_unused_aib71[9], iopad_unused_aib70[9], iopad_unused_aib69[9], iopad_unused_aib68[9], - LO, iopad_unused_aib66[9], iopad_fs_adapt_rstn[9], LO, - LO, iopad_unused_aib62[9], HI, iopad_unused_aib60[9], - iopad_fs_rcv_clkb[9], LO, iopad_fs_rcv_clk[9], iopad_ns_adapt_rstn[9], - iopad_ns_rcv_div2_clkb[9], iopad_ns_fwd_div2_clkb[9], iopad_ns_fwd_div2_clk[9], iopad_unused_aib52[9], - iopad_unused_aib51[9], iopad_unused_aib50[9], iopad_fs_mac_rdy[9], iopad_ns_rcv_div2_clk[9], - iopad_unused_aib47[9], iopad_unused_aib46[9], HI, iopad_fs_mac_rdy[9], - iopad_fs_fwd_clk[9], iopad_fs_fwd_clkb[9], iopad_ns_fwd_clk[9], iopad_ns_fwd_clkb[9], + .io_aib_ch9 ({ iopad_ns_sr_data[9], iopad_ns_sr_load[9], iopad_fs_sr_data[9], iopad_fs_sr_load[9], + iopad_unused_aib91[9], iopad_unused_aib90[9], iopad_unused_aib89[9], iopad_unused_aib88[9], + iopad_ns_rcv_clk[9], iopad_ns_rcv_clkb[9], iopad_ns_sr_clkb[9], iopad_ns_sr_clk[9], + iopad_fs_sr_clk[9], iopad_fs_sr_clkb[9], iopad_unused_aib81[9], iopad_unused_aib80[9], + iopad_unused_aib79[9], iopad_unused_aib78[9], iopad_unused_aib77[9], iopad_unused_aib76[9], + iopad_unused_aib75[9], iopad_unused_aib74[9], iopad_unused_aib73[9], iopad_unused_aib72[9], + iopad_unused_aib71[9], iopad_unused_aib70[9], iopad_unused_aib69[9], iopad_unused_aib68[9], + iopad_unused_aib67[9], iopad_unused_aib66[9], iopad_fs_adapter_rstn[9], iopad_unused_aib64[9], + iopad_unused_aib63[9], iopad_unused_aib62[9], iopad_unused_aib61[9], iopad_unused_aib60[9], + iopad_fs_rcv_clkb[9], iopad_unused_aib58[9], iopad_fs_rcv_clk[9], iopad_ns_adapter_rstn[9], + iopad_ns_rcv_div2_clkb[9], iopad_ns_fwd_div2_clkb[9], iopad_ns_fwd_div2_clk[9], iopad_unused_aib52[9], + iopad_unused_aib51[9], iopad_unused_aib50[9], iopad_fs_mac_rdy[9], iopad_ns_rcv_div2_clk[9], + iopad_unused_aib47[9], iopad_unused_aib46[9], iopad_unused_aib45[9], iopad_fs_mac_rdy[9], + iopad_fs_fwd_clk[9], iopad_fs_fwd_clkb[9], iopad_ns_fwd_clk[9], iopad_ns_fwd_clkb[9], iopad_rx[199:180], iopad_tx[199:180]}), - - .io_aib_ch10 ({ iopad_ns_sr_data[10], iopad_ns_sr_load[10], iopad_fs_sr_data[10], iopad_fs_sr_load[10], - iopad_unused_aib91[10], iopad_unused_aib90[10], LO, LO, - iopad_ns_rcv_clk[10], iopad_ns_rcv_clkb[10], iopad_ns_sr_clkb[10], iopad_ns_sr_clk[10], - iopad_fs_sr_clk[10], iopad_fs_sr_clkb[10], LO, LO, - LO, LO, iopad_unused_aib77[10], iopad_unused_aib76[10], - iopad_unused_aib75[10], LO, LO, LO, - iopad_unused_aib71[10], iopad_unused_aib70[10], iopad_unused_aib69[10], iopad_unused_aib68[10], - LO, iopad_unused_aib66[10], iopad_fs_adapt_rstn[10], LO, - LO, iopad_unused_aib62[10], HI, iopad_unused_aib60[10], - iopad_fs_rcv_clkb[10], LO, iopad_fs_rcv_clk[10], iopad_ns_adapt_rstn[10], - iopad_ns_rcv_div2_clkb[10], iopad_ns_fwd_div2_clkb[10], iopad_ns_fwd_div2_clk[10], iopad_unused_aib52[10], - iopad_unused_aib51[10], iopad_unused_aib50[10], iopad_fs_mac_rdy[10], iopad_ns_rcv_div2_clk[10], - iopad_unused_aib47[10], iopad_unused_aib46[10], HI, iopad_fs_mac_rdy[10], - iopad_fs_fwd_clk[10], iopad_fs_fwd_clkb[10], iopad_ns_fwd_clk[10], iopad_ns_fwd_clkb[10], + .io_aib_ch10 ({ iopad_ns_sr_data[10], iopad_ns_sr_load[10], iopad_fs_sr_data[10], iopad_fs_sr_load[10], + iopad_unused_aib91[10], iopad_unused_aib90[10], iopad_unused_aib89[10], iopad_unused_aib88[10], + iopad_ns_rcv_clk[10], iopad_ns_rcv_clkb[10], iopad_ns_sr_clkb[10], iopad_ns_sr_clk[10], + iopad_fs_sr_clk[10], iopad_fs_sr_clkb[10], iopad_unused_aib81[10], iopad_unused_aib80[10], + iopad_unused_aib79[10], iopad_unused_aib78[10], iopad_unused_aib77[10], iopad_unused_aib76[10], + iopad_unused_aib75[10], iopad_unused_aib74[10], iopad_unused_aib73[10], iopad_unused_aib72[10], + iopad_unused_aib71[10], iopad_unused_aib70[10], iopad_unused_aib69[10], iopad_unused_aib68[10], + iopad_unused_aib67[10], iopad_unused_aib66[10], iopad_fs_adapter_rstn[10], iopad_unused_aib64[10], + iopad_unused_aib63[10], iopad_unused_aib62[10], iopad_unused_aib61[10], iopad_unused_aib60[10], + iopad_fs_rcv_clkb[10], iopad_unused_aib58[10], iopad_fs_rcv_clk[10], iopad_ns_adapter_rstn[10], + iopad_ns_rcv_div2_clkb[10], iopad_ns_fwd_div2_clkb[10], iopad_ns_fwd_div2_clk[10], iopad_unused_aib52[10], + iopad_unused_aib51[10], iopad_unused_aib50[10], iopad_fs_mac_rdy[10], iopad_ns_rcv_div2_clk[10], + iopad_unused_aib47[10], iopad_unused_aib46[10], iopad_unused_aib45[10], iopad_fs_mac_rdy[10], + iopad_fs_fwd_clk[10], iopad_fs_fwd_clkb[10], iopad_ns_fwd_clk[10], iopad_ns_fwd_clkb[10], iopad_rx[219:200], iopad_tx[219:200]}), - - .io_aib_ch11 ({ iopad_ns_sr_data[11], iopad_ns_sr_load[11], iopad_fs_sr_data[11], iopad_fs_sr_load[11], - iopad_unused_aib91[11], iopad_unused_aib90[11], LO, LO, - iopad_ns_rcv_clk[11], iopad_ns_rcv_clkb[11], iopad_ns_sr_clkb[11], iopad_ns_sr_clk[11], - iopad_fs_sr_clk[11], iopad_fs_sr_clkb[11], LO, LO, - LO, LO, iopad_unused_aib77[11], iopad_unused_aib76[11], - iopad_unused_aib75[11], LO, LO, LO, - iopad_unused_aib71[11], iopad_unused_aib70[11], iopad_unused_aib69[11], iopad_unused_aib68[11], - LO, iopad_unused_aib66[11], iopad_fs_adapt_rstn[11], LO, - LO, iopad_unused_aib62[11], HI, iopad_unused_aib60[11], - iopad_fs_rcv_clkb[11], LO, iopad_fs_rcv_clk[11], iopad_ns_adapt_rstn[11], - iopad_ns_rcv_div2_clkb[11], iopad_ns_fwd_div2_clkb[11], iopad_ns_fwd_div2_clk[11], iopad_unused_aib52[11], - iopad_unused_aib51[11], iopad_unused_aib50[11], iopad_fs_mac_rdy[11], iopad_ns_rcv_div2_clk[11], - iopad_unused_aib47[11], iopad_unused_aib46[11], HI, iopad_fs_mac_rdy[11], - iopad_fs_fwd_clk[11], iopad_fs_fwd_clkb[11], iopad_ns_fwd_clk[11], iopad_ns_fwd_clkb[11], + .io_aib_ch11 ({ iopad_ns_sr_data[11], iopad_ns_sr_load[11], iopad_fs_sr_data[11], iopad_fs_sr_load[11], + iopad_unused_aib91[11], iopad_unused_aib90[11], iopad_unused_aib89[11], iopad_unused_aib88[11], + iopad_ns_rcv_clk[11], iopad_ns_rcv_clkb[11], iopad_ns_sr_clkb[11], iopad_ns_sr_clk[11], + iopad_fs_sr_clk[11], iopad_fs_sr_clkb[11], iopad_unused_aib81[11], iopad_unused_aib80[11], + iopad_unused_aib79[11], iopad_unused_aib78[11], iopad_unused_aib77[11], iopad_unused_aib76[11], + iopad_unused_aib75[11], iopad_unused_aib74[11], iopad_unused_aib73[11], iopad_unused_aib72[11], + iopad_unused_aib71[11], iopad_unused_aib70[11], iopad_unused_aib69[11], iopad_unused_aib68[11], + iopad_unused_aib67[11], iopad_unused_aib66[11], iopad_fs_adapter_rstn[11], iopad_unused_aib64[11], + iopad_unused_aib63[11], iopad_unused_aib62[11], iopad_unused_aib61[11], iopad_unused_aib60[11], + iopad_fs_rcv_clkb[11], iopad_unused_aib58[11], iopad_fs_rcv_clk[11], iopad_ns_adapter_rstn[11], + iopad_ns_rcv_div2_clkb[11], iopad_ns_fwd_div2_clkb[11], iopad_ns_fwd_div2_clk[11], iopad_unused_aib52[11], + iopad_unused_aib51[11], iopad_unused_aib50[11], iopad_fs_mac_rdy[11], iopad_ns_rcv_div2_clk[11], + iopad_unused_aib47[11], iopad_unused_aib46[11], iopad_unused_aib45[11], iopad_fs_mac_rdy[11], + iopad_fs_fwd_clk[11], iopad_fs_fwd_clkb[11], iopad_ns_fwd_clk[11], iopad_ns_fwd_clkb[11], iopad_rx[239:220], iopad_tx[239:220]}), - - .io_aib_ch12 ({ iopad_ns_sr_data[12], iopad_ns_sr_load[12], iopad_fs_sr_data[12], iopad_fs_sr_load[12], - iopad_unused_aib91[12], iopad_unused_aib90[12], LO, LO, - iopad_ns_rcv_clk[12], iopad_ns_rcv_clkb[12], iopad_ns_sr_clkb[12], iopad_ns_sr_clk[12], - iopad_fs_sr_clk[12], iopad_fs_sr_clkb[12], LO, LO, - LO, LO, iopad_unused_aib77[12], iopad_unused_aib76[12], - iopad_unused_aib75[12], LO, LO, LO, - iopad_unused_aib71[12], iopad_unused_aib70[12], iopad_unused_aib69[12], iopad_unused_aib68[12], - LO, iopad_unused_aib66[12], iopad_fs_adapt_rstn[12], LO, - LO, iopad_unused_aib62[12], HI, iopad_unused_aib60[12], - iopad_fs_rcv_clkb[12], LO, iopad_fs_rcv_clk[12], iopad_ns_adapt_rstn[12], - iopad_ns_rcv_div2_clkb[12], iopad_ns_fwd_div2_clkb[12], iopad_ns_fwd_div2_clk[12], iopad_unused_aib52[12], - iopad_unused_aib51[12], iopad_unused_aib50[12], iopad_fs_mac_rdy[12], iopad_ns_rcv_div2_clk[12], - iopad_unused_aib47[12], iopad_unused_aib46[12], HI, iopad_fs_mac_rdy[12], - iopad_fs_fwd_clk[12], iopad_fs_fwd_clkb[12], iopad_ns_fwd_clk[12], iopad_ns_fwd_clkb[12], + .io_aib_ch12 ({ iopad_ns_sr_data[12], iopad_ns_sr_load[12], iopad_fs_sr_data[12], iopad_fs_sr_load[12], + iopad_unused_aib91[12], iopad_unused_aib90[12], iopad_unused_aib89[12], iopad_unused_aib88[12], + iopad_ns_rcv_clk[12], iopad_ns_rcv_clkb[12], iopad_ns_sr_clkb[12], iopad_ns_sr_clk[12], + iopad_fs_sr_clk[12], iopad_fs_sr_clkb[12], iopad_unused_aib81[12], iopad_unused_aib80[12], + iopad_unused_aib79[12], iopad_unused_aib78[12], iopad_unused_aib77[12], iopad_unused_aib76[12], + iopad_unused_aib75[12], iopad_unused_aib74[12], iopad_unused_aib73[12], iopad_unused_aib72[12], + iopad_unused_aib71[12], iopad_unused_aib70[12], iopad_unused_aib69[12], iopad_unused_aib68[12], + iopad_unused_aib67[12], iopad_unused_aib66[12], iopad_fs_adapter_rstn[12], iopad_unused_aib64[12], + iopad_unused_aib63[12], iopad_unused_aib62[12], iopad_unused_aib61[12], iopad_unused_aib60[12], + iopad_fs_rcv_clkb[12], iopad_unused_aib58[12], iopad_fs_rcv_clk[12], iopad_ns_adapter_rstn[12], + iopad_ns_rcv_div2_clkb[12], iopad_ns_fwd_div2_clkb[12], iopad_ns_fwd_div2_clk[12], iopad_unused_aib52[12], + iopad_unused_aib51[12], iopad_unused_aib50[12], iopad_fs_mac_rdy[12], iopad_ns_rcv_div2_clk[12], + iopad_unused_aib47[12], iopad_unused_aib46[12], iopad_unused_aib45[12], iopad_fs_mac_rdy[12], + iopad_fs_fwd_clk[12], iopad_fs_fwd_clkb[12], iopad_ns_fwd_clk[12], iopad_ns_fwd_clkb[12], iopad_rx[259:240], iopad_tx[259:240]}), - - .io_aib_ch13 ({ iopad_ns_sr_data[13], iopad_ns_sr_load[13], iopad_fs_sr_data[13], iopad_fs_sr_load[13], - iopad_unused_aib91[13], iopad_unused_aib90[13], LO, LO, - iopad_ns_rcv_clk[13], iopad_ns_rcv_clkb[13], iopad_ns_sr_clkb[13], iopad_ns_sr_clk[13], - iopad_fs_sr_clk[13], iopad_fs_sr_clkb[13], LO, LO, - LO, LO, iopad_unused_aib77[13], iopad_unused_aib76[13], - iopad_unused_aib75[13], LO, LO, LO, - iopad_unused_aib71[13], iopad_unused_aib70[13], iopad_unused_aib69[13], iopad_unused_aib68[13], - LO, iopad_unused_aib66[13], iopad_fs_adapt_rstn[13], LO, - LO, iopad_unused_aib62[13], HI, iopad_unused_aib60[13], - iopad_fs_rcv_clkb[13], LO, iopad_fs_rcv_clk[13], iopad_ns_adapt_rstn[13], - iopad_ns_rcv_div2_clkb[13], iopad_ns_fwd_div2_clkb[13], iopad_ns_fwd_div2_clk[13], iopad_unused_aib52[13], - iopad_unused_aib51[13], iopad_unused_aib50[13], iopad_fs_mac_rdy[13], iopad_ns_rcv_div2_clk[13], - iopad_unused_aib47[13], iopad_unused_aib46[13], HI, iopad_fs_mac_rdy[13], - iopad_fs_fwd_clk[13], iopad_fs_fwd_clkb[13], iopad_ns_fwd_clk[13], iopad_ns_fwd_clkb[13], + .io_aib_ch13 ({ iopad_ns_sr_data[13], iopad_ns_sr_load[13], iopad_fs_sr_data[13], iopad_fs_sr_load[13], + iopad_unused_aib91[13], iopad_unused_aib90[13], iopad_unused_aib89[13], iopad_unused_aib88[13], + iopad_ns_rcv_clk[13], iopad_ns_rcv_clkb[13], iopad_ns_sr_clkb[13], iopad_ns_sr_clk[13], + iopad_fs_sr_clk[13], iopad_fs_sr_clkb[13], iopad_unused_aib81[13], iopad_unused_aib80[13], + iopad_unused_aib79[13], iopad_unused_aib78[13], iopad_unused_aib77[13], iopad_unused_aib76[13], + iopad_unused_aib75[13], iopad_unused_aib74[13], iopad_unused_aib73[13], iopad_unused_aib72[13], + iopad_unused_aib71[13], iopad_unused_aib70[13], iopad_unused_aib69[13], iopad_unused_aib68[13], + iopad_unused_aib67[13], iopad_unused_aib66[13], iopad_fs_adapter_rstn[13], iopad_unused_aib64[13], + iopad_unused_aib63[13], iopad_unused_aib62[13], iopad_unused_aib61[13], iopad_unused_aib60[13], + iopad_fs_rcv_clkb[13], iopad_unused_aib58[13], iopad_fs_rcv_clk[13], iopad_ns_adapter_rstn[13], + iopad_ns_rcv_div2_clkb[13], iopad_ns_fwd_div2_clkb[13], iopad_ns_fwd_div2_clk[13], iopad_unused_aib52[13], + iopad_unused_aib51[13], iopad_unused_aib50[13], iopad_fs_mac_rdy[13], iopad_ns_rcv_div2_clk[13], + iopad_unused_aib47[13], iopad_unused_aib46[13], iopad_unused_aib45[13], iopad_fs_mac_rdy[13], + iopad_fs_fwd_clk[13], iopad_fs_fwd_clkb[13], iopad_ns_fwd_clk[13], iopad_ns_fwd_clkb[13], iopad_rx[279:260], iopad_tx[279:260]}), - - .io_aib_ch14 ({ iopad_ns_sr_data[14], iopad_ns_sr_load[14], iopad_fs_sr_data[14], iopad_fs_sr_load[14], - iopad_unused_aib91[14], iopad_unused_aib90[14], LO, LO, - iopad_ns_rcv_clk[14], iopad_ns_rcv_clkb[14], iopad_ns_sr_clkb[14], iopad_ns_sr_clk[14], - iopad_fs_sr_clk[14], iopad_fs_sr_clkb[14], LO, LO, - LO, LO, iopad_unused_aib77[14], iopad_unused_aib76[14], - iopad_unused_aib75[14], LO, LO, LO, - iopad_unused_aib71[14], iopad_unused_aib70[14], iopad_unused_aib69[14], iopad_unused_aib68[14], - LO, iopad_unused_aib66[14], iopad_fs_adapt_rstn[14], LO, - LO, iopad_unused_aib62[14], HI, iopad_unused_aib60[14], - iopad_fs_rcv_clkb[14], LO, iopad_fs_rcv_clk[14], iopad_ns_adapt_rstn[14], - iopad_ns_rcv_div2_clkb[14], iopad_ns_fwd_div2_clkb[14], iopad_ns_fwd_div2_clk[14], iopad_unused_aib52[14], - iopad_unused_aib51[14], iopad_unused_aib50[14], iopad_fs_mac_rdy[14], iopad_ns_rcv_div2_clk[14], - iopad_unused_aib47[14], iopad_unused_aib46[14], HI, iopad_fs_mac_rdy[14], - iopad_fs_fwd_clk[14], iopad_fs_fwd_clkb[14], iopad_ns_fwd_clk[14], iopad_ns_fwd_clkb[14], + .io_aib_ch14 ({ iopad_ns_sr_data[14], iopad_ns_sr_load[14], iopad_fs_sr_data[14], iopad_fs_sr_load[14], + iopad_unused_aib91[14], iopad_unused_aib90[14], iopad_unused_aib89[14], iopad_unused_aib88[14], + iopad_ns_rcv_clk[14], iopad_ns_rcv_clkb[14], iopad_ns_sr_clkb[14], iopad_ns_sr_clk[14], + iopad_fs_sr_clk[14], iopad_fs_sr_clkb[14], iopad_unused_aib81[14], iopad_unused_aib80[14], + iopad_unused_aib79[14], iopad_unused_aib78[14], iopad_unused_aib77[14], iopad_unused_aib76[14], + iopad_unused_aib75[14], iopad_unused_aib74[14], iopad_unused_aib73[14], iopad_unused_aib72[14], + iopad_unused_aib71[14], iopad_unused_aib70[14], iopad_unused_aib69[14], iopad_unused_aib68[14], + iopad_unused_aib67[14], iopad_unused_aib66[14], iopad_fs_adapter_rstn[14], iopad_unused_aib64[14], + iopad_unused_aib63[14], iopad_unused_aib62[14], iopad_unused_aib61[14], iopad_unused_aib60[14], + iopad_fs_rcv_clkb[14], iopad_unused_aib58[14], iopad_fs_rcv_clk[14], iopad_ns_adapter_rstn[14], + iopad_ns_rcv_div2_clkb[14], iopad_ns_fwd_div2_clkb[14], iopad_ns_fwd_div2_clk[14], iopad_unused_aib52[14], + iopad_unused_aib51[14], iopad_unused_aib50[14], iopad_fs_mac_rdy[14], iopad_ns_rcv_div2_clk[14], + iopad_unused_aib47[14], iopad_unused_aib46[14], iopad_unused_aib45[14], iopad_fs_mac_rdy[14], + iopad_fs_fwd_clk[14], iopad_fs_fwd_clkb[14], iopad_ns_fwd_clk[14], iopad_ns_fwd_clkb[14], iopad_rx[299:280], iopad_tx[299:280]}), - - .io_aib_ch15 ({ iopad_ns_sr_data[15], iopad_ns_sr_load[15], iopad_fs_sr_data[15], iopad_fs_sr_load[15], - iopad_unused_aib91[15], iopad_unused_aib90[15], LO, LO, - iopad_ns_rcv_clk[15], iopad_ns_rcv_clkb[15], iopad_ns_sr_clkb[15], iopad_ns_sr_clk[15], - iopad_fs_sr_clk[15], iopad_fs_sr_clkb[15], LO, LO, - LO, LO, iopad_unused_aib77[15], iopad_unused_aib76[15], - iopad_unused_aib75[15], LO, LO, LO, - iopad_unused_aib71[15], iopad_unused_aib70[15], iopad_unused_aib69[15], iopad_unused_aib68[15], - LO, iopad_unused_aib66[15], iopad_fs_adapt_rstn[15], LO, - LO, iopad_unused_aib62[15], HI, iopad_unused_aib60[15], - iopad_fs_rcv_clkb[15], LO, iopad_fs_rcv_clk[15], iopad_ns_adapt_rstn[15], - iopad_ns_rcv_div2_clkb[15], iopad_ns_fwd_div2_clkb[15], iopad_ns_fwd_div2_clk[15], iopad_unused_aib52[15], - iopad_unused_aib51[15], iopad_unused_aib50[15], iopad_fs_mac_rdy[15], iopad_ns_rcv_div2_clk[15], - iopad_unused_aib47[15], iopad_unused_aib46[15], HI, iopad_fs_mac_rdy[15], - iopad_fs_fwd_clk[15], iopad_fs_fwd_clkb[15], iopad_ns_fwd_clk[15], iopad_ns_fwd_clkb[15], + .io_aib_ch15 ({ iopad_ns_sr_data[15], iopad_ns_sr_load[15], iopad_fs_sr_data[15], iopad_fs_sr_load[15], + iopad_unused_aib91[15], iopad_unused_aib90[15], iopad_unused_aib89[15], iopad_unused_aib88[15], + iopad_ns_rcv_clk[15], iopad_ns_rcv_clkb[15], iopad_ns_sr_clkb[15], iopad_ns_sr_clk[15], + iopad_fs_sr_clk[15], iopad_fs_sr_clkb[15], iopad_unused_aib81[15], iopad_unused_aib80[15], + iopad_unused_aib79[15], iopad_unused_aib78[15], iopad_unused_aib77[15], iopad_unused_aib76[15], + iopad_unused_aib75[15], iopad_unused_aib74[15], iopad_unused_aib73[15], iopad_unused_aib72[15], + iopad_unused_aib71[15], iopad_unused_aib70[15], iopad_unused_aib69[15], iopad_unused_aib68[15], + iopad_unused_aib67[15], iopad_unused_aib66[15], iopad_fs_adapter_rstn[15], iopad_unused_aib64[15], + iopad_unused_aib63[15], iopad_unused_aib62[15], iopad_unused_aib61[15], iopad_unused_aib60[15], + iopad_fs_rcv_clkb[15], iopad_unused_aib58[15], iopad_fs_rcv_clk[15], iopad_ns_adapter_rstn[15], + iopad_ns_rcv_div2_clkb[15], iopad_ns_fwd_div2_clkb[15], iopad_ns_fwd_div2_clk[15], iopad_unused_aib52[15], + iopad_unused_aib51[15], iopad_unused_aib50[15], iopad_fs_mac_rdy[15], iopad_ns_rcv_div2_clk[15], + iopad_unused_aib47[15], iopad_unused_aib46[15], iopad_unused_aib45[15], iopad_fs_mac_rdy[15], + iopad_fs_fwd_clk[15], iopad_fs_fwd_clkb[15], iopad_ns_fwd_clk[15], iopad_ns_fwd_clkb[15], iopad_rx[319:300], iopad_tx[319:300]}), - - .io_aib_ch16 ({ iopad_ns_sr_data[16], iopad_ns_sr_load[16], iopad_fs_sr_data[16], iopad_fs_sr_load[16], - iopad_unused_aib91[16], iopad_unused_aib90[16], LO, LO, - iopad_ns_rcv_clk[16], iopad_ns_rcv_clkb[16], iopad_ns_sr_clkb[16], iopad_ns_sr_clk[16], - iopad_fs_sr_clk[16], iopad_fs_sr_clkb[16], LO, LO, - LO, LO, iopad_unused_aib77[16], iopad_unused_aib76[16], - iopad_unused_aib75[16], LO, LO, LO, - iopad_unused_aib71[16], iopad_unused_aib70[16], iopad_unused_aib69[16], iopad_unused_aib68[16], - LO, iopad_unused_aib66[16], iopad_fs_adapt_rstn[16], LO, - LO, iopad_unused_aib62[16], HI, iopad_unused_aib60[16], - iopad_fs_rcv_clkb[16], LO, iopad_fs_rcv_clk[16], iopad_ns_adapt_rstn[16], - iopad_ns_rcv_div2_clkb[16], iopad_ns_fwd_div2_clkb[16], iopad_ns_fwd_div2_clk[16], iopad_unused_aib52[16], - iopad_unused_aib51[16], iopad_unused_aib50[16], iopad_fs_mac_rdy[16], iopad_ns_rcv_div2_clk[16], - iopad_unused_aib47[16], iopad_unused_aib46[16], HI, iopad_fs_mac_rdy[16], - iopad_fs_fwd_clk[16], iopad_fs_fwd_clkb[16], iopad_ns_fwd_clk[16], iopad_ns_fwd_clkb[16], + .io_aib_ch16 ({ iopad_ns_sr_data[16], iopad_ns_sr_load[16], iopad_fs_sr_data[16], iopad_fs_sr_load[16], + iopad_unused_aib91[16], iopad_unused_aib90[16], iopad_unused_aib89[16], iopad_unused_aib88[16], + iopad_ns_rcv_clk[16], iopad_ns_rcv_clkb[16], iopad_ns_sr_clkb[16], iopad_ns_sr_clk[16], + iopad_fs_sr_clk[16], iopad_fs_sr_clkb[16], iopad_unused_aib81[16], iopad_unused_aib80[16], + iopad_unused_aib79[16], iopad_unused_aib78[16], iopad_unused_aib77[16], iopad_unused_aib76[16], + iopad_unused_aib75[16], iopad_unused_aib74[16], iopad_unused_aib73[16], iopad_unused_aib72[16], + iopad_unused_aib71[16], iopad_unused_aib70[16], iopad_unused_aib69[16], iopad_unused_aib68[16], + iopad_unused_aib67[16], iopad_unused_aib66[16], iopad_fs_adapter_rstn[16], iopad_unused_aib64[16], + iopad_unused_aib63[16], iopad_unused_aib62[16], iopad_unused_aib61[16], iopad_unused_aib60[16], + iopad_fs_rcv_clkb[16], iopad_unused_aib58[16], iopad_fs_rcv_clk[16], iopad_ns_adapter_rstn[16], + iopad_ns_rcv_div2_clkb[16], iopad_ns_fwd_div2_clkb[16], iopad_ns_fwd_div2_clk[16], iopad_unused_aib52[16], + iopad_unused_aib51[16], iopad_unused_aib50[16], iopad_fs_mac_rdy[16], iopad_ns_rcv_div2_clk[16], + iopad_unused_aib47[16], iopad_unused_aib46[16], iopad_unused_aib45[16], iopad_fs_mac_rdy[16], + iopad_fs_fwd_clk[16], iopad_fs_fwd_clkb[16], iopad_ns_fwd_clk[16], iopad_ns_fwd_clkb[16], iopad_rx[339:320], iopad_tx[339:320]}), - - .io_aib_ch17 ({ iopad_ns_sr_data[17], iopad_ns_sr_load[17], iopad_fs_sr_data[17], iopad_fs_sr_load[17], - iopad_unused_aib91[17], iopad_unused_aib90[17], LO, LO, - iopad_ns_rcv_clk[17], iopad_ns_rcv_clkb[17], iopad_ns_sr_clkb[17], iopad_ns_sr_clk[17], - iopad_fs_sr_clk[17], iopad_fs_sr_clkb[17], LO, LO, - LO, LO, iopad_unused_aib77[17], iopad_unused_aib76[17], - iopad_unused_aib75[17], LO, LO, LO, - iopad_unused_aib71[17], iopad_unused_aib70[17], iopad_unused_aib69[17], iopad_unused_aib68[17], - LO, iopad_unused_aib66[17], iopad_fs_adapt_rstn[17], LO, - LO, iopad_unused_aib62[17], HI, iopad_unused_aib60[17], - iopad_fs_rcv_clkb[17], LO, iopad_fs_rcv_clk[17], iopad_ns_adapt_rstn[17], - iopad_ns_rcv_div2_clkb[17], iopad_ns_fwd_div2_clkb[17], iopad_ns_fwd_div2_clk[17], iopad_unused_aib52[17], - iopad_unused_aib51[17], iopad_unused_aib50[17], iopad_fs_mac_rdy[17], iopad_ns_rcv_div2_clk[17], - iopad_unused_aib47[17], iopad_unused_aib46[17], HI, iopad_fs_mac_rdy[17], - iopad_fs_fwd_clk[17], iopad_fs_fwd_clkb[17], iopad_ns_fwd_clk[17], iopad_ns_fwd_clkb[17], + .io_aib_ch17 ({ iopad_ns_sr_data[17], iopad_ns_sr_load[17], iopad_fs_sr_data[17], iopad_fs_sr_load[17], + iopad_unused_aib91[17], iopad_unused_aib90[17], iopad_unused_aib89[17], iopad_unused_aib88[17], + iopad_ns_rcv_clk[17], iopad_ns_rcv_clkb[17], iopad_ns_sr_clkb[17], iopad_ns_sr_clk[17], + iopad_fs_sr_clk[17], iopad_fs_sr_clkb[17], iopad_unused_aib81[17], iopad_unused_aib80[17], + iopad_unused_aib79[17], iopad_unused_aib78[17], iopad_unused_aib77[17], iopad_unused_aib76[17], + iopad_unused_aib75[17], iopad_unused_aib74[17], iopad_unused_aib73[17], iopad_unused_aib72[17], + iopad_unused_aib71[17], iopad_unused_aib70[17], iopad_unused_aib69[17], iopad_unused_aib68[17], + iopad_unused_aib67[17], iopad_unused_aib66[17], iopad_fs_adapter_rstn[17], iopad_unused_aib64[17], + iopad_unused_aib63[17], iopad_unused_aib62[17], iopad_unused_aib61[17], iopad_unused_aib60[17], + iopad_fs_rcv_clkb[17], iopad_unused_aib58[17], iopad_fs_rcv_clk[17], iopad_ns_adapter_rstn[17], + iopad_ns_rcv_div2_clkb[17], iopad_ns_fwd_div2_clkb[17], iopad_ns_fwd_div2_clk[17], iopad_unused_aib52[17], + iopad_unused_aib51[17], iopad_unused_aib50[17], iopad_fs_mac_rdy[17], iopad_ns_rcv_div2_clk[17], + iopad_unused_aib47[17], iopad_unused_aib46[17], iopad_unused_aib45[17], iopad_fs_mac_rdy[17], + iopad_fs_fwd_clk[17], iopad_fs_fwd_clkb[17], iopad_ns_fwd_clk[17], iopad_ns_fwd_clkb[17], iopad_rx[359:340], iopad_tx[359:340]}), - .io_aib_ch18 ({ iopad_ns_sr_data[18], iopad_ns_sr_load[18], iopad_fs_sr_data[18], iopad_fs_sr_load[18], - iopad_unused_aib91[18], iopad_unused_aib90[18], LO, LO, - iopad_ns_rcv_clk[18], iopad_ns_rcv_clkb[18], iopad_ns_sr_clkb[18], iopad_ns_sr_clk[18], - iopad_fs_sr_clk[18], iopad_fs_sr_clkb[18], LO, LO, - LO, LO, iopad_unused_aib77[18], iopad_unused_aib76[18], - iopad_unused_aib75[18], LO, LO, LO, - iopad_unused_aib71[18], iopad_unused_aib70[18], iopad_unused_aib69[18], iopad_unused_aib68[18], - LO, iopad_unused_aib66[18], iopad_fs_adapt_rstn[18], LO, - LO, iopad_unused_aib62[18], HI, iopad_unused_aib60[18], - iopad_fs_rcv_clkb[18], LO, iopad_fs_rcv_clk[18], iopad_ns_adapt_rstn[18], - iopad_ns_rcv_div2_clkb[18], iopad_ns_fwd_div2_clkb[18], iopad_ns_fwd_div2_clk[18], iopad_unused_aib52[18], - iopad_unused_aib51[18], iopad_unused_aib50[18], iopad_fs_mac_rdy[18], iopad_ns_rcv_div2_clk[18], - iopad_unused_aib47[18], iopad_unused_aib46[18], HI, iopad_fs_mac_rdy[18], - iopad_fs_fwd_clk[18], iopad_fs_fwd_clkb[18], iopad_ns_fwd_clk[18], iopad_ns_fwd_clkb[18], + .io_aib_ch18 ({ iopad_ns_sr_data[18], iopad_ns_sr_load[18], iopad_fs_sr_data[18], iopad_fs_sr_load[18], + iopad_unused_aib91[18], iopad_unused_aib90[18], iopad_unused_aib89[18], iopad_unused_aib88[18], + iopad_ns_rcv_clk[18], iopad_ns_rcv_clkb[18], iopad_ns_sr_clkb[18], iopad_ns_sr_clk[18], + iopad_fs_sr_clk[18], iopad_fs_sr_clkb[18], iopad_unused_aib81[18], iopad_unused_aib80[18], + iopad_unused_aib79[18], iopad_unused_aib78[18], iopad_unused_aib77[18], iopad_unused_aib76[18], + iopad_unused_aib75[18], iopad_unused_aib74[18], iopad_unused_aib73[18], iopad_unused_aib72[18], + iopad_unused_aib71[18], iopad_unused_aib70[18], iopad_unused_aib69[18], iopad_unused_aib68[18], + iopad_unused_aib67[18], iopad_unused_aib66[18], iopad_fs_adapter_rstn[18], iopad_unused_aib64[18], + iopad_unused_aib63[18], iopad_unused_aib62[18], iopad_unused_aib61[18], iopad_unused_aib60[18], + iopad_fs_rcv_clkb[18], iopad_unused_aib58[18], iopad_fs_rcv_clk[18], iopad_ns_adapter_rstn[18], + iopad_ns_rcv_div2_clkb[18], iopad_ns_fwd_div2_clkb[18], iopad_ns_fwd_div2_clk[18], iopad_unused_aib52[18], + iopad_unused_aib51[18], iopad_unused_aib50[18], iopad_fs_mac_rdy[18], iopad_ns_rcv_div2_clk[18], + iopad_unused_aib47[18], iopad_unused_aib46[18], iopad_unused_aib45[18], iopad_fs_mac_rdy[18], + iopad_fs_fwd_clk[18], iopad_fs_fwd_clkb[18], iopad_ns_fwd_clk[18], iopad_ns_fwd_clkb[18], iopad_rx[379:360], iopad_tx[379:360]}), - - .io_aib_ch19 ({ iopad_ns_sr_data[19], iopad_ns_sr_load[19], iopad_fs_sr_data[19], iopad_fs_sr_load[19], - iopad_unused_aib91[19], iopad_unused_aib90[19], LO, LO, - iopad_ns_rcv_clk[19], iopad_ns_rcv_clkb[19], iopad_ns_sr_clkb[19], iopad_ns_sr_clk[19], - iopad_fs_sr_clk[19], iopad_fs_sr_clkb[19], LO, LO, - LO, LO, iopad_unused_aib77[19], iopad_unused_aib76[19], - iopad_unused_aib75[19], LO, LO, LO, - iopad_unused_aib71[19], iopad_unused_aib70[19], iopad_unused_aib69[19], iopad_unused_aib68[19], - LO, iopad_unused_aib66[19], iopad_fs_adapt_rstn[19], LO, - LO, iopad_unused_aib62[19], HI, iopad_unused_aib60[19], - iopad_fs_rcv_clkb[19], LO, iopad_fs_rcv_clk[19], iopad_ns_adapt_rstn[19], - iopad_ns_rcv_div2_clkb[19], iopad_ns_fwd_div2_clkb[19], iopad_ns_fwd_div2_clk[19], iopad_unused_aib52[19], - iopad_unused_aib51[19], iopad_unused_aib50[19], iopad_fs_mac_rdy[19], iopad_ns_rcv_div2_clk[19], - iopad_unused_aib47[19], iopad_unused_aib46[19], HI, iopad_fs_mac_rdy[19], - iopad_fs_fwd_clk[19], iopad_fs_fwd_clkb[19], iopad_ns_fwd_clk[19], iopad_ns_fwd_clkb[19], + .io_aib_ch19 ({ iopad_ns_sr_data[19], iopad_ns_sr_load[19], iopad_fs_sr_data[19], iopad_fs_sr_load[19], + iopad_unused_aib91[19], iopad_unused_aib90[19], iopad_unused_aib89[19], iopad_unused_aib88[19], + iopad_ns_rcv_clk[19], iopad_ns_rcv_clkb[19], iopad_ns_sr_clkb[19], iopad_ns_sr_clk[19], + iopad_fs_sr_clk[19], iopad_fs_sr_clkb[19], iopad_unused_aib81[19], iopad_unused_aib80[19], + iopad_unused_aib79[19], iopad_unused_aib78[19], iopad_unused_aib77[19], iopad_unused_aib76[19], + iopad_unused_aib75[19], iopad_unused_aib74[19], iopad_unused_aib73[19], iopad_unused_aib72[19], + iopad_unused_aib71[19], iopad_unused_aib70[19], iopad_unused_aib69[19], iopad_unused_aib68[19], + iopad_unused_aib67[19], iopad_unused_aib66[19], iopad_fs_adapter_rstn[19], iopad_unused_aib64[19], + iopad_unused_aib63[19], iopad_unused_aib62[19], iopad_unused_aib61[19], iopad_unused_aib60[19], + iopad_fs_rcv_clkb[19], iopad_unused_aib58[19], iopad_fs_rcv_clk[19], iopad_ns_adapter_rstn[19], + iopad_ns_rcv_div2_clkb[19], iopad_ns_fwd_div2_clkb[19], iopad_ns_fwd_div2_clk[19], iopad_unused_aib52[19], + iopad_unused_aib51[19], iopad_unused_aib50[19], iopad_fs_mac_rdy[19], iopad_ns_rcv_div2_clk[19], + iopad_unused_aib47[19], iopad_unused_aib46[19], iopad_unused_aib45[19], iopad_fs_mac_rdy[19], + iopad_fs_fwd_clk[19], iopad_fs_fwd_clkb[19], iopad_ns_fwd_clk[19], iopad_ns_fwd_clkb[19], iopad_rx[399:380], iopad_tx[399:380]}), - .io_aib_ch20 ({ iopad_ns_sr_data[20], iopad_ns_sr_load[20], iopad_fs_sr_data[20], iopad_fs_sr_load[20], - iopad_unused_aib91[20], iopad_unused_aib90[20], LO, LO, - iopad_ns_rcv_clk[20], iopad_ns_rcv_clkb[20], iopad_ns_sr_clkb[20], iopad_ns_sr_clk[20], - iopad_fs_sr_clk[20], iopad_fs_sr_clkb[20], LO, LO, - LO, LO, iopad_unused_aib77[20], iopad_unused_aib76[20], - iopad_unused_aib75[20], LO, LO, LO, - iopad_unused_aib71[20], iopad_unused_aib70[20], iopad_unused_aib69[20], iopad_unused_aib68[20], - LO, iopad_unused_aib66[20], iopad_fs_adapt_rstn[20], LO, - LO, iopad_unused_aib62[20], HI, iopad_unused_aib60[20], - iopad_fs_rcv_clkb[20], LO, iopad_fs_rcv_clk[20], iopad_ns_adapt_rstn[20], - iopad_ns_rcv_div2_clkb[20], iopad_ns_fwd_div2_clkb[20], iopad_ns_fwd_div2_clk[20], iopad_unused_aib52[20], - iopad_unused_aib51[20], iopad_unused_aib50[20], iopad_fs_mac_rdy[20], iopad_ns_rcv_div2_clk[20], - iopad_unused_aib47[20], iopad_unused_aib46[20], HI, iopad_fs_mac_rdy[20], - iopad_fs_fwd_clk[20], iopad_fs_fwd_clkb[20], iopad_ns_fwd_clk[20], iopad_ns_fwd_clkb[20], + .io_aib_ch20 ({ iopad_ns_sr_data[20], iopad_ns_sr_load[20], iopad_fs_sr_data[20], iopad_fs_sr_load[20], + iopad_unused_aib91[20], iopad_unused_aib90[20], iopad_unused_aib89[20], iopad_unused_aib88[20], + iopad_ns_rcv_clk[20], iopad_ns_rcv_clkb[20], iopad_ns_sr_clkb[20], iopad_ns_sr_clk[20], + iopad_fs_sr_clk[20], iopad_fs_sr_clkb[20], iopad_unused_aib81[20], iopad_unused_aib80[20], + iopad_unused_aib79[20], iopad_unused_aib78[20], iopad_unused_aib77[20], iopad_unused_aib76[20], + iopad_unused_aib75[20], iopad_unused_aib74[20], iopad_unused_aib73[20], iopad_unused_aib72[20], + iopad_unused_aib71[20], iopad_unused_aib70[20], iopad_unused_aib69[20], iopad_unused_aib68[20], + iopad_unused_aib67[20], iopad_unused_aib66[20], iopad_fs_adapter_rstn[20], iopad_unused_aib64[20], + iopad_unused_aib63[20], iopad_unused_aib62[20], iopad_unused_aib61[20], iopad_unused_aib60[20], + iopad_fs_rcv_clkb[20], iopad_unused_aib58[20], iopad_fs_rcv_clk[20], iopad_ns_adapter_rstn[20], + iopad_ns_rcv_div2_clkb[20], iopad_ns_fwd_div2_clkb[20], iopad_ns_fwd_div2_clk[20], iopad_unused_aib52[20], + iopad_unused_aib51[20], iopad_unused_aib50[20], iopad_fs_mac_rdy[20], iopad_ns_rcv_div2_clk[20], + iopad_unused_aib47[20], iopad_unused_aib46[20], iopad_unused_aib45[20], iopad_fs_mac_rdy[20], + iopad_fs_fwd_clk[20], iopad_fs_fwd_clkb[20], iopad_ns_fwd_clk[20], iopad_ns_fwd_clkb[20], iopad_rx[419:400], iopad_tx[419:400]}), - - .io_aib_ch21 ({ iopad_ns_sr_data[21], iopad_ns_sr_load[21], iopad_fs_sr_data[21], iopad_fs_sr_load[21], - iopad_unused_aib91[21], iopad_unused_aib90[21], LO, LO, - iopad_ns_rcv_clk[21], iopad_ns_rcv_clkb[21], iopad_ns_sr_clkb[21], iopad_ns_sr_clk[21], - iopad_fs_sr_clk[21], iopad_fs_sr_clkb[21], LO, LO, - LO, LO, iopad_unused_aib77[21], iopad_unused_aib76[21], - iopad_unused_aib75[21], LO, LO, LO, - iopad_unused_aib71[21], iopad_unused_aib70[21], iopad_unused_aib69[21], iopad_unused_aib68[21], - LO, iopad_unused_aib66[21], iopad_fs_adapt_rstn[21], LO, - LO, iopad_unused_aib62[21], HI, iopad_unused_aib60[21], - iopad_fs_rcv_clkb[21], LO, iopad_fs_rcv_clk[21], iopad_ns_adapt_rstn[21], - iopad_ns_rcv_div2_clkb[21], iopad_ns_fwd_div2_clkb[21], iopad_ns_fwd_div2_clk[21], iopad_unused_aib52[21], - iopad_unused_aib51[21], iopad_unused_aib50[21], iopad_fs_mac_rdy[21], iopad_ns_rcv_div2_clk[21], - iopad_unused_aib47[21], iopad_unused_aib46[21], HI, iopad_fs_mac_rdy[21], - iopad_fs_fwd_clk[21], iopad_fs_fwd_clkb[21], iopad_ns_fwd_clk[21], iopad_ns_fwd_clkb[21], + .io_aib_ch21 ({ iopad_ns_sr_data[21], iopad_ns_sr_load[21], iopad_fs_sr_data[21], iopad_fs_sr_load[21], + iopad_unused_aib91[21], iopad_unused_aib90[21], iopad_unused_aib89[21], iopad_unused_aib88[21], + iopad_ns_rcv_clk[21], iopad_ns_rcv_clkb[21], iopad_ns_sr_clkb[21], iopad_ns_sr_clk[21], + iopad_fs_sr_clk[21], iopad_fs_sr_clkb[21], iopad_unused_aib81[21], iopad_unused_aib80[21], + iopad_unused_aib79[21], iopad_unused_aib78[21], iopad_unused_aib77[21], iopad_unused_aib76[21], + iopad_unused_aib75[21], iopad_unused_aib74[21], iopad_unused_aib73[21], iopad_unused_aib72[21], + iopad_unused_aib71[21], iopad_unused_aib70[21], iopad_unused_aib69[21], iopad_unused_aib68[21], + iopad_unused_aib67[21], iopad_unused_aib66[21], iopad_fs_adapter_rstn[21], iopad_unused_aib64[21], + iopad_unused_aib63[21], iopad_unused_aib62[21], iopad_unused_aib61[21], iopad_unused_aib60[21], + iopad_fs_rcv_clkb[21], iopad_unused_aib58[21], iopad_fs_rcv_clk[21], iopad_ns_adapter_rstn[21], + iopad_ns_rcv_div2_clkb[21], iopad_ns_fwd_div2_clkb[21], iopad_ns_fwd_div2_clk[21], iopad_unused_aib52[21], + iopad_unused_aib51[21], iopad_unused_aib50[21], iopad_fs_mac_rdy[21], iopad_ns_rcv_div2_clk[21], + iopad_unused_aib47[21], iopad_unused_aib46[21], iopad_unused_aib45[21], iopad_fs_mac_rdy[21], + iopad_fs_fwd_clk[21], iopad_fs_fwd_clkb[21], iopad_ns_fwd_clk[21], iopad_ns_fwd_clkb[21], iopad_rx[439:420], iopad_tx[439:420]}), - - .io_aib_ch22 ({ iopad_ns_sr_data[22], iopad_ns_sr_load[22], iopad_fs_sr_data[22], iopad_fs_sr_load[22], - iopad_unused_aib91[22], iopad_unused_aib90[22], LO, LO, - iopad_ns_rcv_clk[22], iopad_ns_rcv_clkb[22], iopad_ns_sr_clkb[22], iopad_ns_sr_clk[22], - iopad_fs_sr_clk[22], iopad_fs_sr_clkb[22], LO, LO, - LO, LO, iopad_unused_aib77[22], iopad_unused_aib76[22], - iopad_unused_aib75[22], LO, LO, LO, - iopad_unused_aib71[22], iopad_unused_aib70[22], iopad_unused_aib69[22], iopad_unused_aib68[22], - LO, iopad_unused_aib66[22], iopad_fs_adapt_rstn[22], LO, - LO, iopad_unused_aib62[22], HI, iopad_unused_aib60[22], - iopad_fs_rcv_clkb[22], LO, iopad_fs_rcv_clk[22], iopad_ns_adapt_rstn[22], - iopad_ns_rcv_div2_clkb[22], iopad_ns_fwd_div2_clkb[22], iopad_ns_fwd_div2_clk[22], iopad_unused_aib52[22], - iopad_unused_aib51[22], iopad_unused_aib50[22], iopad_fs_mac_rdy[22], iopad_ns_rcv_div2_clk[22], - iopad_unused_aib47[22], iopad_unused_aib46[22], HI, iopad_fs_mac_rdy[22], - iopad_fs_fwd_clk[22], iopad_fs_fwd_clkb[22], iopad_ns_fwd_clk[22], iopad_ns_fwd_clkb[22], + .io_aib_ch22 ({ iopad_ns_sr_data[22], iopad_ns_sr_load[22], iopad_fs_sr_data[22], iopad_fs_sr_load[22], + iopad_unused_aib91[22], iopad_unused_aib90[22], iopad_unused_aib89[22], iopad_unused_aib88[22], + iopad_ns_rcv_clk[22], iopad_ns_rcv_clkb[22], iopad_ns_sr_clkb[22], iopad_ns_sr_clk[22], + iopad_fs_sr_clk[22], iopad_fs_sr_clkb[22], iopad_unused_aib81[22], iopad_unused_aib80[22], + iopad_unused_aib79[22], iopad_unused_aib78[22], iopad_unused_aib77[22], iopad_unused_aib76[22], + iopad_unused_aib75[22], iopad_unused_aib74[22], iopad_unused_aib73[22], iopad_unused_aib72[22], + iopad_unused_aib71[22], iopad_unused_aib70[22], iopad_unused_aib69[22], iopad_unused_aib68[22], + iopad_unused_aib67[22], iopad_unused_aib66[22], iopad_fs_adapter_rstn[22], iopad_unused_aib64[22], + iopad_unused_aib63[22], iopad_unused_aib62[22], iopad_unused_aib61[22], iopad_unused_aib60[22], + iopad_fs_rcv_clkb[22], iopad_unused_aib58[22], iopad_fs_rcv_clk[22], iopad_ns_adapter_rstn[22], + iopad_ns_rcv_div2_clkb[22], iopad_ns_fwd_div2_clkb[22], iopad_ns_fwd_div2_clk[22], iopad_unused_aib52[22], + iopad_unused_aib51[22], iopad_unused_aib50[22], iopad_fs_mac_rdy[22], iopad_ns_rcv_div2_clk[22], + iopad_unused_aib47[22], iopad_unused_aib46[22], iopad_unused_aib45[22], iopad_fs_mac_rdy[22], + iopad_fs_fwd_clk[22], iopad_fs_fwd_clkb[22], iopad_ns_fwd_clk[22], iopad_ns_fwd_clkb[22], iopad_rx[459:440], iopad_tx[459:440]}), - .io_aib_ch23 ({ iopad_ns_sr_data[23], iopad_ns_sr_load[23], iopad_fs_sr_data[23], iopad_fs_sr_load[23], - iopad_unused_aib91[23], iopad_unused_aib90[23], LO, LO, - iopad_ns_rcv_clk[23], iopad_ns_rcv_clkb[23], iopad_ns_sr_clkb[23], iopad_ns_sr_clk[23], - iopad_fs_sr_clk[23], iopad_fs_sr_clkb[23], LO, LO, - LO, LO, iopad_unused_aib77[23], iopad_unused_aib76[23], - iopad_unused_aib75[23], LO, LO, LO, - iopad_unused_aib71[23], iopad_unused_aib70[23], iopad_unused_aib69[23], iopad_unused_aib68[23], - LO, iopad_unused_aib66[23], iopad_fs_adapt_rstn[23], LO, - LO, iopad_unused_aib62[23], HI, iopad_unused_aib60[23], - iopad_fs_rcv_clkb[23], LO, iopad_fs_rcv_clk[23], iopad_ns_adapt_rstn[23], - iopad_ns_rcv_div2_clkb[23], iopad_ns_fwd_div2_clkb[23], iopad_ns_fwd_div2_clk[23], iopad_unused_aib52[23], - iopad_unused_aib51[23], iopad_unused_aib50[23], iopad_fs_mac_rdy[23], iopad_ns_rcv_div2_clk[23], - iopad_unused_aib47[23], iopad_unused_aib46[23], HI, iopad_fs_mac_rdy[23], - iopad_fs_fwd_clk[23], iopad_fs_fwd_clkb[23], iopad_ns_fwd_clk[23], iopad_ns_fwd_clkb[23], + .io_aib_ch23 ({ iopad_ns_sr_data[23], iopad_ns_sr_load[23], iopad_fs_sr_data[23], iopad_fs_sr_load[23], + iopad_unused_aib91[23], iopad_unused_aib90[23], iopad_unused_aib89[23], iopad_unused_aib88[23], + iopad_ns_rcv_clk[23], iopad_ns_rcv_clkb[23], iopad_ns_sr_clkb[23], iopad_ns_sr_clk[23], + iopad_fs_sr_clk[23], iopad_fs_sr_clkb[23], iopad_unused_aib81[23], iopad_unused_aib80[23], + iopad_unused_aib79[23], iopad_unused_aib78[23], iopad_unused_aib77[23], iopad_unused_aib76[23], + iopad_unused_aib75[23], iopad_unused_aib74[23], iopad_unused_aib73[23], iopad_unused_aib72[23], + iopad_unused_aib71[23], iopad_unused_aib70[23], iopad_unused_aib69[23], iopad_unused_aib68[23], + iopad_unused_aib67[23], iopad_unused_aib66[23], iopad_fs_adapter_rstn[23], iopad_unused_aib64[23], + iopad_unused_aib63[23], iopad_unused_aib62[23], iopad_unused_aib61[23], iopad_unused_aib60[23], + iopad_fs_rcv_clkb[23], iopad_unused_aib58[23], iopad_fs_rcv_clk[23], iopad_ns_adapter_rstn[23], + iopad_ns_rcv_div2_clkb[23], iopad_ns_fwd_div2_clkb[23], iopad_ns_fwd_div2_clk[23], iopad_unused_aib52[23], + iopad_unused_aib51[23], iopad_unused_aib50[23], iopad_fs_mac_rdy[23], iopad_ns_rcv_div2_clk[23], + iopad_unused_aib47[23], iopad_unused_aib46[23], iopad_unused_aib45[23], iopad_fs_mac_rdy[23], + iopad_fs_fwd_clk[23], iopad_fs_fwd_clkb[23], iopad_ns_fwd_clk[23], iopad_ns_fwd_clkb[23], iopad_rx[479:460], iopad_tx[479:460]}), - .io_aib_aux (io_aib_aux), + .io_aib_aux ({iopad_unused_aux95_88, iopad_power_on_reset_r, iopad_unused_aux86, iopad_power_on_reset, + iopad_unused_aux84_76, iopad_device_detect_r, iopad_device_detect, iopad_unused_aux73_0}), .io_aux_bg_ext_2k (io_aux_bg_ext_2k), .i_iocsr_rdy_aibaux (i_iocsr_rdy_aibaux), .i_aibaux_por_vccl_ovrd (i_aibaux_por_vccl_ovrd), @@ -658,7 +665,7 @@ assign fs_mac_rdy = o_rx_xcvrif_rst_n; .i_aibdft2osc (i_aibdft2osc), .o_aibdft2osc (o_aibdft2osc), .o_last_bs_out (o_last_bs_out), - .o_por (o_por), + .o_por (m_power_on_reset), .o_osc_monitor (o_osc_monitor), .i_aux_atpg_mode_n (i_aux_atpg_mode_n), .i_aux_atpg_pipeline_global_en (i_aux_atpg_pipeline_global_en), diff --git a/aib_lib/c3aibadapt_wrap/rtl/c3aib_master.sv b/aib_lib/c3aibadapt_wrap/rtl/c3aib_master.sv index 3ac4328..244510c 100644 --- a/aib_lib/c3aibadapt_wrap/rtl/c3aib_master.sv +++ b/aib_lib/c3aibadapt_wrap/rtl/c3aib_master.sv @@ -87,10 +87,10 @@ module c3aib_master ( inout iopad_fs_fwd_clk, inout iopad_fs_mac_rdy, inout iopad_ns_mac_rdy, - inout iopad_ns_adapt_rstn, + inout iopad_ns_adapter_rstn, inout iopad_fs_rcv_clk, inout iopad_fs_rcv_clkb, - inout iopad_fs_adapt_rstn, + inout iopad_fs_adapter_rstn, inout iopad_fs_sr_clkb, inout iopad_fs_sr_clk, inout iopad_ns_sr_clk, @@ -103,6 +103,39 @@ module c3aib_master ( inout iopad_fs_sr_data, inout iopad_ns_sr_load, inout iopad_ns_sr_data, + inout iopad_unused_aib45, + inout iopad_unused_aib46, + inout iopad_unused_aib47, + inout iopad_unused_aib50, + inout iopad_unused_aib51, + inout iopad_unused_aib52, + inout iopad_unused_aib58, + inout iopad_unused_aib60, + inout iopad_unused_aib61, + inout iopad_unused_aib62, + inout iopad_unused_aib63, + inout iopad_unused_aib64, + inout iopad_unused_aib66, + inout iopad_unused_aib67, + inout iopad_unused_aib68, + inout iopad_unused_aib69, + inout iopad_unused_aib70, + inout iopad_unused_aib71, + inout iopad_unused_aib72, + inout iopad_unused_aib73, + inout iopad_unused_aib74, + inout iopad_unused_aib75, + inout iopad_unused_aib76, + inout iopad_unused_aib77, + inout iopad_unused_aib78, + inout iopad_unused_aib79, + inout iopad_unused_aib80, + inout iopad_unused_aib81, + inout iopad_unused_aib88, + inout iopad_unused_aib89, + inout iopad_unused_aib90, + inout iopad_unused_aib91, + //================================================================================================ // DFT related interface // DFT CLK All go to c3dfx_aibadaptwrap_tcb. @@ -203,23 +236,6 @@ wire o_tx_transfer_clk; wire o_tx_transfer_div2_clk; wire [39:0] o_tx_pma_data; wire o_rx_xcvrif_rst_n; -wire iopad_unused_aib46; -wire iopad_unused_aib47; -wire iopad_unused_aib50; -wire iopad_unused_aib51; -wire iopad_unused_aib52; -wire iopad_unused_aib60; -wire iopad_unused_aib66; -wire iopad_unused_aib68; -wire iopad_unused_aib69; -wire iopad_unused_aib70; -wire iopad_unused_aib71; -wire iopad_unused_aib75; -wire iopad_unused_aib76; -wire iopad_unused_aib77; -wire iopad_unused_aib84; -wire iopad_unused_aib90; -wire iopad_unused_aib91; wire HI, LO; assign HI = 1'b1; assign LO = 1'b0; @@ -323,8 +339,8 @@ assign fs_mac_rdy = o_rx_xcvrif_rst_n; .io_aib42 (iopad_fs_fwd_clkb), .io_aib43 (iopad_fs_fwd_clk), .io_aib44 (iopad_fs_mac_rdy), - //.io_aib45 (aib45), - .io_aib45 (HI), //From Tim's 3/26 aib_bump_map + .io_aib45 (iopad_unused_aib45), + //.io_aib45 (HI), //From Tim's 3/26 aib_bump_map .io_aib46 (iopad_unused_aib46), .io_aib47 (iopad_unused_aib47), .io_aib48 (iopad_ns_rcv_div2_clk), @@ -336,57 +352,57 @@ assign fs_mac_rdy = o_rx_xcvrif_rst_n; .io_aib53 (iopad_ns_fwd_div2_clk), .io_aib54 (iopad_ns_fwd_div2_clkb), .io_aib55 (iopad_ns_rcv_div2_clkb), - .io_aib56 (iopad_ns_adapt_rstn), + .io_aib56 (iopad_ns_adapter_rstn), .io_aib57 (iopad_fs_rcv_clk), - //.io_aib58 (aib58), - .io_aib58 (LO), //From Tim's 3/26 aib_bump_map + .io_aib58 (iopad_unused_aib58), + //.io_aib58 (LO), //From Tim's 3/26 aib_bump_map .io_aib59 (iopad_fs_rcv_clkb), .io_aib6 (iopad_tx[6]), .io_aib60 (iopad_unused_aib60), - //.io_aib61 (aib61), - .io_aib61 (HI), //From Tim's 3/26 aib_bump_map + .io_aib61 (iopad_unused_aib61), + //.io_aib61 (HI), //From Tim's 3/26 aib_bump_map .io_aib62 (iopad_unused_aib62), - //.io_aib63 (aib63), - .io_aib63 (LO), //From Tim's 3/26 aib_bump_map - //.io_aib64 (aib64), - .io_aib64 (LO), //From Tim's 3/26 aib_bump_map - .io_aib65 (iopad_fs_adapt_rstn), + .io_aib63 (iopad_unused_aib63), + //.io_aib63 (LO), //From Tim's 3/26 aib_bump_map + .io_aib64 (iopad_unused_aib64), + //.io_aib64 (LO), //From Tim's 3/26 aib_bump_map + .io_aib65 (iopad_fs_adapter_rstn), .io_aib66 (iopad_unused_aib66), - //.io_aib67 (aib67), - .io_aib67 (LO), //From Tim's 3/26 aib_bump_map + .io_aib67 (iopad_unused_aib67), + //.io_aib67 (LO), //From Tim's 3/26 aib_bump_map .io_aib68 (iopad_unused_aib68), .io_aib69 (iopad_unused_aib69), .io_aib7 (iopad_tx[7]), .io_aib70 (iopad_unused_aib70), .io_aib71 (iopad_unused_aib71), - //.io_aib72 (aib72), - //.io_aib73 (aib73), - //.io_aib74 (aib74), - .io_aib72 (LO), //From Tim's 3/26 aib_bump_map - .io_aib73 (LO), //From Tim's 3/26 aib_bump_map - .io_aib74 (LO), //From Tim's 3/26 aib_bump_map + .io_aib72 (iopad_unused_aib72), + .io_aib73 (iopad_unused_aib73), + .io_aib74 (iopad_unused_aib74), + //.io_aib72 (LO), //From Tim's 3/26 aib_bump_map + //.io_aib73 (LO), //From Tim's 3/26 aib_bump_map + //.io_aib74 (LO), //From Tim's 3/26 aib_bump_map .io_aib75 (iopad_unused_aib75), .io_aib76 (iopad_unused_aib76), .io_aib77 (iopad_unused_aib77), - //.io_aib78 (aib78), - //.io_aib79 (aib79), - //.io_aib80 (aib80), - //.io_aib81 (aib81), - .io_aib78 (LO), //From Tim's 3/26 aib_bump_map - .io_aib79 (LO), //From Tim's 3/26 aib_bump_map + .io_aib78 (iopad_unused_aib78), + .io_aib79 (iopad_unused_aib79), + .io_aib80 (iopad_unused_aib80), + .io_aib81 (iopad_unused_aib81), + //.io_aib78 (LO), //From Tim's 3/26 aib_bump_map + //.io_aib79 (LO), //From Tim's 3/26 aib_bump_map .io_aib8 (iopad_tx[8]), - .io_aib80 (LO), //From Tim's 3/26 aib_bump_map - .io_aib81 (LO), //From Tim's 3/26 aib_bump_map + //.io_aib80 (LO), //From Tim's 3/26 aib_bump_map + //.io_aib81 (LO), //From Tim's 3/26 aib_bump_map .io_aib82 (iopad_fs_sr_clkb), .io_aib83 (iopad_fs_sr_clk), .io_aib84 (iopad_ns_sr_clk), .io_aib85 (iopad_ns_sr_clkb), .io_aib86 (iopad_ns_rcv_clkb), .io_aib87 (iopad_ns_rcv_clk), - //.io_aib88 (aib88), - //.io_aib89 (aib89), - .io_aib88 (LO), //From Tim's 3/26 aib_bump_map - .io_aib89 (LO), //From Tim's 3/26 aib_bump_map + .io_aib88 (iopad_unused_aib88), + .io_aib89 (iopad_unused_aib89), + //.io_aib88 (LO), //From Tim's 3/26 aib_bump_map + //.io_aib89 (LO), //From Tim's 3/26 aib_bump_map .io_aib9 (iopad_tx[9]), .io_aib90 (iopad_unused_aib90), .io_aib91 (iopad_unused_aib91), diff --git a/docs/AIB_Intel_Specification 1_1.pdf b/docs/AIB_Intel_Specification 1_1.pdf index 83d8f3c..3f27280 100644 Binary files a/docs/AIB_Intel_Specification 1_1.pdf and b/docs/AIB_Intel_Specification 1_1.pdf differ diff --git a/docs/Stratix 10 Chiplet AIB Profile_v1_0.pdf b/docs/Stratix 10 Chiplet AIB Profile_v1_0.pdf index 7dac05c..55a4066 100644 Binary files a/docs/Stratix 10 Chiplet AIB Profile_v1_0.pdf and b/docs/Stratix 10 Chiplet AIB Profile_v1_0.pdf differ diff --git a/docs/USERGUIDE.txt b/docs/USERGUIDE.txt index 22d87a6..ca4ccbf 100644 --- a/docs/USERGUIDE.txt +++ b/docs/USERGUIDE.txt @@ -73,9 +73,9 @@ inout iopad_por_copy, input [39:0] data_in, //output data to pad output [39:0] data_out, //input data from pad input m_ns_fwd_clk, //near side forward clock from MAC -output m_fs_rvc_clk, //far side receive clcok to MAC +output m_fs_rcv_clk, //far side receive clcok to MAC output m_fs_fwd_clk, //far side forward clock to MAC -input m_ns_rvc_clk, //near side receive clock from MAC +input m_ns_rcv_clk, //near side receive clock from MAC input ms_ns_adapter_rstn, //master adapter reset from MAC input sl_ns_adapter_rstn, //slave adapter reset from MAC diff --git a/how2use/README.txt b/how2use/README.txt index 46e4aaf..d1b591b 100644 --- a/how2use/README.txt +++ b/how2use/README.txt @@ -58,4 +58,8 @@ sim_mod2mod: This test show how master model works with slave model. How to run: 1) cd sim_mod2mod 2) ./runsim -3) ./simv \ No newline at end of file +3) ./simv + +sim_sl2ms_lpbk: This test shows how open source IP connect to Stratix 10 MAIB channel in loopback test. +VCS/Cadence/Modelsim simulators run scripts are provided. See README.txt for detail. + diff --git a/how2use/sim_aib_top/top.sv b/how2use/sim_aib_top/top.sv index 4ebd7c0..cc2c887 100644 --- a/how2use/sim_aib_top/top.sv +++ b/how2use/sim_aib_top/top.sv @@ -148,7 +148,15 @@ module top; wire o_txen_out_chain2; // From dut of c3aibadapt_wrap.v wire [81*24-1:0] ms_sideband; wire [73*24-1:0] sl_sideband; - wire [95:0] AIB_AUX; + wire [7:0] iopad_unused_aux95_88; + wire iopad_power_on_reset_r; //iopad_aib_aux[87] power on redundency from slave + wire iopad_unused_aux86; + wire iopad_power_on_reset; //iopad_aib_aux[85] power on from slave. + wire [8:0] iopad_unused_aux84_76; + wire iopad_device_detect_r; //iopad_aib_aux[75] device detect redundency to slave + wire iopad_device_detect; //iopad_aib_aux[74] device detect to slave + wire [73:0] iopad_unused_aux73_0; + wire [24*20-1:0] iopad_tx; wire [24*20-1:0] iopad_rx; wire [23:0] iopad_ns_fwd_clkb; @@ -157,10 +165,10 @@ module top; wire [23:0] iopad_fs_fwd_clk; wire [23:0] iopad_fs_mac_rdy; wire [23:0] iopad_ns_mac_rdy; - wire [23:0] iopad_ns_adapt_rstn; + wire [23:0] iopad_ns_adapter_rstn; wire [23:0] iopad_fs_rcv_clk; wire [23:0] iopad_fs_rcv_clkb; - wire [23:0] iopad_fs_adapt_rstn; + wire [23:0] iopad_fs_adapter_rstn; wire [23:0] iopad_fs_sr_clkb; wire [23:0] iopad_fs_sr_clk; wire [23:0] iopad_ns_sr_clk; @@ -180,7 +188,7 @@ module top; The following pins are tied to high so that the loopback test will work: iopad_fs_sr_data - iopad_fs_adapt_rstn + iopad_fs_adapter_rstn */////////////////////////////////////////////////////////////////////////// //----------------------------------------------------------------------------------------- @@ -230,10 +238,10 @@ module top; .iopad_fs_fwd_clk (iopad_ns_fwd_clk), .iopad_fs_mac_rdy (iopad_ns_mac_rdy), .iopad_ns_mac_rdy (iopad_ns_mac_rdy), - .iopad_ns_adapt_rstn (iopad_ns_adapt_rstn), + .iopad_ns_adapter_rstn (iopad_ns_adapter_rstn), .iopad_fs_rcv_clk (iopad_ns_fwd_clk), .iopad_fs_rcv_clkb (iopad_ns_fwd_clkb), - .iopad_fs_adapt_rstn (HI24), + .iopad_fs_adapter_rstn (HI24), .iopad_fs_sr_clkb (iopad_ns_sr_clkb), .iopad_fs_sr_clk (iopad_ns_sr_clk), .iopad_ns_sr_clk (iopad_ns_sr_clk), @@ -244,8 +252,15 @@ module top; .iopad_fs_sr_data (HI24), .iopad_ns_sr_load (iopad_ns_sr_load), .iopad_ns_sr_data (iopad_ns_sr_data), - .io_aib_aux (AIB_AUX), -// .io_aib_aux (), + // .io_aib_aux (AIB_AUX), + .iopad_unused_aux95_88 (iopad_unused_aux95_88), + .iopad_power_on_reset_r (iopad_power_on_reset_r), + .iopad_unused_aux86 (iopad_unused_aux86), + .iopad_power_on_reset (iopad_power_on_reset), + .iopad_unused_aux84_76 (iopad_unused_aux84_76), + .iopad_device_detect_r (iopad_device_detect_r), + .iopad_device_detect (iopad_device_detect), + .iopad_unused_aux73_0 (iopad_unused_aux73_0), .io_aux_bg_ext_2k (io_aux_bg_ext_2k), .i_iocsr_rdy_aibaux (top_io.i_adpt_hard_rst_n), .i_aibaux_por_vccl_ovrd (1'b1), @@ -280,7 +295,7 @@ module top; .i_aibdft2osc ({1'b0, 1'b1, i_rx_pma_div2_clk}), .o_aibdft2osc (), .o_last_bs_out (), - .o_por (), + .m_power_on_reset (), .o_osc_monitor (), .i_aux_atpg_mode_n (1'b1), //FIXME .i_aux_atpg_pipeline_global_en (1'b0), //FIXME diff --git a/how2use/sim_aib_top_ncsim/top.sv b/how2use/sim_aib_top_ncsim/top.sv index 4ebd7c0..cc2c887 100644 --- a/how2use/sim_aib_top_ncsim/top.sv +++ b/how2use/sim_aib_top_ncsim/top.sv @@ -148,7 +148,15 @@ module top; wire o_txen_out_chain2; // From dut of c3aibadapt_wrap.v wire [81*24-1:0] ms_sideband; wire [73*24-1:0] sl_sideband; - wire [95:0] AIB_AUX; + wire [7:0] iopad_unused_aux95_88; + wire iopad_power_on_reset_r; //iopad_aib_aux[87] power on redundency from slave + wire iopad_unused_aux86; + wire iopad_power_on_reset; //iopad_aib_aux[85] power on from slave. + wire [8:0] iopad_unused_aux84_76; + wire iopad_device_detect_r; //iopad_aib_aux[75] device detect redundency to slave + wire iopad_device_detect; //iopad_aib_aux[74] device detect to slave + wire [73:0] iopad_unused_aux73_0; + wire [24*20-1:0] iopad_tx; wire [24*20-1:0] iopad_rx; wire [23:0] iopad_ns_fwd_clkb; @@ -157,10 +165,10 @@ module top; wire [23:0] iopad_fs_fwd_clk; wire [23:0] iopad_fs_mac_rdy; wire [23:0] iopad_ns_mac_rdy; - wire [23:0] iopad_ns_adapt_rstn; + wire [23:0] iopad_ns_adapter_rstn; wire [23:0] iopad_fs_rcv_clk; wire [23:0] iopad_fs_rcv_clkb; - wire [23:0] iopad_fs_adapt_rstn; + wire [23:0] iopad_fs_adapter_rstn; wire [23:0] iopad_fs_sr_clkb; wire [23:0] iopad_fs_sr_clk; wire [23:0] iopad_ns_sr_clk; @@ -180,7 +188,7 @@ module top; The following pins are tied to high so that the loopback test will work: iopad_fs_sr_data - iopad_fs_adapt_rstn + iopad_fs_adapter_rstn */////////////////////////////////////////////////////////////////////////// //----------------------------------------------------------------------------------------- @@ -230,10 +238,10 @@ module top; .iopad_fs_fwd_clk (iopad_ns_fwd_clk), .iopad_fs_mac_rdy (iopad_ns_mac_rdy), .iopad_ns_mac_rdy (iopad_ns_mac_rdy), - .iopad_ns_adapt_rstn (iopad_ns_adapt_rstn), + .iopad_ns_adapter_rstn (iopad_ns_adapter_rstn), .iopad_fs_rcv_clk (iopad_ns_fwd_clk), .iopad_fs_rcv_clkb (iopad_ns_fwd_clkb), - .iopad_fs_adapt_rstn (HI24), + .iopad_fs_adapter_rstn (HI24), .iopad_fs_sr_clkb (iopad_ns_sr_clkb), .iopad_fs_sr_clk (iopad_ns_sr_clk), .iopad_ns_sr_clk (iopad_ns_sr_clk), @@ -244,8 +252,15 @@ module top; .iopad_fs_sr_data (HI24), .iopad_ns_sr_load (iopad_ns_sr_load), .iopad_ns_sr_data (iopad_ns_sr_data), - .io_aib_aux (AIB_AUX), -// .io_aib_aux (), + // .io_aib_aux (AIB_AUX), + .iopad_unused_aux95_88 (iopad_unused_aux95_88), + .iopad_power_on_reset_r (iopad_power_on_reset_r), + .iopad_unused_aux86 (iopad_unused_aux86), + .iopad_power_on_reset (iopad_power_on_reset), + .iopad_unused_aux84_76 (iopad_unused_aux84_76), + .iopad_device_detect_r (iopad_device_detect_r), + .iopad_device_detect (iopad_device_detect), + .iopad_unused_aux73_0 (iopad_unused_aux73_0), .io_aux_bg_ext_2k (io_aux_bg_ext_2k), .i_iocsr_rdy_aibaux (top_io.i_adpt_hard_rst_n), .i_aibaux_por_vccl_ovrd (1'b1), @@ -280,7 +295,7 @@ module top; .i_aibdft2osc ({1'b0, 1'b1, i_rx_pma_div2_clk}), .o_aibdft2osc (), .o_last_bs_out (), - .o_por (), + .m_power_on_reset (), .o_osc_monitor (), .i_aux_atpg_mode_n (1'b1), //FIXME .i_aux_atpg_pipeline_global_en (1'b0), //FIXME diff --git a/how2use/sim_dcc/c3aib_master.sv b/how2use/sim_dcc/c3aib_master.sv index c07ed6a..c6d0486 100644 --- a/how2use/sim_dcc/c3aib_master.sv +++ b/how2use/sim_dcc/c3aib_master.sv @@ -1,5 +1,6 @@ // SPDX-License-Identifier: Apache-2.0 // Copyright (C) 2019 Intel Corporation. All rights reserved +// Mapping file to map single channel opensource IP IO ports to AIB specification 1.1 `timescale 1ps/1fs @@ -84,24 +85,61 @@ module c3aib_master ( inout [19:0] iopad_rx, inout iopad_ns_fwd_clkb, inout iopad_ns_fwd_clk, + inout iopad_ns_fwd_div2_clkb, + inout iopad_ns_fwd_div2_clk, inout iopad_fs_fwd_clkb, inout iopad_fs_fwd_clk, inout iopad_fs_mac_rdy, inout iopad_ns_mac_rdy, - inout iopad_ns_adapt_rstn, + inout iopad_ns_adapter_rstn, inout iopad_fs_rcv_clk, inout iopad_fs_rcv_clkb, - inout iopad_fs_adapt_rstn, + inout iopad_fs_adapter_rstn, inout iopad_fs_sr_clkb, inout iopad_fs_sr_clk, inout iopad_ns_sr_clk, inout iopad_ns_sr_clkb, inout iopad_ns_rcv_clkb, inout iopad_ns_rcv_clk, + inout iopad_ns_rcv_div2_clkb, + inout iopad_ns_rcv_div2_clk, inout iopad_fs_sr_load, inout iopad_fs_sr_data, inout iopad_ns_sr_load, inout iopad_ns_sr_data, + inout iopad_unused_aib45, + inout iopad_unused_aib46, + inout iopad_unused_aib47, + inout iopad_unused_aib50, + inout iopad_unused_aib51, + inout iopad_unused_aib52, + inout iopad_unused_aib58, + inout iopad_unused_aib60, + inout iopad_unused_aib61, + inout iopad_unused_aib62, + inout iopad_unused_aib63, + inout iopad_unused_aib64, + inout iopad_unused_aib66, + inout iopad_unused_aib67, + inout iopad_unused_aib68, + inout iopad_unused_aib69, + inout iopad_unused_aib70, + inout iopad_unused_aib71, + inout iopad_unused_aib72, + inout iopad_unused_aib73, + inout iopad_unused_aib74, + inout iopad_unused_aib75, + inout iopad_unused_aib76, + inout iopad_unused_aib77, + inout iopad_unused_aib78, + inout iopad_unused_aib79, + inout iopad_unused_aib80, + inout iopad_unused_aib81, + inout iopad_unused_aib88, + inout iopad_unused_aib89, + inout iopad_unused_aib90, + inout iopad_unused_aib91, + //================================================================================================ // DFT related interface // DFT CLK All go to c3dfx_aibadaptwrap_tcb. @@ -202,28 +240,6 @@ wire o_tx_transfer_clk; wire o_tx_transfer_div2_clk; wire [77:0] o_tx_elane_data; wire o_rx_xcvrif_rst_n; -wire iopad_unused_aib46; -wire iopad_unused_aib47; -wire iopad_unused_aib48; -wire iopad_unused_aib49; -wire iopad_unused_aib50; -wire iopad_unused_aib51; -wire iopad_unused_aib52; -wire iopad_unused_aib53; -wire iopad_unused_aib54; -wire iopad_unused_aib55; -wire iopad_unused_aib60; -wire iopad_unused_aib66; -wire iopad_unused_aib68; -wire iopad_unused_aib69; -wire iopad_unused_aib70; -wire iopad_unused_aib71; -wire iopad_unused_aib75; -wire iopad_unused_aib76; -wire iopad_unused_aib77; -wire iopad_unused_aib84; -wire iopad_unused_aib90; -wire iopad_unused_aib91; wire HI, LO; assign HI = 1'b1; assign LO = 1'b0; @@ -329,70 +345,70 @@ assign fs_mac_rdy = o_rx_xcvrif_rst_n; .io_aib42 (iopad_fs_fwd_clkb), .io_aib43 (iopad_fs_fwd_clk), .io_aib44 (iopad_fs_mac_rdy), - //.io_aib45 (aib45), - .io_aib45 (HI), //From Tim's 3/26 aib_bump_map + .io_aib45 (iopad_unused_aib45), + //.io_aib45 (HI), //From Tim's 3/26 aib_bump_map .io_aib46 (iopad_unused_aib46), .io_aib47 (iopad_unused_aib47), - .io_aib48 (iopad_unused_aib48), + .io_aib48 (iopad_ns_rcv_div2_clk), .io_aib49 (iopad_ns_mac_rdy), .io_aib5 (iopad_tx[5]), .io_aib50 (iopad_unused_aib50), .io_aib51 (iopad_unused_aib51), .io_aib52 (iopad_unused_aib52), - .io_aib53 (iopad_unused_aib53), - .io_aib54 (iopad_unused_aib54), - .io_aib55 (iopad_unused_aib55), - .io_aib56 (iopad_ns_adapt_rstn), + .io_aib53 (iopad_ns_fwd_div2_clk), + .io_aib54 (iopad_ns_fwd_div2_clkb), + .io_aib55 (iopad_ns_rcv_div2_clkb), + .io_aib56 (iopad_ns_adapter_rstn), .io_aib57 (iopad_fs_rcv_clk), - //.io_aib58 (aib58), - .io_aib58 (LO), //From Tim's 3/26 aib_bump_map + .io_aib58 (iopad_unused_aib58), + //.io_aib58 (LO), //From Tim's 3/26 aib_bump_map .io_aib59 (iopad_fs_rcv_clkb), .io_aib6 (iopad_tx[6]), .io_aib60 (iopad_unused_aib60), - //.io_aib61 (aib61), - .io_aib61 (HI), //From Tim's 3/26 aib_bump_map + .io_aib61 (iopad_unused_aib61), + //.io_aib61 (HI), //From Tim's 3/26 aib_bump_map .io_aib62 (iopad_unused_aib62), - //.io_aib63 (aib63), - .io_aib63 (LO), //From Tim's 3/26 aib_bump_map - //.io_aib64 (aib64), - .io_aib64 (LO), //From Tim's 3/26 aib_bump_map - .io_aib65 (iopad_fs_adapt_rstn), + .io_aib63 (iopad_unused_aib63), + //.io_aib63 (LO), //From Tim's 3/26 aib_bump_map + .io_aib64 (iopad_unused_aib64), + //.io_aib64 (LO), //From Tim's 3/26 aib_bump_map + .io_aib65 (iopad_fs_adapter_rstn), .io_aib66 (iopad_unused_aib66), - //.io_aib67 (aib67), - .io_aib67 (LO), //From Tim's 3/26 aib_bump_map + .io_aib67 (iopad_unused_aib67), + //.io_aib67 (LO), //From Tim's 3/26 aib_bump_map .io_aib68 (iopad_unused_aib68), .io_aib69 (iopad_unused_aib69), .io_aib7 (iopad_tx[7]), .io_aib70 (iopad_unused_aib70), .io_aib71 (iopad_unused_aib71), - //.io_aib72 (aib72), - //.io_aib73 (aib73), - //.io_aib74 (aib74), - .io_aib72 (LO), //From Tim's 3/26 aib_bump_map - .io_aib73 (LO), //From Tim's 3/26 aib_bump_map - .io_aib74 (LO), //From Tim's 3/26 aib_bump_map + .io_aib72 (iopad_unused_aib72), + .io_aib73 (iopad_unused_aib73), + .io_aib74 (iopad_unused_aib74), + //.io_aib72 (LO), //From Tim's 3/26 aib_bump_map + //.io_aib73 (LO), //From Tim's 3/26 aib_bump_map + //.io_aib74 (LO), //From Tim's 3/26 aib_bump_map .io_aib75 (iopad_unused_aib75), .io_aib76 (iopad_unused_aib76), .io_aib77 (iopad_unused_aib77), - //.io_aib78 (aib78), - //.io_aib79 (aib79), - //.io_aib80 (aib80), - //.io_aib81 (aib81), - .io_aib78 (LO), //From Tim's 3/26 aib_bump_map - .io_aib79 (LO), //From Tim's 3/26 aib_bump_map + .io_aib78 (iopad_unused_aib78), + .io_aib79 (iopad_unused_aib79), + .io_aib80 (iopad_unused_aib80), + .io_aib81 (iopad_unused_aib81), + //.io_aib78 (LO), //From Tim's 3/26 aib_bump_map + //.io_aib79 (LO), //From Tim's 3/26 aib_bump_map .io_aib8 (iopad_tx[8]), - .io_aib80 (LO), //From Tim's 3/26 aib_bump_map - .io_aib81 (LO), //From Tim's 3/26 aib_bump_map + //.io_aib80 (LO), //From Tim's 3/26 aib_bump_map + //.io_aib81 (LO), //From Tim's 3/26 aib_bump_map .io_aib82 (iopad_fs_sr_clkb), .io_aib83 (iopad_fs_sr_clk), .io_aib84 (iopad_ns_sr_clk), .io_aib85 (iopad_ns_sr_clkb), .io_aib86 (iopad_ns_rcv_clkb), .io_aib87 (iopad_ns_rcv_clk), - //.io_aib88 (aib88), - //.io_aib89 (aib89), - .io_aib88 (LO), //From Tim's 3/26 aib_bump_map - .io_aib89 (LO), //From Tim's 3/26 aib_bump_map + .io_aib88 (iopad_unused_aib88), + .io_aib89 (iopad_unused_aib89), + //.io_aib88 (LO), //From Tim's 3/26 aib_bump_map + //.io_aib89 (LO), //From Tim's 3/26 aib_bump_map .io_aib9 (iopad_tx[9]), .io_aib90 (iopad_unused_aib90), .io_aib91 (iopad_unused_aib91), diff --git a/how2use/sim_dcc/top.sv b/how2use/sim_dcc/top.sv index 21f44ed..638a995 100644 --- a/how2use/sim_dcc/top.sv +++ b/how2use/sim_dcc/top.sv @@ -174,10 +174,10 @@ module top; wire iopad_fs_fwd_clk; wire iopad_fs_mac_rdy; wire iopad_ns_mac_rdy; - wire iopad_ns_adapt_rstn; + wire iopad_ns_adapter_rstn; wire iopad_fs_rcv_clk; wire iopad_fs_rcv_clkb; - wire iopad_fs_adapt_rstn; + wire iopad_fs_adapter_rstn; wire iopad_fs_sr_clkb; wire iopad_fs_sr_clk; wire iopad_ns_sr_clk; @@ -197,7 +197,7 @@ module top; The following pins are tied to high so that the loopback test will work: iopad_fs_sr_data - iopad_fs_adapt_rstn + iopad_fs_adapter_rstn */////////////////////////////////////////////////////////////////////////// //----------------------------------------------------------------------------------------- @@ -281,10 +281,10 @@ module top; .iopad_fs_fwd_clk (iopad_ns_fwd_clk), .iopad_fs_mac_rdy (iopad_ns_mac_rdy), .iopad_ns_mac_rdy (iopad_ns_mac_rdy), - .iopad_ns_adapt_rstn (iopad_ns_adapt_rstn), + .iopad_ns_adapter_rstn (iopad_ns_adapter_rstn), .iopad_fs_rcv_clk (iopad_ns_fwd_clk), .iopad_fs_rcv_clkb (iopad_ns_fwd_clkb), - .iopad_fs_adapt_rstn (1'b1), + .iopad_fs_adapter_rstn (1'b1), .iopad_fs_sr_clkb (iopad_ns_sr_clkb), .iopad_fs_sr_clk (iopad_ns_sr_clk), .iopad_ns_sr_clk (iopad_ns_sr_clk), diff --git a/how2use/sim_mod2mod/tb_top.sv b/how2use/sim_mod2mod/tb_top.sv index a9f39b2..f822372 100644 --- a/how2use/sim_mod2mod/tb_top.sv +++ b/how2use/sim_mod2mod/tb_top.sv @@ -51,13 +51,13 @@ reg ms_device_detect, sl_por; reg [DATAWIDTH*2-1:0] ms_data_in; wire [DATAWIDTH*2-1:0] sl_data_out; wire [DATAWIDTH*2-1:0] ms_data_out; -wire ms_m_ns_fwd_clk, ms_m_ns_rvc_clk; -wire sl_m_ns_fwd_clk, sl_m_ns_rvc_clk; +wire ms_m_ns_fwd_clk, ms_m_ns_rcv_clk; +wire sl_m_ns_fwd_clk, sl_m_ns_rcv_clk; assign ms_m_ns_fwd_clk = clk; -assign ms_m_ns_rvc_clk = clk; +assign ms_m_ns_rcv_clk = clk; assign sl_m_ns_fwd_clk = clk; -assign sl_m_ns_rvc_clk = clk; +assign sl_m_ns_rcv_clk = clk; int err_count; @@ -183,9 +183,9 @@ master .data_in(ms_data_in[DATAWIDTH*2 -1:0]), //output data to pad .data_out(ms_data_out[DATAWIDTH*2 -1:0]), //input data from pad .m_ns_fwd_clk(ms_m_ns_fwd_clk), //output data clock - .m_fs_rvc_clk(), + .m_fs_rcv_clk(), .m_fs_fwd_clk(), - .m_ns_rvc_clk(ms_m_ns_rvc_clk), + .m_ns_rcv_clk(ms_m_ns_rcv_clk), .ms_ns_adapter_rstn(ms_ns_adapter_rstn), .sl_ns_adapter_rstn(sl_ns_adapter_rstn), @@ -280,9 +280,9 @@ slave .data_in(sl_data_out[DATAWIDTH*2-1:0]), //output data to pad .data_out(sl_data_out[DATAWIDTH*2-1:0]), //input data from pad .m_ns_fwd_clk(sl_m_ns_fwd_clk), //output data clock - .m_fs_rvc_clk(), + .m_fs_rcv_clk(), .m_fs_fwd_clk(), - .m_ns_rvc_clk(sl_m_ns_rvc_clk), + .m_ns_rcv_clk(sl_m_ns_rcv_clk), .ms_ns_adapter_rstn(ms_ns_adapter_rstn), .sl_ns_adapter_rstn(sl_ns_adapter_rstn), diff --git a/how2use/sim_phasecom/c3aib_master.sv b/how2use/sim_phasecom/c3aib_master.sv index c07ed6a..c6d0486 100644 --- a/how2use/sim_phasecom/c3aib_master.sv +++ b/how2use/sim_phasecom/c3aib_master.sv @@ -1,5 +1,6 @@ // SPDX-License-Identifier: Apache-2.0 // Copyright (C) 2019 Intel Corporation. All rights reserved +// Mapping file to map single channel opensource IP IO ports to AIB specification 1.1 `timescale 1ps/1fs @@ -84,24 +85,61 @@ module c3aib_master ( inout [19:0] iopad_rx, inout iopad_ns_fwd_clkb, inout iopad_ns_fwd_clk, + inout iopad_ns_fwd_div2_clkb, + inout iopad_ns_fwd_div2_clk, inout iopad_fs_fwd_clkb, inout iopad_fs_fwd_clk, inout iopad_fs_mac_rdy, inout iopad_ns_mac_rdy, - inout iopad_ns_adapt_rstn, + inout iopad_ns_adapter_rstn, inout iopad_fs_rcv_clk, inout iopad_fs_rcv_clkb, - inout iopad_fs_adapt_rstn, + inout iopad_fs_adapter_rstn, inout iopad_fs_sr_clkb, inout iopad_fs_sr_clk, inout iopad_ns_sr_clk, inout iopad_ns_sr_clkb, inout iopad_ns_rcv_clkb, inout iopad_ns_rcv_clk, + inout iopad_ns_rcv_div2_clkb, + inout iopad_ns_rcv_div2_clk, inout iopad_fs_sr_load, inout iopad_fs_sr_data, inout iopad_ns_sr_load, inout iopad_ns_sr_data, + inout iopad_unused_aib45, + inout iopad_unused_aib46, + inout iopad_unused_aib47, + inout iopad_unused_aib50, + inout iopad_unused_aib51, + inout iopad_unused_aib52, + inout iopad_unused_aib58, + inout iopad_unused_aib60, + inout iopad_unused_aib61, + inout iopad_unused_aib62, + inout iopad_unused_aib63, + inout iopad_unused_aib64, + inout iopad_unused_aib66, + inout iopad_unused_aib67, + inout iopad_unused_aib68, + inout iopad_unused_aib69, + inout iopad_unused_aib70, + inout iopad_unused_aib71, + inout iopad_unused_aib72, + inout iopad_unused_aib73, + inout iopad_unused_aib74, + inout iopad_unused_aib75, + inout iopad_unused_aib76, + inout iopad_unused_aib77, + inout iopad_unused_aib78, + inout iopad_unused_aib79, + inout iopad_unused_aib80, + inout iopad_unused_aib81, + inout iopad_unused_aib88, + inout iopad_unused_aib89, + inout iopad_unused_aib90, + inout iopad_unused_aib91, + //================================================================================================ // DFT related interface // DFT CLK All go to c3dfx_aibadaptwrap_tcb. @@ -202,28 +240,6 @@ wire o_tx_transfer_clk; wire o_tx_transfer_div2_clk; wire [77:0] o_tx_elane_data; wire o_rx_xcvrif_rst_n; -wire iopad_unused_aib46; -wire iopad_unused_aib47; -wire iopad_unused_aib48; -wire iopad_unused_aib49; -wire iopad_unused_aib50; -wire iopad_unused_aib51; -wire iopad_unused_aib52; -wire iopad_unused_aib53; -wire iopad_unused_aib54; -wire iopad_unused_aib55; -wire iopad_unused_aib60; -wire iopad_unused_aib66; -wire iopad_unused_aib68; -wire iopad_unused_aib69; -wire iopad_unused_aib70; -wire iopad_unused_aib71; -wire iopad_unused_aib75; -wire iopad_unused_aib76; -wire iopad_unused_aib77; -wire iopad_unused_aib84; -wire iopad_unused_aib90; -wire iopad_unused_aib91; wire HI, LO; assign HI = 1'b1; assign LO = 1'b0; @@ -329,70 +345,70 @@ assign fs_mac_rdy = o_rx_xcvrif_rst_n; .io_aib42 (iopad_fs_fwd_clkb), .io_aib43 (iopad_fs_fwd_clk), .io_aib44 (iopad_fs_mac_rdy), - //.io_aib45 (aib45), - .io_aib45 (HI), //From Tim's 3/26 aib_bump_map + .io_aib45 (iopad_unused_aib45), + //.io_aib45 (HI), //From Tim's 3/26 aib_bump_map .io_aib46 (iopad_unused_aib46), .io_aib47 (iopad_unused_aib47), - .io_aib48 (iopad_unused_aib48), + .io_aib48 (iopad_ns_rcv_div2_clk), .io_aib49 (iopad_ns_mac_rdy), .io_aib5 (iopad_tx[5]), .io_aib50 (iopad_unused_aib50), .io_aib51 (iopad_unused_aib51), .io_aib52 (iopad_unused_aib52), - .io_aib53 (iopad_unused_aib53), - .io_aib54 (iopad_unused_aib54), - .io_aib55 (iopad_unused_aib55), - .io_aib56 (iopad_ns_adapt_rstn), + .io_aib53 (iopad_ns_fwd_div2_clk), + .io_aib54 (iopad_ns_fwd_div2_clkb), + .io_aib55 (iopad_ns_rcv_div2_clkb), + .io_aib56 (iopad_ns_adapter_rstn), .io_aib57 (iopad_fs_rcv_clk), - //.io_aib58 (aib58), - .io_aib58 (LO), //From Tim's 3/26 aib_bump_map + .io_aib58 (iopad_unused_aib58), + //.io_aib58 (LO), //From Tim's 3/26 aib_bump_map .io_aib59 (iopad_fs_rcv_clkb), .io_aib6 (iopad_tx[6]), .io_aib60 (iopad_unused_aib60), - //.io_aib61 (aib61), - .io_aib61 (HI), //From Tim's 3/26 aib_bump_map + .io_aib61 (iopad_unused_aib61), + //.io_aib61 (HI), //From Tim's 3/26 aib_bump_map .io_aib62 (iopad_unused_aib62), - //.io_aib63 (aib63), - .io_aib63 (LO), //From Tim's 3/26 aib_bump_map - //.io_aib64 (aib64), - .io_aib64 (LO), //From Tim's 3/26 aib_bump_map - .io_aib65 (iopad_fs_adapt_rstn), + .io_aib63 (iopad_unused_aib63), + //.io_aib63 (LO), //From Tim's 3/26 aib_bump_map + .io_aib64 (iopad_unused_aib64), + //.io_aib64 (LO), //From Tim's 3/26 aib_bump_map + .io_aib65 (iopad_fs_adapter_rstn), .io_aib66 (iopad_unused_aib66), - //.io_aib67 (aib67), - .io_aib67 (LO), //From Tim's 3/26 aib_bump_map + .io_aib67 (iopad_unused_aib67), + //.io_aib67 (LO), //From Tim's 3/26 aib_bump_map .io_aib68 (iopad_unused_aib68), .io_aib69 (iopad_unused_aib69), .io_aib7 (iopad_tx[7]), .io_aib70 (iopad_unused_aib70), .io_aib71 (iopad_unused_aib71), - //.io_aib72 (aib72), - //.io_aib73 (aib73), - //.io_aib74 (aib74), - .io_aib72 (LO), //From Tim's 3/26 aib_bump_map - .io_aib73 (LO), //From Tim's 3/26 aib_bump_map - .io_aib74 (LO), //From Tim's 3/26 aib_bump_map + .io_aib72 (iopad_unused_aib72), + .io_aib73 (iopad_unused_aib73), + .io_aib74 (iopad_unused_aib74), + //.io_aib72 (LO), //From Tim's 3/26 aib_bump_map + //.io_aib73 (LO), //From Tim's 3/26 aib_bump_map + //.io_aib74 (LO), //From Tim's 3/26 aib_bump_map .io_aib75 (iopad_unused_aib75), .io_aib76 (iopad_unused_aib76), .io_aib77 (iopad_unused_aib77), - //.io_aib78 (aib78), - //.io_aib79 (aib79), - //.io_aib80 (aib80), - //.io_aib81 (aib81), - .io_aib78 (LO), //From Tim's 3/26 aib_bump_map - .io_aib79 (LO), //From Tim's 3/26 aib_bump_map + .io_aib78 (iopad_unused_aib78), + .io_aib79 (iopad_unused_aib79), + .io_aib80 (iopad_unused_aib80), + .io_aib81 (iopad_unused_aib81), + //.io_aib78 (LO), //From Tim's 3/26 aib_bump_map + //.io_aib79 (LO), //From Tim's 3/26 aib_bump_map .io_aib8 (iopad_tx[8]), - .io_aib80 (LO), //From Tim's 3/26 aib_bump_map - .io_aib81 (LO), //From Tim's 3/26 aib_bump_map + //.io_aib80 (LO), //From Tim's 3/26 aib_bump_map + //.io_aib81 (LO), //From Tim's 3/26 aib_bump_map .io_aib82 (iopad_fs_sr_clkb), .io_aib83 (iopad_fs_sr_clk), .io_aib84 (iopad_ns_sr_clk), .io_aib85 (iopad_ns_sr_clkb), .io_aib86 (iopad_ns_rcv_clkb), .io_aib87 (iopad_ns_rcv_clk), - //.io_aib88 (aib88), - //.io_aib89 (aib89), - .io_aib88 (LO), //From Tim's 3/26 aib_bump_map - .io_aib89 (LO), //From Tim's 3/26 aib_bump_map + .io_aib88 (iopad_unused_aib88), + .io_aib89 (iopad_unused_aib89), + //.io_aib88 (LO), //From Tim's 3/26 aib_bump_map + //.io_aib89 (LO), //From Tim's 3/26 aib_bump_map .io_aib9 (iopad_tx[9]), .io_aib90 (iopad_unused_aib90), .io_aib91 (iopad_unused_aib91), diff --git a/how2use/sim_phasecom/top.sv b/how2use/sim_phasecom/top.sv index 738e564..8d9c6f5 100644 --- a/how2use/sim_phasecom/top.sv +++ b/how2use/sim_phasecom/top.sv @@ -163,10 +163,10 @@ module top; wire iopad_fs_fwd_clk; wire iopad_fs_mac_rdy; wire iopad_ns_mac_rdy; - wire iopad_ns_adapt_rstn; + wire iopad_ns_adapter_rstn; wire iopad_fs_rcv_clk; wire iopad_fs_rcv_clkb; - wire iopad_fs_adapt_rstn; + wire iopad_fs_adapter_rstn; wire iopad_fs_sr_clkb; wire iopad_fs_sr_clk; wire iopad_ns_sr_clk; @@ -190,7 +190,7 @@ module top; The following pins are tied to high so that the loopback test will work: iopad_fs_sr_data - iopad_fs_adapt_rstn + iopad_fs_adapter_rstn */////////////////////////////////////////////////////////////////////////// //----------------------------------------------------------------------------------------- @@ -274,10 +274,10 @@ module top; .iopad_fs_fwd_clk (iopad_ns_fwd_clk), .iopad_fs_mac_rdy (iopad_ns_mac_rdy), .iopad_ns_mac_rdy (iopad_ns_mac_rdy), - .iopad_ns_adapt_rstn (iopad_ns_adapt_rstn), + .iopad_ns_adapter_rstn (iopad_ns_adapter_rstn), .iopad_fs_rcv_clk (iopad_ns_fwd_clk), .iopad_fs_rcv_clkb (iopad_ns_fwd_clkb), - .iopad_fs_adapt_rstn (HI), + .iopad_fs_adapter_rstn (HI), .iopad_fs_sr_clkb (iopad_ns_sr_clkb), .iopad_fs_sr_clk (iopad_ns_sr_clk), .iopad_ns_sr_clk (iopad_ns_sr_clk), diff --git a/how2use/sim_sl2ms_lpbk/README.txt b/how2use/sim_sl2ms_lpbk/README.txt new file mode 100644 index 0000000..9398297 --- /dev/null +++ b/how2use/sim_sl2ms_lpbk/README.txt @@ -0,0 +1,22 @@ +07/03/2019 + +============================================================ +Test bench(top.sv) description +============================================================ +c3aib c3aib_master and (CHIP AIB(aib) model or s10aib FPGA aib model) are instantiated in the test bench. the left side as slave, the right side is c3aib. +Both clocks and data are supplied at the slave side. c3aib was properly configured in loopback mode and release the reset. No transfer clocks and data supplied at master side. + + ------------ --------------- + random | | | rx-->|| + data tx---->| s10aib |<=========================>| c3aib V|(data loopback at FPGA fabric side) + | | | tx<--|| + data rx<----| | | | + checker | | | | + ----------- --------------- + slave master + + +Three simulator supported: +./runsim -- VCS +./runnc -- Cadence +./runvsim -- Modelsim diff --git a/how2use/sim_sl2ms_lpbk/dut_io.sv b/how2use/sim_sl2ms_lpbk/dut_io.sv new file mode 100644 index 0000000..5fd1d99 --- /dev/null +++ b/how2use/sim_sl2ms_lpbk/dut_io.sv @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +`timescale 1ps/1ps +interface dut_io (input bit i_osc_clk, + input bit i_rx_pma_clk, + input bit i_tx_pma_clk, + input bit i_cfg_avmm_clk); + + + logic i_adpt_hard_rst_n; + logic ns_mac_rdy; + logic [6-1:0] i_channel_id; + logic i_cfg_avmm_rst_n; + logic [16:0] i_cfg_avmm_addr; + logic [ 3:0] i_cfg_avmm_byte_en; + logic i_cfg_avmm_read; + logic i_cfg_avmm_write; + logic [31:0] i_cfg_avmm_wdata; + logic i_adpt_cfg_rdatavld; + logic i_adpt_cfg_waitreq; + logic [31:0] i_adpt_cfg_rdata; + + logic [31:0] o_cfg_avmm_rdata; + logic o_cfg_avmm_rdatavld; + logic o_cfg_avmm_waitreq; + logic o_osc_clk; + + logic [65-1:0] i_chnl_ssr; + logic [40-1:0] i_rx_pma_data; + logic [65-1:0] o_chnl_ssr; + logic [40-1:0] o_tx_pma_data; + + logic o_rx_xcvrif_rst_n; + logic o_tx_xcvrif_rst_n; + logic o_tx_transfer_clk; + logic o_tx_transfer_div2_clk; + + //rx_pma_clk domain + clocking cb_rx_pma @ (posedge i_rx_pma_clk); + default input #1 output #1; + output i_rx_pma_data; + endclocking // cb + + //cfg_avmm_clk domain + clocking cb_cfg_avmm @(posedge i_cfg_avmm_clk); + default input #1 output #1; + output i_channel_id; + output i_cfg_avmm_write; + output i_cfg_avmm_read; + output i_cfg_avmm_addr; + output i_cfg_avmm_byte_en; + output i_cfg_avmm_wdata; + output i_adpt_cfg_rdatavld; + output i_adpt_cfg_rdata; + output i_adpt_cfg_waitreq; + + input o_cfg_avmm_waitreq; + input o_cfg_avmm_rdatavld; + input o_cfg_avmm_rdata; + + endclocking // cb + + //osc_clk domain + clocking cb_osc @ (posedge i_osc_clk); + + default input #1 output #1; + output i_chnl_ssr; + input o_chnl_ssr; + + endclocking + + modport TB (clocking cb_osc, + clocking cb_rx_pma, + clocking cb_cfg_avmm, + output i_adpt_hard_rst_n, + output ns_mac_rdy, + output i_cfg_avmm_rst_n); + +endinterface // dut_io diff --git a/how2use/sim_sl2ms_lpbk/multidie.f b/how2use/sim_sl2ms_lpbk/multidie.f new file mode 100644 index 0000000..b240d31 --- /dev/null +++ b/how2use/sim_sl2ms_lpbk/multidie.f @@ -0,0 +1,627 @@ ++incdir+../../aib_lib/aibcr3_lib/rtl/ ++incdir+../../aib_lib/aibcr3pnr_lib/rtl/ ++incdir+../../aib_lib/c3dfx/rtl/defines/ +../../aib_lib/c3lib/rtl/defines/c3lib_dv_defines.sv +../../aib_lib/c3dfx/rtl/defines/c3dfx.vh + +// pointer to standalone DCC - DCC, c3 and DLL pnr block +../../aib_lib/aibcr3_lib/rtl/aibcr3_dcc_8ph_intp.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dcc_crsdlyline.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dcc_dll.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dcc_dlyline64.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dcc_dlyline.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dcc_dly.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dcc_gry2thm64.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dcc_helper.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dcc_interpolator.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dcc_phasedet.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dcc_top.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dll_custom.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dll_lock_dly.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dlycell_dcc.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_svt16_scdffcdn_cust.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_svt16_scdffsdn_cust.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_ulvt16_2xarstsyncdff1_b2.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_ulvt16_dffcdn_cust.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_io_cmos_nand_x64.v + +//aibcr3 model + +../../aib_lib/aibcr3_lib/rtl/aibcr3_top_wrp.v + +// this section is for strobe align circuits + +../../aib_lib/aibcr3_lib/rtl/aibcr3_str_align.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_clktree_mimic.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_clktree.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_cmos_nand_x64.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dll_8ph_intp.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dll_dlyline64.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dll_gry2thm64.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dll_ibkmux.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dlycell_dll.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dlycell_dll_c.v + +// other aibcr models +../../aib_lib/aibcr3_lib/rtl/aibcr3_scan_iomux.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_2to4dec.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_analog.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_avmm1.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_avmm2.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_buffx1_top.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_buffx1.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_clktree_avmm_mimic.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_clktree_avmm_pcs.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_clktree_avmm.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_clktree_pcs.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_cmos_fine_dly.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_cmos_nand_x1.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_io_ip8phs.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_digital.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_inv_split_align.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_lvshift.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_preclkbuf.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_quadph_code_gen.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_rxanlg.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_rxdatapath_rx.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_rxdig.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_top.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_txanlg.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_txdatapath_tx.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_txdig.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_nd2d0_custom.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_split_align.v +../../aib_lib/aibcr3_lib/rtl/structured.v + +// NEW for converted RTL (removed logic cells) + +../../aib_lib/aibcr3_lib/rtl/aibcr3_ff_r.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_ff_p.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_ff_rp.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_latch.v + + +// NEW REL3.5 + +../../aib_lib/aibcr3_lib/rtl/aibcr3_red_custom_dig.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_str_ff.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_sync_ff.v + + +//newly added + +../../aib_lib/aibcr3_lib/rtl/aibcr3_dcc_top_dummy.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_esd.v + + +//NEW REL4.0 + +../../aib_lib/aibcr3_lib/rtl/aibcr3_str_ioload.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_red_custom_dig2.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_red_clkmux2.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_red_clkmux3.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_lvshift_lospeed.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_lvshift_diff.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_triinv_dig.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_interface.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_rambit_buf.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_signal_buf.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_data_buf.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_rxdat_mimic.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_txdat_mimic.v + + +../../aib_lib/aibcr3_lib/rtl/aibcr3_dcc_dly_rep.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_dly_mimic.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_io_cmos_8ph_interpolator_rep.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_io_cmos_8ph_interpolator.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_io_nand_delay_line_min_rep.v + +//copied models due to io_common_custom ND and CR conflict + +../../aib_lib/aibcr3_lib/rtl/aibcr3_io_cmos_nand_x1.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_io_cmos_nand_x128.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_io_nand_delay_line_min.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_io_nand_x128_delay_line.v + +//NEW REL4.5 +../../aib_lib/aibcr3_lib/rtl/aibcr3_clkmux2.v + + +//NEW REL4.5 (replacing syncronizer- 3rd party cell issue) + +../../aib_lib/aibcr3_lib/rtl/aibcr3_sync_2ff.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_sync_3ff.v + +//custom alias model + +../../aib_lib/aibcr3_lib/rtl/aibcr3_aliasv.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_aliasd.v + + +../../aib_lib/aibcr3_lib/rtl/aibcr3_ulvt16_dffsdn_cust.v + +// custom esd cells used outside of aibio and aibaux. sits in xcvrcntl +../../aib_lib/aibcr3_lib/rtl/aibcr3_opio_esd.v +../../aib_lib/aibcr3_lib/rtl/aibcr3_anaio_esd.v + +// update for conformal +../../aib_lib/aibcr3_lib/rtl/aibcr3_dlycell_dcc_rep.v + +../../aib_lib/c3lib/rtl/basic/pulse_stretch/cdclib_pulse_stretch.sv + +../../aib_lib/c3lib/rtl/avmm/c3_avmm_rdl_intf.sv +../../aib_lib/c3lib/rtl/avmm/c3lib_cfgcsr_fastslow_pulse_meta.sv +../../aib_lib/c3lib/rtl/avmm/c3lib_cfgcsr_slowfast_pulse_meta.sv +../../aib_lib/c3lib/rtl/avmm/c3lib_avmm_pulse_cross.sv + +../../aib_lib/c3lib/rtl/cdc/async_fifo/c3lib_async_fifo.sv + +../../aib_lib/c3lib/rtl/cdc/bit_synchronizer/c3lib_bitsync.sv +../../aib_lib/c3lib/rtl/cdc/bit_synchronizer/c3lib_sync2_lvt_bitsync.sv +../../aib_lib/c3lib/rtl/cdc/bit_synchronizer/c3lib_sync2_ulvt_bitsync.sv +../../aib_lib/c3lib/rtl/cdc/bit_synchronizer/c3lib_sync3_ulvt_bitsync.sv +../../aib_lib/c3lib/rtl/cdc/gray_code/c3lib_bintogray.sv +../../aib_lib/c3lib/rtl/cdc/gray_code/c3lib_graytobin.sv +../../aib_lib/c3lib/rtl/cdc/level_synchronizer/c3lib_lvlsync.sv +../../aib_lib/c3lib/rtl/cdc/reset_synchronizer/c3lib_rstsync.sv +../../aib_lib/c3lib/rtl/cdc/vector_synchronizer/c3lib_vecsync.sv +../../aib_lib/c3lib/rtl/cdc/vector_synchronizer/c3lib_vecsync_handshake.sv +../../aib_lib/c3lib/rtl/cdc/glitch_free_mux/c3lib_gf_clkmux.sv + +../../aib_lib/c3lib/rtl/ctn/clock_buf/c3lib_ckinv_ctn.sv +../../aib_lib/c3lib/rtl/ctn/clock_buf/c3lib_ckbuf_ctn.sv +../../aib_lib/c3lib/rtl/ctn/clock_buf/c3lib_ckand2_ctn.sv +../../aib_lib/c3lib/rtl/ctn/clock_gater/c3lib_ckg_async_posedge_ctn.sv +../../aib_lib/c3lib/rtl/ctn/clock_gater/c3lib_ckg_negedge_ctn.sv +../../aib_lib/c3lib/rtl/ctn/clock_gater/c3lib_ckg_posedge_ctn.sv +../../aib_lib/c3lib/rtl/ctn/clock_mux/c3lib_mux2_ctn.sv +../../aib_lib/c3lib/rtl/ctn/clock_mux/c3lib_mux3_ctn.sv +../../aib_lib/c3lib/rtl/ctn/clock_mux/c3lib_mux4_ctn.sv +../../aib_lib/c3lib/rtl/ctn/clock_divider/c3lib_ckdiv2_ctn.sv +../../aib_lib/c3lib/rtl/ctn/clock_divider/c3lib_ckdiv4_ctn.sv +../../aib_lib/c3lib/rtl/ctn/clock_divider/c3lib_ckdiv8_ctn.sv + +../../aib_lib/c3lib/rtl/lcell/c3lib_and2_lcell.sv +../../aib_lib/c3lib/rtl/lcell/c3lib_buf_lcell.sv +../../aib_lib/c3lib/rtl/lcell/c3lib_mux2_lcell.sv +../../aib_lib/c3lib/rtl/lcell/c3lib_nand2_lcell.sv +../../aib_lib/c3lib/rtl/lcell/c3lib_or2_lcell.sv +../../aib_lib/c3lib/rtl/lcell/c3lib_tie_bus_lcell.sv +../../aib_lib/c3lib/rtl/lcell/c3lib_tieh_lcell.sv +../../aib_lib/c3lib/rtl/lcell/c3lib_tiel_lcell.sv +../../aib_lib/c3lib/rtl/lcell/c3lib_mtieh_lcell.sv +../../aib_lib/c3lib/rtl/lcell/c3lib_mtiel_lcell.sv +../../aib_lib/c3lib/rtl/lcell/c3lib_dff_scan_lcell.sv + +../../aib_lib/c3lib/rtl/ecc/c3lib_ecc_dec_c39_d32.sv +../../aib_lib/c3lib/rtl/ecc/c3lib_ecc_dec_c88_d80.sv +../../aib_lib/c3lib/rtl/ecc/c3lib_ecc_enc_d32_c39.sv +../../aib_lib/c3lib/rtl/ecc/c3lib_ecc_enc_d80_c88.sv + +../../aib_lib/c3lib/rtl/primitives/c3lib_sync2_reset_lvt_gate.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_sync2_reset_ulvt_gate.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_sync3_reset_ulvt_gate.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_sync2_set_lvt_gate.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_sync2_set_ulvt_gate.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_sync3_set_ulvt_gate.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_tie0_svt_1x.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_tie1_svt_1x.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_mtie0_ds.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_mtie1_ds.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_or2_svt_2x.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_nand2_svt_2x.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_mux2_svt_2x.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_ckmux4_ulvt_gate.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_ckmux4_lvt_gate.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_ckinv_lvt_12x.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_ckinv_svt_8x.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_ckg_lvt_8x.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_ckbuf_lvt_4x.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_buf_svt_4x.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_and2_svt_2x.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_and2_svt_4x.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_dff0_reset_lvt_2x.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_dff0_set_lvt_2x.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_dff0_scan_reset_svt_2x.sv +../../aib_lib/c3lib/rtl/primitives/c3lib_sync_metastable_behav_gate.sv + +../../aib_lib/c3dfx/rtl/tcm/c3dfx_tcm_wrap.sv +../../aib_lib/c3dfx/rtl/tcm/c3dfx_tcm.sv +../../aib_lib/c3aibadapt/rtl/c3aibadapt.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1_async.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1clk_ctl.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1_config.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_hwcfg_dec.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_cfg_csr.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_usr_csr.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1_transfer.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2_async.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2clk_ctl.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2_config.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2_transfer.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_async.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_cfg_rdmux.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmmclk_dcg.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmmclk_gate.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_cmdbuilder.sv +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_dec_arb.sv +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_decode.sv +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_rdfifo.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmmrst_ctl.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_usr32_exp.sv +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_hrdrst_clkctl.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_hrdrst_rstctrl.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_async_capture_bit.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_async_capture_bus.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkand2.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkgate_high.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkgate.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkinv.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkmux2_cell.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkmux2.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_comp_cntr.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_dist_dw.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_dist_pair_dw.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_dist_pair.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_dist.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_dft_clk_ctlr.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_latency_measure.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_occ_clkgate.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_occ_enable_logic.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_occ_gray_cntr.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_occ_test_ctlregs.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_parity_checker.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_parity_gen.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_pulse_stretch.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_dprio_status_sync_regs.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_shadow_status_regs.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_capture.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_direct.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_rsvd_capture.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_rsvd_update.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_update.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxchnl_testbus.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxchnl.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxclk_ctl.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxclk_gate.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_asn.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_async_fifo.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_cp_bond.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_del_sm.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_fifo_ptr.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_fifo_ram.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_fifo.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_map.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rx_dprio.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_rxeq_sm.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_txeq_sm.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_txeq.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxrst_ctl.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_fsr_in.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_fsr_out.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_async_capture_bit.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_async_capture_bus.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_srclk_ctl.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_in_bit.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_out_bit.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_srrst_ctl.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_sm.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_ssr_in.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_ssr_out.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_async_update.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_hip_async_capture.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_hip_async_update.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_capture.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_direct.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_rsvd_capture.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_rsvd_update.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_update.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txchnl_testbus.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txchnl.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txclk_ctl.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txclk_gate.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_async_fifo.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_cp_bond.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_fifo_ptr.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_fifo_ram.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_fifo.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_map.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_tx_dprio.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_word_align.v +../../aib_lib/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txrst_ctl.v + +../../aib_lib/aibcr3pnr_lib/rtl/aibcr3pnr_redundancy.v +../../aib_lib/aibcr3pnr_lib/rtl/aibcr3pnr_jtag_bscan.v +../../aib_lib/aibcr3pnr_lib/rtl/aibcr3pnr_bsr_red_wrap.v + +../../aib_lib/aibcr3pnr_lib/rtl/aibcr3pnr_half_cycle_code_gen.v +../../aib_lib/aibcr3pnr_lib/rtl/aibcr3pnr_self_lock_assertion.v +../../aib_lib/aibcr3pnr_lib/rtl/aibcr3pnr_dll_ctrl.v +../../aib_lib/aibcr3pnr_lib/rtl/aibcr3pnr_dll_core.v +../../aib_lib/aibcr3pnr_lib/rtl/aibcr3pnr_dll_pnr.v +../../aib_lib/aibcr3pnr_lib/rtl/aibcr3pnr_rstsync.sv + +../../aib_lib/c3dfx/rtl/tcb/c3dfx_aibadaptwrap_tcb.sv +../../aib_lib/c3aibadapt_wrap/rtl/c3aibadapt_wrap.v +../../aib_lib/c3aibadapt_wrap/rtl/c3aib_master.sv ++incdir+../../maib_rtl/cfg_shared/rtl/block_function/hdpldadapt/rtl/block_function ++incdir+../../maib_rtl/cfg_shared/rtl/block_function/cdclib/rtl/block_function ++incdir+../../maib_rtl/cfg_shared/rtl/block_function/cfg_shared/rtl/block_function ++incdir+../../maib_rtl/aibnd_lib/rtl/block_function ++incdir+../../maib_rtl/io_common_custom/rtl/block_function ++incdir+../../maib_rtl/aibndpnr_lib/rtl/block_function ++incdir+../../maib_rtl/cdclib/rtl/block_function +../../maib_rtl/s10aib/rtl/ndaibadapt_wrap.v +../../maib_rtl/s10aib/rtl/an.v +../../maib_rtl/s10aib/rtl/s10aib.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1_async.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1_config.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1_dprio_mapping.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1_transfer.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm2_async.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm2_transfer.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm2.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_async_update.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmmclk_ctl.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_cmdfifo.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_cmn_intf.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_dprio_reg.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_rdfifo.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmmrst_ctl.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_async.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_hrdrst_rstctrl.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_hrdrst_clkctl.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_fsr_in.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_fsr_out.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_srclk_ctl.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_sr_in_bit.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_sr_out_bit.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_srrst_ctl.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_sr_sm.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_sr.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_ssr_in.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_ssr_out.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_async_update.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_reserved_capture.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_reserved_update.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_hip_async_capture.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_hip_async_update.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_capture.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_direct.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_update.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_chnl.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_txclk_ctl.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_async_fifo.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_fifo_ram.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_fifo_pointers.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_chnl_testbus.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_cp_bond.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_dv_gen.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_fifo.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_frame_gen.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_word_mark.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_txrst_ctl.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_pulse_stretch.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_reserved_capture.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_reserved_update.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_capture.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_direct.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_update.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_chnl.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rxclk_ctl.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_asn.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_async_fifo.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_cp_bond.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_fifo.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_fifo_ram.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_fifo_pointers.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_insert_sm.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_del_sm.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_word_align.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rxrst_ctl.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_pulse_stretch.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_chnl_testbus.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_async_capture_bit.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_comp_cntr.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_pair_dw.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_async_capture_bus.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_dw.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_pair.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_latency_measure.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_pulse_stretch.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_parity_gen.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_parity_checker.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkand2.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay_map.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay_cell.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkgate.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkinv.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkmux2_cell.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkmux2.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkor2.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_dft_clock_controller.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_clkgate.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_enable_logic.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_gray_code_counter.v +../../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_test_control_register.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_bintogray.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_bintogray_inc8.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_bitsync2.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_sync2_reset_type_l_gate.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_sync2_reset_type_n_gate.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_sync2_reset_type_w_gate.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_sync2_set_type_l_gate.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_sync2_set_type_n_gate.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_sync2_set_type_w_gate.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_bitsync4.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_sync4_reset_type_l_gate.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_sync4_reset_type_w_gate.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_sync4_set_type_l_gate.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_sync4_set_type_w_gate.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_graytobin.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_graytobin_inc2.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_graytobin_inc8.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_rst_n_sync.v +../../maib_rtl/cdclib/rtl/block_function/cdclib_rst_n_sync_core.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_csr_reg_bit.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_csr_reg_nbits.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_csr_reg_nregs.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_cmn_non_scan_reg.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_readdata_mux.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_interface_top.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_csr_test_mux.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_cmn_clk_mux.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_reg_bit.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_reg_nbits.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_reg_nregs.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_reg_chnl.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_reg_top.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_dis_ctrl_cvp.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_readdata_sel.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_status_reg_nbits.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_status_reg_nregs.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_status_sync_regs.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_shadow_status_regs.v +../../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_shadow_status_nregs.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_top_wrp.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_top.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dly_rep.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dly_mimic.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_io_dly_interpolator_rep.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_io_nand_delay_line_min_rep.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_latch.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_hgy_latch.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_ff_r.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_ff_rp.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_2ff_scan.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_aliasd.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_aliasv.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_2to4dec.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_analog.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_avmm1.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_avmm2.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_buffx1_top.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_buffx1.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clkbuf.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_avmm.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_avmm_mimic.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_avmm_pcs.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_mimic.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_pcs.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_fine_dly.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x6.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x1.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_d8xsesdd1.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_d8xsesdd2.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_5b_b2tc_x1.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_5b_b2tc.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dll.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_ff.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_fine_dly.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_mux.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_top.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_digital.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dll_phdet.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dll_custom.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_inv_split_align.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_quadph_code_gen.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_preclkbuf.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxdatapath_rx.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxdig.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_align.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_txdatapath_tx.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_txdig.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxanlg.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_txanlg.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_fine_dly_x1.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_fine_dly_x1.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dly_inv.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_fine_dly_inv.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_ff.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_helper.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_clktree_mimic.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dly.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_custom_dig.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_preclkbuf.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_nand_x64_delay_line.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_clktree.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_sync_ff.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x64.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_signal_buf.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_custom_dig2.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_avmm_rst_sync.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_data_buf.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_interface.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_rambit_buf.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_inv.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_nand2.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_nor2.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_clkmux2.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_clkmux3.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_txdat_mimic.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxdat_mimic.v +../../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clkmux2.v +//Looks fine to me. All behavior and from Nightfury + +../../maib_rtl/io_common_custom/rtl/block_function/io_interp_mux.v +../../maib_rtl/io_common_custom/rtl/block_function/io_ip16phs.v +../../maib_rtl/io_common_custom/rtl/block_function/io_cmos_16ph_decode.v +../../maib_rtl/io_common_custom/rtl/block_function/io_interp_misc.v +../../maib_rtl/io_common_custom/rtl/block_function/io_interp_output.v +../../maib_rtl/io_common_custom/rtl/block_function/io_interp_latch_in.v +../../maib_rtl/io_common_custom/rtl/block_function/io_interp_mux_pair.v +../../maib_rtl/io_common_custom/rtl/block_function/io_interp_pdn.v +../../maib_rtl/io_common_custom/rtl/block_function/io_min_interp_mux.v +../../maib_rtl/io_common_custom/rtl/block_function/io_min_ip16phs.v +../../maib_rtl/io_common_custom/rtl/block_function/io_min_output.v +../../maib_rtl/io_common_custom/rtl/block_function/io_min_misc.v +../../maib_rtl/io_common_custom/rtl/block_function/io_min_pdn.v +../../maib_rtl/io_common_custom/rtl/block_function/io_dly_interpolator.v +../../maib_rtl/io_common_custom/rtl/block_function/io_dly_interpclk.v +../../maib_rtl/io_common_custom/rtl/block_function/io_ip8phs_3in.v +../../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x1.v +../../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x128.v +../../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x64_decode.v +../../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x128_decode.v +../../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x6.v +../../maib_rtl/io_common_custom/rtl/block_function/io_nand_x128_delay_line.v +../../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x64.v +../../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x4.v +../../maib_rtl/io_common_custom/rtl/block_function/io_split_align.v +../../maib_rtl/io_common_custom/rtl/block_function/io_dll_phdet.v +../../maib_rtl/io_common_custom/rtl/block_function/io_nand_delay_line_min.v +../../maib_rtl/soc_std_macro/rtl/block_function/i14socnd/soc_simulation_defines.v +// Not used +// Standard Cell, OK to use with ALTR_HPS_INTEL_MACROS_OFF option +../../maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckinv.v +../../maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckmux21.v +../../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_redundancy.v +../../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_jtag_bscan.v +../../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_bsr_red_wrap.v +../../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_half_cycle_code_gen.v +../../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_self_lock_assertion.v +../../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_ctrl.v +../../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_core.v +../../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_pnr.v +../../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkgate_cgc00.v +../../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkgate_cgc01.v +../../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkmux.v diff --git a/how2use/sim_sl2ms_lpbk/nda_drv.sv b/how2use/sim_sl2ms_lpbk/nda_drv.sv new file mode 100644 index 0000000..3768987 --- /dev/null +++ b/how2use/sim_sl2ms_lpbk/nda_drv.sv @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + + logic [2:0] csr_config; + logic [2:0] csr_in; + logic nfrzdrv_in; + logic csr_rdy_in; + logic usermode_in; + logic sl_ns_mac_rdy; + + reg csr_clk_in = 1'b0; + reg pld_rx_clk1_rowclk = 1'b0; + reg pld_rx_clk2_rowclk = 1'b0; + reg pld_tx_clk1_rowclk = 1'b0; + reg pld_tx_clk2_rowclk = 1'b0; + reg pld_rx_clk1_dcm = 1'b0; + reg pld_rx_clk2_dcm = 1'b0; + reg pld_tx_clk1_dcm = 1'b0; + reg pld_tx_clk2_dcm = 1'b0; + + + //clock gen + //Default set value + initial + begin + run_for_n_pkts = 20; + csr_rdy_in = 1'b0; + sl_ns_mac_rdy = 1'b0; + pld_adapter_tx_pld_rst_n = 1'b0; + pld_adapter_rx_pld_rst_n = 1'b0; + pld_tx_dll_lock_req = 1'b0; + pld_rx_dll_lock_req = 1'b0; +// dut.i_adpt_hard_rst_n = 1'b0; + #1000ns; + sl_ns_mac_rdy = 1'b1; + csr_rdy_in = 1'b1; + // @(dut.i_adpt_hard_rst_n) + // dut.i_adpt_hard_rst_n = 1'b1; + #1000ns; + pld_adapter_rx_pld_rst_n = 1'b1; + pld_adapter_tx_pld_rst_n = 1'b1; + pld_tx_dll_lock_req = 1'b1; + pld_rx_dll_lock_req = 1'b1; + #1000ns; + // wait_xfer_ready (); + + $display ("[%t] Xfer Ready", $time); + + $display ("[%t] start AIB chiplet standalone loopback testing by running %d packets", $time, run_for_n_pkts); + fork + data_xmit (); + data_rcv (); + join + $display ("[%t] ######### Debug: All Tasks are finished normally #############", $time); + Finish (); + + end //initial begin + + task data_xmit (); + static int pkts_gen = 0; + static bit [79:0] data = 0; + data[39] = 1'b0; + data[79] = 1'b1; + + + while (pkts_gen < run_for_n_pkts) begin + data[31:0] = $urandom_range(32'hffff_ffff,0); + data[38:32] = $urandom_range(7'h7f,0); + data[71:40] = $urandom_range(32'hffff_ffff,0); + data[78:72] = $urandom_range(7'h7f,0); + $display ("[%t] Generating data[%d] = %x \n", $time, pkts_gen, data); + + @(posedge tx_coreclkin); + tx_parallel_data <= data; + xmit_q.push_back(data); + pkts_gen++; + end + endtask + + task data_rcv (); + static bit [79:0] data_exp = 0; + static int pkts_rcvd = 0; + begin + while(pkts_rcvd < run_for_n_pkts) begin + @ (posedge rx_coreclkin); + if (rx_parallel_data[38:0] != 0) begin + $display ("[%t] Receiving data[%d] = %x \n", $time, pkts_rcvd, rx_parallel_data); + data_exp = xmit_q.pop_front(); + pkts_rcvd++; + if (rx_parallel_data!= data_exp) begin + err_count++; + $display ("[%t]DATA COMPARE ERROR: received = %x | expected = %x\n", $time, rx_parallel_data, data_exp); + end + end + end + if (xmit_q.size() != 0) //check if all the data are received + $display("[%t]ERROR: Tramit Queue Not Empty, still %d data left\n", $time, xmit_q.size()); + + end + endtask // mstr_req_rcv + + task Finish (); + begin + $display("%0t: %m: finishing simulation..", $time); + repeat (100) @(posedge rx_coreclkin); + $display("\n////////////////////////////////////////////////////////////////////////////"); + $display("%0t: Simulation ended, ERROR count: %0d", $time, err_count); + $display("////////////////////////////////////////////////////////////////////////////\n"); + if (err_count == 0) begin + $display("+++++++++++++++++++++++++++++++++\n"); + $display("TEST PASSED!!!!!!!!!!!\n"); + $display("+++++++++++++++++++++++++++++++++\n"); + end + $finish; + end + endtask + + + + + //Nadder Adapter Forces + initial begin // { + @ (csr_rdy_in) + + //MAIB Configuration + // + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.aib_csr_ctrl[463:0] = 464'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_1c00_7f1c_0000_0000_0004_0002_45c3_3f07_b000_0040_0002_0000_2619_0000_0000_0000_0000_0000_0000; + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.aib_dprio_ctrl[39:0] = 40'h400; //Bit 10 is dll bypass. + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.avmm1_csr_ctrl[55:0] = 56'h07_ff00_3000_f800; + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.avmm1_dprio_ctrl[7:0] = 8'h0; + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.avmm2_csr_ctrl[55:0] = 56'h07_ff00_3000_f800; + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.avmm2_dprio_ctrl[7:0] = 8'h0; + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.avmm_csr_ctrl[55:0] = 56'h00_0018_0000_0300; + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.avmm_res_csr_ctrl[7:0] = 8'h0; +//bit 164 r_rx_hrdrst_user_ctl_en bit 164 to overwrite reset for fifo due to dead FSM +// force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.rx_chnl_dprio_ctrl[167:0] = 168'hc8_17c8_c905_6c42_0040_4040_4c00_0303_0018_ca82_cf01; + //bit 140 r_rx_fifo_wr_clk_sel for rx fifo source clock sel. bit 38 Loopback enable + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.rx_chnl_dprio_ctrl[167:0] = 168'hd8_17c8_c905_6c42_0040_4040_4c00_0303_0018_ca82_4f01; + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.sr_dprio_ctrl[23:0] = 24'h0; +// force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.tx_chnl_dprio_ctrl[135:0] = 136'h2c_e086_11c5_00ce_2308_00cb_0300_6a22_ee00; + // bit 122 r_tx_hrdrst_user_ctl_en to set to 1 to over write fifo reset by reset fsm + // have to set r_tx_fifo_rd_clk_sel[1:0] bit 111:110 to 2'b10 to get clock pld_tx_clk2_dcm + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.tx_chnl_dprio_ctrl[135:0] = 136'h2c_e486_91c5_00ce_2308_008b_0300_6a22_ee00; + + force `NDADAPT_RTB.hdpldadapt_avmm.r_rx_async_pld_pma_ltd_b_rst_val = 1'b0; +// force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.avmm_csr_ctrl[17] = 1'b1; //r_sr_reserbits_in_en + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.avmm_csr_ctrl[18] = 1'b1; //r_sr_reserbits_out_en + //force `NDADAPT_RTB.hdpldadapt_sr.r_sr_reserbits_in_en = 1'b1; + //force `NDADAPT_RTB.hdpldadapt_sr.r_sr_reserbits_out_en = 1'b1; + end + diff --git a/how2use/sim_sl2ms_lpbk/nda_port.sv b/how2use/sim_sl2ms_lpbk/nda_port.sv new file mode 100644 index 0000000..2081ab8 --- /dev/null +++ b/how2use/sim_sl2ms_lpbk/nda_port.sv @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + + +wire [79:0] pld_rx_fabric_data_out; +wire rx_clkout; +wire sl_m_fs_fwd_clk; + +s10aib s10_wrap ( + .iopad_ns_mac_rdy(ms_iopad_fs_mac_rdy), + .iopad_fs_mac_rdy(ms_iopad_ns_mac_rdy), + .iopad_ns_adapter_rstn(ms_iopad_fs_adapter_rstn), + .iopad_fs_adapter_rstn(ms_iopad_ns_adapter_rstn), + + .iopad_tx(ms_iopad_rx), + .iopad_ns_fwd_clk(ms_iopad_fs_fwd_clk), + .iopad_ns_fwd_clkb(ms_iopad_fs_fwd_clkb), + .iopad_ns_rcv_clk(ms_iopad_fs_rcv_clk), + .iopad_ns_rcv_clkb(ms_iopad_fs_rcv_clkb), + + + .iopad_rx(ms_iopad_tx), + .iopad_fs_fwd_clk(ms_iopad_ns_fwd_clk), + .iopad_fs_fwd_clkb(ms_iopad_ns_fwd_clkb), + .iopad_fs_fwd_div2_clk(ms_iopad_ns_fwd_div2_clk), + .iopad_fs_fwd_div2_clkb(ms_iopad_ns_fwd_div2_clkb), + .iopad_fs_rcv_clk(ms_iopad_ns_rcv_clk), + .iopad_fs_rcv_clkb(ms_iopad_ns_rcv_clkb), + .iopad_fs_rcv_div2_clk(ms_iopad_ns_rcv_div2_clk), + .iopad_fs_rcv_div2_clkb(ms_iopad_ns_rcv_div2_clkb), + + .iopad_ns_sr_data(ms_iopad_fs_sr_data), + .iopad_ns_sr_load(ms_iopad_fs_sr_load), + .iopad_ns_sr_clk(ms_iopad_fs_sr_clk), + .iopad_ns_sr_clkb(ms_iopad_fs_sr_clkb), + + + .iopad_fs_sr_clk(ms_iopad_ns_sr_clk), + .iopad_fs_sr_clkb(ms_iopad_ns_sr_clkb), + .iopad_fs_sr_data(ms_iopad_ns_sr_data), + .iopad_fs_sr_load(ms_iopad_ns_sr_load), + + .iopad_unused_aib45, + .iopad_unused_aib46, + .iopad_unused_aib47, + .iopad_unused_aib50, + .iopad_unused_aib51, + .iopad_unused_aib52, + .iopad_unused_aib58, + .iopad_unused_aib60, + .iopad_unused_aib61, + .iopad_unused_aib62, + .iopad_unused_aib63, + .iopad_unused_aib64, + .iopad_unused_aib66, + .iopad_unused_aib67, + .iopad_unused_aib68, + .iopad_unused_aib69, + .iopad_unused_aib70, + .iopad_unused_aib71, + .iopad_unused_aib72, + .iopad_unused_aib73, + .iopad_unused_aib74, + .iopad_unused_aib75, + .iopad_unused_aib76, + .iopad_unused_aib77, + .iopad_unused_aib78, + .iopad_unused_aib79, + .iopad_unused_aib80, + .iopad_unused_aib81, + .iopad_unused_aib88, + .iopad_unused_aib89, + .iopad_unused_aib90, + .iopad_unused_aib91, + + + .tx_parallel_data(tx_parallel_data), // pld_tx_fabric_data_in + .rx_parallel_data(rx_parallel_data), // pld_rx_fabric_data_out + .tx_coreclkin(tx_coreclkin), // pld_tx_clk1_rowclk or pld_tx_clk1_dcm + .m_ns_fwd_clk(sl_m_ns_fwd_clk), + .tx_clkout(tx_clkout), // pld_pcs_tx_clk_out1_dcm + .rx_coreclkin(rx_coreclkin), // pld_rx_clk1_dcm + .rx_clkout(rx_clkout), // pld_pcs_rx_clk_out1_dcm + .m_fs_fwd_clk(sl_m_fs_fwd_clk), + .config_done(csr_rdy_in), + .fs_mac_rdy(fs_mac_rdy), //(use c3 pld_pma_clkdiv_rx_user pin). Drive by Master + .ns_mac_rdy(sl_ns_mac_rdy), //nd pld_pma_rxpma_rstb. This signal should be high before ns_adapter_rstn go high. + .ns_adapter_rstn(pld_adapter_rx_pld_rst_n), //Reset Main adapter and pass over to the fs. + + .sl_rx_dcc_dll_lock_req(pld_rx_dll_lock_req), + .sl_tx_dcc_dll_lock_req(pld_tx_dll_lock_req), + .ms_rx_transfer_en(), + .ms_tx_transfer_en(), + .sl_rx_transfer_en(), + .sl_tx_transfer_en(), + .ms_sideband(), + .sl_sideband()); + diff --git a/how2use/sim_sl2ms_lpbk/ndut_declare.sv b/how2use/sim_sl2ms_lpbk/ndut_declare.sv new file mode 100644 index 0000000..584dca5 --- /dev/null +++ b/how2use/sim_sl2ms_lpbk/ndut_declare.sv @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + //Config + /*input */ logic [2:0] csr_pipe_in; + /*input */ logic [3:0] hip_aib_fsr_in; + /*input */ logic [39:0] hip_aib_ssr_in; + /*input */ logic hip_avmm_read; + /*input */ logic [20:0] hip_avmm_reg_addr; + /*input */ logic hip_avmm_write; + /*input */ logic [7:0] hip_avmm_writedata; + /*input */ logic pld_adapter_rx_pld_rst_n; + /*input */ logic pld_adapter_tx_pld_rst_n; + /*input */ logic pld_avmm1_clk_rowclk; + /*input */ logic pld_avmm1_read; + /*input */ logic [9:0] pld_avmm1_reg_addr; + /*input */ logic pld_avmm1_request; + /*input */ logic pld_avmm1_write; + /*input */ logic [7:0] pld_avmm1_writedata; + /*input */ logic [8:0] pld_avmm1_reserved_in; + /*input */ logic pld_avmm2_clk_rowclk; + /*input */ logic pld_avmm2_read; + /*input */ logic [8:0] pld_avmm2_reg_addr; + /*input */ logic pld_avmm2_request; + /*input */ logic pld_avmm2_write; + /*input */ logic [7:0] pld_avmm2_writedata; + /*input */ logic [9:0] pld_avmm2_reserved_in; + /*input */ logic pld_bitslip; + /*input */ logic [1:0] pld_fpll_shared_direct_async_in; + /*input */ logic pld_fpll_shared_direct_async_in_rowclk; + /*input */ logic pld_fpll_shared_direct_async_in_dcm; + /*input */ logic pld_ltr; + /*input */ logic pr_channel_freeze_n; + /*input */ logic pld_pcs_rx_pld_rst_n; + /*input */ logic pld_pcs_tx_pld_rst_n; + /*input */ logic pld_pma_adapt_start; + /*input */ logic pld_pma_coreclkin_rowclk; + /*input */ logic pld_pma_csr_test_dis; + /*input */ logic pld_pma_early_eios; + /*input */ logic [5:0] pld_pma_eye_monitor; + /*input */ logic [3:0] pld_pma_fpll_cnt_sel; + /*input */ logic pld_pma_fpll_extswitch; + /*input */ logic pld_pma_fpll_lc_csr_test_dis; + /*input */ logic [2:0] pld_pma_fpll_num_phase_shifts; + /*input */ logic pld_pma_fpll_pfden; + /*input */ logic pld_pma_fpll_up_dn_lc_lf_rstn; + /*input */ logic pld_pma_ltd_b; + /*input */ logic pld_pma_nrpi_freeze; + /*input */ logic [1:0] pld_pma_pcie_switch; + /*input */ logic pld_pma_ppm_lock; + /*input */ logic [4:0] pld_pma_reserved_out; + /*input */ logic pld_pma_rs_lpbk_b; + /*input */ logic pld_pma_rxpma_rstb; + /*input */ logic pld_pma_tx_bitslip; + /*input */ logic pld_pma_txdetectrx; + /*input */ logic pld_pma_txpma_rstb; + /*input */ logic pld_pmaif_rxclkslip; + /*input */ logic pld_polinv_rx; + /*input */ logic pld_polinv_tx; + /*input */// logic pld_rx_clk1_rowclk; + /*input */// logic pld_rx_clk2_rowclk; + /*input */ logic pld_rx_dll_lock_req; + /*input */ logic pld_rx_fabric_fifo_align_clr; + /*input */ logic pld_rx_fabric_fifo_rd_en; + /*input */ logic pld_rx_prbs_err_clr; + /*input */ logic pld_sclk1_rowclk; + /*input */ logic pld_sclk2_rowclk; + /*input */ logic pld_syncsm_en; + /*input */ // logic pld_tx_clk1_rowclk; + /*input */ // logic pld_tx_clk2_rowclk; + /*input */ // logic [79:0] pld_tx_fabric_data_in; + /*input */ //logic [PLD_FABRIC_DATA_WIDTH-1:0] pld_tx_fabric_data_in; + /*input */ logic pld_txelecidle; + /*input */ logic pld_tx_dll_lock_req; + /*input */ logic pld_tx_fifo_latency_adj_en; + /*input */ logic pld_rx_fifo_latency_adj_en; + /*input */ logic pld_aib_fabric_rx_dll_lock_req; + /*input */ logic pld_aib_fabric_tx_dcd_cal_req; + /*input */ logic pld_aib_hssi_tx_dcd_cal_req; + /*input */ logic pld_aib_hssi_tx_dll_lock_req; + /*input */ logic pld_aib_hssi_rx_dcd_cal_req; + /*input */ logic [2:0] pld_tx_ssr_reserved_in; + /*input */ logic [1:0] pld_rx_ssr_reserved_in; + /*input */ logic pld_pma_tx_qpi_pulldn; + /*input */ logic pld_pma_tx_qpi_pullup; + /*input */ logic pld_pma_rx_qpi_pullup; + /*input */ logic pld_8g_a1a2_size; + /*input */ logic pld_8g_bitloc_rev_en; + /*input */ logic pld_8g_byte_rev_en; + /*input */ logic [2:0] pld_8g_eidleinfersel; + /*input */ logic pld_8g_encdt; + /*input */ logic [4:0] pld_8g_tx_boundary_sel; + /*input */ logic pld_10g_krfec_rx_clr_errblk_cnt; + /*input */ logic pld_10g_rx_align_clr; + /*input */ logic pld_10g_rx_clr_ber_count; + /*input */ logic [6:0] pld_10g_tx_bitslip; + /*input */ logic pld_10g_tx_burst_en; + /*input */ logic [1:0] pld_10g_tx_diag_status; + /*input */ logic pld_10g_tx_wordslip; + + + // PLD DCM + /*input */ // logic pld_rx_clk1_dcm; + /*input */ // logic pld_tx_clk1_dcm; + /*input */ // logic pld_tx_clk2_dcm; + + /*input */ logic dft_adpt_aibiobsr_fastclkn; + /*input */ logic adapter_scan_rst_n; + /*input */ logic adapter_scan_mode_n; + /*input */ logic adapter_scan_shift_n; + /*input */ logic adapter_scan_shift_clk; + /*input */ logic adapter_scan_user_clk0; + /*input */ logic adapter_scan_user_clk1; + /*input */ logic adapter_scan_user_clk2; + /*input */ logic adapter_scan_user_clk3; + /*input */ logic adapter_clk_sel_n; + /*input */ logic adapter_occ_enable; + /*input */ logic adapter_global_pipe_se; + /*input */ logic [3:0] adapter_config_scan_in; + /*input */ logic [1:0] adapter_scan_in_occ1; + /*input */ logic [4:0] adapter_scan_in_occ2; + /*input */ logic adapter_scan_in_occ3; + /*input */ logic adapter_scan_in_occ4; + /*input */ logic [1:0] adapter_scan_in_occ5; + /*input */ logic [10:0] adapter_scan_in_occ6; + /*input */ logic adapter_scan_in_occ7; + /*input */ logic adapter_scan_in_occ8; + /*input */ logic adapter_scan_in_occ9; + /*input */ logic adapter_scan_in_occ10; + /*input */ logic adapter_scan_in_occ11; + /*input */ logic adapter_scan_in_occ12; + /*input */ logic adapter_scan_in_occ13; + /*input */ logic adapter_scan_in_occ14; + /*input */ logic adapter_scan_in_occ15; + /*input */ logic adapter_scan_in_occ16; + /*input */ logic adapter_scan_in_occ17; + /*input */ logic [1:0] adapter_scan_in_occ18; + /*input */ logic adapter_scan_in_occ19; + /*input */ logic adapter_scan_in_occ20; + /*input */ logic [1:0] adapter_scan_in_occ21; + /*input */ logic adapter_non_occ_scan_in; + /*input */ logic adapter_occ_scan_in; + /*input */ logic [2:0] dft_fabric_iaibdftcore2dll; + + //DFT + /*input */ logic [12:0] oaibdftdll2core; + + //Nadder AIB Signals + /*input */ logic iatpg_pipeline_global_en; + /*input */ logic iatpg_scan_clk_in0; + /*input */ logic iatpg_scan_clk_in1; + /*input */ logic iatpg_scan_in0; + /*input */ logic iatpg_scan_in1; + /*input */ logic iatpg_scan_shift_n; + /*input */ logic iatpg_scan_mode_n; + /*input */ logic iatpg_scan_rst_n; + /*input */ logic ijtag_clkdr_in_chain; + /*input */ logic ijtag_last_bs_in_chain; + /*input */ logic ijtag_tx_scan_in_chain; + /*input */ logic ired_directin_data_in_chain1; + /*input */ logic ired_directin_data_in_chain2; + /*input */ logic [2:0] ired_irxen_in_chain1; + /*input */ logic [2:0] ired_irxen_in_chain2; + /*input */ logic ired_shift_en_in_chain1; + /*input */ logic ired_shift_en_in_chain2; + /*input */ logic jtag_clksel; + /*input */ logic jtag_intest; + /*input */ logic jtag_mode_in; + /*input */ logic jtag_rstb; + /*input */ logic jtag_rstb_en; + /*input */ logic jtag_tx_scanen_in; + /*input */ logic jtag_weakpdn; + /*input */ logic jtag_weakpu; + diff --git a/how2use/sim_sl2ms_lpbk/ndut_default.sv b/how2use/sim_sl2ms_lpbk/ndut_default.sv new file mode 100644 index 0000000..8a5cb6e --- /dev/null +++ b/how2use/sim_sl2ms_lpbk/ndut_default.sv @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + initial + begin + hip_aib_fsr_in[3:0] = 4'b0; + hip_aib_ssr_in[39:0] = 40'h0; + hip_avmm_read = 1'b0; + hip_avmm_reg_addr[20:0] = 21'h0; + hip_avmm_write = 1'b0; + hip_avmm_writedata[7:0] = 8'h0; + + pld_pma_csr_test_dis = 1'b0; + pld_pma_fpll_lc_csr_test_dis = 1'b0; + + ired_directin_data_in_chain1 = 1'b0; + ired_directin_data_in_chain2 = 1'b0; + ired_irxen_in_chain1[2:0] = 3'b0; + ired_irxen_in_chain2[2:0] = 3'b0; + ired_shift_en_in_chain1 = 1'b0; + ired_shift_en_in_chain2 = 1'b0; + +// pld_adapter_tx_pld_rst_n = 1'b1; + pld_adapter_rx_pld_rst_n = 1'b1; + pld_aib_fabric_rx_dll_lock_req = 1'b0; + pld_aib_fabric_tx_dcd_cal_req = 1'b0; + pld_aib_hssi_rx_dcd_cal_req = 1'b0; + pld_aib_hssi_tx_dcd_cal_req = 1'b0; + pld_aib_hssi_tx_dll_lock_req = 1'b0; + + pld_avmm1_request = 1'b0; + pld_avmm1_reserved_in[8:0] = 9'h0; + pld_avmm2_request = 1'b0; + pld_avmm2_reserved_in[9:0] = 10'h0; + + pld_bitslip = 1'b0; + pld_fpll_shared_direct_async_in[1:0] = 2'b0; + pld_fpll_shared_direct_async_in_dcm = 1'b0; + pld_fpll_shared_direct_async_in_rowclk = 1'b0; + pld_ltr = 1'b0; + pld_pcs_rx_pld_rst_n = 1'b0; + pld_pcs_tx_pld_rst_n = 1'b0; + pld_pma_adapt_start = 1'b0; + //pld_pma_coreclkin_rowclk = 1'b0; + pld_pma_csr_test_dis = 1'b0; + pld_pma_early_eios = 1'b0; + pld_pma_eye_monitor[5:0] = 6'b0; + pld_pma_fpll_cnt_sel[3:0] = 4'b0; + pld_pma_fpll_extswitch = 1'b0; + pld_pma_fpll_lc_csr_test_dis = 1'b0; + pld_pma_fpll_num_phase_shifts[2:0] = 3'b0; + pld_pma_fpll_pfden = 1'b0; + pld_pma_fpll_up_dn_lc_lf_rstn = 1'b0; + pld_pma_ltd_b = 1'b0; + //pld_pma_nrpi_freeze = 1'b0; + pld_pma_pcie_switch[1:0] = 1'b0; + pld_pma_ppm_lock = 1'b0; + pld_pma_reserved_out[4:0] = 1'b0; + pld_pma_rs_lpbk_b = 1'b0; + pld_pma_rx_qpi_pullup = 1'b0; + pld_pma_rxpma_rstb = 1'b0; + pld_pma_tx_bitslip = 1'b0; + pld_pma_tx_qpi_pulldn = 1'b0; + pld_pma_txdetectrx = 1'b0; + pld_pma_txpma_rstb = 1'b0; + pld_pmaif_rxclkslip = 1'b0; + pld_polinv_rx = 1'b0; + pld_polinv_tx = 1'b0; + //pld_rx_clk1_dcm = 1'b0; + //pld_rx_clk1_rowclk = 1'b0; + //pld_rx_clk2_rowclk = 1'b0; + pld_rx_dll_lock_req = 1'b0; + pld_rx_fabric_fifo_align_clr = 1'b0; + `ifdef SS_EN_ND_FIFO_ELASTIC_BUF // For Testing ND FIFO Elastic Mode + pld_rx_fabric_fifo_rd_en = 1'b1; + `else + pld_rx_fabric_fifo_rd_en = 1'b0; + `endif + pld_rx_fifo_latency_adj_en = 1'b0; + pld_rx_prbs_err_clr = 1'b0; + pld_rx_ssr_reserved_in[1:0] = 2'b00; //This ensures fifo latency from Adapter is selected rather than xcvrif + //pld_sclk1_rowclk = 1'b0; + //pld_sclk2_rowclk = 1'b0; + pld_syncsm_en = 1'b0; + //pld_tx_clk1_dcm = 1'b0; + //pld_tx_clk1_rowclk = 1'b0; + //pld_tx_clk2_dcm = 1'b0; + //pld_tx_clk2_rowclk = 1'b0; + pld_tx_dll_lock_req = 1'b0; + // pld_tx_fabric_data_in[79:0] = 80'h0; + pld_tx_fifo_latency_adj_en = 1'b0; + pld_tx_ssr_reserved_in[2:0] = 3'b11; + pld_txelecidle = 1'b0; + pr_channel_freeze_n = 1'b1; + + + // + pld_8g_a1a2_size = 1'b0; + pld_8g_bitloc_rev_en = 1'b0; + pld_8g_byte_rev_en = 1'b0; + pld_8g_eidleinfersel[2:0] = 3'h0; + pld_8g_encdt = 1'b0; + pld_8g_tx_boundary_sel[4:0] = 5'h0; + pld_10g_krfec_rx_clr_errblk_cnt = 1'b0; + pld_10g_rx_align_clr = 1'b0; + pld_10g_rx_clr_ber_count = 1'b0; + pld_10g_tx_bitslip[6:0] = 7'h0; + pld_10g_tx_burst_en = 1'b0; + pld_10g_tx_diag_status[1:0] = 1'b0; + pld_10g_tx_wordslip = 1'b0; + +//Added by JZ + pld_avmm1_clk_rowclk = 1'b0; + pld_avmm1_read = 1'b0; + pld_avmm1_reg_addr = 'h0; + pld_avmm1_write = 1'b0; + pld_avmm1_writedata = 'h0; + pld_avmm2_clk_rowclk = 1'b0; + pld_avmm2_read = 1'b0; + pld_avmm2_reg_addr = 'h0; + pld_avmm2_write = 1'b0; + pld_avmm2_writedata = 'h0; + end diff --git a/how2use/sim_sl2ms_lpbk/ndut_io.sv b/how2use/sim_sl2ms_lpbk/ndut_io.sv new file mode 100644 index 0000000..6846600 --- /dev/null +++ b/how2use/sim_sl2ms_lpbk/ndut_io.sv @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +interface ndut_io (); + //Config + /*input */ logic [2:0] csr_config; + /*input */ logic csr_clk_in; // + /*input */ logic [2:0] csr_in; + /*input */ logic [2:0] csr_pipe_in; + /*input */ logic csr_rdy_dly_in; + /*input */ logic csr_rdy_in; + /*input */ logic nfrzdrv_in; + /*input */ logic usermode_in; + + /*input */ logic [3:0] hip_aib_fsr_in; + /*input */ logic [39:0] hip_aib_ssr_in; + /*input */ logic hip_avmm_read; + /*input */ logic [20:0] hip_avmm_reg_addr; + /*input */ logic hip_avmm_write; + /*input */ logic [7:0] hip_avmm_writedata; + /*input */ logic pld_adapter_rx_pld_rst_n; + /*input */ logic pld_adapter_tx_pld_rst_n; + /*input */ logic pld_avmm1_clk_rowclk; + /*input */ logic pld_avmm1_read; + /*input */ logic [9:0] pld_avmm1_reg_addr; + /*input */ logic pld_avmm1_request; + /*input */ logic pld_avmm1_write; + /*input */ logic [7:0] pld_avmm1_writedata; + /*input */ logic [8:0] pld_avmm1_reserved_in; + /*input */ logic pld_avmm2_clk_rowclk; + /*input */ logic pld_avmm2_read; + /*input */ logic [8:0] pld_avmm2_reg_addr; + /*input */ logic pld_avmm2_request; + /*input */ logic pld_avmm2_write; + /*input */ logic [7:0] pld_avmm2_writedata; + /*input */ logic [9:0] pld_avmm2_reserved_in; + /*input */ logic pld_bitslip; + /*input */ logic [1:0] pld_fpll_shared_direct_async_in; + /*input */ logic pld_fpll_shared_direct_async_in_rowclk; + /*input */ logic pld_fpll_shared_direct_async_in_dcm; + /*input */ logic pld_ltr; + /*input */ logic pr_channel_freeze_n; + /*input */ logic pld_pcs_rx_pld_rst_n; + /*input */ logic pld_pcs_tx_pld_rst_n; + /*input */ logic pld_pma_adapt_start; + /*input */ logic pld_pma_coreclkin_rowclk; + /*input */ logic pld_pma_csr_test_dis; + /*input */ logic pld_pma_early_eios; + /*input */ logic [5:0] pld_pma_eye_monitor; + /*input */ logic [3:0] pld_pma_fpll_cnt_sel; + /*input */ logic pld_pma_fpll_extswitch; + /*input */ logic pld_pma_fpll_lc_csr_test_dis; + /*input */ logic [2:0] pld_pma_fpll_num_phase_shifts; + /*input */ logic pld_pma_fpll_pfden; + /*input */ logic pld_pma_fpll_up_dn_lc_lf_rstn; + /*input */ logic pld_pma_ltd_b; + /*input */ logic pld_pma_nrpi_freeze; + /*input */ logic [1:0] pld_pma_pcie_switch; + /*input */ logic pld_pma_ppm_lock; + /*input */ logic [4:0] pld_pma_reserved_out; + /*input */ logic pld_pma_rs_lpbk_b; + /*input */ logic pld_pma_rxpma_rstb; + /*input */ logic pld_pma_tx_bitslip; + /*input */ logic pld_pma_txdetectrx; + /*input */ logic pld_pma_txpma_rstb; + /*input */ logic pld_pmaif_rxclkslip; + /*input */ logic pld_polinv_rx; + /*input */ logic pld_polinv_tx; + /*input */ logic pld_rx_clk1_rowclk; + /*input */ logic pld_rx_clk2_rowclk; + /*input */ logic pld_rx_dll_lock_req; + /*input */ logic pld_rx_fabric_fifo_align_clr; + /*input */ logic pld_rx_fabric_fifo_rd_en; + /*input */ logic pld_rx_prbs_err_clr; + /*input */ logic pld_sclk1_rowclk; + /*input */ logic pld_sclk2_rowclk; + /*input */ logic pld_syncsm_en; + /*input */ logic pld_tx_clk1_rowclk; + /*input */ logic pld_tx_clk2_rowclk; + /*input */ logic [79:0] pld_tx_fabric_data_in; + /*input */ //logic [PLD_FABRIC_DATA_WIDTH-1:0] pld_tx_fabric_data_in; + /*input */ logic pld_txelecidle; + /*input */ logic pld_tx_dll_lock_req; + /*input */ logic pld_tx_fifo_latency_adj_en; + /*input */ logic pld_rx_fifo_latency_adj_en; + /*input */ logic pld_aib_fabric_rx_dll_lock_req; + /*input */ logic pld_aib_fabric_tx_dcd_cal_req; + /*input */ logic pld_aib_hssi_tx_dcd_cal_req; + /*input */ logic pld_aib_hssi_tx_dll_lock_req; + /*input */ logic pld_aib_hssi_rx_dcd_cal_req; + /*input */ logic [2:0] pld_tx_ssr_reserved_in; + /*input */ logic [1:0] pld_rx_ssr_reserved_in; + /*input */ logic pld_pma_tx_qpi_pulldn; + /*input */ logic pld_pma_tx_qpi_pullup; + /*input */ logic pld_pma_rx_qpi_pullup; + /*input */ logic pld_8g_a1a2_size; + /*input */ logic pld_8g_bitloc_rev_en; + /*input */ logic pld_8g_byte_rev_en; + /*input */ logic [2:0] pld_8g_eidleinfersel; + /*input */ logic pld_8g_encdt; + /*input */ logic [4:0] pld_8g_tx_boundary_sel; + /*input */ logic pld_10g_krfec_rx_clr_errblk_cnt; + /*input */ logic pld_10g_rx_align_clr; + /*input */ logic pld_10g_rx_clr_ber_count; + /*input */ logic [6:0] pld_10g_tx_bitslip; + /*input */ logic pld_10g_tx_burst_en; + /*input */ logic [1:0] pld_10g_tx_diag_status; + /*input */ logic pld_10g_tx_wordslip; + + + // PLD DCM + /*input */ logic pld_rx_clk1_dcm; + /*input */ logic pld_tx_clk1_dcm; + /*input */ logic pld_tx_clk2_dcm; + + /*input */ logic dft_adpt_aibiobsr_fastclkn; + /*input */ logic adapter_scan_rst_n; + /*input */ logic adapter_scan_mode_n; + /*input */ logic adapter_scan_shift_n; + /*input */ logic adapter_scan_shift_clk; + /*input */ logic adapter_scan_user_clk0; + /*input */ logic adapter_scan_user_clk1; + /*input */ logic adapter_scan_user_clk2; + /*input */ logic adapter_scan_user_clk3; + /*input */ logic adapter_clk_sel_n; + /*input */ logic adapter_occ_enable; + /*input */ logic adapter_global_pipe_se; + /*input */ logic [3:0] adapter_config_scan_in; + /*input */ logic [1:0] adapter_scan_in_occ1; + /*input */ logic [4:0] adapter_scan_in_occ2; + /*input */ logic adapter_scan_in_occ3; + /*input */ logic adapter_scan_in_occ4; + /*input */ logic [1:0] adapter_scan_in_occ5; + /*input */ logic [10:0] adapter_scan_in_occ6; + /*input */ logic adapter_scan_in_occ7; + /*input */ logic adapter_scan_in_occ8; + /*input */ logic adapter_scan_in_occ9; + /*input */ logic adapter_scan_in_occ10; + /*input */ logic adapter_scan_in_occ11; + /*input */ logic adapter_scan_in_occ12; + /*input */ logic adapter_scan_in_occ13; + /*input */ logic adapter_scan_in_occ14; + /*input */ logic adapter_scan_in_occ15; + /*input */ logic adapter_scan_in_occ16; + /*input */ logic adapter_scan_in_occ17; + /*input */ logic [1:0] adapter_scan_in_occ18; + /*input */ logic adapter_scan_in_occ19; + /*input */ logic adapter_scan_in_occ20; + /*input */ logic [1:0] adapter_scan_in_occ21; + /*input */ logic adapter_non_occ_scan_in; + /*input */ logic adapter_occ_scan_in; + /*input */ logic [2:0] dft_fabric_iaibdftcore2dll; + + //DFT + /*input */ logic [12:0] oaibdftdll2core; + + //Nadder AIB Signals + /*input */ logic iatpg_pipeline_global_en; + /*input */ logic iatpg_scan_clk_in0; + /*input */ logic iatpg_scan_clk_in1; + /*input */ logic iatpg_scan_in0; + /*input */ logic iatpg_scan_in1; + /*input */ logic iatpg_scan_shift_n; + /*input */ logic iatpg_scan_mode_n; + /*input */ logic iatpg_scan_rst_n; + /*input */ logic ijtag_clkdr_in_chain; + /*input */ logic ijtag_last_bs_in_chain; + /*input */ logic ijtag_tx_scan_in_chain; + /*input */ logic ired_directin_data_in_chain1; + /*input */ logic ired_directin_data_in_chain2; + /*input */ logic [2:0] ired_irxen_in_chain1; + /*input */ logic [2:0] ired_irxen_in_chain2; + /*input */ logic ired_shift_en_in_chain1; + /*input */ logic ired_shift_en_in_chain2; + /*input */ logic jtag_clksel; + /*input */ logic jtag_intest; + /*input */ logic jtag_mode_in; + /*input */ logic jtag_rstb; + /*input */ logic jtag_rstb_en; + /*input */ logic jtag_tx_scanen_in; + /*input */ logic jtag_weakpdn; + /*input */ logic jtag_weakpu; + + +endinterface // ndut_io diff --git a/how2use/sim_sl2ms_lpbk/redundancy_ctrl_sim.vh b/how2use/sim_sl2ms_lpbk/redundancy_ctrl_sim.vh new file mode 100644 index 0000000..2254fb4 --- /dev/null +++ b/how2use/sim_sl2ms_lpbk/redundancy_ctrl_sim.vh @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//Redundancy control inputs signals +//All the inputs tied to "0" are for no repaire + //example of repairing setting for tx[16] in master + //master //slave + .shift_en_tx({(DATAWIDTH/4){4'h0}}), //20'h0ffff //{(DATAWIDTH/4){4'h0}} + .shift_en_rx({(DATAWIDTH/4){4'h0}}), //{(DATAWIDTH/4){4'h0}} //20'h0ffff + .shift_en_txclkb(1'b0), //1'b1 //1'b0 + .shift_en_txfckb(1'b0), //1'b1 //1'b0 + .shift_en_stckb(1'b0), //1'b1 //1'b0 + .shift_en_stl(1'b0), //1'b1 //1'b0 + .shift_en_arstno(1'b0), //1'b1 //1'b0 + .shift_en_txclk(1'b0), //1'b1 //1'b0 + .shift_en_std(1'b0), //1'b1 //1'b0 + .shift_en_stck(1'b0), //1'b1 //1'b0 + .shift_en_txfck(1'b0), //1'b1 //1'b0 + .shift_en_rstno(1'b0), //1'b1 //1'b0 + .shift_en_rxclkb(1'b0), //1'b0 //1'b1 + .shift_en_rxfckb(1'b0), //1'b0 //1'b1 + .shift_en_srckb(1'b0), //1'b0 //1'b1 + .shift_en_srl(1'b0), //1'b0 //1'b1 + .shift_en_arstni(1'b0), //1'b0 //1'b1 + .shift_en_rxclk(1'b0), //1'b0 //1'b1 + .shift_en_rxfck(1'b0), //1'b0 //1'b1 + .shift_en_srck(1'b0), //1'b0 //1'b1 + .shift_en_srd(1'b0), //1'b0 //1'b1 + .shift_en_rstni(1'b0), //1'b0 //1'b1 + diff --git a/how2use/sim_sl2ms_lpbk/runnc b/how2use/sim_sl2ms_lpbk/runnc new file mode 100644 index 0000000..6e35b47 --- /dev/null +++ b/how2use/sim_sl2ms_lpbk/runnc @@ -0,0 +1,3 @@ +rm -rf INCA_libs + +irun -sv -timescale 1ps/1ps -f ./multidie.f ./top.sv ./dut_io.sv ./test.sv -vlog_ext +.vh +define+TIMESCALE_EN+ALTR_HPS_INTEL_MACROS_OFF -access rwc -input sim_input.tcl diff --git a/how2use/sim_sl2ms_lpbk/runsim b/how2use/sim_sl2ms_lpbk/runsim new file mode 100644 index 0000000..6be7c9f --- /dev/null +++ b/how2use/sim_sl2ms_lpbk/runsim @@ -0,0 +1,3 @@ +#!/bin/csh -fb +rm -rf csrc simv simv.daidir +vcs -sverilog +v2k -full64 +vcs+vcdpluson -timescale=1ps/1ps +define+VCS+TIMESCALE_EN+ALTR_HPS_INTEL_MACROS_OFF -f ./multidie.f ./top.sv ./dut_io.sv ./test.sv -l compile.log diff --git a/how2use/sim_sl2ms_lpbk/runvsim b/how2use/sim_sl2ms_lpbk/runvsim new file mode 100644 index 0000000..6b0060a --- /dev/null +++ b/how2use/sim_sl2ms_lpbk/runvsim @@ -0,0 +1,22 @@ +echo "Cleaning old files" +#ls | grep -v *.sh | xargs rm -rf +rm -rf work/ transcript *.bsf *.qip *.wlf *~cd + +echo "executing self_test.do" +vsim -t 1ps -c -do self_test.do >> sim.log + +p=`grep "PASSED" sim.log` +# echo $p8l6g + +if [ "$p" = "" ] + then + echo "Failed" + exit 66 +else + + echo "PASSED" + echo "PASSED" >> reg.rout + +fi + + diff --git a/how2use/sim_sl2ms_lpbk/self_test.do b/how2use/sim_sl2ms_lpbk/self_test.do new file mode 100644 index 0000000..bb2ddbf --- /dev/null +++ b/how2use/sim_sl2ms_lpbk/self_test.do @@ -0,0 +1,8 @@ +onerror resume +vlib work +do vlog.do +vsim -t 1ps top +add log -r vsim:/top/* +add wave dut/* +run -a +quit diff --git a/how2use/sim_sl2ms_lpbk/sim_input.tcl b/how2use/sim_sl2ms_lpbk/sim_input.tcl new file mode 100644 index 0000000..518d38b --- /dev/null +++ b/how2use/sim_sl2ms_lpbk/sim_input.tcl @@ -0,0 +1,4 @@ +database -shm -default sim_waveform +probe -shm top -depth all -all -memories +run + diff --git a/how2use/sim_sl2ms_lpbk/test.sv b/how2use/sim_sl2ms_lpbk/test.sv new file mode 100644 index 0000000..c568929 --- /dev/null +++ b/how2use/sim_sl2ms_lpbk/test.sv @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +program automatic test (dut_io.TB dut); + + int err_count; + int run_for_n_pkts; + int run_for_n_wa_cycle; + + logic [39:0] xmit_q [$]; + logic [31:0] read_data_reg; + + // Main + + initial + begin + // $vpdpluson; + run_for_n_pkts = 10; + reset_sequence (); + +// wait_xfer_ready (); + // $display ("[%t] Xfer Ready", $time); + // $display ("[%t] start AIB chiplet standalone loopback testing by running %d packets", $time, run_for_n_pkts); + // init_wa_toggle (); + // fork + // data_xmit (); + // data_rcv (); + // join +// $display ("[%t] ######### Debug: All Tasks are finished normally #############", $time); + //if (slv_sb.is_empty ()) + //configuration_read; +// Finish (); + #10000ns; + end + + //****************************************************************************** + // Reset Tasks + //****************************************************************************** + task reset_sequence (); + int random_dly_cycle; + + begin + dut.i_adpt_hard_rst_n <= 1'b0; + dut.i_cfg_avmm_rst_n <= 1'b0; + dut.ns_mac_rdy <= 1'b0; + + err_count <= 0; + + //cfg_avmm_clk domain + dut.cb_cfg_avmm.i_channel_id <= 0; + dut.cb_cfg_avmm.i_cfg_avmm_write <= 0; + dut.cb_cfg_avmm.i_cfg_avmm_read <= 0; + dut.cb_cfg_avmm.i_cfg_avmm_addr <= 0; + dut.cb_cfg_avmm.i_cfg_avmm_byte_en<= 0; + dut.cb_cfg_avmm.i_cfg_avmm_wdata <= 0; + dut.cb_cfg_avmm.i_adpt_cfg_rdatavld <= 0; + dut.cb_cfg_avmm.i_adpt_cfg_rdata <= 0; + dut.cb_cfg_avmm.i_adpt_cfg_waitreq <= 0; + + + // cb_rx_pma + dut.cb_rx_pma.i_rx_pma_data <= 0; + + // cb_osc + dut.cb_osc.i_chnl_ssr <= 0; + + $display("\n////////////////////////////////////////////////////////////////////////////"); + $display("%0t: System Reset", $time); + $display("////////////////////////////////////////////////////////////////////////////\n"); + random_dly_cycle = ({$random} % 50) + 5; + repeat (random_dly_cycle) @ (posedge top.i_osc_clk); + $display("%0t: %m: de-asserting configuration reset and start configuration setup", $time); + dut.i_cfg_avmm_rst_n <= 1'b1; + configuration_setup(); + $display ("[%t] Done configuration", $time); + dut.ns_mac_rdy <= 1'b1; + $display ("[%t] ns_mac_rdy is up. Clock should be stable prior to this", $time); + repeat (random_dly_cycle) @ (posedge top.i_cfg_avmm_clk); + dut.i_adpt_hard_rst_n <= 1'b1; + $display("%0t: %m: de-asserting adapter hard reset", $time); + + // + random_dly_cycle = ({$random} % 50) + 5; + repeat (10*random_dly_cycle) @ (posedge top.i_osc_clk); + + end + endtask // Reset + + task cfg_avmm_write (input [10:0] addr, + input [ 3:0] be, + input [31:0] wdata + ); + begin + @(posedge top.i_cfg_avmm_clk); + dut.cb_cfg_avmm.i_cfg_avmm_write <= 1'b1; + dut.cb_cfg_avmm.i_cfg_avmm_addr <= {6'h0, addr}; + dut.cb_cfg_avmm.i_cfg_avmm_byte_en <= be; + dut.cb_cfg_avmm.i_cfg_avmm_wdata <= wdata; + repeat (3) @(posedge top.i_cfg_avmm_clk); + dut.cb_cfg_avmm.i_cfg_avmm_write <= 1'b0; + end + + endtask +/* + task cfg_avmm_read (input [10:0] addr, + input [ 3:0] be, + output [31:0] rdata + ); + begin + @(posedge top.i_cfg_avmm_clk); + dut.cb_cfg_avmm.i_cfg_avmm_read <= 1'b1; + dut.cb_cfg_avmm.i_cfg_avmm_addr <= {6'h0, addr}; + dut.cb_cfg_avmm.i_cfg_avmm_byte_en <= be; + repeat (3) @(posedge top.i_cfg_avmm_clk); + @(posedge top.o_cfg_avmm_rdatavld); + rdata = top.o_cfg_avmm_rdata; + $display("READ_MM: address %x = %x", addr, rdata); + @(negedge top.o_cfg_avmm_rdatavld); + dut.cb_cfg_avmm.i_cfg_avmm_read <= 1'b0; + end + + endtask +*/ + + task cfg_avmm_read (input [10:0] addr, + input [ 3:0] be, + output [31:0] rdata + ); + begin + @(posedge top.i_cfg_avmm_clk); + dut.cb_cfg_avmm.i_cfg_avmm_read <= 1'b1; + dut.cb_cfg_avmm.i_cfg_avmm_addr <= {6'h0, addr}; + dut.cb_cfg_avmm.i_cfg_avmm_byte_en <= be; + repeat (3) @(posedge top.i_cfg_avmm_clk); + @(posedge top.o_cfg_avmm_rdatavld); + rdata = top.o_cfg_avmm_rdata; + $display("READ_MM: address %x = %x", addr, rdata); +// @(negedge top.o_cfg_avmm_rdatavld); + dut.cb_cfg_avmm.i_cfg_avmm_read <= 1'b0; + end + + endtask + + + //************************************************ + // task to setup the configuration + //************************************************ + task configuration_setup; + begin + repeat (10) @(posedge top.i_cfg_avmm_clk); //wait some clock cycles for adapter to be stable + //configuration_read; + cfg_avmm_write(11'h204, 4'hf, 32'h0000_0000); + cfg_avmm_write(11'h208, 4'hf, 32'h0278_0204); + cfg_avmm_write(11'h20c, 4'hf, 32'h0000_0282); + cfg_avmm_write(11'h210, 4'hf, 32'h0287_1f00); + cfg_avmm_write(11'h214, 4'hf, 32'h0000_80c3); + cfg_avmm_write(11'h218, 4'hf, 32'h4700_8004); +// cfg_avmm_write(11'h21c, 4'hf, 32'h0000_0024); + cfg_avmm_write(11'h21c, 4'hf, 32'h0100_c024); //turn on bit 24 for enable aib_lpbk_mode, bit 15:14 if 1, 1x mode, if 2, 2xmode, 3, loopback before tx fifo. + cfg_avmm_write(11'h220, 4'hf, 32'he388_c00a); + cfg_avmm_write(11'h224, 4'hf, 32'h3014_7f38); //bit 18:16 is rx_fifo_rd_clk_sel[2:0] here to set 4 so that tx_aib_transfer_clk is selected. + cfg_avmm_write(11'h228, 4'hf, 32'h0000_7451); + cfg_avmm_write(11'h22c, 4'hf, 32'h0000_0000); +// cfg_avmm_write(11'h230, 4'hf, 32'h38f6_007b); + cfg_avmm_write(11'h230, 4'hf, 32'h20f6_047b); //DLL bypass, disable + cfg_avmm_write(11'h234, 4'hf, 32'h0000_0000); + cfg_avmm_write(11'h238, 4'hf, 32'h0000_0000); + cfg_avmm_write(11'h23c, 4'hf, 32'h0000_0000); + cfg_avmm_write(11'h240, 4'hf, 32'h0000_0000); + cfg_avmm_write(11'h2fc, 4'hf, 32'h000f_0000); + cfg_avmm_write(11'h300, 4'hf, 32'h0000_0000); + cfg_avmm_write(11'h304, 4'hf, 32'h0000_0000); + cfg_avmm_write(11'h308, 4'hf, 32'h0000_0000); + cfg_avmm_write(11'h30c, 4'hf, 32'h0000_0000); + cfg_avmm_write(11'h310, 4'hf, 32'h000f_0000); +// cfg_avmm_write(11'h314, 4'hf, 32'h0000_000e); + cfg_avmm_write(11'h314, 4'hf, 32'h0000_0000); //turn off sr_reserved_in_en/out_en sr_parity_en for spec compliance + cfg_avmm_write(11'h318, 4'hf, 32'h0010_0f86); + cfg_avmm_write(11'h31c, 4'hf, 32'h0000_0f80); + cfg_avmm_write(11'h320, 4'hf, 32'h0000_0000); + cfg_avmm_write(11'h324, 4'hf, 32'h0000_0000); + cfg_avmm_write(11'h328, 4'hf, 32'h0000_0000); + cfg_avmm_write(11'h32c, 4'hf, 32'h5555_a019); + + cfg_avmm_write(11'h330, 4'hf, 32'h0040_0082); + // cfg_avmm_write(11'h334, 4'hf, 32'hbf0f_b000); + cfg_avmm_write(11'h334, 4'hf, 32'hbf0f_9000); //DCC bypass + cfg_avmm_write(11'h338, 4'hf, 32'h0002_a9e1); + cfg_avmm_write(11'h33c, 4'hf, 32'h00ff_fff0); + cfg_avmm_write(11'h340, 4'hf, 32'h7f1c_0000); + cfg_avmm_write(11'h344, 4'hf, 32'h0000_1c00); + cfg_avmm_write(11'h348, 4'hf, 32'h0000_0000); + cfg_avmm_write(11'h34c, 4'hf, 32'h0000_0000); + cfg_avmm_write(11'h350, 4'hf, 32'h0000_0000); + cfg_avmm_write(11'h354, 4'hf, 32'h0000_0000); + + end + endtask + + task config_unuse_pin; + begin + repeat (10) @(posedge top.i_cfg_avmm_clk); + // cfg_avmm_write(11'h32c, 4'hf, 32'h5555_a099); //Disable AIB 45 set irx_en[2:0] = 3'b010; 32c bit [7] + cfg_avmm_write(11'h334, 4'hf, 32'hbf0d_b000); //Disable AIB 46 set tx_en = 1'b0; bit 17 + end + endtask + + //************************************************ + // task to read back the configuration + //************************************************ + task configuration_read; + begin + repeat (10) @(posedge top.i_cfg_avmm_clk); //wait some clock cycles for adapter to be stable + cfg_avmm_read(11'h204, 4'hf, read_data_reg); + cfg_avmm_read(11'h208, 4'hf, read_data_reg); + cfg_avmm_read(11'h20c, 4'hf, read_data_reg); + cfg_avmm_read(11'h210, 4'hf, read_data_reg); + cfg_avmm_read(11'h214, 4'hf, read_data_reg); + cfg_avmm_read(11'h218, 4'hf, read_data_reg); + cfg_avmm_read(11'h21c, 4'hf, read_data_reg); + cfg_avmm_read(11'h220, 4'hf, read_data_reg); + cfg_avmm_read(11'h22c, 4'hf, read_data_reg); + cfg_avmm_read(11'h304, 4'hf, read_data_reg); + cfg_avmm_write(11'h304, 4'hf, 32'hf537bbfa); + cfg_avmm_read(11'h304, 4'hf, read_data_reg); + end + endtask + + +endprogram // test + diff --git a/how2use/sim_sl2ms_lpbk/top.sv b/how2use/sim_sl2ms_lpbk/top.sv new file mode 100644 index 0000000..aaf2f06 --- /dev/null +++ b/how2use/sim_sl2ms_lpbk/top.sv @@ -0,0 +1,407 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +`timescale 1ps/1fs + +`define NDADAPT_RTB top.s10_wrap.ndut.hdpldadapt +`include "c3dfx.vh" + +module top; + + + //------------------------------------------------------------------------------------------ + // Clock generation + + parameter CFG_AVMM_CLK_PERIOD = 4000; + parameter OSC_CLK_PERIOD = 1000; + parameter PMA_CLK_PERIOD = 1000; + parameter USR_CLK_PERIOD = 5000; + parameter FWD_CLK_PERIOD = 2500; + + reg i_cfg_avmm_clk = 1'b0; + reg i_osc_clk = 1'b0; + reg i_rx_pma_clk = 1'b0; + reg i_rx_pma_div2_clk = 1'b0; + reg i_tx_pma_clk = 1'b0; + reg tx_coreclkin = 1'b0; + reg rx_coreclkin = 1'b0; + reg sl_m_ns_fwd_clk = 1'b0; + + //clock gen + always #(CFG_AVMM_CLK_PERIOD/2) i_cfg_avmm_clk = ~i_cfg_avmm_clk; + always #(OSC_CLK_PERIOD/2) i_osc_clk = ~i_osc_clk; +// always #(PMA_CLK_PERIOD/2) i_rx_pma_clk = ~i_rx_pma_clk; +// always #(PMA_CLK_PERIOD) i_rx_pma_div2_clk = ~i_rx_pma_div2_clk; +// always #(PMA_CLK_PERIOD/2) i_tx_pma_clk = ~i_tx_pma_clk; + + //================================================================================= + //Below are DFx related signals, temporarily tie them off to 0s, need to be changed later + logic [79:0] tx_parallel_data = 0; + logic [79:0] rx_parallel_data; + + always #(USR_CLK_PERIOD/2) tx_coreclkin = ~tx_coreclkin; + always #(USR_CLK_PERIOD/2) rx_coreclkin = ~rx_coreclkin; + always #(FWD_CLK_PERIOD/2) sl_m_ns_fwd_clk = ~sl_m_ns_fwd_clk; + int run_for_n_pkts; + logic [79:0] xmit_q [$]; + int err_count; + logic i_scan_clk, + i_test_clk_125m, + i_test_clk_1g, + i_test_clk_250m, + i_test_clk_500m, + i_test_clk_62m; + + logic [`AIBADAPTWRAPTCB_SCAN_CHAINS_RNG] i_test_c3adapt_scan_in; + logic [`AIBADAPTWRAPTCB_STATIC_COMMON_RNG] i_test_c3adapt_tcb_static_common; + logic [`AIBADAPTWRAPTCB_SCAN_CHAINS_RNG] o_test_c3adapt_scan_out; + logic [`AIBADAPTWRAPTCB_JTAG_OUT_RNG] o_test_c3adapttcb_jtag; + + logic i_jtag_rstb_in, + i_jtag_rstb_en_in, + i_jtag_clkdr_in, + i_jtag_clksel_in, + i_jtag_intest_in, + i_jtag_mode_in, + i_jtag_weakpdn_in, + i_jtag_weakpu_in, + i_jtag_bs_scanen_in, + i_jtag_bs_chain_in, + i_jtag_last_bs_chain_in, + i_por_aib_vcchssi, + i_por_aib_vccl, + i_red_idataselb_in_chain1, + i_red_idataselb_in_chain2, + i_red_shift_en_in_chain1, + i_red_shift_en_in_chain2, + i_txen_in_chain1, + i_txen_in_chain2, + i_directout_data_chain1_in, + i_directout_data_chain2_in; + + + initial begin + i_scan_clk = 1'b0; + i_test_clk_125m = 1'b0; + i_test_clk_1g = 1'b0; + i_test_clk_250m = 1'b0; + i_test_clk_500m = 1'b0; + i_test_clk_62m = 1'b0; + + i_jtag_rstb_in = 1'b0; + i_jtag_rstb_en_in = 1'b0; + i_jtag_clkdr_in = 1'b0; + i_jtag_clksel_in = 1'b0; + i_jtag_intest_in = 1'b0; + i_jtag_mode_in = 1'b0; + i_jtag_weakpdn_in = 1'b0; + i_jtag_weakpu_in = 1'b0; + i_jtag_bs_scanen_in = 1'b0; + i_jtag_bs_chain_in = 1'b0; + i_jtag_last_bs_chain_in = 0; + i_por_aib_vcchssi = 1'b0; + i_por_aib_vccl = 1'b0; + i_red_idataselb_in_chain1 = 1'b0; + i_red_idataselb_in_chain2 = 1'b0; + i_red_shift_en_in_chain1 = 1'b0; + i_red_shift_en_in_chain2 = 1'b0; + i_txen_in_chain1 = 1'b0; + i_txen_in_chain2 = 1'b0; + i_directout_data_chain1_in = 1'b0; + i_directout_data_chain2_in = 1'b0; + i_test_c3adapt_scan_in = 0; + i_test_c3adapt_tcb_static_common = 0; + + end // initial begin + + //================================================================================= + // AIB IOs + wire[19:0] ms_iopad_tx; + wire[19:0] ms_iopad_rx; + wire ms_iopad_ns_fwd_clkb; + wire ms_iopad_ns_fwd_clk; + wire ms_iopad_fs_fwd_clkb; + wire ms_iopad_fs_fwd_clk; + wire ms_iopad_fs_mac_rdy; + wire ms_iopad_ns_mac_rdy; + wire ms_iopad_ns_adapter_rstn; + wire ms_iopad_fs_rcv_clk; + wire ms_iopad_fs_rcv_clkb; + wire ms_iopad_fs_adapter_rstn; + wire ms_iopad_fs_sr_clkb; + wire ms_iopad_fs_sr_clk; + wire ms_iopad_ns_sr_clk; + wire ms_iopad_ns_sr_clkb; + wire ms_iopad_ns_rcv_clkb; + wire ms_iopad_ns_rcv_clk; + wire ms_iopad_fs_sr_load; + wire ms_iopad_fs_sr_data; + wire ms_iopad_ns_sr_load; + wire ms_iopad_ns_sr_data; + wire iopad_unused_aib45; + wire iopad_unused_aib46; + wire iopad_unused_aib47; + wire iopad_unused_aib50; + wire iopad_unused_aib51; + wire iopad_unused_aib52; + wire iopad_unused_aib58; + wire iopad_unused_aib60; + wire iopad_unused_aib61; + wire iopad_unused_aib62; + wire iopad_unused_aib63; + wire iopad_unused_aib64; + wire iopad_unused_aib66; + wire iopad_unused_aib67; + wire iopad_unused_aib68; + wire iopad_unused_aib69; + wire iopad_unused_aib70; + wire iopad_unused_aib71; + wire iopad_unused_aib72; + wire iopad_unused_aib73; + wire iopad_unused_aib74; + wire iopad_unused_aib75; + wire iopad_unused_aib76; + wire iopad_unused_aib77; + wire iopad_unused_aib78; + wire iopad_unused_aib79; + wire iopad_unused_aib80; + wire iopad_unused_aib81; + wire iopad_unused_aib88; + wire iopad_unused_aib89; + wire iopad_unused_aib90; + wire iopad_unused_aib91; + + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [16:0] o_adpt_cfg_addr; // From dut of c3aibadapt_wrap.v + wire [3:0] o_adpt_cfg_byte_en; // From dut of c3aibadapt_wrap.v + wire o_adpt_cfg_clk; // From dut of c3aibadapt_wrap.v + wire o_adpt_cfg_read; // From dut of c3aibadapt_wrap.v + wire o_adpt_cfg_rst_n; // From dut of c3aibadapt_wrap.v + wire [31:0] o_adpt_cfg_wdata; // From dut of c3aibadapt_wrap.v + wire o_adpt_cfg_write; // From dut of c3aibadapt_wrap.v + wire o_adpt_hard_rst_n; // From dut of c3aibadapt_wrap.v + wire [12:0] o_aibdftdll2adjch; // From dut of c3aibadapt_wrap.v + wire [31:0] o_cfg_avmm_rdata; // From dut of c3aibadapt_wrap.v + wire o_cfg_avmm_rdatavld; // From dut of c3aibadapt_wrap.v + wire o_cfg_avmm_waitreq; // From dut of c3aibadapt_wrap.v + wire [60:0] o_chnl_ssr; // From dut of c3aibadapt_wrap.v + wire o_directout_data_chain1_out;// From dut of c3aibadapt_wrap.v + wire o_directout_data_chain2_out;// From dut of c3aibadapt_wrap.v + wire [2:0] o_ehip_init_status; // From dut of c3aibadapt_wrap.v + wire o_jtag_bs_chain_out; // From dut of c3aibadapt_wrap.v + wire o_jtag_bs_scanen_out; // From dut of c3aibadapt_wrap.v + wire o_jtag_clkdr_out; // From dut of c3aibadapt_wrap.v + wire o_jtag_clksel_out; // From dut of c3aibadapt_wrap.v + wire o_jtag_intest_out; // From dut of c3aibadapt_wrap.v + wire o_jtag_last_bs_chain_out;// From dut of c3aibadapt_wrap.v + wire o_jtag_mode_out; // From dut of c3aibadapt_wrap.v + wire o_jtag_rstb_en_out; // From dut of c3aibadapt_wrap.v + wire o_jtag_rstb_out; // From dut of c3aibadapt_wrap.v + wire o_jtag_weakpdn_out; // From dut of c3aibadapt_wrap.v + wire o_jtag_weakpu_out; // From dut of c3aibadapt_wrap.v + wire o_osc_clk; // From dut of c3aibadapt_wrap.v + wire o_por_aib_vcchssi; // From dut of c3aibadapt_wrap.v + wire o_por_aib_vccl; // From dut of c3aibadapt_wrap.v + wire o_red_idataselb_out_chain1;// From dut of c3aibadapt_wrap.v + wire o_red_idataselb_out_chain2;// From dut of c3aibadapt_wrap.v + wire o_red_shift_en_out_chain1;// From dut of c3aibadapt_wrap.v + wire o_red_shift_en_out_chain2;// From dut of c3aibadapt_wrap.v + wire o_rx_xcvrif_rst_n; // From dut of c3aibadapt_wrap.v + wire [39:0] o_tx_pma_data; // From dut of c3aibadapt_wrap.v + wire o_tx_transfer_clk; // From dut of c3aibadapt_wrap.v + wire o_tx_transfer_div2_clk; // From dut of c3aibadapt_wrap.v + wire o_tx_xcvrif_rst_n; // From dut of c3aibadapt_wrap.v + wire o_txen_out_chain1; // From dut of c3aibadapt_wrap.v + wire o_txen_out_chain2; // From dut of c3aibadapt_wrap.v + wire HI; + wire LO; + wire [80:0] ms_sideband; + wire [72:0] sl_sideband; + // End of automatics + + //----------------------------------------------------------------------------------------- + // Interface instantiation + + dut_io top_io (.i_osc_clk (i_osc_clk), + .i_rx_pma_clk (i_rx_pma_clk), + .i_tx_pma_clk (i_tx_pma_clk), + .i_cfg_avmm_clk (i_cfg_avmm_clk) + ); +// ndut_io maib_io (); + + //----------------------------------------------------------------------------------------- + // Testbench instantiation + test t (top_io); + + //----------------------------------------------------------------------------------------- + // DUT instantiation + + c3aib_master dut (/*AUTOINST*/ + // Outputs + .o_adpt_hard_rst_n (o_adpt_hard_rst_n), + .fs_mac_rdy (o_rx_xcvrif_rst_n), + .o_tx_xcvrif_rst_n (o_tx_xcvrif_rst_n), + .sl_tx_transfer_en (o_ehip_init_status[0]), + .ms_tx_transfer_en (o_ehip_init_status[1]), + .ms_osc_transfer_alive (o_ehip_init_status[2]), + .o_cfg_avmm_rdatavld (o_cfg_avmm_rdatavld), + .o_cfg_avmm_rdata (o_cfg_avmm_rdata[31:0]), + .o_cfg_avmm_waitreq (o_cfg_avmm_waitreq), + .o_adpt_cfg_clk (o_adpt_cfg_clk), + .o_adpt_cfg_rst_n (o_adpt_cfg_rst_n), + .o_adpt_cfg_addr (o_adpt_cfg_addr[16:0]), + .o_adpt_cfg_byte_en (o_adpt_cfg_byte_en[3:0]), + .o_adpt_cfg_read (o_adpt_cfg_read), + .o_adpt_cfg_write (o_adpt_cfg_write), + .o_adpt_cfg_wdata (o_adpt_cfg_wdata[31:0]), + .o_osc_clk (o_osc_clk), + .o_chnl_ssr (o_chnl_ssr[60:0]), + .m_fs_fwd_clk (o_tx_transfer_clk), + .m_fs_fwd_div2_clk (o_tx_transfer_div2_clk), + .data_out (o_tx_pma_data[39:0]), + .ns_mac_rdy (top_io.ns_mac_rdy), + .ms_sideband (ms_sideband), + .sl_sideband (sl_sideband), + .o_test_c3adapt_scan_out(o_test_c3adapt_scan_out[`AIBADAPTWRAPTCB_SCAN_CHAINS_RNG]), + .o_test_c3adapttcb_jtag(o_test_c3adapttcb_jtag[`AIBADAPTWRAPTCB_JTAG_OUT_RNG]), + .o_jtag_clkdr_out (o_jtag_clkdr_out), + .o_jtag_clksel_out (o_jtag_clksel_out), + .o_jtag_intest_out (o_jtag_intest_out), + .o_jtag_mode_out (o_jtag_mode_out), + .o_jtag_rstb_en_out (o_jtag_rstb_en_out), + .o_jtag_rstb_out (o_jtag_rstb_out), + .o_jtag_weakpdn_out (o_jtag_weakpdn_out), + .o_jtag_weakpu_out (o_jtag_weakpu_out), + .o_jtag_bs_chain_out (o_jtag_bs_chain_out), + .o_jtag_bs_scanen_out (o_jtag_bs_scanen_out), + .o_jtag_last_bs_chain_out(o_jtag_last_bs_chain_out), + .o_por_aib_vcchssi (o_por_aib_vcchssi), + .o_por_aib_vccl (o_por_aib_vccl), + .o_red_idataselb_out_chain1(o_red_idataselb_out_chain1), + .o_red_idataselb_out_chain2(o_red_idataselb_out_chain2), + .o_red_shift_en_out_chain1(o_red_shift_en_out_chain1), + .o_red_shift_en_out_chain2(o_red_shift_en_out_chain2), + .o_txen_out_chain1 (o_txen_out_chain1), + .o_txen_out_chain2 (o_txen_out_chain2), + .o_directout_data_chain1_out(o_directout_data_chain1_out), + .o_directout_data_chain2_out(o_directout_data_chain2_out), + .o_aibdftdll2adjch (o_aibdftdll2adjch[12:0]), + // Inouts + .iopad_tx (ms_iopad_tx), + .iopad_rx (ms_iopad_rx), + .iopad_ns_fwd_clkb (ms_iopad_ns_fwd_clkb), + .iopad_ns_fwd_clk (ms_iopad_ns_fwd_clk), + .iopad_ns_fwd_div2_clkb(ms_iopad_ns_fwd_div2_clkb), + .iopad_ns_fwd_div2_clk (ms_iopad_ns_fwd_div2_clk), + .iopad_fs_fwd_clkb (ms_iopad_fs_fwd_clkb), + .iopad_fs_fwd_clk (ms_iopad_fs_fwd_clk), + .iopad_fs_mac_rdy (ms_iopad_fs_mac_rdy), + .iopad_ns_mac_rdy (ms_iopad_ns_mac_rdy), + .iopad_ns_adapter_rstn (ms_iopad_ns_adapter_rstn), + .iopad_fs_rcv_clk (ms_iopad_fs_rcv_clk), + .iopad_fs_rcv_clkb (ms_iopad_fs_rcv_clkb), + .iopad_fs_adapter_rstn (ms_iopad_fs_adapter_rstn), + .iopad_fs_sr_clkb (ms_iopad_fs_sr_clkb), + .iopad_fs_sr_clk (ms_iopad_fs_sr_clk), + .iopad_ns_sr_clk (ms_iopad_ns_sr_clk), + .iopad_ns_sr_clkb (ms_iopad_ns_sr_clkb), + .iopad_ns_rcv_clkb (ms_iopad_ns_rcv_clkb), + .iopad_ns_rcv_clk (ms_iopad_ns_rcv_clk), + .iopad_ns_rcv_div2_clkb(ms_iopad_ns_rcv_div2_clkb), + .iopad_ns_rcv_div2_clk (ms_iopad_ns_rcv_div2_clk), + .iopad_fs_sr_load (ms_iopad_fs_sr_load), + .iopad_fs_sr_data (ms_iopad_fs_sr_data), + .iopad_ns_sr_load (ms_iopad_ns_sr_load), + .iopad_ns_sr_data (ms_iopad_ns_sr_data), + .iopad_unused_aib45, + .iopad_unused_aib46, + .iopad_unused_aib47, + .iopad_unused_aib50, + .iopad_unused_aib51, + .iopad_unused_aib52, + .iopad_unused_aib58, + .iopad_unused_aib60, + .iopad_unused_aib61, + .iopad_unused_aib62, + .iopad_unused_aib63, + .iopad_unused_aib64, + .iopad_unused_aib66, + .iopad_unused_aib67, + .iopad_unused_aib68, + .iopad_unused_aib69, + .iopad_unused_aib70, + .iopad_unused_aib71, + .iopad_unused_aib72, + .iopad_unused_aib73, + .iopad_unused_aib74, + .iopad_unused_aib75, + .iopad_unused_aib76, + .iopad_unused_aib77, + .iopad_unused_aib78, + .iopad_unused_aib79, + .iopad_unused_aib80, + .iopad_unused_aib81, + .iopad_unused_aib88, + .iopad_unused_aib89, + .iopad_unused_aib90, + .iopad_unused_aib91, + + // Inputs + .i_adpt_hard_rst_n (top_io.i_adpt_hard_rst_n), + .i_channel_id (top_io.i_channel_id[5:0]), + .i_cfg_avmm_clk (i_cfg_avmm_clk), + .i_cfg_avmm_rst_n (top_io.i_cfg_avmm_rst_n), + .i_cfg_avmm_addr (top_io.i_cfg_avmm_addr[16:0]), + .i_cfg_avmm_byte_en (top_io.i_cfg_avmm_byte_en[3:0]), + .i_cfg_avmm_read (top_io.i_cfg_avmm_read), + .i_cfg_avmm_write (top_io.i_cfg_avmm_write), + .i_cfg_avmm_wdata (top_io.i_cfg_avmm_wdata[31:0]), + .i_adpt_cfg_rdatavld (top_io.i_adpt_cfg_rdatavld), + .i_adpt_cfg_rdata (top_io.i_adpt_cfg_rdata[31:0]), +// .i_adpt_cfg_waitreq (top_io.i_adpt_cfg_waitreq), + .i_adpt_cfg_waitreq (1'b1), + .m_ns_fwd_clk (i_rx_pma_clk), + .m_ns_fwd_div2_clk (i_rx_pma_div2_clk), + .i_osc_clk (i_osc_clk), + .i_chnl_ssr (top_io.i_chnl_ssr[64:0]), + .data_in (top_io.i_rx_pma_data[39:0]), + .m_ns_rcv_clk (i_tx_pma_clk), + .i_scan_clk (i_scan_clk), + .i_test_clk_1g (i_test_clk_1g), + .i_test_clk_500m (i_test_clk_500m), + .i_test_clk_250m (i_test_clk_250m), + .i_test_clk_125m (i_test_clk_125m), + .i_test_clk_62m (i_test_clk_62m), + .i_test_c3adapt_tcb_static_common(i_test_c3adapt_tcb_static_common[`AIBADAPTWRAPTCB_STATIC_COMMON_RNG]), + .i_test_c3adapt_scan_in(i_test_c3adapt_scan_in[`AIBADAPTWRAPTCB_SCAN_CHAINS_RNG]), + .i_jtag_rstb_in (i_jtag_rstb_in), + .i_jtag_rstb_en_in (i_jtag_rstb_en_in), + .i_jtag_clkdr_in (i_jtag_clkdr_in), + .i_jtag_clksel_in (i_jtag_clksel_in), + .i_jtag_intest_in (i_jtag_intest_in), + .i_jtag_mode_in (i_jtag_mode_in), + .i_jtag_weakpdn_in (i_jtag_weakpdn_in), + .i_jtag_weakpu_in (i_jtag_weakpu_in), + .i_jtag_bs_scanen_in (i_jtag_bs_scanen_in), + .i_jtag_bs_chain_in (i_jtag_bs_chain_in), + .i_jtag_last_bs_chain_in(i_jtag_last_bs_chain_in), + .i_por_aib_vcchssi (i_por_aib_vcchssi), + .i_por_aib_vccl (i_por_aib_vccl), + .i_red_idataselb_in_chain1(i_red_idataselb_in_chain1), + .i_red_idataselb_in_chain2(i_red_idataselb_in_chain2), + .i_red_shift_en_in_chain1(i_red_shift_en_in_chain1), + .i_red_shift_en_in_chain2(i_red_shift_en_in_chain2), + .i_txen_in_chain1 (i_txen_in_chain1), + .i_txen_in_chain2 (i_txen_in_chain2), + .i_directout_data_chain1_in(i_directout_data_chain1_in), + .i_directout_data_chain2_in(i_directout_data_chain2_in), + .i_aibdftdll2adjch (13'h0)); + +`include "ndut_declare.sv" +`include "ndut_default.sv" +`include "nda_drv.sv" +`include "nda_port.sv" + +endmodule diff --git a/how2use/sim_sl2ms_lpbk/vlog.do b/how2use/sim_sl2ms_lpbk/vlog.do new file mode 100644 index 0000000..547aabe --- /dev/null +++ b/how2use/sim_sl2ms_lpbk/vlog.do @@ -0,0 +1,578 @@ +set AIB_LIB ../../aib_lib +set MAIB_LIB ../../maib_rtl +set MODEL_RTL ../../rtl +vlog -mfcu -sv +acc +define+ALTR_HPS_INTEL_MACROS_OFF+TIMESCALE_EN ./dut_io.sv ./test.sv ./top.sv \ ++incdir+$AIB_LIB/c3dfx/rtl/defines +incdir+./ \ +$AIB_LIB/c3lib/rtl/defines/c3lib_dv_defines.sv +incdir+$AIB_LIB/c3lib/rtl/defines \ +$AIB_LIB/c3dfx/rtl/defines/c3dfx.vh +incdir+$AIB_LIB/c3dfx/rtl/defines \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_8ph_intp.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_crsdlyline.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_dll.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_dlyline64.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_dlyline.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_dly.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_gry2thm64.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_helper.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_interpolator.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_phasedet.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_top.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dll_custom.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dll_lock_dly.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dlycell_dcc.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_svt16_scdffcdn_cust.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_svt16_scdffsdn_cust.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_ulvt16_2xarstsyncdff1_b2.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_ulvt16_dffcdn_cust.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_io_cmos_nand_x64.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_top_wrp.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_str_align.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_clktree_mimic.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_clktree.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_cmos_nand_x64.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dll_8ph_intp.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dll_dlyline64.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dll_gry2thm64.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dll_ibkmux.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dlycell_dll.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dlycell_dll_c.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_scan_iomux.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_2to4dec.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_analog.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_avmm1.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_avmm2.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_buffx1_top.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_buffx1.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_clktree_avmm_mimic.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_clktree_avmm_pcs.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_clktree_avmm.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_clktree_pcs.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_cmos_fine_dly.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_cmos_nand_x1.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_io_ip8phs.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_digital.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_inv_split_align.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_lvshift.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_preclkbuf.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_quadph_code_gen.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_rxanlg.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_rxdatapath_rx.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_rxdig.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_top.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_txanlg.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_txdatapath_tx.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_txdig.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_nd2d0_custom.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_split_align.v \ +$AIB_LIB/aibcr3_lib/rtl/structured.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_ff_r.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_ff_p.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_ff_rp.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_latch.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_red_custom_dig.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_str_ff.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_sync_ff.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_top_dummy.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_esd.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_str_ioload.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_red_custom_dig2.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_red_clkmux2.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_red_clkmux3.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_lvshift_lospeed.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_lvshift_diff.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_triinv_dig.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_interface.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_rambit_buf.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_signal_buf.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_data_buf.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_rxdat_mimic.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_txdat_mimic.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_dly_rep.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dly_mimic.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_io_cmos_8ph_interpolator_rep.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_io_cmos_8ph_interpolator.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_io_nand_delay_line_min_rep.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_io_cmos_nand_x1.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_io_cmos_nand_x128.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_io_nand_delay_line_min.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_io_nand_x128_delay_line.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_clkmux2.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_sync_2ff.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_sync_3ff.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_aliasv.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_aliasd.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_ulvt16_dffsdn_cust.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_opio_esd.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_anaio_esd.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dlycell_dcc_rep.v \ +$AIB_LIB/c3lib/rtl/basic/pulse_stretch/cdclib_pulse_stretch.sv \ +$AIB_LIB/c3lib/rtl/avmm/c3_avmm_rdl_intf.sv \ +$AIB_LIB/c3lib/rtl/avmm/c3lib_cfgcsr_fastslow_pulse_meta.sv \ +$AIB_LIB/c3lib/rtl/avmm/c3lib_cfgcsr_slowfast_pulse_meta.sv \ +$AIB_LIB/c3lib/rtl/avmm/c3lib_avmm_pulse_cross.sv \ +$AIB_LIB/c3lib/rtl/cdc/async_fifo/c3lib_async_fifo.sv \ +$AIB_LIB/c3lib/rtl/cdc/bit_synchronizer/c3lib_bitsync.sv \ +$AIB_LIB/c3lib/rtl/cdc/bit_synchronizer/c3lib_sync2_lvt_bitsync.sv \ +$AIB_LIB/c3lib/rtl/cdc/bit_synchronizer/c3lib_sync2_ulvt_bitsync.sv \ +$AIB_LIB/c3lib/rtl/cdc/bit_synchronizer/c3lib_sync3_ulvt_bitsync.sv \ +$AIB_LIB/c3lib/rtl/cdc/gray_code/c3lib_bintogray.sv \ +$AIB_LIB/c3lib/rtl/cdc/gray_code/c3lib_graytobin.sv \ +$AIB_LIB/c3lib/rtl/cdc/level_synchronizer/c3lib_lvlsync.sv \ +$AIB_LIB/c3lib/rtl/cdc/reset_synchronizer/c3lib_rstsync.sv \ +$AIB_LIB/c3lib/rtl/cdc/vector_synchronizer/c3lib_vecsync.sv \ +$AIB_LIB/c3lib/rtl/cdc/vector_synchronizer/c3lib_vecsync_handshake.sv \ +$AIB_LIB/c3lib/rtl/cdc/glitch_free_mux/c3lib_gf_clkmux.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_buf/c3lib_ckinv_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_buf/c3lib_ckbuf_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_buf/c3lib_ckand2_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_gater/c3lib_ckg_async_posedge_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_gater/c3lib_ckg_negedge_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_gater/c3lib_ckg_posedge_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_mux/c3lib_mux2_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_mux/c3lib_mux3_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_mux/c3lib_mux4_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_divider/c3lib_ckdiv2_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_divider/c3lib_ckdiv4_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_divider/c3lib_ckdiv8_ctn.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_and2_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_buf_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_mux2_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_nand2_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_or2_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_tie_bus_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_tieh_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_tiel_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_mtieh_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_mtiel_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_dff_scan_lcell.sv \ +$AIB_LIB/c3lib/rtl/ecc/c3lib_ecc_dec_c39_d32.sv \ +$AIB_LIB/c3lib/rtl/ecc/c3lib_ecc_dec_c88_d80.sv \ +$AIB_LIB/c3lib/rtl/ecc/c3lib_ecc_enc_d32_c39.sv \ +$AIB_LIB/c3lib/rtl/ecc/c3lib_ecc_enc_d80_c88.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_sync2_reset_lvt_gate.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_sync2_reset_ulvt_gate.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_sync3_reset_ulvt_gate.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_sync2_set_lvt_gate.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_sync2_set_ulvt_gate.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_sync3_set_ulvt_gate.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_tie0_svt_1x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_tie1_svt_1x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_mtie0_ds.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_mtie1_ds.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_or2_svt_2x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_nand2_svt_2x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_mux2_svt_2x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_ckmux4_ulvt_gate.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_ckmux4_lvt_gate.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_ckinv_lvt_12x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_ckinv_svt_8x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_ckg_lvt_8x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_ckbuf_lvt_4x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_buf_svt_4x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_and2_svt_2x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_and2_svt_4x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_dff0_reset_lvt_2x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_dff0_set_lvt_2x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_dff0_scan_reset_svt_2x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_sync_metastable_behav_gate.sv \ +$AIB_LIB/c3dfx/rtl/tcm/c3dfx_tcm_wrap.sv \ +$AIB_LIB/c3dfx/rtl/tcm/c3dfx_tcm.sv \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1_async.v \ +$AIB_LIB/c3dfx/rtl/defines/c3dfx.vh $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1clk_ctl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1_config.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_hwcfg_dec.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_cfg_csr.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_usr_csr.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1_transfer.v \ +$AIB_LIB/c3dfx/rtl/defines/c3dfx.vh $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2_async.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2clk_ctl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2_config.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2_transfer.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_async.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_cfg_rdmux.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmmclk_dcg.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmmclk_gate.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_cmdbuilder.sv \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_dec_arb.sv \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_decode.sv \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_rdfifo.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmmrst_ctl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_usr32_exp.sv \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_hrdrst_clkctl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_hrdrst_rstctrl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_async_capture_bit.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_async_capture_bus.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkand2.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkgate_high.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkgate.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkinv.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkmux2_cell.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkmux2.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_comp_cntr.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_dist_dw.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_dist_pair_dw.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_dist_pair.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_dist.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_dft_clk_ctlr.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_latency_measure.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_occ_clkgate.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_occ_enable_logic.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_occ_gray_cntr.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_occ_test_ctlregs.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_parity_checker.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_parity_gen.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_pulse_stretch.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_dprio_status_sync_regs.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_shadow_status_regs.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_capture.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_direct.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_rsvd_capture.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_rsvd_update.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_update.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxchnl_testbus.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxchnl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxclk_ctl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxclk_gate.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_asn.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_async_fifo.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_cp_bond.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_del_sm.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_fifo_ptr.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_fifo_ram.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_fifo.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_map.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rx_dprio.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_rxeq_sm.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_txeq_sm.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_txeq.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxrst_ctl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_fsr_in.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_fsr_out.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_async_capture_bit.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_async_capture_bus.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_srclk_ctl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_in_bit.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_out_bit.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_srrst_ctl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_sm.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_ssr_in.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_ssr_out.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_async_update.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_hip_async_capture.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_hip_async_update.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_capture.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_direct.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_rsvd_capture.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_rsvd_update.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_update.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txchnl_testbus.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txchnl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txclk_ctl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txclk_gate.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_async_fifo.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_cp_bond.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_fifo_ptr.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_fifo_ram.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_fifo.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_map.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_tx_dprio.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_word_align.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txrst_ctl.v \ +$AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_redundancy.v \ +$AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_jtag_bscan.v \ +$AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_bsr_red_wrap.v \ +$AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_half_cycle_code_gen.v \ +$AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_self_lock_assertion.v \ +$AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_dll_ctrl.v \ +$AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_dll_core.v \ +$AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_dll_pnr.v \ +$AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_rstsync.sv \ +$AIB_LIB/c3dfx/rtl/tcb/c3dfx_aibadaptwrap_tcb.sv \ +$AIB_LIB/c3aibadapt_wrap/rtl/c3aibadapt_wrap.v \ +$AIB_LIB/c3aibadapt_wrap/rtl/c3aib_master.sv \ +$MODEL_RTL/dll.sv $MODEL_RTL/aib_io_buffer.sv \ +$MODEL_RTL/aib_dcc.v \ +$MODEL_RTL/aib_aux_channel.v \ +$MODEL_RTL/aib_bitsync.v \ +$MODEL_RTL/aib_bsr_red_wrap.v \ +$MODEL_RTL/aib_buffx1_top.v \ +$MODEL_RTL/aib_ioring.v \ +$MODEL_RTL/aib_jtag_bscan.v \ +$MODEL_RTL/aib_mux21.v \ +$MODEL_RTL/aib_osc_clk.sv \ +$MODEL_RTL/aib_redundancy.v \ +$MODEL_RTL/aib_rstnsync.v \ +$MODEL_RTL/aib_sm.v \ +$MODEL_RTL/aib_sr_ms.v \ +$MODEL_RTL/aib_sr_sl.v \ +$MODEL_RTL/aib_channel.v \ +$MODEL_RTL/aib.v \ +$MAIB_LIB/s10aib/rtl/ndaibadapt_wrap.v \ +$MAIB_LIB/s10aib/rtl/an.v \ +$MAIB_LIB/s10aib/rtl/s10aib.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1_async.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1_config.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1_dprio_mapping.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1_transfer.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm2_async.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm2_transfer.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm2.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_async_update.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmmclk_ctl.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_cmdfifo.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_cmn_intf.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_dprio_reg.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_rdfifo.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmmrst_ctl.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_async.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_hrdrst_rstctrl.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_hrdrst_clkctl.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_fsr_in.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_fsr_out.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_srclk_ctl.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_sr_in_bit.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_sr_out_bit.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_srrst_ctl.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_sr_sm.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_sr.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_ssr_in.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_ssr_out.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_async_update.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_reserved_capture.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_reserved_update.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_hip_async_capture.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_hip_async_update.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_capture.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_direct.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_update.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_chnl.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_txclk_ctl.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_async_fifo.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_fifo_ram.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_fifo_pointers.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_chnl_testbus.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_cp_bond.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_dv_gen.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_fifo.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_frame_gen.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_word_mark.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_txrst_ctl.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_pulse_stretch.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_reserved_capture.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_reserved_update.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_capture.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_direct.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_update.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_chnl.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rxclk_ctl.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_asn.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_async_fifo.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_cp_bond.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_fifo.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_fifo_ram.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_fifo_pointers.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_insert_sm.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_del_sm.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_word_align.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rxrst_ctl.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_pulse_stretch.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_chnl_testbus.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_async_capture_bit.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_comp_cntr.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_pair_dw.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_async_capture_bus.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_dw.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_pair.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_latency_measure.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_pulse_stretch.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_parity_gen.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_parity_checker.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkand2.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay_map.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay_cell.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkgate.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkinv.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkmux2_cell.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkmux2.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkor2.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_dft_clock_controller.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_clkgate.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_enable_logic.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_gray_code_counter.v \ +$MAIB_LIB/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_test_control_register.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_bintogray.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_bintogray_inc8.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_bitsync2.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_sync2_reset_type_l_gate.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_sync2_reset_type_n_gate.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_sync2_reset_type_w_gate.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_sync2_set_type_l_gate.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_sync2_set_type_n_gate.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_sync2_set_type_w_gate.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_bitsync4.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_sync4_reset_type_l_gate.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_sync4_reset_type_w_gate.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_sync4_set_type_l_gate.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_sync4_set_type_w_gate.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_graytobin.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_graytobin_inc2.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_graytobin_inc8.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_rst_n_sync.v \ +$MAIB_LIB/cdclib/rtl/block_function/cdclib_rst_n_sync_core.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_dprio_csr_reg_bit.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_dprio_csr_reg_nbits.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_dprio_csr_reg_nregs.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_cmn_non_scan_reg.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_dprio_readdata_mux.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_interface_top.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_dprio_csr_test_mux.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_cmn_clk_mux.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_dprio_ctrl_reg_bit.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_dprio_ctrl_reg_nbits.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_dprio_ctrl_reg_nregs.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_reg_chnl.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_reg_top.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_dprio_dis_ctrl_cvp.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_dprio_readdata_sel.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_dprio_status_reg_nbits.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_dprio_status_reg_nregs.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_dprio_status_sync_regs.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_dprio_shadow_status_regs.v \ +$MAIB_LIB/cfg_shared/rtl/block_function/cfg_dprio_shadow_status_nregs.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_top_wrp.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_top.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_dcc_dly_rep.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_dly_mimic.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_io_dly_interpolator_rep.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_io_nand_delay_line_min_rep.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_latch.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_hgy_latch.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_ff_r.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_ff_rp.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_2ff_scan.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_aliasd.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_aliasv.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_2to4dec.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_analog.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_avmm1.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_avmm2.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_buffx1_top.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_buffx1.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_clkbuf.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_clktree.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_clktree_avmm.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_clktree_avmm_mimic.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_clktree_avmm_pcs.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_clktree_mimic.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_clktree_pcs.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_cmos_fine_dly.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x6.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x1.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_d8xsesdd1.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_d8xsesdd2.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_dcc_5b_b2tc_x1.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_dcc_5b_b2tc.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_dcc_dll.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_dcc_ff.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_dcc_fine_dly.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_dcc_mux.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_dcc_top.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_digital.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_dll_phdet.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_dll_custom.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_inv_split_align.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_quadph_code_gen.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_preclkbuf.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_rxdatapath_rx.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_rxdig.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_str_align.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_txdatapath_tx.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_txdig.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_rxanlg.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_txanlg.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_dcc_fine_dly_x1.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_fine_dly_x1.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_dcc_dly_inv.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_fine_dly_inv.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_str_ff.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_dcc_helper.v \ + $MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_str_clktree_mimic.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_dcc_dly.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_red_custom_dig.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_str_preclkbuf.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_nand_x64_delay_line.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_str_clktree.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_sync_ff.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x64.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_signal_buf.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_red_custom_dig2.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_avmm_rst_sync.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_data_buf.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_interface.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_rambit_buf.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_inv.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_nand2.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_nor2.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_red_clkmux2.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_red_clkmux3.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_txdat_mimic.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_rxdat_mimic.v \ +$MAIB_LIB/aibnd_lib/rtl/block_function/aibnd_clkmux2.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_interp_mux.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_ip16phs.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_cmos_16ph_decode.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_interp_misc.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_interp_output.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_interp_latch_in.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_interp_mux_pair.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_interp_pdn.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_min_interp_mux.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_min_ip16phs.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_min_output.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_min_misc.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_min_pdn.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_dly_interpolator.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_dly_interpclk.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_ip8phs_3in.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_cmos_nand_x1.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_cmos_nand_x128.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_cmos_nand_x64_decode.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_cmos_nand_x128_decode.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_cmos_nand_x6.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_nand_x128_delay_line.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_cmos_nand_x64.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_cmos_nand_x4.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_split_align.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_dll_phdet.v \ +$MAIB_LIB/io_common_custom/rtl/block_function/io_nand_delay_line_min.v \ +$MAIB_LIB/soc_std_macro/rtl/block_function/i14socnd/soc_simulation_defines.v \ +$MAIB_LIB/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckinv.v \ +$MAIB_LIB/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckmux21.v \ +$MAIB_LIB/aibndpnr_lib/rtl/block_function/aibndpnr_redundancy.v \ +$MAIB_LIB/aibndpnr_lib/rtl/block_function/aibndpnr_jtag_bscan.v \ +$MAIB_LIB/aibndpnr_lib/rtl/block_function/aibndpnr_bsr_red_wrap.v \ +$MAIB_LIB/aibndpnr_lib/rtl/block_function/aibndpnr_half_cycle_code_gen.v \ +$MAIB_LIB/aibndpnr_lib/rtl/block_function/aibndpnr_self_lock_assertion.v \ +$MAIB_LIB/aibndpnr_lib/rtl/block_function/aibndpnr_dll_ctrl.v \ +$MAIB_LIB/aibndpnr_lib/rtl/block_function/aibndpnr_dll_core.v \ +$MAIB_LIB/aibndpnr_lib/rtl/block_function/aibndpnr_dll_pnr.v \ +$MAIB_LIB/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkgate_cgc00.v \ +$MAIB_LIB/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkgate_cgc01.v \ +$MAIB_LIB/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkmux.v diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_2ff_scan.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_2ff_scan.v new file mode 100644 index 0000000..c5be00e --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_2ff_scan.v @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module aibnd_2ff_scan ( + input wire clk, + input wire d, + output wire o, + input wire rb, + input wire si, + output wire so, + input wire ssb +); + + wire mgm_d2_row1; + wire mgm_d2_row2; + wire mgm_d2_row3; + + wire q1, q2, q3, q4; + + assign o = !q1; + //assign q1_inv = !q1; + assign so = !q1 & !ssb; + + //assign d_inv = !d; + //assign si_inv = !si_inv; + //assign ssb_inv = !ssb; + + assign mgm_d2_row1 = !d & !si; + assign mgm_d2_row2 = !d & ssb; + assign mgm_d2_row3 = !si & !ssb; + + assign mgm_d2 = mgm_d2_row1 | mgm_d2_row2 | mgm_d2_row3; + +aibnd_hgy_latch aibnd_hgy_latch_inst0 ( + .q (q1), + .set (1'b0), + .preset (!rb), + .clk (clk), + .d (!q4) +); + +aibnd_hgy_latch aibnd_hgy_latch_inst1 ( + .q (q2), + .set (1'b0), + .preset (!rb), + .clk (clk), + .d (q3) +); + +aibnd_hgy_latch aibnd_hgy_latch_inst2 ( + .q (q3), + .set (1'b0), + .preset (!rb), + .clk (!clk), + .d (mgm_d2) +); + +aibnd_hgy_latch aibnd_hgy_latch_inst3 ( + .q (q4), + .set (!rb), + .preset (1'b0), + .clk (!clk), + .d (!q2) +); + +endmodule + + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_2to4dec.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_2to4dec.v new file mode 100644 index 0000000..280de75 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_2to4dec.v @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_2to4dec, View - schematic +// LAST TIME SAVED: Dec 11 15:13:26 2014 +// NETLIST TIME: Dec 17 10:24:02 2014 + +module aibnd_2to4dec ( nsel_out0b, nsel_out1b, nsel_out2b, nsel_out3b, + psel_out0, psel_out1, psel_out2, psel_out3, enable, nsel_in, + psel_in, vccl_aibnd, vssl_aibnd ); + +output nsel_out0b, nsel_out1b, nsel_out2b, nsel_out3b, psel_out0, + psel_out1, psel_out2, psel_out3; + +input enable, vccl_aibnd, vssl_aibnd; + +input [1:0] psel_in; +input [1:0] nsel_in; + +wire psel_out1, psel0_en, psel_out2, nsel0_en, enable, psel_out3, nsel1_en, nsel_out2b, nsel_out1b, nsel_out3b, psel_out0, nsel_out0b; // Conversion Sript Generated + + + +assign psel_out1 = psel0_en | psel_out2; +assign nsel0_en = nsel_in[0] & enable; +assign psel_out2 = psel_in[1] & enable; +assign psel0_en = psel_in[0] & enable; +assign psel_out3 = enable & psel_in[0] & psel_in[1]; +assign nsel1_en = !nsel_out2b; +assign nsel_out2b = !(nsel_in[1] & enable); +assign nsel_out1b = !(nsel0_en | nsel1_en); +assign nsel_out3b = !(enable & nsel_in[0] & nsel_in[1]); +assign psel_out0 = !nsel_out0b; +assign nsel_out0b = !enable; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_aliasd.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_aliasd.v new file mode 100644 index 0000000..d177e3b --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_aliasd.v @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module aibnd_aliasd ( PLUS, MINUS ); + + input PLUS; + output MINUS; + + assign MINUS = PLUS; + +endmodule + + + + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_aliasv.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_aliasv.v new file mode 100644 index 0000000..7ced7ec --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_aliasv.v @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module aibnd_aliasv ( .PLUS(w), .MINUS(w) ); + + inout w; + wire w; + +endmodule + + + + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_analog.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_analog.v new file mode 100644 index 0000000..1f3b03a --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_analog.v @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_analog, View - schematic +// LAST TIME SAVED: Dec 11 16:48:20 2014 +// NETLIST TIME: Dec 17 10:24:02 2014 + +module aibnd_analog ( oclkn, oclkp, odat, odat_async, iopad, clk_en, + data_en, iclkn, ndrv_enb, pdrv_en, txdin, vccl_aibnd, vssl_aibnd, + weak_pulldownen, weak_pullupenb ); + +output oclkn, oclkp, odat, odat_async; + +inout iopad; + +input clk_en, data_en, iclkn, txdin, vccl_aibnd, vssl_aibnd, + weak_pulldownen, weak_pullupenb; + +input [15:0] pdrv_en; +input [15:0] ndrv_enb; + + + +aibnd_txanlg xtxbuf ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .ndrv_enb(ndrv_enb[15:0]), + .weak_pullupenb(weak_pullupenb), .txpadout(iopad), .din(txdin), + .pdrv_en(pdrv_en[15:0]), .weak_pulldownen(weak_pulldownen)); +aibnd_rxanlg xrxbuf ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .odat_async(odat_async), + .data_en(data_en), .clk_en(clk_en), .odat(odat), .oclkn(oclkn), + .oclkp(oclkp), .iopad(iopad), .iclkn(iclkn)); +aibnd_d8xsesdd1 xesd1 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .iopad(iopad)); +aibnd_d8xsesdd2 xesd2 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .iopad(iopad)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_avmm1.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_avmm1.v new file mode 100644 index 0000000..0ce9e99 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_avmm1.v @@ -0,0 +1,870 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_avmm1, View - schematic +// LAST TIME SAVED: Jul 6 22:41:38 2015 +// NETLIST TIME: Jul 8 13:09:51 2015 +// `timescale 1ns / 1ns + +module aibnd_avmm1 ( avmm1_odat0, avmm1_odat1, avmm2_rx_distclk, + avmm2_rx_strbclk, avmm2_tx_launch_clk_l0, avmm2_tx_launch_clk_l1, + iclkin_dist_vinp0, iclkin_dist_vinp1, idat0_voutp00, + idat0_voutp01, idat1_voutp00, idat1_voutp01, idata0_ssrdout, + idata0_ssrldout, idata1_ssrdout, idata1_ssrldout, + idataselb_ssrdout, idataselb_ssrldout, idataselb_voutp00, + idataselb_voutp01, ilaunch_clk_ssrdout, ilaunch_clk_ssrldout, + ilaunch_clk_voutp00, ilaunch_clk_voutp01, irxen_vinp0, + istrbclk_vinp0, istrbclk_vinp1, itxen_ssrdout, itxen_ssrldout, + itxen_voutp00, itxen_voutp01, jtag_clkdr_in_srcclkinn, + jtag_clkdr_in_ssrdout, jtag_clkdr_in_ssrldout, jtag_clkdr_vinp0, + jtag_clkdr_voutp00, jtag_clkdr_voutp01, jtag_rx_scan_in_srcclkinn, + jtag_rx_scan_in_ssrdout, jtag_rx_scan_in_ssrldout, + jtag_rx_scan_vinp0, jtag_rx_scan_voutp00, jtag_rx_scan_voutp01, + oclk_srclkout, oclkb_srclkout, odat_async_fsrdin, osdrin_odat0, + osdrin_odat1, pcs_clk, pcs_clkb, resetb_sync_buf, + shift_en_srcclkinn, shift_en_ssrdout, shift_en_ssrldout, + shift_en_vinp0, shift_en_voutp00, shift_en_voutp01, + iopad_avmm1_in, iopad_avmm1_out, iopad_clkn, iopad_clkp, + iopad_inclkn, iopad_inclkp, iopad_sdr_in, iopad_sdr_out, + avmm1_idat0, avmm1_idat1, avmm1_rstb, avmm_tx_clk_in, clkdr_xr1l, + clkdr_xr1r, clkdr_xr2l, clkdr_xr2r, clkdr_xr3l, clkdr_xr3r, + clkdr_xr4l, clkdr_xr4r, iasyncdata_oshared2, idat0_clkn, + idat0_clkp, idat0_voutp10, idat0_voutp11, idat1_clkn, idat1_clkp, + idat1_voutp10, idat1_voutp11, idataselb, idataselb_oshared2, + idataselb_voutp10, idataselb_voutp11, indrv_r12, indrv_r34, + ipdrv_r12, ipdrv_r34, irxen_inpshared4, irxen_ptxclkin, irxen_r0, + irxen_r1, irxen_r2, isdrin_idat0, isdrin_idat1, itxen, + itxen_oshared2, itxen_voutp10, itxen_voutp11, + jtag_clkdr_in_dirin5, jtag_clkdr_in_voutp10, + jtag_clkdr_inpshared4, jtag_clkdr_oshared2, jtag_clkdr_ptxclkin, + jtag_clkdr_ptxclkinn, jtag_clksel, jtag_intest, jtag_mode_in, + jtag_rstb, jtag_rstb_en, jtag_rx_scan_in_dirin5, + jtag_rx_scan_in_voutp10, jtag_rx_scan_inpshared4, + jtag_rx_scan_oshared2, jtag_rx_scan_ptxclkin, + jtag_rx_scan_ptxclkinn, jtag_tx_scanen_in, jtag_weakpdn, + jtag_weakpu, oclkn_vinp1, odat0_outpclk1_1, odat1_outpclk1_1, + rx_shift_en, shift_en_inpshared4, shift_en_oshared2, + shift_en_ptxclkin, shift_en_ptxclkinn, shift_en_voutp10, + shift_en_voutp11, vccl_aibnd, vssl_aibnd ); + +output avmm1_odat0, avmm1_odat1, avmm2_rx_distclk, avmm2_rx_strbclk, + avmm2_tx_launch_clk_l0, avmm2_tx_launch_clk_l1, iclkin_dist_vinp0, + iclkin_dist_vinp1, idat0_voutp00, idat0_voutp01, idat1_voutp00, + idat1_voutp01, idata0_ssrdout, idata0_ssrldout, idata1_ssrdout, + idata1_ssrldout, idataselb_ssrdout, idataselb_ssrldout, + idataselb_voutp00, idataselb_voutp01, ilaunch_clk_ssrdout, + ilaunch_clk_ssrldout, ilaunch_clk_voutp00, ilaunch_clk_voutp01, + istrbclk_vinp0, istrbclk_vinp1, itxen_ssrdout, itxen_ssrldout, + itxen_voutp00, itxen_voutp01, jtag_clkdr_in_srcclkinn, + jtag_clkdr_in_ssrdout, jtag_clkdr_in_ssrldout, jtag_clkdr_vinp0, + jtag_clkdr_voutp00, jtag_clkdr_voutp01, jtag_rx_scan_in_srcclkinn, + jtag_rx_scan_in_ssrdout, jtag_rx_scan_in_ssrldout, + jtag_rx_scan_vinp0, jtag_rx_scan_voutp00, jtag_rx_scan_voutp01, + oclk_srclkout, oclkb_srclkout, odat_async_fsrdin, pcs_clk, + pcs_clkb, resetb_sync_buf, shift_en_srcclkinn, shift_en_ssrdout, + shift_en_ssrldout, shift_en_vinp0, shift_en_voutp00, + shift_en_voutp01; + +inout iopad_avmm1_in, iopad_clkn, iopad_clkp, iopad_inclkn, + iopad_inclkp; + +input avmm1_rstb, avmm_tx_clk_in, clkdr_xr1l, clkdr_xr1r, clkdr_xr2l, + clkdr_xr2r, clkdr_xr3l, clkdr_xr3r, clkdr_xr4l, clkdr_xr4r, + iasyncdata_oshared2, idat0_clkn, idat0_clkp, idat0_voutp10, + idat0_voutp11, idat1_clkn, idat1_clkp, idat1_voutp10, + idat1_voutp11, idataselb_oshared2, idataselb_voutp10, + idataselb_voutp11, itxen_oshared2, itxen_voutp10, itxen_voutp11, + jtag_clkdr_in_dirin5, jtag_clkdr_in_voutp10, + jtag_clkdr_inpshared4, jtag_clkdr_oshared2, jtag_clkdr_ptxclkin, + jtag_clkdr_ptxclkinn, jtag_clksel, jtag_intest, jtag_mode_in, + jtag_rstb, jtag_rstb_en, jtag_rx_scan_in_dirin5, + jtag_rx_scan_in_voutp10, jtag_rx_scan_inpshared4, + jtag_rx_scan_oshared2, jtag_rx_scan_ptxclkin, + jtag_rx_scan_ptxclkinn, jtag_tx_scanen_in, jtag_weakpdn, + jtag_weakpu, oclkn_vinp1, odat0_outpclk1_1, odat1_outpclk1_1, + shift_en_inpshared4, shift_en_oshared2, shift_en_ptxclkin, + shift_en_ptxclkinn, shift_en_voutp10, shift_en_voutp11, + vccl_aibnd, vssl_aibnd; + +output [2:0] irxen_vinp0; +output [3:0] osdrin_odat1; +output [3:0] osdrin_odat0; + +inout [1:0] iopad_avmm1_out; +inout [3:0] iopad_sdr_in; +inout [3:0] iopad_sdr_out; + +input [1:0] indrv_r12; +input [1:0] indrv_r34; +input [1:0] ipdrv_r34; +input [2:0] irxen_inpshared4; +input [1:0] avmm1_idat1; +input [2:0] itxen; +input [1:0] avmm1_idat0; +input [2:0] irxen_ptxclkin; +input [2:0] irxen_r1; +input [2:0] irxen_r0; +input [2:0] idataselb; +input [2:0] irxen_r2; +input [1:0] ipdrv_r12; +input [3:0] isdrin_idat1; +input [3:0] isdrin_idat0; +input [14:0] rx_shift_en; + +wire clk_distclk_b_nc, clk_distclk, clk_mimic01_b_nc, clk_mimic01, clk_mimic11_b_nc, clk_mimic11, avmm_pcs_clk, avmm_pcs_clk_buf; // Conversion Sript Generated + +wire oclk_inclkpb_ext; +// Buses in the design + +wire [0:7] rx_distclk_l; + +wire [0:7] rx_distclk_r; + +wire [0:7] tx_launch_clk_l; + +wire [0:7] tx_launch_clk_r; + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_avmm1"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +aibnd_clktree_avmm xout_clktree ( /*.vcc_aibnd(vccl_aibnd), + .vss_aibnd(vssl_aibnd),*/ .lstrbclk_mimic2(nc_clk_mimic), + .lstrbclk_r_7(tx_launch_clk_r[7]), + .lstrbclk_r_6(tx_launch_clk_r[6]), + .lstrbclk_r_5(tx_launch_clk_r[5]), + .lstrbclk_r_4(tx_launch_clk_r[4]), + .lstrbclk_r_3(tx_launch_clk_r[3]), + .lstrbclk_r_2(tx_launch_clk_r[2]), + .lstrbclk_r_1(tx_launch_clk_r[1]), + .lstrbclk_r_0(tx_launch_clk_r[0]), + .lstrbclk_mimic1(nc_clk_mimic1), .lstrbclk_mimic0(nc_clk_mimic0), + .lstrbclk_l_0(tx_launch_clk_l[0]), + .lstrbclk_l_1(tx_launch_clk_l[1]), + .lstrbclk_l_2(tx_launch_clk_l[2]), + .lstrbclk_l_3(tx_launch_clk_l[3]), + .lstrbclk_l_4(tx_launch_clk_l[4]), + .lstrbclk_l_5(tx_launch_clk_l[5]), + .lstrbclk_l_6(tx_launch_clk_l[6]), + .lstrbclk_l_7(tx_launch_clk_l[7]), .lstrbclk_rep(nc_clk_rep), + .clkin(avmm_tx_clk_in_dly)); +assign clk_distclk_b_nc = !clk_distclk; + +assign clk_mimic01_b_nc = !clk_mimic01; + +assign clk_mimic11_b_nc = !clk_mimic11; + +aibnd_aliasd aliasd6 ( .MINUS(ilaunch_clk_voutp01), .PLUS(tx_launch_clk_l[6])); +aibnd_aliasd aliasd2 ( .MINUS(idataselb_voutp00), .PLUS(idataselb[0])); +aibnd_aliasd aliasd7 ( .MINUS(idataselb_voutp01), .PLUS(idataselb[0])); +aibnd_aliasd aliasv33 ( .MINUS(ilaunch_clk_ssrldout), .PLUS(tx_launch_clk_r[6])); +aibnd_aliasd aliasd4 ( .MINUS(itxen_voutp00), .PLUS(itxen[0])); +aibnd_aliasd aliasd5 ( .MINUS(itxen_voutp01), .PLUS(itxen[0])); +aibnd_aliasd aliasd15 ( .MINUS(shift_en_ssrdout), .PLUS(rx_shift_en[7])); +aibnd_aliasd aliasv62 ( .MINUS(iclkin_dist_vinp0), .PLUS(rx_distclk_l[3])); +aibnd_aliasd aliasv36 ( .MINUS(itxen_ssrldout), .PLUS(itxen[2])); +aibnd_aliasd aliasv63 ( .MINUS(avmm2_tx_launch_clk_l0), .PLUS(tx_launch_clk_l[0])); +aibnd_aliasd aliasv60 ( .MINUS(avmm2_rx_strbclk), .PLUS(rx_distclk_l[6])); +aibnd_aliasd aliasv61 ( .MINUS(avmm2_rx_distclk), .PLUS(rx_distclk_l[6])); +aibnd_aliasd aliasv32 ( .MINUS(idataselb_ssrldout), .PLUS(idataselb[2])); +aibnd_aliasd aliasd11 ( .MINUS(shift_en_srcclkinn), .PLUS(rx_shift_en[4])); +aibnd_aliasd aliasd14 ( .MINUS(shift_en_ssrldout), .PLUS(rx_shift_en[14])); +aibnd_aliasd aliasv31 ( .MINUS(ilaunch_clk_ssrdout), .PLUS(tx_launch_clk_r[7])); +aibnd_aliasd aliasv0 ( .MINUS(tx_clkn), .PLUS(tx_launch_clk_r[4])); +aibnd_aliasd aliasv24[2:0] ( .MINUS(irxen_vinp0[2:0]), .PLUS(irxen_r0[2:0])); +aibnd_aliasd aliasd13 ( .MINUS(shift_en_voutp01), .PLUS(rx_shift_en[11])); +aibnd_aliasd aliasd12 ( .MINUS(shift_en_voutp00), .PLUS(rx_shift_en[10])); +aibnd_aliasd aliasd16 ( .MINUS(istrbclk_vinp1), .PLUS(rx_distclk_l[2])); +aibnd_aliasd aliasd17 ( .MINUS(iclkin_dist_vinp1), .PLUS(rx_distclk_l[2])); +aibnd_aliasd aliasv30 ( .MINUS(idataselb_ssrdout), .PLUS(idataselb[2])); +aibnd_aliasd aliasv64 ( .MINUS(avmm2_tx_launch_clk_l1), .PLUS(tx_launch_clk_l[1])); +aibnd_aliasd aliasv25 ( .MINUS(istrbclk_vinp0), .PLUS(rx_distclk_l[3])); +aibnd_aliasd aliasv1 ( .MINUS(tx_clkp), .PLUS(tx_launch_clk_r[5])); +aibnd_aliasd aliasd10 ( .MINUS(shift_en_vinp0), .PLUS(rx_shift_en[3])); +aibnd_aliasd aliasv55 ( .MINUS(itxen_ssrdout), .PLUS(itxen[2])); +aibnd_aliasd aliasd3 ( .MINUS(ilaunch_clk_voutp00), .PLUS(tx_launch_clk_l[7])); +aibnd_buffx1_top xtx_clkn ( .idata1_in1_jtag_out(idat1_srcclkoutn), + .async_dat_in1_jtag_out(nc_async_dat_srcclkoutn), + .idata0_in1_jtag_out(idat0_srcclkoutn), + .jtag_clkdr_outn(jtag_clkdr_outn_srcclkoutn), + .prev_io_shift_en(shift_en_ptxclkinn), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(avmm1_rstb), + .pd_data_aib(ncdrx_pd_data_out0_txclkn), + .oclk_out(ncdrx_oclk_txclkp), .oclkb_out(ncdrx_oclkb_txclkp), + .odat0_out(ncdrx_odat0_txclkp), .odat1_out(ncdrx_odat1_txclkp), + .odat_async_out(ncdrx_odat_async_txclkp), + .pd_data_out(ncdrx_pd_data_txclkp), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_srcclkoutn), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0_clkn), + .idata0_in1(vssl_aibnd), .idata1_in0(idat1_clkn), + .idata1_in1(vssl_aibnd), .idataselb_in0(idataselb[1]), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(tx_clkn), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r34[1:0]), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0(ipdrv_r34[1:0]), + .ipdrv_in1({vssl_aibnd, vssl_aibnd}), .irxen_in0({vssl_aibnd, + vccl_aibnd, vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .istrbclk_in0(jtag_clkdr_outn_srcclkoutn), + .istrbclk_in1(vssl_aibnd), .itxen_in0(itxen[1]), + .itxen_in1(vssl_aibnd), .oclk_in1(vssl_aibnd), + .odat_async_aib(ncdrx_odat_async_out0_txclkn), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[12]), .pd_data_in1(vssl_aibnd), + .dig_rstb(resetb_sync_buf), + .jtag_clkdr_out(jtag_clkdr_srcclkoutn), + .odat1_aib(ncdrx_odat1_out0_txclkn), + .jtag_rx_scan_out(jtag_rx_scan_srcclkoutn), + .odat0_aib(ncdrx_odat0_out0_txclkn), + .oclk_aib(ncdrx_oclk_out0_txclkn), + .last_bs_out(last_bs_out_dirout3), + .oclkb_aib(ncdrx_oclkb_out0_txclkn), .jtag_clkdr_in(clkdr_xr4r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_ptxclkinn), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_clkn), .oclkn(oclkn_srcclkoutn), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xavmm1_out1 ( .idata1_in1_jtag_out(idat1_voutp01), + .async_dat_in1_jtag_out(nc_async_dat_voutp01), + .idata0_in1_jtag_out(idat0_voutp01), + .jtag_clkdr_outn(jtag_clkdr_outn_voutp01), + .prev_io_shift_en(shift_en_voutp11), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(avmm1_rstb), .pd_data_aib(nc_pd_data_avmout01), + .oclk_out(nc_oclk_avmout1), .oclkb_out(nc_oclkb_avmout1), + .odat0_out(nc_odat0_avmout1), .odat1_out(nc_odat1_avmout1), + .odat_async_out(nc_odat_async_avmout1), + .pd_data_out(nc_pd_data_avmout1), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_voutp01), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(avmm1_idat0[1]), + .idata0_in1(idat0_voutp11), .idata1_in0(avmm1_idat1[1]), + .idata1_in1(idat1_voutp11), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb_voutp11), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(tx_launch_clk_l[2]), + .ilaunch_clk_in1(tx_launch_clk_l[2]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r34[1:0]), + .indrv_in1(indrv_r34[1:0]), .ipdrv_in0(ipdrv_r34[1:0]), + .ipdrv_in1(ipdrv_r34[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_voutp01), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen_voutp11), + .oclk_in1(vssl_aibnd), .odat_async_aib(nc_odat_async_avmout01), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[11]), .pd_data_in1(vssl_aibnd), + .dig_rstb(resetb_sync_buf), .jtag_clkdr_out(jtag_clkdr_voutp01), + .odat1_aib(nc_odat1_avmout01), + .jtag_rx_scan_out(jtag_rx_scan_voutp01), + .odat0_aib(nc_odat0_avmout01), .oclk_aib(nc_oclk_avmout01), + .last_bs_out(last_bs_out_voutp01), .oclkb_aib(nc_oclkb_avmout01), + .jtag_clkdr_in(clkdr_xr4l), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_in_dirin5), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_avmm1_out[1]), .oclkn(nc_oclkn_avmout01), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xsdr_in1 ( .idata1_in1_jtag_out(nc_idat1_fsrldin), + .async_dat_in1_jtag_out(nc_async_dat_fsrldin), + .idata0_in1_jtag_out(nc_idat0_fsrldin), + .jtag_clkdr_outn(jtag_clkdr_outn_fsrldin), + .prev_io_shift_en(shift_en_oshared2), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(avmm1_rstb), .pd_data_aib(nc_pd0_data_fsrldin), + .oclk_out(nc_oclk_fsrldin), .oclkb_out(nc_oclkb_fsrldin), + .odat0_out(osdrin_odat0[1]), .odat1_out(osdrin_odat1[1]), + .odat_async_out(nc_odat_async_fsrldin), + .pd_data_out(nc_pd_data_fsrldin), .async_dat_in0(vssl_aibnd), + .async_dat_in1(iasyncdata_oshared2), + .iclkin_dist_in0(rx_distclk_r[2]), .iclkin_dist_in1(vssl_aibnd), + .idata0_in0(vssl_aibnd), .idata0_in1(vssl_aibnd), + .idata1_in0(vssl_aibnd), .idata1_in1(vssl_aibnd), + .idataselb_in0(vccl_aibnd), .idataselb_in1(idataselb_oshared2), + .iddren_in0(vssl_aibnd), .iddren_in1(vssl_aibnd), + .ilaunch_clk_in0(vssl_aibnd), .ilaunch_clk_in1(vssl_aibnd), + .ilpbk_dat_in0(vssl_aibnd), .ilpbk_dat_in1(vssl_aibnd), + .ilpbk_en_in0(vssl_aibnd), .ilpbk_en_in1(vssl_aibnd), + .indrv_in0({vssl_aibnd, vssl_aibnd}), .indrv_in1(indrv_r12[1:0]), + .ipdrv_in0({vssl_aibnd, vssl_aibnd}), .ipdrv_in1(ipdrv_r12[1:0]), + .irxen_in0(irxen_r2[2:0]), .irxen_in1({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .istrbclk_in0(rx_distclk_r[2]), + .istrbclk_in1(vssl_aibnd), .itxen_in0(vssl_aibnd), + .itxen_in1(itxen_oshared2), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_out0_fsrldin), + .oclkb_in1(vssl_aibnd), .odat0_in1(ossrldin_odat0), + .odat1_in1(ossrldin_odat1), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[6]), .pd_data_in1(vssl_aibnd), + .dig_rstb(resetb_sync_buf), + .jtag_clkdr_out(jtag_clkdr_out_fsrldin), + .odat1_aib(nc_odat0_out1_fsrldin), + .jtag_rx_scan_out(jtag_rx_scan_out_fsrldin), + .odat0_aib(nc_odat0_out0_fsrldin), + .oclk_aib(nc_oclk_out0_fsrldin), + .last_bs_out(last_bs_out_fsrldin), + .oclkb_aib(nc_oclkb_out0_fsrldin), .jtag_clkdr_in(clkdr_xr2r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_oshared2), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_sdr_in[1]), .oclkn(nc_oclkn_out0_fsrldin), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xsdr_in0 ( .idata1_in1_jtag_out(nc_idat1_ssrldin), + .async_dat_in1_jtag_out(nc_async_dat_ssrldin), + .idata0_in1_jtag_out(nc_idat0_ssrldin), + .jtag_clkdr_outn(jtag_clkdr_outn_ssrldin), + .prev_io_shift_en(rx_shift_en[6]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(avmm1_rstb), .pd_data_aib(nc_pd_data_out0_ssrldin), + .oclk_out(nc_oclk_ssrldin), .oclkb_out(nc_oclkb_ssrldin), + .odat0_out(osdrin_odat0[0]), .odat1_out(osdrin_odat1[0]), + .odat_async_out(nc_odat_async_ssrldin), + .pd_data_out(nc_pd_data_ssrldin), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_r[0]), + .iclkin_dist_in1(rx_distclk_r[2]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r2[2:0]), .irxen_in1(irxen_r2[2:0]), + .istrbclk_in0(rx_distclk_r[0]), .istrbclk_in1(rx_distclk_r[0]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_out0_ssrldin), + .oclkb_in1(vssl_aibnd), .odat0_in1(odat0_srcclkinn), + .odat1_in1(odat1_srcclkinn), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[5]), .pd_data_in1(vssl_aibnd), + .dig_rstb(resetb_sync_buf), + .jtag_clkdr_out(jtag_clkdr_out_ssrldin), + .odat1_aib(ossrldin_odat1), + .jtag_rx_scan_out(jtag_rx_scan_out_ssrldin), + .odat0_aib(ossrldin_odat0), .oclk_aib(nc_oclk_out0_ssrldin), + .last_bs_out(last_bs_out_ssrldin), + .oclkb_aib(nc_oclkb_out0_ssrldin), .jtag_clkdr_in(clkdr_xr2r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_fsrldin), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_sdr_in[0]), .oclkn(nc_oclkn_out0_ssrldin), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xrx_clkn ( .idata1_in1_jtag_out(nc_idat1_srcclkinn), + .async_dat_in1_jtag_out(nc_async_dat_srcclkinn), + .idata0_in1_jtag_out(nc_idat0_srcclkinn), + .jtag_clkdr_outn(jtag_clkdr_outn_srcclkinn), + .prev_io_shift_en(rx_shift_en[5]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(avmm1_rstb), .pd_data_aib(pd_data_srcclkinn), + .oclk_out(oclk_inclkn), .oclkb_out(oclk_inclknb), + .odat0_out(ncdrx_odat0_inclkn), .odat1_out(ncdrx_odat1_inclkn), + .odat_async_out(odirectin_data_inclkn), + .pd_data_out(pd_data_inclkn), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_r[4]), + .iclkin_dist_in1(rx_distclk_r[0]), .idata0_in0(vccl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .irxen_in1(irxen_r2[2:0]), .istrbclk_in0(rx_distclk_r[4]), + .istrbclk_in1(rx_distclk_r[4]), .itxen_in0(vssl_aibnd), + .itxen_in1(vssl_aibnd), .oclk_in1(vssl_aibnd), + .odat_async_aib(odirectin_data_srcclkinn), .oclkb_in1(vssl_aibnd), + .odat0_in1(vssl_aibnd), .odat1_in1(vssl_aibnd), + .odat_async_in1(vssl_aibnd), .shift_en(rx_shift_en[4]), + .pd_data_in1(vssl_aibnd), .dig_rstb(resetb_sync_buf), + .jtag_clkdr_out(jtag_clkdr_in_srcclkinn), + .odat1_aib(odat1_srcclkinn), + .jtag_rx_scan_out(jtag_rx_scan_in_srcclkinn), + .odat0_aib(odat0_srcclkinn), .oclk_aib(nc_oclk_srcclkinn), + .last_bs_out(nc), .oclkb_aib(nc_oclkb_srcclkinn), + .jtag_clkdr_in(clkdr_xr2r), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_out_ssrldin), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_inclkn), .oclkn(oclkn_inclkn), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xtx_clkp ( .idata1_in1_jtag_out(idat1_srclkout), + .async_dat_in1_jtag_out(nc_async_dat_srclkout), + .idata0_in1_jtag_out(idat0_srclkout), + .jtag_clkdr_outn(jtag_clkdr_outn_srclkout), + .prev_io_shift_en(shift_en_ptxclkin), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(avmm1_rstb), .pd_data_aib(ncdrx_pd_data_out0_txclkp), + .oclk_out(ncdrx_oclk_txclkp1), .oclkb_out(ncdrx_oclkb_txclkp1), + .odat0_out(ncdrx_odat0_txclkp1), .odat1_out(ncdrx_odat1_txclkp1), + .odat_async_out(ncdrx_odat_async_txclkp1), + .pd_data_out(ncdrx_pd_data_txclkp1), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_srclkout), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0_clkp), + .idata0_in1(vssl_aibnd), .idata1_in0(idat1_clkp), + .idata1_in1(vssl_aibnd), .idataselb_in0(idataselb[1]), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(tx_clkp), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r34[1:0]), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0(ipdrv_r34[1:0]), + .ipdrv_in1({vssl_aibnd, vssl_aibnd}), .irxen_in0({vssl_aibnd, + vccl_aibnd, vssl_aibnd}), .irxen_in1(irxen_ptxclkin[2:0]), + .istrbclk_in0(jtag_clkdr_outn_srclkout), + .istrbclk_in1(vssl_aibnd), .itxen_in0(itxen[1]), + .itxen_in1(vssl_aibnd), .oclk_in1(vssl_aibnd), + .odat_async_aib(ncdrx_odat_async_out0_txclkp), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[9]), .pd_data_in1(vssl_aibnd), + .dig_rstb(resetb_sync_buf), .jtag_clkdr_out(jtag_clkdr_srclkout), + .odat1_aib(ncdrx_odat1_out0_txclkp), + .jtag_rx_scan_out(jtag_rx_scan_srclkout), + .odat0_aib(ncdrx_odat0_out0_txclkp), .oclk_aib(oclk_srclkout), + .last_bs_out(last_bs_out_directout0), .oclkb_aib(oclkb_srclkout), + .jtag_clkdr_in(clkdr_xr3r), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_ptxclkin), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_clkp), .oclkn(ncdrx_oclkn_txclkp), + .iclkn(oclkn_srcclkoutn), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xsdr_out1 ( .idata1_in1_jtag_out(idat1_fsrdout), + .async_dat_in1_jtag_out(nc_async_dat_fsrdout), + .idata0_in1_jtag_out(idat0_fsrdout), + .jtag_clkdr_outn(jtag_clkdr_outn_fsrdout), + .prev_io_shift_en(rx_shift_en[12]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(avmm1_rstb), .pd_data_aib(nc_pd_data_out0_fsrlout), + .oclk_out(nc_oclk_fsrout), .oclkb_out(nc_oclkb_fsrout), + .odat0_out(nc_odat0_fsrout), .odat1_out(nc_odat1_fsrout), + .odat_async_out(nc_odat_async_fsrout), + .pd_data_out(nc_pd_data_fsrout), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_fsrdout), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(isdrin_idat0[1]), + .idata0_in1(idat0_srcclkoutn), .idata1_in0(isdrin_idat1[1]), + .idata1_in1(idat1_srcclkoutn), .idataselb_in0(idataselb[2]), + .idataselb_in1(idataselb[1]), .iddren_in0(vssl_aibnd), + .iddren_in1(vccl_aibnd), .ilaunch_clk_in0(tx_launch_clk_r[0]), + .ilaunch_clk_in1(tx_launch_clk_r[0]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r34[1:0]), + .indrv_in1(indrv_r34[1:0]), .ipdrv_in0(ipdrv_r34[1:0]), + .ipdrv_in1(ipdrv_r34[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_fsrdout), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[2]), .itxen_in1(itxen[1]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_out0_fsrlout), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[13]), .pd_data_in1(vssl_aibnd), + .dig_rstb(resetb_sync_buf), + .jtag_clkdr_out(jtag_clkdr_out_fsrdout), + .odat1_aib(nc_odat1_out0_fsrlout), + .jtag_rx_scan_out(jtag_rx_scan_out_fsrdout), + .odat0_aib(nc_odat0_out0_fsrlout), + .oclk_aib(nc_oclk_out0_fsrlout), + .last_bs_out(last_bs_out_fsrdout), + .oclkb_aib(nc_oclkb_out0_fsrlout), .jtag_clkdr_in(clkdr_xr4r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_srcclkoutn), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_sdr_out[1]), .oclkn(nc_oclkn_out0_fsrlout), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xsdr_out0 ( .idata1_in1_jtag_out(idata1_ssrldout), + .async_dat_in1_jtag_out(nc_async_dat_ssrldout), + .idata0_in1_jtag_out(idata0_ssrldout), + .jtag_clkdr_outn(jtag_clkdr_outn_ssrldout), + .prev_io_shift_en(rx_shift_en[13]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(avmm1_rstb), .pd_data_aib(nc_pd_data_out0_ssrldrout), + .oclk_out(nc_oclk_ssrldout), .oclkb_out(nc_oclkb_ssrldout), + .odat0_out(nc_odat0_ssrldout), .odat1_out(nc_odat1_ssrldout), + .odat_async_out(nc_odat_async_ssrldout), + .pd_data_out(nc_pd_data_ssrldout), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_ssrldout), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(isdrin_idat0[0]), + .idata0_in1(idat0_fsrdout), .idata1_in0(isdrin_idat1[0]), + .idata1_in1(idat1_fsrdout), .idataselb_in0(idataselb[2]), + .idataselb_in1(idataselb[2]), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(tx_launch_clk_r[2]), + .ilaunch_clk_in1(tx_launch_clk_r[2]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r34[1:0]), + .indrv_in1(indrv_r34[1:0]), .ipdrv_in0(ipdrv_r34[1:0]), + .ipdrv_in1(ipdrv_r34[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_ssrldout), + .istrbclk_in1(vssl_aibnd), .itxen_in0(itxen[2]), + .itxen_in1(itxen[2]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_out0_ssrldrout), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[14]), .pd_data_in1(vssl_aibnd), + .dig_rstb(resetb_sync_buf), + .jtag_clkdr_out(jtag_clkdr_in_ssrldout), + .odat1_aib(nc_odat1_out0_ssrldrout), + .jtag_rx_scan_out(jtag_rx_scan_in_ssrldout), + .odat0_aib(nc_odat0_out0_ssrldrout), + .oclk_aib(nc_oclk_out0_ssrldrout), + .last_bs_out(last_bs_out_ssrldout), + .oclkb_aib(nc_oclkb_out0_ssrldrout), .jtag_clkdr_in(clkdr_xr4r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_fsrdout), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_fsrdout), .iopad(iopad_sdr_out[0]), + .oclkn(nc_oclkn_out0_ssrldrout), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xsdr_in3 ( .idata1_in1_jtag_out(nc_idat1_fsrdin), + .async_dat_in1_jtag_out(nc_async_dat_fsrdin), + .idata0_in1_jtag_out(nc_idat0_fsrdin), + .jtag_clkdr_outn(jtag_clkdr_outn_fsrdin), + .prev_io_shift_en(shift_en_inpshared4), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(avmm1_rstb), + .pd_data_aib(nc_pd_data_out0_fsrdin), .oclk_out(nc_oclk_fsrdin), + .oclkb_out(nc_oclkb_fsrdin), .odat0_out(osdrin_odat0[3]), + .odat1_out(osdrin_odat1[3]), + .odat_async_out(nc_odat_async_fsrdin), + .pd_data_out(nc_pd_data_fsrdin), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_r[3]), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r2[2:0]), .irxen_in1(irxen_inpshared4[2:0]), + .istrbclk_in0(rx_distclk_r[3]), .istrbclk_in1(vssl_aibnd), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(odat_async_fsrdin), + .oclkb_in1(vssl_aibnd), .odat0_in1(ossrdin_odat0), + .odat1_in1(ossrdin_odat1), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[0]), .pd_data_in1(vssl_aibnd), + .dig_rstb(resetb_sync_buf), + .jtag_clkdr_out(jtag_clkdr_out_fsrdin), + .odat1_aib(nc_odat1_out0_fsrdin), + .jtag_rx_scan_out(jtag_rx_scan_out_fsrdin), + .odat0_aib(nc_odat0_out0_fsrdin), .oclk_aib(nc_oclk_out0_fsrdin), + .last_bs_out(last_bs_out_fsrdin), + .oclkb_aib(nc_oclkb_out0_fsrdin), .jtag_clkdr_in(clkdr_xr1r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_inpshared4), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_sdr_in[3]), .oclkn(nc_oclkn_out0_fsrdin), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xrx_clkp ( .idata1_in1_jtag_out(nc_idat1_srcclkin), + .async_dat_in1_jtag_out(nc_async_dat_srcclkin), + .idata0_in1_jtag_out(nc_idat0_srcclkin), + .jtag_clkdr_outn(jtag_clkdr_outn_srcclkin), + .prev_io_shift_en(rx_shift_en[1]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(avmm1_rstb), .pd_data_aib(pd_data_srcclkin), + .oclk_out(oclk_inclkp), .oclkb_out(oclk_inclkpb), + .odat0_out(ncdrx_odat0_inclkp), .odat1_out(ncdrx_odat1_inclkp), + .odat_async_out(odirectin_data_inclkp), + .pd_data_out(pd_data_inclkp), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_r[5]), + .iclkin_dist_in1(rx_distclk_r[1]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vccl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r1[2:0]), .irxen_in1(irxen_r2[2:0]), + .istrbclk_in0(rx_distclk_r[5]), .istrbclk_in1(rx_distclk_r[5]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(oclk_vinp0), .odat_async_aib(odirectin_data_srcclkin), + .oclkb_in1(oclk_inclkpb_ext), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[2]), .pd_data_in1(vssl_aibnd), + .dig_rstb(resetb_sync_buf), + .jtag_clkdr_out(jtag_clkdr_in_srcclkin), + .odat1_aib(odat1_srcclkin), + .jtag_rx_scan_out(jtag_rx_scan_in_srcclkin), + .odat0_aib(odat0_srcclkin), .oclk_aib(ncdrx_oclk_srcclkin), + .last_bs_out(last_bs_out_srcclkin), + .oclkb_aib(drx_oclkb_srcclkin), .jtag_clkdr_in(clkdr_xr1r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_ssrdin), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_inclkp), .oclkn(ncdrx_oclkn_srcclkin), + .iclkn(oclkn_inclkn), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xavmm1_out0 ( .idata1_in1_jtag_out(idat1_voutp00), + .async_dat_in1_jtag_out(nc_async_dat_voutp00), + .idata0_in1_jtag_out(idat0_voutp00), + .jtag_clkdr_outn(jtag_clkdr_outn_voutp00), + .prev_io_shift_en(shift_en_voutp10), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(avmm1_rstb), .pd_data_aib(nc_pd_data_avmout0), + .oclk_out(nc_oclk_avmout011), .oclkb_out(nc_oclkb_avmout011), + .odat0_out(nc_odat0_avmout011), .odat1_out(nc_odat1_avmout011), + .odat_async_out(nc_odat_async_avmout011), + .pd_data_out(nc_pd_data_avmout011), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_voutp00), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(avmm1_idat0[0]), + .idata0_in1(idat0_voutp10), .idata1_in0(avmm1_idat1[0]), + .idata1_in1(idat1_voutp10), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb_voutp10), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(tx_launch_clk_l[3]), + .ilaunch_clk_in1(tx_launch_clk_l[3]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r34[1:0]), + .indrv_in1(indrv_r34[1:0]), .ipdrv_in0(ipdrv_r34[1:0]), + .ipdrv_in1(ipdrv_r34[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_voutp00), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen_voutp10), + .oclk_in1(vssl_aibnd), .odat_async_aib(nc_odat_async_avmout0), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[10]), .pd_data_in1(vssl_aibnd), + .dig_rstb(resetb_sync_buf), .jtag_clkdr_out(jtag_clkdr_voutp00), + .odat1_aib(nc_odat1_avmout0), + .jtag_rx_scan_out(jtag_rx_scan_voutp00), + .odat0_aib(nc_odat0_avmout0), .oclk_aib(nc_oclk_avmout0), + .last_bs_out(last_bs_out_voutp00), .oclkb_aib(nc_oclkb_avmout0), + .jtag_clkdr_in(clkdr_xr3l), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_in_voutp10), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_avmm1_out[0]), .oclkn(nc_oclkn_avmout0), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xsdr_out3 ( .idata1_in1_jtag_out(idat1_fsrldout), + .async_dat_in1_jtag_out(nc_async_dat_fsrldout), + .idata0_in1_jtag_out(idat0_fsrldout), + .jtag_clkdr_outn(jtag_clkdr_outn_fsrldout), + .prev_io_shift_en(rx_shift_en[9]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(avmm1_rstb), .pd_data_aib(nc_pd_data_out0_fsrout), + .oclk_out(nc_oclk_fsrout1), .oclkb_out(nc_oclkb_fsrout1), + .odat0_out(nc_odat0_fsrout1), .odat1_out(nc_odat1_fsrout1), + .odat_async_out(nc_odat_async_fsrout1), + .pd_data_out(nc_pd_data_fsrout1), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_fsrldout), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(isdrin_idat0[3]), + .idata0_in1(idat0_srclkout), .idata1_in0(isdrin_idat1[3]), + .idata1_in1(idat1_srclkout), .idataselb_in0(idataselb[2]), + .idataselb_in1(idataselb[1]), .iddren_in0(vssl_aibnd), + .iddren_in1(vccl_aibnd), .ilaunch_clk_in0(tx_launch_clk_r[1]), + .ilaunch_clk_in1(tx_launch_clk_r[1]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r34[1:0]), + .indrv_in1(indrv_r34[1:0]), .ipdrv_in0(ipdrv_r34[1:0]), + .ipdrv_in1(ipdrv_r34[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_fsrldout), + .istrbclk_in1(vssl_aibnd), .itxen_in0(itxen[2]), + .itxen_in1(itxen[1]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_out0_fsrout), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[8]), .pd_data_in1(vssl_aibnd), + .dig_rstb(resetb_sync_buf), + .jtag_clkdr_out(jtag_clkdr_out_fsrldout), + .odat1_aib(nc_odat1_out0_fsrout), + .jtag_rx_scan_out(jtag_rx_scan_out_fsrldout), + .odat0_aib(nc_odat0_out0_fsrout), .oclk_aib(nc_oclk_out0_fsrout), + .last_bs_out(last_bs_out_fsrldout), + .oclkb_aib(nc_oclkb_out0_fsrout), .jtag_clkdr_in(clkdr_xr3r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_srclkout), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_sdr_out[3]), .oclkn(nc_oclkn_out0_fsrout), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xsdr_in2 ( .idata1_in1_jtag_out(nc_idat1_ssrdin), + .async_dat_in1_jtag_out(nc_async_dat_ssrdin), + .idata0_in1_jtag_out(nc_idat0_ssrdin), + .jtag_clkdr_outn(jtag_clkdr_outn_ssrdin), + .prev_io_shift_en(rx_shift_en[0]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(avmm1_rstb), .pd_data_aib(nc_pd_data_out0_ssrdin), + .oclk_out(nc_oclk_ssrdin), .oclkb_out(nc_oclkb_ssrdin), + .odat0_out(osdrin_odat0[2]), .odat1_out(osdrin_odat1[2]), + .odat_async_out(nc_odat_async_ssrdin), + .pd_data_out(nc_pd_data_ssrdin), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_r[1]), + .iclkin_dist_in1(rx_distclk_r[3]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r2[2:0]), .irxen_in1(irxen_r2[2:0]), + .istrbclk_in0(rx_distclk_r[1]), .istrbclk_in1(rx_distclk_r[1]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(nc_odat_async_out0_ssrdin), + .oclkb_in1(vssl_aibnd), .odat0_in1(odat0_srcclkin), + .odat1_in1(odat1_srcclkin), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[1]), .pd_data_in1(vssl_aibnd), + .dig_rstb(resetb_sync_buf), + .jtag_clkdr_out(jtag_clkdr_out_ssrdin), .odat1_aib(ossrdin_odat1), + .jtag_rx_scan_out(jtag_rx_scan_out_ssrdin), + .odat0_aib(ossrdin_odat0), .oclk_aib(nc_oclk_out0_ssrdin), + .last_bs_out(last_bs_out_ssrdin), + .oclkb_aib(nc_oclkb_out0_ssrdin), .jtag_clkdr_in(clkdr_xr1r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_fsrdin), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_sdr_in[2]), .oclkn(nc_oclkn_out0_ssrdin), + .test_weakpd(jtag_weakpdn), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu)); +aibnd_buffx1_top xrx ( .idata1_in1_jtag_out(nc_idat1_vinp0), + .async_dat_in1_jtag_out(nc_async_dat_vinp0), + .idata0_in1_jtag_out(nc_idat0_vinp0), + .jtag_clkdr_outn(jtag_clkdr_outn_vinp0), + .prev_io_shift_en(rx_shift_en[2]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(avmm1_rstb), .pd_data_aib(nc_pd_data_out0_rx), + .oclk_out(nc_oclk_rx), .oclkb_out(nc_oclkb_rx), + .odat0_out(avmm1_odat0), .odat1_out(avmm1_odat1), + .odat_async_out(nc_odat_async_rx), .pd_data_out(nc_pd_data_rx), + .async_dat_in0(vssl_aibnd), .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(rx_distclk_l[7]), .iclkin_dist_in1(vssl_aibnd), + .idata0_in0(vssl_aibnd), .idata0_in1(vssl_aibnd), + .idata1_in0(vssl_aibnd), .idata1_in1(vssl_aibnd), + .idataselb_in0(vccl_aibnd), .idataselb_in1(vssl_aibnd), + .iddren_in0(vssl_aibnd), .iddren_in1(vssl_aibnd), + .ilaunch_clk_in0(vssl_aibnd), .ilaunch_clk_in1(vssl_aibnd), + .ilpbk_dat_in0(vssl_aibnd), .ilpbk_dat_in1(vssl_aibnd), + .ilpbk_en_in0(vssl_aibnd), .ilpbk_en_in1(vssl_aibnd), + .indrv_in0({vssl_aibnd, vssl_aibnd}), .indrv_in1({vssl_aibnd, + vssl_aibnd}), .ipdrv_in0({vssl_aibnd, vssl_aibnd}), + .ipdrv_in1({vssl_aibnd, vssl_aibnd}), .irxen_in0(irxen_r0[2:0]), + .irxen_in1(irxen_r1[2:0]), .istrbclk_in0(rx_distclk_l[7]), + .istrbclk_in1(vssl_aibnd), .itxen_in0(vssl_aibnd), + .itxen_in1(vssl_aibnd), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_out0_rx), .oclkb_in1(vssl_aibnd), + .odat0_in1(odat0_outpclk1_1), .odat1_in1(odat1_outpclk1_1), + .odat_async_in1(vssl_aibnd), .shift_en(rx_shift_en[3]), + .pd_data_in1(vssl_aibnd), .dig_rstb(resetb_sync_buf), + .jtag_clkdr_out(jtag_clkdr_vinp0), .odat1_aib(nc_odat1_out0_rx), + .jtag_rx_scan_out(jtag_rx_scan_vinp0), + .odat0_aib(nc_odat0_out0_rx), .oclk_aib(oclk_vinp0), + .last_bs_out(last_bs_out_vinp0), .oclkb_aib(oclkb_vinp0), + .jtag_clkdr_in(clkdr_xr1l), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_in_srcclkin), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_avmm1_in), .oclkn(nc_oclkn_out0_rx), + .iclkn(oclkn_vinp1), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xsdr_out2 ( .idata1_in1_jtag_out(idata1_ssrdout), + .async_dat_in1_jtag_out(nc_async_dat_ssrdout), + .idata0_in1_jtag_out(idata0_ssrdout), + .jtag_clkdr_outn(jtag_clkdr_outn_ssrdout), + .prev_io_shift_en(rx_shift_en[8]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(avmm1_rstb), .pd_data_aib(nc_pd_data_out0_sdrout), + .oclk_out(nc_oclk_sdrout), .oclkb_out(nc_oclkb_ssdrout), + .odat0_out(nc_odat0_sdrout), .odat1_out(nc_odat1_ssdrout), + .odat_async_out(nc_odat_async_sdrout), + .pd_data_out(nc_pd_data_sdrout), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_ssrdout), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(isdrin_idat0[2]), + .idata0_in1(idat0_fsrldout), .idata1_in0(isdrin_idat1[2]), + .idata1_in1(idat1_fsrldout), .idataselb_in0(idataselb[2]), + .idataselb_in1(idataselb[2]), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(tx_launch_clk_r[3]), + .ilaunch_clk_in1(tx_launch_clk_r[3]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r34[1:0]), + .indrv_in1(indrv_r34[1:0]), .ipdrv_in0(ipdrv_r34[1:0]), + .ipdrv_in1(ipdrv_r34[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_ssrdout), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[2]), .itxen_in1(itxen[2]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_out0_sdrout), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[7]), .pd_data_in1(vssl_aibnd), + .dig_rstb(resetb_sync_buf), + .jtag_clkdr_out(jtag_clkdr_in_ssrdout), + .odat1_aib(nc_odat1_out0_ssdrout), + .jtag_rx_scan_out(jtag_rx_scan_in_ssrdout), + .odat0_aib(nc_odat0_out0_sdrout), .oclk_aib(nc_oclk_out0_sdrout), + .last_bs_out(last_bs_out_ssrdout), + .oclkb_aib(nc_oclkb_out0_ssdrout), .jtag_clkdr_in(clkdr_xr3r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_fsrldout), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_fsrldout), .iopad(iopad_sdr_out[2]), + .oclkn(nc_oclkn_out0_ssdrout), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_clktree_avmm_pcs xin_clktree ( /*.vcc_aibnd(vccl_aibnd), + .vss_aibnd(vssl_aibnd),*/ .lstrbclk_mimic2(clk_distclk), + .lstrbclk_r_7(rx_distclk_r[7]), .lstrbclk_r_6(rx_distclk_r[6]), + .lstrbclk_r_5(rx_distclk_r[5]), .lstrbclk_r_4(rx_distclk_r[4]), + .lstrbclk_r_3(rx_distclk_r[3]), .lstrbclk_r_2(rx_distclk_r[2]), + .lstrbclk_r_1(rx_distclk_r[1]), .lstrbclk_r_0(rx_distclk_r[0]), + .lstrbclk_mimic1(clk_mimic11), .lstrbclk_mimic0(clk_mimic01), + .lstrbclk_l_0(rx_distclk_l[0]), .lstrbclk_l_1(rx_distclk_l[1]), + .lstrbclk_l_2(rx_distclk_l[2]), .lstrbclk_l_3(rx_distclk_l[3]), + .lstrbclk_l_4(rx_distclk_l[4]), .lstrbclk_l_5(rx_distclk_l[5]), + .lstrbclk_l_6(rx_distclk_l[6]), .lstrbclk_l_7(rx_distclk_l[7]), + .lstrbclk_rep(avmm_pcs_clk), .clkin(oclk_inclkpb_ext)); +aibnd_txdat_mimic x570 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .idata_out(avmm_tx_clk_in_dly), + .idata_in(avmm_tx_clk_in)); +assign avmm_pcs_clk_buf = avmm_pcs_clk ; +aibnd_rxdat_mimic x571 ( .odat_out(pcs_clk), .odat_in(pre_pcs_clk), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd)); +aibnd_avmm_rst_sync x568 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .pcs_clk(pre_pcs_clk), + .pcs_clkb(pcs_clkb), .resetb_sync_buf(resetb_sync_buf), + .avmm_clk(avmm_pcs_clk_buf), .avmm_rstb(avmm1_rstb)); + + +aibnd_clkmux2 xavmm_rx_clkmx ( + .oclk_out(oclk_inclkpb_ext), + .mux_sel(rx_shift_en[2]), .oclk_in0(drx_oclkb_srcclkin), + .oclk_in1(oclkb_vinp0)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_avmm2.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_avmm2.v new file mode 100644 index 0000000..d46e9ac --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_avmm2.v @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_avmm2, View - schematic +// LAST TIME SAVED: Jul 6 22:07:17 2015 +// NETLIST TIME: Jul 8 13:09:51 2015 +// `timescale 1ns / 1ns + +module aibnd_avmm2 ( avmm2_odat0, avmm2_odat1, idat0_voutp10, + idat0_voutp11, idat1_voutp10, idat1_voutp11, idataselb_voutp10, + idataselb_voutp11, irxen_vinp1, itxen_voutp10, itxen_voutp11, + jtag_clkdr_in_dirin5, jtag_clkdr_in_voutp10, jtag_clkdr_vinp1, + jtag_rx_scan_in_dirin5, jtag_rx_scan_in_voutp10, + jtag_rx_scan_vinp1, oclkn_vinp1, shift_en_vinp1, shift_en_voutp10, + shift_en_voutp11, iopad_avmm2_in, iopad_avmm2_out, + async_dat_outpdir1_1, avmm2_idat0, avmm2_idat1, avmm2_rstb, + avmm_sync_rstb, clkdr_xr2l, clkdr_xr3l, clkdr_xr4l, idataselb, + idataselb_in0_directout2, idataselb_outpdir1_1, + idirectout_data_outpdir2_1, indrv_r34, ipdrv_r34, irxen_r0, itxen, + itxen_in0_directout2, itxen_outpdir1_1, jtag_clkdr_out_dirout2, + jtag_clkdr_out_outpdir1_1, jtag_clkdr_srcclkinn, jtag_clksel, + jtag_intest, jtag_mode_in, jtag_rstb, jtag_rstb_en, + jtag_rx_scan_out_dirout2, jtag_rx_scan_out_outpdir1_1, + jtag_rx_scan_srcclkinn, jtag_tx_scanen_in, jtag_weakpdn, + jtag_weakpu, odat0_outpdir0_1, odat1_outpdir0_1, rshift_en_rx, + rshift_en_tx, rx_distclk_vinp1, rx_strbclk_vinp1, + shift_en_directout2, shift_en_outpdir1_1, shift_en_srcclkinn, + tx_launch_clk_l0, tx_launch_clk_l1, vccl_aibnd, vssl_aibnd ); + +output avmm2_odat0, avmm2_odat1, idat0_voutp10, idat0_voutp11, + idat1_voutp10, idat1_voutp11, idataselb_voutp10, + idataselb_voutp11, itxen_voutp10, itxen_voutp11, + jtag_clkdr_in_dirin5, jtag_clkdr_in_voutp10, jtag_clkdr_vinp1, + jtag_rx_scan_in_dirin5, jtag_rx_scan_in_voutp10, + jtag_rx_scan_vinp1, oclkn_vinp1, shift_en_vinp1, shift_en_voutp10, + shift_en_voutp11; + +inout iopad_avmm2_in; + +input async_dat_outpdir1_1, avmm2_rstb, avmm_sync_rstb, clkdr_xr2l, + clkdr_xr3l, clkdr_xr4l, idataselb, idataselb_in0_directout2, + idataselb_outpdir1_1, idirectout_data_outpdir2_1, itxen, + itxen_in0_directout2, itxen_outpdir1_1, jtag_clkdr_out_dirout2, + jtag_clkdr_out_outpdir1_1, jtag_clkdr_srcclkinn, jtag_clksel, + jtag_intest, jtag_mode_in, jtag_rstb, jtag_rstb_en, + jtag_rx_scan_out_dirout2, jtag_rx_scan_out_outpdir1_1, + jtag_rx_scan_srcclkinn, jtag_tx_scanen_in, jtag_weakpdn, + jtag_weakpu, odat0_outpdir0_1, odat1_outpdir0_1, rshift_en_rx, + rx_distclk_vinp1, rx_strbclk_vinp1, shift_en_directout2, + shift_en_outpdir1_1, shift_en_srcclkinn, tx_launch_clk_l0, + tx_launch_clk_l1, vccl_aibnd, vssl_aibnd; + +output [2:0] irxen_vinp1; + +inout [1:0] iopad_avmm2_out; + +input [1:0] indrv_r34; +input [1:0] ipdrv_r34; +input [2:0] irxen_r0; +input [1:0] avmm2_idat0; +input [1:0] rshift_en_tx; +input [1:0] avmm2_idat1; + +// Buses in the design + +wire [0:1] nctx_oclkn; + +wire [0:1] nctx_odat_async_aib; + +wire [0:1] nctx_oclk; + +wire [0:1] nctx_odat0; + +wire [0:1] nctx_oclkb; + +wire [0:1] nctx_oclk_aib; + +wire [0:1] nctx_odat1; + +wire [0:1] nctx_pd_data_aib; + +wire [0:1] nctx_oclkb_aib; + +wire [0:1] nctx_odat1_aib; + +wire [0:1] nctx_odat_async; + +wire [0:1] nctx_odat0_aib; + +wire [0:1] nctx_pd_data; + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_avmm2"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +aibnd_buffx1_top xtx0 ( .idata1_in1_jtag_out(idat1_voutp10), + .async_dat_in1_jtag_out(nc_async_dat_voutp10), + .idata0_in1_jtag_out(idat0_voutp10), + .jtag_clkdr_outn(jtag_clkdr_outn_voutp10), + .prev_io_shift_en(shift_en_outpdir1_1), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(avmm2_rstb), + .pd_data_aib(nctx_pd_data_aib[0]), .oclk_out(nctx_oclk[0]), + .oclkb_out(nctx_oclkb[0]), .odat0_out(nctx_odat0[0]), + .odat1_out(nctx_odat1[0]), .odat_async_out(nctx_odat_async[0]), + .pd_data_out(nctx_pd_data[0]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(async_dat_outpdir1_1), + .iclkin_dist_in0(jtag_clkdr_outn_voutp10), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(avmm2_idat0[0]), + .idata0_in1(vssl_aibnd), .idata1_in0(avmm2_idat1[0]), + .idata1_in1(vssl_aibnd), .idataselb_in0(idataselb), + .idataselb_in1(idataselb_outpdir1_1), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(tx_launch_clk_l1), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r34[1:0]), + .indrv_in1(indrv_r34[1:0]), .ipdrv_in0(ipdrv_r34[1:0]), + .ipdrv_in1(ipdrv_r34[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_voutp10), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen), .itxen_in1(itxen_outpdir1_1), + .oclk_in1(vssl_aibnd), .odat_async_aib(nctx_odat_async_aib[0]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_tx[0]), .pd_data_in1(vssl_aibnd), + .dig_rstb(avmm_sync_rstb), .jtag_clkdr_out(jtag_clkdr_in_voutp10), + .odat1_aib(nctx_odat1_aib[0]), + .jtag_rx_scan_out(jtag_rx_scan_in_voutp10), + .odat0_aib(nctx_odat0_aib[0]), .oclk_aib(nctx_oclk_aib[0]), + .last_bs_out(nc_last_bs_out_voutp10), + .oclkb_aib(nctx_oclkb_aib[0]), .jtag_clkdr_in(clkdr_xr3l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_outpdir1_1), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_avmm2_out[0]), .oclkn(nctx_oclkn[0]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xtx1 ( .idata1_in1_jtag_out(idat1_voutp11), + .async_dat_in1_jtag_out(nc_async_dat_voutp11), + .idata0_in1_jtag_out(idat0_voutp11), + .jtag_clkdr_outn(jtag_clkdr_outn_voutp11), + .prev_io_shift_en(shift_en_directout2), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(avmm2_rstb), + .pd_data_aib(nctx_pd_data_aib[1]), .oclk_out(nctx_oclk[1]), + .oclkb_out(nctx_oclkb[1]), .odat0_out(nctx_odat0[1]), + .odat1_out(nctx_odat1[1]), .odat_async_out(nctx_odat_async[1]), + .pd_data_out(nctx_pd_data[1]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(idirectout_data_outpdir2_1), + .iclkin_dist_in0(jtag_clkdr_outn_voutp11), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(avmm2_idat0[1]), + .idata0_in1(vssl_aibnd), .idata1_in0(avmm2_idat1[1]), + .idata1_in1(vssl_aibnd), .idataselb_in0(idataselb), + .idataselb_in1(idataselb_in0_directout2), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(tx_launch_clk_l0), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r34[1:0]), + .indrv_in1(indrv_r34[1:0]), .ipdrv_in0(ipdrv_r34[1:0]), + .ipdrv_in1(ipdrv_r34[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_voutp11), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen), .itxen_in1(itxen_in0_directout2), + .oclk_in1(vssl_aibnd), .odat_async_aib(nctx_odat_async_aib[1]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_tx[1]), .pd_data_in1(vssl_aibnd), + .dig_rstb(avmm_sync_rstb), .jtag_clkdr_out(jtag_clkdr_in_dirin5), + .odat1_aib(nctx_odat1_aib[1]), + .jtag_rx_scan_out(jtag_rx_scan_in_dirin5), + .odat0_aib(nctx_odat0_aib[1]), .oclk_aib(nctx_oclk_aib[1]), + .last_bs_out(nc_last_bs_out_voutp11), + .oclkb_aib(nctx_oclkb_aib[1]), .jtag_clkdr_in(clkdr_xr4l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_dirout2), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_avmm2_out[1]), .oclkn(nctx_oclkn[1]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top x96 ( .idata1_in1_jtag_out(nc_idata1_vinp1), + .async_dat_in1_jtag_out(nc_async_dat_vinp1), + .idata0_in1_jtag_out(nc_idata0_vinp1), + .jtag_clkdr_outn(jtag_clkdr_outn_clkdr), + .prev_io_shift_en(shift_en_srcclkinn), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(avmm2_rstb), + .pd_data_aib(ncrx_pd_data_aib), .oclk_out(ncrx_oclk), + .oclkb_out(ncrx_oclkb), .odat0_out(avmm2_odat0), + .odat1_out(avmm2_odat1), .odat_async_out(ncrx_odat_async), + .pd_data_out(ncrx_pd_data), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_vinp1), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .istrbclk_in0(rx_strbclk_vinp1), + .istrbclk_in1(vssl_aibnd), .itxen_in0(vssl_aibnd), + .itxen_in1(vssl_aibnd), .oclk_in1(vssl_aibnd), + .odat_async_aib(ncrx_odat_async_aib), .oclkb_in1(vssl_aibnd), + .odat0_in1(odat0_outpdir0_1), .odat1_in1(odat1_outpdir0_1), + .odat_async_in1(vssl_aibnd), .shift_en(rshift_en_rx), + .pd_data_in1(vssl_aibnd), .dig_rstb(avmm_sync_rstb), + .jtag_clkdr_out(jtag_clkdr_vinp1), .odat1_aib(ncrx_odat1_aib), + .jtag_rx_scan_out(jtag_rx_scan_vinp1), .odat0_aib(ncrx_odat0_aib), + .oclk_aib(ncrx_oclk_aib), .last_bs_out(nc_last_bs_out_avmm2in), + .oclkb_aib(ncrx_oclkb_aib), .jtag_clkdr_in(clkdr_xr2l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_srcclkinn), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_avmm2_in), .oclkn(oclkn_vinp1), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_aliasd aliasv7 ( .MINUS(itxen_voutp10), .PLUS(itxen)); +aibnd_aliasd aliasv16 ( .MINUS(idataselb_voutp10), .PLUS(idataselb)); +aibnd_aliasd aliasv14 ( .MINUS(idataselb_voutp11), .PLUS(idataselb)); +aibnd_aliasd aliasv19[2:0] ( .MINUS(irxen_vinp1[2:0]), .PLUS(irxen_r0[2:0])); +aibnd_aliasd aliasv8 ( .MINUS(itxen_voutp11), .PLUS(itxen)); +aibnd_aliasd aliasd1 ( .MINUS(shift_en_voutp11), .PLUS(rshift_en_tx[1])); +aibnd_aliasd aliasd2 ( .MINUS(shift_en_vinp1), .PLUS(rshift_en_rx)); +aibnd_aliasd aliasd0 ( .MINUS(shift_en_voutp10), .PLUS(rshift_en_tx[0])); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_avmm_rst_sync.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_avmm_rst_sync.v new file mode 100644 index 0000000..ebca66a --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_avmm_rst_sync.v @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_avmm_rst_sync, View - schematic +// LAST TIME SAVED: Apr 22 09:42:47 2015 +// NETLIST TIME: May 12 17:53:10 2015 +// `timescale 1ns / 1ns + +module aibnd_avmm_rst_sync ( pcs_clk, pcs_clkb, resetb_sync_buf, + avmm_clk, avmm_rstb, vccl_aibnd, vssl_aibnd ); + +output pcs_clk, pcs_clkb, resetb_sync_buf; + +input avmm_clk, avmm_rstb, vccl_aibnd, vssl_aibnd; + +wire gated_avmm_clk, pcs_clk, reset_b_sync, resetb_sync_buf, avmm_clk, avmm_clk_inv, pcs_clkb, clockgateb; // Conversion Sript Generated + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_avmm_rst_sync"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +assign pcs_clk = gated_avmm_clk; +assign resetb_sync_buf = reset_b_sync; +assign avmm_clk_inv = !avmm_clk; +assign pcs_clkb = !gated_avmm_clk; +aibnd_2ff_scan xsync ( .d(vccl_aibnd), .clk(avmm_clk), .o(reset_b_sync) /*`ifndef INTCNOPWR , .vcc(vccl_aibnd) `endif*/ , .rb(avmm_rstb), .si(vssl_aibnd) /*`ifndef INTCNOPWR , .vss(vssl_aibnd) `endif*/ , .so(nc_so_sync), .ssb(vccl_aibnd)); +aibnd_ff_r fyn0 ( .o(clockgateb), .d(vccl_aibnd), .clk(avmm_clk_inv) /*`ifndef INTCNOPWR , .vss(vssl_aibnd) , .vcc(vccl_aibnd) `endif*/ , .rb(reset_b_sync)); +assign gated_avmm_clk = avmm_clk & clockgateb; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_bsr_red_wrap.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_bsr_red_wrap.v new file mode 100644 index 0000000..24fa6ca --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_bsr_red_wrap.v @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Verilog HDL and netlist files of +// "aibnd_lib aibnd_bsr_red_wrap schematic" + + +// Library - aibnd_lib(// Library - aibnd_lib), Cell - aibnd_bsr_red_wrap, View - schematic +// LAST TIME SAVED: Oct 24 09:56:41 2014 +// NETLIST TIME: Oct 29 15:26:36 2014 + +module aibnd_bsr_red_wrap ( anlg_rstb_aib, async_data_aib, + dig_rstb_aib, iclkin_dist_out, idat0_aib, idat1_aib, + idataselb_out, iddren_out, ilaunch_clk_out, ilpbk_dat_out, + ilpbk_en_out, indrv_out, ipdrv_out, irxen_out, istrbclk_out, + itxen_aib, jtag_clkdr_out, jtag_rx_scan_out, jtag_tx_scan_out, + last_bs_out, oclk_out, oclkb_out, odat0_out, odat1_out, + odat_async_out, pd_data_out, anlg_rstb_adap, //removed VCCL & VSS port + async_dat_in0, async_dat_in1, dig_rstb_adap, iclkin_dist_in0, + iclkin_dist_in1, idata0_in0, idata0_in1, idata1_in0, idata1_in1, + idataselb_in0, idataselb_in1, iddren_in0, iddren_in1, + ilaunch_clk_in0, ilaunch_clk_in1, ilpbk_dat_in0, ilpbk_dat_in1, + ilpbk_en_in0, ilpbk_en_in1, indrv_in0, indrv_in1, ipdrv_in0, + ipdrv_in1, irxen_in0, irxen_in1, istrbclk_in0, istrbclk_in1, + itxen_in0, itxen_in1, jtag_clkdr_in, jtag_loopbacken_in, + jtag_mode_in, jtag_rst_en, jtag_rstb, jtag_rx_scan_in, + jtag_rx_scanen_in, jtag_tx_scan_in, jtag_tx_scanen_in, last_bs_in, + oclk_aib, oclk_in0, oclk_in1, oclkb_in0, oclkb_in1, odat0_aib, + odat0_in0, odat0_in1, odat1_aib, odat1_in0, odat1_in1, + odat_asyn_aib, odat_async_in0, odat_async_in1, pd_data_in0, + pd_data_in1, shift_en ); + +output anlg_rstb_aib, async_data_aib, dig_rstb_aib, iclkin_dist_out, + idat0_aib, idat1_aib, idataselb_out, iddren_out, ilaunch_clk_out, + ilpbk_dat_out, ilpbk_en_out, istrbclk_out, itxen_aib, + jtag_clkdr_out, jtag_rx_scan_out, jtag_tx_scan_out, last_bs_out, + oclk_out, oclkb_out, odat0_out, odat1_out, odat_async_out, + pd_data_out; + +//input vccl, vssl; + +input anlg_rstb_adap, async_dat_in0, async_dat_in1, dig_rstb_adap, + iclkin_dist_in0, iclkin_dist_in1, idata0_in0, idata0_in1, + idata1_in0, idata1_in1, idataselb_in0, idataselb_in1, iddren_in0, + iddren_in1, ilaunch_clk_in0, ilaunch_clk_in1, ilpbk_dat_in0, + ilpbk_dat_in1, ilpbk_en_in0, ilpbk_en_in1, istrbclk_in0, + istrbclk_in1, itxen_in0, itxen_in1, jtag_clkdr_in, + jtag_loopbacken_in, jtag_mode_in, jtag_rst_en, jtag_rstb, + jtag_rx_scan_in, jtag_rx_scanen_in, jtag_tx_scan_in, + jtag_tx_scanen_in, last_bs_in, oclk_aib, oclk_in0, oclk_in1, + oclkb_in0, oclkb_in1, odat0_aib, odat0_in0, odat0_in1, odat1_aib, + odat1_in0, odat1_in1, odat_asyn_aib, odat_async_in0, + odat_async_in1, pd_data_in0, pd_data_in1, shift_en; + +output [2:0] irxen_out; +output [1:0] ipdrv_out; +output [1:0] indrv_out; + +input [1:0] indrv_in1; +input [2:0] irxen_in0; +input [1:0] ipdrv_in1; +input [2:0] irxen_in1; +input [1:0] ipdrv_in0; +input [1:0] indrv_in0; + + +aibnd_redundancy xredundancy ( //input of input mux +pd_data_in1, pd_data_in0, iclkin_dist_in1, iclkin_dist_in0, idata0_in1, idata0_in0, idata1_in1, idata1_in0, +idataselb_in1, idataselb_in0, iddren_in1, iddren_in0, ilaunch_clk_in1, ilaunch_clk_in0, ilpbk_dat_in1, ilpbk_dat_in0, ilpbk_en_in1, ilpbk_en_in0, +irxen_in1, irxen_in0, istrbclk_in1, istrbclk_in0, itxen_in1, itxen_in0, indrv_in1, indrv_in0, ipdrv_in1, ipdrv_in0, async_dat_in1, async_dat_in0, +//Output of input mux +iclkin_dist_out, idata0_out, idata1_out, idataselb_out, iddren_out, ilaunch_clk_out, ilpbk_dat_out, ilpbk_en_out, +irxen_out, istrbclk_out, itxen_out, indrv_out, ipdrv_out, async_dat_out, + +//input of output mux +oclkb_in1, oclkb_in0, oclk_in1, oclk_in0, odat0_in1, odat0_in0, odat1_in1, odat1_in0, odat_async_in1, odat_async_in0, + +//Output of output mux +pd_data_out, oclkb_out, oclk_out, odat0_out, odat1_out, odat_async_out, + +//Mux selection signal +shift_en ); //removed VCCL & VSS port + + + +aibnd_jtag_bscan xjtag( +.odat0_aib(odat0_aib), //sync data0 RX from AIB +.odat1_aib(odat1_aib), //sync data1 RX from AIB +.odat_asyn_aib(odat_asyn_aib), //async data RX from AIB +.oclk_aib(oclk_aib), //diff clk RX from AIB +.itxen_adap(itxen_out), //OE TX from HSSI Adapter +.idat0_adap(idata0_out), //SDR dat0 TX from HSSI Adapter +.idat1_adap(idata1_out), //SDR dat1 TX from HSSI Adapter +.async_data_adap(async_dat_out), //async data TX from HSSI Adapter +.jtag_tx_scanen_in(jtag_tx_scanen_in), //JTAG shift DR, active high +.jtag_rx_scanen_in(jtag_rx_scanen_in), //JTAG shift DR, active high +.jtag_clkdr_in(jtag_clkdr_in), //JTAG boundary scan clock +.jtag_tx_scan_in(jtag_tx_scan_in), //JTAG TX data scan in +.jtag_rx_scan_in(jtag_rx_scan_in), //JTAG TX data scan in +.jtag_mode_in(jtag_mode_in), //JTAG mode select + + +//.jtag_loopbacken_in(jtag_loopbacken_in), //HIJACK_DFT TW: need to remove from top level schematic +.last_bs_in(last_bs_in), //scan-out loopback feedthru back to SSM +.anlg_rstb_adap(anlg_rstb_adap), //IRSTB from Adaptor +.dig_rstb_adap(dig_rstb_adap), //IRSTB from Adaptor +.jtag_rstb_en(jtag_rst_en), //reset_en from TAP +.jtag_rstb(jtag_rstb), //reset signal from TAP + +.jtag_clkdr_out(jtag_clkdr_out), //CLKDR to remaining BSR +.jtag_tx_scan_out(jtag_tx_scan_out), //JTAG TX scan chain output +.jtag_rx_scan_out(jtag_rx_scan_out), //JTAG TX scan chain output +.odat0_adap(), //sync data0 RX to HSSI Adapter +.odat1_adap(), //sync data1 RX to HSSI Adapter +.oclk_adap(), //sync data1 RX to HSSI Adapter +.odat_asyn_adap(), //async data RX to HSSI Adapter +.itxen_aib(itxen_aib), //OE TX to AIB +.idat0_aib(idat0_aib), //SDR dat0 TX to AIB +.idat1_aib(idat1_aib), //SDR dat1 TX to AIB +.async_data_aib(async_data_aib), //async data TX to AIB +.anlg_rstb_aib(anlg_rstb_aib), //irstb to AIB +.dig_rstb_aib(dig_rstb_aib), //irstb to AIB +.last_bs_out(last_bs_out) //scan-out loopback feedthru back to SSM + +); + + +endmodule + + +// End HDL models + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_buffx1.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_buffx1.v new file mode 100644 index 0000000..debeed0 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_buffx1.v @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_buffx1, View - schematic +// LAST TIME SAVED: Dec 15 17:40:04 2014 +// NETLIST TIME: Dec 17 10:24:02 2014 + +module aibnd_buffx1 ( oclk, oclkb, oclkn, odat0, odat1, odat_async, + pd_data, iopad, async_dat, clkdr, iclkin_dist, iclkn, idat0, + idat1, idataselb, iddren, ilaunch_clk, ilpbk_dat, ilpbk_en, indrv, + ipadrstb, ipdrv, irstb, irxen, istrbclk, itxen, test_weakpd, + test_weakpu, testmode_en, vccl_aibnd, vssl_aibnd ); + +output oclk, oclkb, oclkn, odat0, odat1, odat_async, pd_data; + +inout iopad; + +input async_dat, clkdr, iclkin_dist, iclkn, idat0, idat1, idataselb, + iddren, ilaunch_clk, ilpbk_dat, ilpbk_en, ipadrstb, irstb, + istrbclk, itxen, test_weakpd, test_weakpu, testmode_en, + vccl_aibnd, vssl_aibnd; + +input [1:0] ipdrv; +input [1:0] indrv; +input [2:0] irxen; + + +/* Updated by KS Chia. Update TX drive strength. +aibnd_analog xanlg ( .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .odat_async(odat_async), .clk_en(clkbuf_en), .data_en(datbuf_en), + .weak_pullupenb(weak_pullu_enb), .ndrv_enb({ndrv_sel0, ndrv_sel0, + ndrv_sel0, ndrv_sel0, ndrv_sel0, ndrv_sel0, ndrv_sel0, ndrv_sel0, + ndrv_sel0, ndrv_sel0, ndrv_sel0, ndrv_sel0, ndrv_sel1, ndrv_sel2, + ndrv_sel3, ndrv_sel3}), .odat(rx_idat), .oclkn(oclkb), + .oclkp(oclk), .iopad(iopad), .iclkn(iclkn), .pdrv_en({pdrv_sel0, + pdrv_sel0, pdrv_sel0, pdrv_sel0, pdrv_sel0, pdrv_sel0, pdrv_sel0, + pdrv_sel0, pdrv_sel0, pdrv_sel0, pdrv_sel0, pdrv_sel0, pdrv_sel1, + pdrv_sel2, pdrv_sel3, pdrv_sel3}), .txdin(tx_dat), + .weak_pulldownen(weak_pulld_en)); */ +aibnd_analog xanlg ( .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .odat_async(odat_async), .clk_en(clkbuf_en), .data_en(datbuf_en), + .weak_pullupenb(weak_pullu_enb), .ndrv_enb({ndrv_sel3, ndrv_sel3, + ndrv_sel2, ndrv_sel1, ndrv_sel0, ndrv_sel0, ndrv_sel0, ndrv_sel0, + ndrv_sel0, ndrv_sel0, ndrv_sel0, ndrv_sel0, ndrv_sel1, ndrv_sel2, + ndrv_sel2, ndrv_sel3}), .odat(rx_idat), .oclkn(oclkb), + .oclkp(oclk), .iopad(iopad), .iclkn(iclkn), .pdrv_en({pdrv_sel3, + pdrv_sel2, pdrv_sel1, pdrv_sel0, pdrv_sel0, pdrv_sel0, pdrv_sel0, + pdrv_sel0, pdrv_sel0, pdrv_sel0, pdrv_sel0, pdrv_sel0, pdrv_sel0, + pdrv_sel1, pdrv_sel2, pdrv_sel3}), .txdin(tx_dat), + .weak_pulldownen(weak_pulld_en)); + + +aibnd_digital xdig ( .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd), + .ipadrstb(ipadrstb), .datbuf_en(datbuf_en), .clkdr(clkdr), + .testmode_en(testmode_en), .test_weakpd(test_weakpd), + .test_weakpu(test_weakpu), .weak_pullu_enb(weak_pullu_enb), + .rx_idat(rx_idat), .async_data(async_dat), .pd_dataout(pd_data), + .weak_pulld_en(weak_pulld_en), .clkbuf_en(clkbuf_en), + .ndrv_sel0(ndrv_sel0), .ndrv_sel1(ndrv_sel1), + .ndrv_sel2(ndrv_sel2), .ndrv_sel3(ndrv_sel3), .odat0(odat0), + .odat1(odat1), .pdrv_sel0(pdrv_sel0), .pdrv_sel1(pdrv_sel1), + .pdrv_sel2(pdrv_sel2), .pdrv_sel3(pdrv_sel3), + .rx_disable(rx_disable), .sync_datbuf_en0(sync_datbuf_en0), + .sync_datbuf_en1(sync_datbuf_en1), .tx_dat(tx_dat), + .iclkin_dist(iclkin_dist), .idat0(idat0), .idat1(idat1), + .idataselb(idataselb), .iddrctrl(iddren), + .ilaunch_clk(ilaunch_clk), .ilpbk_dat(ilpbk_dat), + .ilpbk_en(ilpbk_en), .indrv(indrv[1:0]), .ipdrv(ipdrv[1:0]), + .irstb(irstb), .irxen(irxen[2:0]), .istrbclk(istrbclk), + .itx_en(itxen)); +aibnd_aliasd aliasv0 ( .MINUS(oclkn), .PLUS(iopad)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_buffx1_top.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_buffx1_top.v new file mode 100644 index 0000000..c57e931 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_buffx1_top.v @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_buffx1_top, View - schematic +// LAST TIME SAVED: Jul 6 22:01:52 2015 +// NETLIST TIME: Jul 8 13:09:50 2015 +// `timescale 1ns / 1ns + +module aibnd_buffx1_top ( async_dat_in1_jtag_out, idata0_in1_jtag_out, + idata1_in1_jtag_out, jtag_clkdr_out, jtag_clkdr_outn, + jtag_rx_scan_out, last_bs_out, oclk_aib, oclk_out, oclkb_aib, + oclkb_out, oclkn, odat0_aib, odat0_out, odat1_aib, odat1_out, + odat_async_aib, odat_async_out, pd_data_aib, pd_data_out, iopad, + anlg_rstb, async_dat_in0, async_dat_in1, dig_rstb, + iclkin_dist_in0, iclkin_dist_in1, iclkn, idata0_in0, idata0_in1, + idata1_in0, idata1_in1, idataselb_in0, idataselb_in1, iddren_in0, + iddren_in1, ilaunch_clk_in0, ilaunch_clk_in1, ilpbk_dat_in0, + ilpbk_dat_in1, ilpbk_en_in0, ilpbk_en_in1, indrv_in0, indrv_in1, + ipdrv_in0, ipdrv_in1, irxen_in0, irxen_in1, istrbclk_in0, + istrbclk_in1, itxen_in0, itxen_in1, jtag_clkdr_in, jtag_clksel, + jtag_intest, jtag_mode_in, jtag_rstb, jtag_rstb_en, + jtag_tx_scan_in, jtag_tx_scanen_in, last_bs_in, oclk_in1, + oclkb_in1, odat0_in1, odat1_in1, odat_async_in1, pd_data_in1, + prev_io_shift_en, shift_en, test_weakpd, test_weakpu, vccl_aibnd, + vssl_aibnd ); + +output async_dat_in1_jtag_out, idata0_in1_jtag_out, + idata1_in1_jtag_out, jtag_clkdr_out, jtag_clkdr_outn, + jtag_rx_scan_out, last_bs_out, oclk_aib, oclk_out, oclkb_aib, + oclkb_out, oclkn, odat0_aib, odat0_out, odat1_aib, odat1_out, + odat_async_aib, odat_async_out, pd_data_aib, pd_data_out; + +inout iopad; + +input anlg_rstb, async_dat_in0, async_dat_in1, dig_rstb, + iclkin_dist_in0, iclkin_dist_in1, iclkn, idata0_in0, idata0_in1, + idata1_in0, idata1_in1, idataselb_in0, idataselb_in1, iddren_in0, + iddren_in1, ilaunch_clk_in0, ilaunch_clk_in1, ilpbk_dat_in0, + ilpbk_dat_in1, ilpbk_en_in0, ilpbk_en_in1, istrbclk_in0, + istrbclk_in1, itxen_in0, itxen_in1, jtag_clkdr_in, jtag_clksel, + jtag_intest, jtag_mode_in, jtag_rstb, jtag_rstb_en, + jtag_tx_scan_in, jtag_tx_scanen_in, last_bs_in, oclk_in1, + oclkb_in1, odat0_in1, odat1_in1, odat_async_in1, pd_data_in1, + prev_io_shift_en, shift_en, test_weakpd, test_weakpu, vccl_aibnd, + vssl_aibnd; + +input [2:0] irxen_in1; +input [2:0] irxen_in0; +input [1:0] indrv_in0; +input [1:0] ipdrv_in1; +input [1:0] ipdrv_in0; +input [1:0] indrv_in1; + +wire odat1_out_pnr, odat1_out, odat0_out_pnr, odat0_out, odat_async_out_pnr, odat_async_out; // Conversion Sript Generated + +// Buses in the design + +wire [1:0] indrv_aib; + +wire [2:0] irxen_aib; + +wire [1:0] ipdrv_aib; + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_buffx1_top"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +aibnd_buffx1 x0 ( .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .ipadrstb(anlg_rstb_cus), .irxen(irxen_aib[2:0]), + .pd_data(pd_data_aib), .oclk(oclk_aib), + .iclkin_dist(iclkin_dist_in0), .iopad(iopad), .oclkb(oclkb_aib), + .oclkn(oclkn), .odat0(odat0_aib), .odat1(odat1_aib), + .test_weakpd(test_weakpd), .async_dat(async_data_aib), + .iddren(iddren_aib), .iclkn(iclkn), .idat0(idat0_aib), + .idat1(idat1_aib), .idataselb(idataselb_aib), + .test_weakpu(test_weakpu), .testmode_en(vssl_aibnd), + .ilaunch_clk(ilaunch_clk_aib), .ilpbk_dat(ilpbk_dat_in0), + .ilpbk_en(ilpbk_en_in0), .indrv(indrv_aib[1:0]), + .ipdrv(ipdrv_aib[1:0]), .irstb(dig_rstb_aib), .clkdr(vssl_aibnd), + .odat_async(odat_async_aib), .istrbclk(istrbclk_in0), + .itxen(itxen_aib)); +aibndpnr_bsr_red_wrap x1 ( .idata0_red(idata0_in1_jtag_out), + .async_dat_red(async_dat_in1_jtag_out), + .idata1_red(idata1_in1_jtag_out), + .jtag_clkdr_outn(jtag_clkdr_outn), .oclkb_in(oclkb_out/*oclkb_aib*/), + .oclk_in(oclk_out/*oclk_aib*/), .irxen_out(irxen_aib[2:0]), + .async_data_out(async_data_aib), .idata1_out(idat1_aib), + .idata0_out(idat0_aib), .itxen_out(itxen_aib), + //.vssl_aibndpnr(vssl_aibnd), .vccl_aibndpnr(vccl_aibnd), + .jtag_rstb_en(jtag_rstb_en), .jtag_intest(jtag_intest), + .dig_rstb_aib(dig_rstb_aib), .anlg_rstb_aib(anlg_rstb_aib), + .dig_rstb_adap(dig_rstb), .anlg_rstb_adap(anlg_rstb), + .odat_async_in0(odat_async_aib), .odat1_in0(odat1_aib), + .odat0_in0(odat0_aib), .shift_en(shift_en), + .indrv_out(indrv_aib[1:0]), .ipdrv_out(ipdrv_aib[1:0]), + .idataselb_out(idataselb_aib), .iddren_out(iddren_aib), + .odat0_out(odat0_out_pnr), .odat1_out(odat1_out_pnr), + .odat_async_out(odat_async_out_pnr), + .async_dat_in0(async_dat_in0), .async_dat_in1(async_dat_in1), + .idata0_in0(idata0_in0), .idata0_in1(idata0_in1), + .idata1_in0(idata1_in0), .idata1_in1(idata1_in1), + .idataselb_in0(idataselb_in0), .idataselb_in1(idataselb_in1), + .iddren_in0(iddren_in0), .iddren_in1(iddren_in1), + .indrv_in0(indrv_in0[1:0]), .indrv_in1(indrv_in1[1:0]), + .ipdrv_in0(ipdrv_in0[1:0]), .ipdrv_in1(ipdrv_in1[1:0]), + .irxen_in0(irxen_in0[2:0]), .irxen_in1(irxen_in1[2:0]), + .itxen_in0(itxen_in0), .itxen_in1(itxen_in1), + .odat0_in1(odat0_in1), .odat1_in1(odat1_in1), + .odat_async_in1(odat_async_in1), .jtag_clkdr_out(jtag_clkdr_out), + .jtag_rx_scan_out(jtag_rx_scan_out), + .jtag_clkdr_in(jtag_clkdr_in), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_tx_scan_in), + .jtag_tx_scanen_in(jtag_tx_scanen_in)); +aibnd_red_custom_dig x13 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .anlg_rstb_out(anlg_rstb_cus), + .anlg_rstb(anlg_rstb_aib), .prev_io_shift_en(prev_io_shift_en), + .shift_en(shift_en)); +aibnd_red_custom_dig2 x14 ( .istrbclk_in1(vssl_aibnd), + .ilaunch_clk_in0(ilaunch_clk_in0), + .ilaunch_clk_in1(ilaunch_clk_in1), .jtag_clksel(jtag_clksel), + .iclkin_dist_in0(vssl_aibnd), .iclkin_dist_in1(vssl_aibnd), + .istrbclk_in0(vssl_aibnd), .clkdr_in(jtag_clkdr_out), + .iclkin_dist_aib(iclkin_dist_aib), + .ilaunch_clk_aib(ilaunch_clk_aib), .istrbclk_aib(istrbclk_aib), + .oclk_out(oclk_out), .oclkb_out(oclkb_out), .oclk_aib(oclk_aib), + .oclk_in1(oclk_in1), .oclkb_aib(oclkb_aib), .oclkb_in1(oclkb_in1), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .shift_en(shift_en)); +assign odat1_out = odat1_out_pnr; +assign odat0_out = odat0_out_pnr; +assign odat_async_out = odat_async_out_pnr; + +//pdecap xdecap0 ( .g(vssl_aibnd), .b(vccl_aibnd)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clkbuf.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clkbuf.v new file mode 100644 index 0000000..87565e8 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clkbuf.v @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_clkbuf, View - schematic +// LAST TIME SAVED: Oct 28 12:28:02 2014 +// NETLIST TIME: Oct 29 14:53:12 2014 + +module aibnd_clkbuf ( clkout, vccl, vssl, clkin ); + +output clkout; + +inout vccl, vssl; + +input clkin; + +wire clkin, clkout; // Conversion Sript Generated + +assign clkout = !clkin; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clkmux2.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clkmux2.v new file mode 100644 index 0000000..c350355 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clkmux2.v @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_red_clkmux2, View - schematic +// LAST TIME SAVED: Apr 27 12:38:24 2015 +// NETLIST TIME: May 11 08:44:04 2015 +//`timescale 1ns / 1ns + +module aibnd_clkmux2 ( mux_sel, oclk_in1, oclk_in0, oclk_out ); + +output oclk_out; + +input oclk_in1, oclk_in0, mux_sel; + +// List of primary aliased buses + +/* +specify + specparam CDS_LIBNAME = "aibnd_lib"; + specparam CDS_CELLNAME = "aibnd_red_clkmux2"; + specparam CDS_VIEWNAME = "schematic"; +endspecify +*/ + +assign oclk_out = mux_sel ? oclk_in1 : oclk_in0 ; + + +endmodule + + +// End HDL models + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clkmux2.v.hack b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clkmux2.v.hack new file mode 100644 index 0000000..3bcb335 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clkmux2.v.hack @@ -0,0 +1,30 @@ +// Library - aibnd_lib, Cell - aibnd_red_clkmux2, View - schematic +// LAST TIME SAVED: Apr 27 12:38:24 2015 +// NETLIST TIME: May 11 08:44:04 2015 +//`timescale 1ns / 1ns + +module aibnd_clkmux2 ( mux_sel, oclk_in1, oclk_in0, oclk_out ); + +output oclk_out; + +input oclk_in1, oclk_in0, mux_sel; + +// List of primary aliased buses + +/* +specify + specparam CDS_LIBNAME = "aibnd_lib"; + specparam CDS_CELLNAME = "aibnd_red_clkmux2"; + specparam CDS_VIEWNAME = "schematic"; +endspecify +*/ + +assign oclk_out = mux_sel ? oclk_in1 : oclk_in0 ; + + +endmodule + + +// End HDL models + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree.v new file mode 100644 index 0000000..cfe892d --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree.v @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #6 $ +// Date: $DateTime: 2015/07/27 23:57:02 $ +//------------------------------------------------------------------------ +// Description: skew-matched clock distribution network +//------------------------------------------------------------------------ + +module aibnd_clktree +#( +parameter SKEW_DELAY = 60 //min:20ps; typ :60ps; max:100ps +) +( + input wire clkin, //clock source + output wire lstrbclk_l_0, //buffered clock + output wire lstrbclk_l_1, //buffered clock + output wire lstrbclk_l_2, //buffered clock + output wire lstrbclk_l_3, //buffered clock + output wire lstrbclk_l_4, //buffered clock + output wire lstrbclk_l_5, //buffered clock + output wire lstrbclk_l_6, //buffered clock + output wire lstrbclk_l_7, //buffered clock + output wire lstrbclk_l_8, //buffered clock + output wire lstrbclk_l_9, //buffered clock + output wire lstrbclk_l_10, //buffered clock + output wire lstrbclk_l_11, //buffered clock + output wire lstrbclk_r_0, //buffered clock + output wire lstrbclk_r_1, //buffered clock + output wire lstrbclk_r_2, //buffered clock + output wire lstrbclk_r_3, //buffered clock + output wire lstrbclk_r_4, //buffered clock + output wire lstrbclk_r_5, //buffered clock + output wire lstrbclk_r_6, //buffered clock + output wire lstrbclk_r_7, //buffered clock + output wire lstrbclk_r_8, //buffered clock + output wire lstrbclk_r_9, //buffered clock + output wire lstrbclk_r_10, //buffered clock + output wire lstrbclk_r_11, //buffered clock + output wire lstrbclk_rep, //replica for DLL + output wire lstrbclk_mimic0, //mimic path for load matching + output wire lstrbclk_mimic1, //mimic path for load matching + output wire lstrbclk_mimic2 //mimic path for load matching +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + + assign #SKEW_DELAY lstrbclk_l_0 = clkin; + assign #SKEW_DELAY lstrbclk_l_1 = clkin; + assign #SKEW_DELAY lstrbclk_l_2 = clkin; + assign #SKEW_DELAY lstrbclk_l_3 = clkin; + assign #SKEW_DELAY lstrbclk_l_4 = clkin; + assign #SKEW_DELAY lstrbclk_l_5 = clkin; + assign #SKEW_DELAY lstrbclk_l_6 = clkin; + assign #SKEW_DELAY lstrbclk_l_7 = clkin; + assign #SKEW_DELAY lstrbclk_l_8 = clkin; + assign #SKEW_DELAY lstrbclk_l_9 = clkin; + assign #SKEW_DELAY lstrbclk_l_10 = clkin; + assign #SKEW_DELAY lstrbclk_l_11 = clkin; + assign #SKEW_DELAY lstrbclk_r_0 = clkin; + assign #SKEW_DELAY lstrbclk_r_1 = clkin; + assign #SKEW_DELAY lstrbclk_r_2 = clkin; + assign #SKEW_DELAY lstrbclk_r_3 = clkin; + assign #SKEW_DELAY lstrbclk_r_4 = clkin; + assign #SKEW_DELAY lstrbclk_r_5 = clkin; + assign #SKEW_DELAY lstrbclk_r_6 = clkin; + assign #SKEW_DELAY lstrbclk_r_7 = clkin; + assign #SKEW_DELAY lstrbclk_r_8 = clkin; + assign #SKEW_DELAY lstrbclk_r_9 = clkin; + assign #SKEW_DELAY lstrbclk_r_10 = clkin; + assign #SKEW_DELAY lstrbclk_r_11 = clkin; + assign #SKEW_DELAY lstrbclk_rep = clkin; + assign #SKEW_DELAY lstrbclk_mimic0 = clkin; + assign #SKEW_DELAY lstrbclk_mimic1 = clkin; + assign #SKEW_DELAY lstrbclk_mimic2 = clkin; + +endmodule // aibnd_clktree + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_avmm.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_avmm.v new file mode 100644 index 0000000..c1bd7e5 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_avmm.v @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #6 $ +// Date: $DateTime: 2015/07/27 23:57:02 $ +//------------------------------------------------------------------------ +// Description: skew-matched clock distribution network +//------------------------------------------------------------------------ + +module aibnd_clktree_avmm +#( +parameter SKEW_DELAY = 60 //min:20ps; typ :60ps; max:100ps +) +( + input wire clkin, //clock source + output wire lstrbclk_l_0, //buffered clock + output wire lstrbclk_l_1, //buffered clock + output wire lstrbclk_l_2, //buffered clock + output wire lstrbclk_l_3, //buffered clock + output wire lstrbclk_l_4, //buffered clock + output wire lstrbclk_l_5, //buffered clock + output wire lstrbclk_l_6, //buffered clock + output wire lstrbclk_l_7, //buffered clock + output wire lstrbclk_r_0, //buffered clock + output wire lstrbclk_r_1, //buffered clock + output wire lstrbclk_r_2, //buffered clock + output wire lstrbclk_r_3, //buffered clock + output wire lstrbclk_r_4, //buffered clock + output wire lstrbclk_r_5, //buffered clock + output wire lstrbclk_r_6, //buffered clock + output wire lstrbclk_r_7, //buffered clock + output wire lstrbclk_rep, //replica for DLL + output wire lstrbclk_mimic0, //mimic path for load matching + output wire lstrbclk_mimic1, //mimic path for load matching + output wire lstrbclk_mimic2 //mimic path for load matching +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + + assign #SKEW_DELAY lstrbclk_l_0 = clkin; + assign #SKEW_DELAY lstrbclk_l_1 = clkin; + assign #SKEW_DELAY lstrbclk_l_2 = clkin; + assign #SKEW_DELAY lstrbclk_l_3 = clkin; + assign #SKEW_DELAY lstrbclk_l_4 = clkin; + assign #SKEW_DELAY lstrbclk_l_5 = clkin; + assign #SKEW_DELAY lstrbclk_l_6 = clkin; + assign #SKEW_DELAY lstrbclk_l_7 = clkin; + assign #SKEW_DELAY lstrbclk_r_0 = clkin; + assign #SKEW_DELAY lstrbclk_r_1 = clkin; + assign #SKEW_DELAY lstrbclk_r_2 = clkin; + assign #SKEW_DELAY lstrbclk_r_3 = clkin; + assign #SKEW_DELAY lstrbclk_r_4 = clkin; + assign #SKEW_DELAY lstrbclk_r_5 = clkin; + assign #SKEW_DELAY lstrbclk_r_6 = clkin; + assign #SKEW_DELAY lstrbclk_r_7 = clkin; + assign #SKEW_DELAY lstrbclk_rep = clkin; + assign #SKEW_DELAY lstrbclk_mimic0 = clkin; + assign #SKEW_DELAY lstrbclk_mimic1 = clkin; + assign #SKEW_DELAY lstrbclk_mimic2 = clkin; + +endmodule // aibnd_clktree_avmm + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_avmm_mimic.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_avmm_mimic.v new file mode 100644 index 0000000..d1d90d9 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_avmm_mimic.v @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #6 $ +// Date: $DateTime: 2015/07/27 23:57:02 $ +//------------------------------------------------------------------------ +// Description: skew-matched clock distribution network +//------------------------------------------------------------------------ + +module aibnd_clktree_avmm_mimic +#( +parameter SKEW_DELAY = 60 //min:20ps; typ :60ps; max:100ps +) +( + input wire clkin, //clock source + output wire lstrbclk_l_0, //buffered clock + output wire lstrbclk_l_1, //buffered clock + output wire lstrbclk_l_2, //buffered clock + output wire lstrbclk_l_3, //buffered clock + output wire lstrbclk_l_4, //buffered clock + output wire lstrbclk_l_5, //buffered clock + output wire lstrbclk_l_6, //buffered clock + output wire lstrbclk_l_7, //buffered clock + output wire lstrbclk_rep, //replica for DLL + output wire lstrbclk_mimic0 //mimic path for load matching +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + + assign #SKEW_DELAY lstrbclk_l_0 = clkin; + assign #SKEW_DELAY lstrbclk_l_1 = clkin; + assign #SKEW_DELAY lstrbclk_l_2 = clkin; + assign #SKEW_DELAY lstrbclk_l_3 = clkin; + assign #SKEW_DELAY lstrbclk_l_4 = clkin; + assign #SKEW_DELAY lstrbclk_l_5 = clkin; + assign #SKEW_DELAY lstrbclk_l_6 = clkin; + assign #SKEW_DELAY lstrbclk_l_7 = clkin; + assign #SKEW_DELAY lstrbclk_rep = clkin; + assign #SKEW_DELAY lstrbclk_mimic0 = clkin; + +endmodule // aibnd_clktree_avmm_mimic + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_avmm_pcs.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_avmm_pcs.v new file mode 100644 index 0000000..04d0105 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_avmm_pcs.v @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #6 $ +// Date: $DateTime: 2015/07/27 23:57:02 $ +//------------------------------------------------------------------------ +// Description: skew-matched clock distribution network +//------------------------------------------------------------------------ + +module aibnd_clktree_avmm_pcs +#( +parameter SKEW_DELAY = 60 //min:20ps; typ :60ps; max:100ps +) +( + input wire clkin, //clock source + output wire lstrbclk_l_0, //buffered clock + output wire lstrbclk_l_1, //buffered clock + output wire lstrbclk_l_2, //buffered clock + output wire lstrbclk_l_3, //buffered clock + output wire lstrbclk_l_4, //buffered clock + output wire lstrbclk_l_5, //buffered clock + output wire lstrbclk_l_6, //buffered clock + output wire lstrbclk_l_7, //buffered clock + output wire lstrbclk_r_0, //buffered clock + output wire lstrbclk_r_1, //buffered clock + output wire lstrbclk_r_2, //buffered clock + output wire lstrbclk_r_3, //buffered clock + output wire lstrbclk_r_4, //buffered clock + output wire lstrbclk_r_5, //buffered clock + output wire lstrbclk_r_6, //buffered clock + output wire lstrbclk_r_7, //buffered clock + output wire lstrbclk_rep, //replica for DLL + output wire lstrbclk_mimic0, //mimic path for load matching + output wire lstrbclk_mimic1, //mimic path for load matching + output wire lstrbclk_mimic2 //mimic path for load matching +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + + assign #SKEW_DELAY lstrbclk_l_0 = clkin; + assign #SKEW_DELAY lstrbclk_l_1 = clkin; + assign #SKEW_DELAY lstrbclk_l_2 = clkin; + assign #SKEW_DELAY lstrbclk_l_3 = clkin; + assign #SKEW_DELAY lstrbclk_l_4 = clkin; + assign #SKEW_DELAY lstrbclk_l_5 = clkin; + assign #SKEW_DELAY lstrbclk_l_6 = clkin; + assign #SKEW_DELAY lstrbclk_l_7 = clkin; + assign #SKEW_DELAY lstrbclk_r_0 = clkin; + assign #SKEW_DELAY lstrbclk_r_1 = clkin; + assign #SKEW_DELAY lstrbclk_r_2 = clkin; + assign #SKEW_DELAY lstrbclk_r_3 = clkin; + assign #SKEW_DELAY lstrbclk_r_4 = clkin; + assign #SKEW_DELAY lstrbclk_r_5 = clkin; + assign #SKEW_DELAY lstrbclk_r_6 = clkin; + assign #SKEW_DELAY lstrbclk_r_7 = clkin; + assign #SKEW_DELAY lstrbclk_rep = clkin; + assign #SKEW_DELAY lstrbclk_mimic0 = clkin; + assign #SKEW_DELAY lstrbclk_mimic1 = clkin; + assign #SKEW_DELAY lstrbclk_mimic2 = clkin; + +endmodule // aibnd_clktree_avmm_pcs + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_mimic.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_mimic.v new file mode 100644 index 0000000..4687e00 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_mimic.v @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #6 $ +// Date: $DateTime: 2015/07/27 23:57:02 $ +//------------------------------------------------------------------------ +// Description: skew-matched clock distribution network +//------------------------------------------------------------------------ + +module aibnd_clktree_mimic +#( +parameter SKEW_DELAY = 60 //min:20ps; typ :60ps; max:100ps +) +( + input wire clkin, //clock source + output wire lstrbclk_l_0, //buffered clock + output wire lstrbclk_l_1, //buffered clock + output wire lstrbclk_l_2, //buffered clock + output wire lstrbclk_l_3, //buffered clock + output wire lstrbclk_l_4, //buffered clock + output wire lstrbclk_l_5, //buffered clock + output wire lstrbclk_l_6, //buffered clock + output wire lstrbclk_l_7, //buffered clock + output wire lstrbclk_l_8, //buffered clock + output wire lstrbclk_l_9, //buffered clock + output wire lstrbclk_l_10, //buffered clock + output wire lstrbclk_l_11, //buffered clock + output wire lstrbclk_rep, //replica for DLL + output wire lstrbclk_mimic0 //mimic path for load matching +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + + assign #SKEW_DELAY lstrbclk_l_0 = clkin; + assign #SKEW_DELAY lstrbclk_l_1 = clkin; + assign #SKEW_DELAY lstrbclk_l_2 = clkin; + assign #SKEW_DELAY lstrbclk_l_3 = clkin; + assign #SKEW_DELAY lstrbclk_l_4 = clkin; + assign #SKEW_DELAY lstrbclk_l_5 = clkin; + assign #SKEW_DELAY lstrbclk_l_6 = clkin; + assign #SKEW_DELAY lstrbclk_l_7 = clkin; + assign #SKEW_DELAY lstrbclk_l_8 = clkin; + assign #SKEW_DELAY lstrbclk_l_9 = clkin; + assign #SKEW_DELAY lstrbclk_l_10 = clkin; + assign #SKEW_DELAY lstrbclk_l_11 = clkin; + assign #SKEW_DELAY lstrbclk_rep = clkin; + assign #SKEW_DELAY lstrbclk_mimic0 = clkin; + +endmodule // aibnd_clktree_mimic + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_pcs.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_pcs.v new file mode 100644 index 0000000..c1f3fb8 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_pcs.v @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #6 $ +// Date: $DateTime: 2015/07/27 23:57:02 $ +//------------------------------------------------------------------------ +// Description: skew-matched clock distribution network +//------------------------------------------------------------------------ + +module aibnd_clktree_pcs +#( +parameter SKEW_DELAY = 60 //min:20ps; typ :60ps; max:100ps +) +( + input wire clkin, //clock source + output wire lstrbclk_l_0, //buffered clock + output wire lstrbclk_l_1, //buffered clock + output wire lstrbclk_l_2, //buffered clock + output wire lstrbclk_l_3, //buffered clock + output wire lstrbclk_l_4, //buffered clock + output wire lstrbclk_l_5, //buffered clock + output wire lstrbclk_l_6, //buffered clock + output wire lstrbclk_l_7, //buffered clock + output wire lstrbclk_l_8, //buffered clock + output wire lstrbclk_l_9, //buffered clock + output wire lstrbclk_l_10, //buffered clock + output wire lstrbclk_l_11, //buffered clock + output wire lstrbclk_r_0, //buffered clock + output wire lstrbclk_r_1, //buffered clock + output wire lstrbclk_r_2, //buffered clock + output wire lstrbclk_r_3, //buffered clock + output wire lstrbclk_r_4, //buffered clock + output wire lstrbclk_r_5, //buffered clock + output wire lstrbclk_r_6, //buffered clock + output wire lstrbclk_r_7, //buffered clock + output wire lstrbclk_r_8, //buffered clock + output wire lstrbclk_r_9, //buffered clock + output wire lstrbclk_r_10, //buffered clock + output wire lstrbclk_r_11, //buffered clock + output wire lstrbclk_rep, //replica for DLL + output wire lstrbclk_mimic0, //mimic path for load matching + output wire lstrbclk_mimic1, //mimic path for load matching + output wire lstrbclk_mimic2 //mimic path for load matching +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + + assign #SKEW_DELAY lstrbclk_l_0 = clkin; + assign #SKEW_DELAY lstrbclk_l_1 = clkin; + assign #SKEW_DELAY lstrbclk_l_2 = clkin; + assign #SKEW_DELAY lstrbclk_l_3 = clkin; + assign #SKEW_DELAY lstrbclk_l_4 = clkin; + assign #SKEW_DELAY lstrbclk_l_5 = clkin; + assign #SKEW_DELAY lstrbclk_l_6 = clkin; + assign #SKEW_DELAY lstrbclk_l_7 = clkin; + assign #SKEW_DELAY lstrbclk_l_8 = clkin; + assign #SKEW_DELAY lstrbclk_l_9 = clkin; + assign #SKEW_DELAY lstrbclk_l_10 = clkin; + assign #SKEW_DELAY lstrbclk_l_11 = clkin; + assign #SKEW_DELAY lstrbclk_r_0 = clkin; + assign #SKEW_DELAY lstrbclk_r_1 = clkin; + assign #SKEW_DELAY lstrbclk_r_2 = clkin; + assign #SKEW_DELAY lstrbclk_r_3 = clkin; + assign #SKEW_DELAY lstrbclk_r_4 = clkin; + assign #SKEW_DELAY lstrbclk_r_5 = clkin; + assign #SKEW_DELAY lstrbclk_r_6 = clkin; + assign #SKEW_DELAY lstrbclk_r_7 = clkin; + assign #SKEW_DELAY lstrbclk_r_8 = clkin; + assign #SKEW_DELAY lstrbclk_r_9 = clkin; + assign #SKEW_DELAY lstrbclk_r_10 = clkin; + assign #SKEW_DELAY lstrbclk_r_11 = clkin; + assign #SKEW_DELAY lstrbclk_rep = clkin; + assign #SKEW_DELAY lstrbclk_mimic0 = clkin; + assign #SKEW_DELAY lstrbclk_mimic1 = clkin; + assign #SKEW_DELAY lstrbclk_mimic2 = clkin; + +endmodule // aibnd_clktree_pcs + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_fine_dly.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_fine_dly.v new file mode 100644 index 0000000..be8f3f3 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_fine_dly.v @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// aibnd_cmos_fine_dly +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module aibnd_cmos_fine_dly ( +input vcc_aibnd, vss_aibnd, vcc_io, +input [2:0] gray, +input ck, fout_p, nrst, se_n, si, code_valid, +output so, out_p +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +wire pg0,ng0,pg1,ng1,pg2,ng2; +wire sp0,sn0,sp1,sn1,sp2,sn2,sp3,sn3,sp4,sn4,sp5,sn5,sp6,sn6,sp7,sn7; +wire sp1_a,sn1_a,sp2_a,sn2_a,sp3_a,sn3_a,sp4_a,sn4_a,sp5_a,sn5_a,sp6_a,sn6_a,sp7_a,sn7_a; +wire so0,so1,so2,so3,so4,so5,so6,so7,so8,so9,so10,so11,so12; +wire sp0_a; +wire sn0_a; +integer intrinsic, step, calc_delay, total_delay; + +assign ng2 = ~gray[2]; +assign pg2 = gray[2]; +assign ng1 = ~gray[1]; +assign pg1 = gray[1]; +assign ng0 = ~gray[0]; +assign pg0 = gray[0]; + +assign sp7_a = ~(pg2&ng1&ng0); +assign sn7_a = ~sp7_a; +assign sp6_a = ~((pg2&ng1&pg0) | sn7_a); +assign sn6_a = ~sp6_a; +assign sp5_a = ~((pg2&pg1&pg0) | sn6_a); +assign sn5_a = ~sp5_a; +assign sp4_a = ~((pg2&pg1&ng0) | sn5_a); +assign sn4_a = ~sp4_a; +assign sp3_a = ~((ng2&pg1&ng0) | sn4_a); +assign sn3_a = ~sp3_a; +assign sp2_a = ~((ng2&pg1&pg0) | sn3_a); +assign sn2_a = ~sp2_a; +assign sp1_a = ~((ng2&ng1&pg0) | sn2_a); +assign sn1_a = ~sp1_a; +assign sp0_a = ~((ng2&ng1&ng0) | sn1_a); +assign sn0_a = ~sp0_a; + +aibnd_str_ff x127 ( .se_n(se_n), .so(so), .si(so12),.rb(nrst), .clk(ck), .d(sn7_a), .code_valid(code_valid), .q(sn7)); +aibnd_str_ff x118 ( .se_n(se_n), .so(so0), .si(si), .rb(nrst), .clk(ck), .d(sp1_a), .code_valid(code_valid), .q(sp1)); +aibnd_str_ff x104 ( .se_n(se_n), .so(so1), .si(so0), .rb(nrst), .clk(ck), .d(sp2_a), .code_valid(code_valid), .q(sp2)); +aibnd_str_ff x101 ( .se_n(se_n), .so(so2), .si(so1), .rb(nrst), .clk(ck), .d(sp3_a), .code_valid(code_valid), .q(sp3)); +aibnd_str_ff x99 ( .se_n(se_n), .so(so3), .si(so2), .rb(nrst), .clk(ck), .d(sp4_a), .code_valid(code_valid), .q(sp4)); +aibnd_str_ff x97 ( .se_n(se_n), .so(so4), .si(so3), .rb(nrst), .clk(ck), .d(sp5_a), .code_valid(code_valid), .q(sp5)); +aibnd_str_ff x95 ( .se_n(se_n), .so(so5), .si(so4), .rb(nrst), .clk(ck), .d(sp6_a), .code_valid(code_valid), .q(sp6)); +aibnd_str_ff x93 ( .se_n(se_n), .so(so6), .si(so5), .rb(nrst), .clk(ck), .d(sp7_a), .code_valid(code_valid), .q(sp7)); +aibnd_str_ff x129 ( .se_n(se_n), .so(so12),.si(so11),.rb(nrst), .clk(ck), .d(sn6_a), .code_valid(code_valid), .q(sn6)); +aibnd_str_ff x131 ( .se_n(se_n), .so(so11),.si(so10),.rb(nrst), .clk(ck), .d(sn5_a), .code_valid(code_valid), .q(sn5)); +aibnd_str_ff x133 ( .se_n(se_n), .so(so10),.si(so9), .rb(nrst), .clk(ck), .d(sn4_a), .code_valid(code_valid), .q(sn4)); +aibnd_str_ff x135 ( .se_n(se_n), .so(so9), .si(so8), .rb(nrst), .clk(ck), .d(sn3_a), .code_valid(code_valid), .q(sn3)); +aibnd_str_ff x137 ( .se_n(se_n), .so(so8), .si(so7), .rb(nrst), .clk(ck), .d(sn2_a), .code_valid(code_valid), .q(sn2)); +aibnd_str_ff x140 ( .se_n(se_n), .so(so7), .si(so6), .rb(nrst), .clk(ck), .d(sn1_a), .code_valid(code_valid), .q(sn1)); + +initial step = 32'd4; + +always @(*) + if (sn7 == 1'b1) calc_delay = (7 * step); + else if (sn6 == 1'b1) calc_delay = (6 * step); + else if (sn5 == 1'b1) calc_delay = (5 * step); + else if (sn4 == 1'b1) calc_delay = (4 * step); + else if (sn3 == 1'b1) calc_delay = (3 * step); + else if (sn2 == 1'b1) calc_delay = (2 * step); + else if (sn1 == 1'b1) calc_delay = (1 * step); + else calc_delay = (0 * step); + +initial intrinsic = 32'd50; //min:10ps; typ:50ps; max:80ps +// assign delay = intrinsic + calc_delay; + always @(*) total_delay = intrinsic + calc_delay; + assign #total_delay out_p = fout_p; + +endmodule + + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x1.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x1.v new file mode 100644 index 0000000..37915f0 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x1.v @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// aibnd_cmos_nand_x1 +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module aibnd_cmos_nand_x1 ( +input in_p, +input bk, +input ci_p, +input code_valid, +input ck, nrst, se_n, si, +output out_p, so, +output co_p +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter NAND_DELAY = 15; //min: 5ps; typ: 10ps; max: 20ps + +reg tp; + +aibnd_str_ff xsync ( .se_n(se_n), .so(so), .si(si), .rb(nrst), .code_valid(code_valid), .clk(ck), .d(bk), .q(bk_sync)); + +assign #NAND_DELAY co_p = ~(in_p & bk_sync); + +always @(*) + if (~in_p) tp <= #NAND_DELAY 1'b1; + else if (~bk_sync) tp <= #NAND_DELAY 1'b0; + +assign #NAND_DELAY out_p = ~(tp & ci_p); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x128.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x128.v new file mode 100644 index 0000000..74619ba --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x128.v @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_cmos_nand_x128, View - schematic +// LAST TIME SAVED: Nov 27 15:06:31 2014 +// NETLIST TIME: Dec 17 10:24:03 2014 + +module aibnd_cmos_nand_x128 ( out_p, vcc_io, vcc_regphy, vss_io, gray, + in_p ); + +output out_p; + +inout vcc_io, vcc_regphy, vss_io; + +input in_p; + +input [6:0] gray; + +wire svcc, vss_io; // Conversion Sript Generated + +// Buses in the design + +wire [127:0] bk; + + + +assign svcc = !vss_io; +io_cmos_nand_x128_decode xdec ( //.vcc_io(vcc_io), .vss_io(vss_io), + .bk(bk[127:0]), .gray(gray[6:0])); +aibnd_cmos_nand_x6 xnand_x6_20 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(vss_io), .bk4(bk[124]), .bk3(bk[123]), + .bk2(bk[122]), .bk1(bk[121]), .bk0(bk[120]), .co_p(a125), + .ci_p(svcc), .in_p(a119), .out_p(b119)); +aibnd_cmos_nand_x6 xnand_x6_16 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[101]), .bk4(bk[100]), .bk3(bk[99]), + .bk2(bk[98]), .bk1(bk[97]), .bk0(bk[96]), .co_p(a101), + .ci_p(b101), .in_p(a95), .out_p(b95)); +aibnd_cmos_nand_x6 xnand_x6_15 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[95]), .bk4(bk[94]), .bk3(bk[93]), + .bk2(bk[92]), .bk1(bk[91]), .bk0(bk[90]), .co_p(a95), .ci_p(b95), + .in_p(a89), .out_p(b89)); +aibnd_cmos_nand_x6 xnand_x6_14 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[89]), .bk4(bk[88]), .bk3(bk[87]), + .bk2(bk[86]), .bk1(bk[85]), .bk0(bk[84]), .co_p(a89), .ci_p(b89), + .in_p(a83), .out_p(b83)); +aibnd_cmos_nand_x6 xnand_x6_13 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[83]), .bk4(bk[82]), .bk3(bk[81]), + .bk2(bk[80]), .bk1(bk[79]), .bk0(bk[78]), .co_p(a83), .ci_p(b83), + .in_p(a77), .out_p(b77)); +aibnd_cmos_nand_x6 xnand_x6_0 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[5]), .bk4(bk[4]), .bk3(bk[3]), + .bk2(bk[2]), .bk1(bk[1]), .bk0(bk[0]), .co_p(a5), .ci_p(b5), + .in_p(in_p), .out_p(out_p)); +aibnd_cmos_nand_x6 xnand_x6_11 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[71]), .bk4(bk[70]), .bk3(bk[69]), + .bk2(bk[68]), .bk1(bk[67]), .bk0(bk[66]), .co_p(a71), .ci_p(b71), + .in_p(a65), .out_p(b65)); +aibnd_cmos_nand_x6 xnand_x6_18 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[113]), .bk4(bk[112]), .bk3(bk[111]), + .bk2(bk[110]), .bk1(bk[109]), .bk0(bk[108]), .co_p(a113), + .ci_p(b113), .in_p(a107), .out_p(b107)); +aibnd_cmos_nand_x6 xnand_x6_10 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[65]), .bk4(bk[64]), .bk3(bk[63]), + .bk2(bk[62]), .bk1(bk[61]), .bk0(bk[60]), .co_p(a65), .ci_p(b65), + .in_p(a59), .out_p(b59)); +aibnd_cmos_nand_x6 xnand_x6_9 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[59]), .bk4(bk[58]), .bk3(bk[57]), + .bk2(bk[56]), .bk1(bk[55]), .bk0(bk[54]), .co_p(a59), .ci_p(b59), + .in_p(a53), .out_p(b53)); +aibnd_cmos_nand_x6 xnand_x6_8 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[53]), .bk4(bk[52]), .bk3(bk[51]), + .bk2(bk[50]), .bk1(bk[49]), .bk0(bk[48]), .co_p(a53), .ci_p(b53), + .in_p(a47), .out_p(b47)); +aibnd_cmos_nand_x6 xnand_x6_7 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[47]), .bk4(bk[46]), .bk3(bk[45]), + .bk2(bk[44]), .bk1(bk[43]), .bk0(bk[42]), .co_p(a47), .ci_p(b47), + .in_p(a41), .out_p(b41)); +aibnd_cmos_nand_x6 xnand_x6_6 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[41]), .bk4(bk[40]), .bk3(bk[39]), + .bk2(bk[38]), .bk1(bk[37]), .bk0(bk[36]), .co_p(a41), .ci_p(b41), + .in_p(a35), .out_p(b35)); +aibnd_cmos_nand_x6 xnand_x6_19 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[119]), .bk4(bk[118]), .bk3(bk[117]), + .bk2(bk[116]), .bk1(bk[115]), .bk0(bk[114]), .co_p(a119), + .ci_p(b119), .in_p(a113), .out_p(b113)); +aibnd_cmos_nand_x6 xnand_x6_5 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[35]), .bk4(bk[34]), .bk3(bk[33]), + .bk2(bk[32]), .bk1(bk[31]), .bk0(bk[30]), .co_p(a35), .ci_p(b35), + .in_p(a29), .out_p(b29)); +aibnd_cmos_nand_x6 xnand_x6_4 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[29]), .bk4(bk[28]), .bk3(bk[27]), + .bk2(bk[26]), .bk1(bk[25]), .bk0(bk[24]), .co_p(a29), .ci_p(b29), + .in_p(a23), .out_p(b23)); +aibnd_cmos_nand_x6 xnand_x6_3 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[23]), .bk4(bk[22]), .bk3(bk[21]), + .bk2(bk[20]), .bk1(bk[19]), .bk0(bk[18]), .co_p(a23), .ci_p(b23), + .in_p(a17), .out_p(b17)); +aibnd_cmos_nand_x6 xnand_x6_2 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[17]), .bk4(bk[16]), .bk3(bk[15]), + .bk2(bk[14]), .bk1(bk[13]), .bk0(bk[12]), .co_p(a17), .ci_p(b17), + .in_p(a11), .out_p(b11)); +aibnd_cmos_nand_x6 xnand_x6_1 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[11]), .bk4(bk[10]), .bk3(bk[9]), + .bk2(bk[8]), .bk1(bk[7]), .bk0(bk[6]), .co_p(a11), .ci_p(b11), + .in_p(a5), .out_p(b5)); +aibnd_cmos_nand_x6 xnand_x6_17 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[107]), .bk4(bk[106]), .bk3(bk[105]), + .bk2(bk[104]), .bk1(bk[103]), .bk0(bk[102]), .co_p(a107), + .ci_p(b107), .in_p(a101), .out_p(b101)); +aibnd_cmos_nand_x6 xnand_x64_12 ( //.vcc_regphy(vcc_regphy), + //.vss_io(vss_io), + .bk5(bk[77]), .bk4(bk[76]), .bk3(bk[75]), + .bk2(bk[74]), .bk1(bk[73]), .bk0(bk[72]), .co_p(a77), .ci_p(b77), + .in_p(a71), .out_p(b71)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x6.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x6.v new file mode 100644 index 0000000..9c2841b --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x6.v @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_cmos_nand_x6, View - schematic +// LAST TIME SAVED: Mar 26 07:33:49 2015 +// NETLIST TIME: Apr 3 13:57:16 2015 +// `timescale 1ns / 1ns + +module aibnd_cmos_nand_x6 ( co_p, out_p, so, bk0, bk1, bk2, + bk3, bk4, bk5, ci_p, ck, code_valid, in_p, nrst, se_n, si, + vcc_aibnd, vss_aibnd ); + +output co_p, out_p, so; + +input bk0, bk1, bk2, bk3, bk4, bk5, ci_p, ck, code_valid, in_p, nrst, + se_n, si, vcc_aibnd, vss_aibnd; + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_cmos_nand_x6"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +aibnd_cmos_nand_x1 xd00 ( .code_valid(code_valid), .ck(ck), .so(so0), + .si(si), .se_n(se_n), .nrst(nrst), //.vcc_io(vcc_aibnd), + .in_p(in_p), .bk(bk0), //.vss_io(vss_aibnd), + .co_p(a0), .ci_p(b0), + .out_p(out_p)); +aibnd_cmos_nand_x1 xd01 ( .code_valid(code_valid), .ck(ck), .so(so1), + .si(so0), .se_n(se_n), .nrst(nrst), //.vcc_io(vcc_aibnd), + .in_p(a0), .bk(bk1), //.vss_io(vss_aibnd), + .co_p(a1), .ci_p(b1), .out_p(b0)); +aibnd_cmos_nand_x1 xd02 ( .code_valid(code_valid), .ck(ck), .so(so2), + .si(so1), .se_n(se_n), .nrst(nrst), //.vcc_io(vcc_aibnd), + .in_p(a1), .bk(bk2), //.vss_io(vss_aibnd), + .co_p(a2), .ci_p(b2), .out_p(b1)); +aibnd_cmos_nand_x1 xd03 ( .code_valid(code_valid), .ck(ck), .so(so3), + .si(so2), .se_n(se_n), .nrst(nrst), //.vcc_io(vcc_aibnd), + .in_p(a2), .bk(bk3), //.vss_io(vss_aibnd), + .co_p(a3), .ci_p(b3), .out_p(b2)); +aibnd_cmos_nand_x1 xd04 ( .code_valid(code_valid), .ck(ck), .so(so4), + .si(so3), .se_n(se_n), .nrst(nrst), //.vcc_io(vcc_aibnd), + .in_p(a3), .bk(bk4), //.vss_io(vss_aibnd), + .co_p(a4), .ci_p(b4), .out_p(b3)); +aibnd_cmos_nand_x1 xd05 ( .code_valid(code_valid), .ck(ck), .so(so), + .si(so4), .se_n(se_n), .nrst(nrst), //.vcc_io(vcc_aibnd), + .in_p(a4), .bk(bk5), //.vss_io(vss_aibnd), + .co_p(co_p), .ci_p(ci_p), .out_p(b4)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x64.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x64.v new file mode 100644 index 0000000..45a92af --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x64.v @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_cmos_nand_x64, View - schematic +// LAST TIME SAVED: Mar 26 07:33:49 2015 +// NETLIST TIME: May 12 17:53:10 2015 +// `timescale 1ns / 1ns + +module aibnd_cmos_nand_x64 ( out_p, so, ck, code_valid, gray, in_p, + nrst, se_n, si, vcc_aibnd, vcc_io, vss_aibnd ); + +output out_p, so; + +input ck, code_valid, in_p, nrst, se_n, si, vcc_aibnd, vcc_io, + vss_aibnd; + +input [6:0] gray; + +wire svcc, vss_aibnd; // Conversion Sript Generated + +// Buses in the design + +wire [127:0] bk; + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_cmos_nand_x64"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +assign svcc = !vss_aibnd; +io_cmos_nand_x128_decode xdec ( //.vcc_io(vcc_aibnd), + //.vss_io(vss_aibnd), + .bk(bk[127:0]), .gray(gray[6:0])); +aibnd_cmos_nand_x6 xnand_x6_0 ( .vcc_aibnd(vcc_aibnd), + .vss_aibnd(vss_aibnd), .code_valid(code_valid), .ck(ck), + .nrst(nrst), .se_n(se_n), .si(si), .so(so5), .bk5(bk[5]), + .bk4(bk[4]), .bk3(bk[3]), .bk2(bk[2]), .bk1(bk[1]), .bk0(bk[0]), + .co_p(a5), .ci_p(b5), .in_p(in_p), .out_p(out_p)); +aibnd_cmos_nand_x6 xnand_x6_10 ( .vcc_aibnd(vcc_aibnd), + .vss_aibnd(vss_aibnd), .code_valid(code_valid), .ck(ck), + .nrst(nrst), .se_n(se_n), .si(so59), .so(so), .bk5(vss_aibnd), + .bk4(bk[64]), .bk3(bk[63]), .bk2(bk[62]), .bk1(bk[61]), + .bk0(bk[60]), .co_p(a65), .ci_p(svcc), .in_p(a59), .out_p(b59)); +aibnd_cmos_nand_x6 xnand_x6_9 ( .vcc_aibnd(vcc_aibnd), + .vss_aibnd(vss_aibnd), .code_valid(code_valid), .ck(ck), + .nrst(nrst), .se_n(se_n), .si(so53), .so(so59), .bk5(bk[59]), + .bk4(bk[58]), .bk3(bk[57]), .bk2(bk[56]), .bk1(bk[55]), + .bk0(bk[54]), .co_p(a59), .ci_p(b59), .in_p(a53), .out_p(b53)); +aibnd_cmos_nand_x6 xnand_x6_8 ( .vcc_aibnd(vcc_aibnd), + .vss_aibnd(vss_aibnd), .code_valid(code_valid), .ck(ck), + .nrst(nrst), .se_n(se_n), .si(so47), .so(so53), .bk5(bk[53]), + .bk4(bk[52]), .bk3(bk[51]), .bk2(bk[50]), .bk1(bk[49]), + .bk0(bk[48]), .co_p(a53), .ci_p(b53), .in_p(a47), .out_p(b47)); +aibnd_cmos_nand_x6 xnand_x6_7 ( .vcc_aibnd(vcc_aibnd), + .vss_aibnd(vss_aibnd), .code_valid(code_valid), .ck(ck), + .nrst(nrst), .se_n(se_n), .si(so41), .so(so47), .bk5(bk[47]), + .bk4(bk[46]), .bk3(bk[45]), .bk2(bk[44]), .bk1(bk[43]), + .bk0(bk[42]), .co_p(a47), .ci_p(b47), .in_p(a41), .out_p(b41)); +aibnd_cmos_nand_x6 xnand_x6_6 ( .vcc_aibnd(vcc_aibnd), + .vss_aibnd(vss_aibnd), .code_valid(code_valid), .ck(ck), + .nrst(nrst), .se_n(se_n), .si(so35), .so(so41), .bk5(bk[41]), + .bk4(bk[40]), .bk3(bk[39]), .bk2(bk[38]), .bk1(bk[37]), + .bk0(bk[36]), .co_p(a41), .ci_p(b41), .in_p(a35), .out_p(b35)); +aibnd_cmos_nand_x6 xnand_x6_5 ( .vcc_aibnd(vcc_aibnd), + .vss_aibnd(vss_aibnd), .code_valid(code_valid), .ck(ck), + .nrst(nrst), .se_n(se_n), .si(so29), .so(so35), .bk5(bk[35]), + .bk4(bk[34]), .bk3(bk[33]), .bk2(bk[32]), .bk1(bk[31]), + .bk0(bk[30]), .co_p(a35), .ci_p(b35), .in_p(a29), .out_p(b29)); +aibnd_cmos_nand_x6 xnand_x6_4 ( .vcc_aibnd(vcc_aibnd), + .vss_aibnd(vss_aibnd), .code_valid(code_valid), .ck(ck), + .nrst(nrst), .se_n(se_n), .si(so23), .so(so29), .bk5(bk[29]), + .bk4(bk[28]), .bk3(bk[27]), .bk2(bk[26]), .bk1(bk[25]), + .bk0(bk[24]), .co_p(a29), .ci_p(b29), .in_p(a23), .out_p(b23)); +aibnd_cmos_nand_x6 xnand_x6_3 ( .vcc_aibnd(vcc_aibnd), + .vss_aibnd(vss_aibnd), .code_valid(code_valid), .ck(ck), + .nrst(nrst), .se_n(se_n), .si(so17), .so(so23), .bk5(bk[23]), + .bk4(bk[22]), .bk3(bk[21]), .bk2(bk[20]), .bk1(bk[19]), + .bk0(bk[18]), .co_p(a23), .ci_p(b23), .in_p(a17), .out_p(b17)); +aibnd_cmos_nand_x6 xnand_x6_2 ( .vcc_aibnd(vcc_aibnd), + .vss_aibnd(vss_aibnd), .code_valid(code_valid), .ck(ck), + .nrst(nrst), .se_n(se_n), .si(so11), .so(so17), .bk5(bk[17]), + .bk4(bk[16]), .bk3(bk[15]), .bk2(bk[14]), .bk1(bk[13]), + .bk0(bk[12]), .co_p(a17), .ci_p(b17), .in_p(a11), .out_p(b11)); +aibnd_cmos_nand_x6 xnand_x6_1 ( .vcc_aibnd(vcc_aibnd), + .vss_aibnd(vss_aibnd), .code_valid(code_valid), .ck(ck), + .nrst(nrst), .se_n(se_n), .si(so5), .so(so11), .bk5(bk[11]), + .bk4(bk[10]), .bk3(bk[9]), .bk2(bk[8]), .bk1(bk[7]), .bk0(bk[6]), + .co_p(a11), .ci_p(b11), .in_p(a5), .out_p(b5)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_d8xsesdd1.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_d8xsesdd1.v new file mode 100644 index 0000000..cde607f --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_d8xsesdd1.v @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_d8xsesdd1, View - schematic +// LAST TIME SAVED: Nov 20 19:10:52 2014 +// NETLIST TIME: Nov 21 11:04:30 2014 + +module aibnd_d8xsesdd1 ( iopad, vccl_aibnd, vssl_aibnd ); + +inout iopad; + +input vccl_aibnd, vssl_aibnd; + +/* +specify + specparam CDS_LIBNAME = "aibnd_lib"; + specparam CDS_CELLNAME = "aibnd_d8xsesdd1"; + specparam CDS_VIEWNAME = "schematic"; +endspecify +*/ + + + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_d8xsesdd2.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_d8xsesdd2.v new file mode 100644 index 0000000..1818b2d --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_d8xsesdd2.v @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_d8xsesdd2, View - schematic +// LAST TIME SAVED: Nov 20 19:10:52 2014 +// NETLIST TIME: Nov 21 11:04:30 2014 + +module aibnd_d8xsesdd2 ( iopad, vccl_aibnd, vssl_aibnd ); + +inout iopad; + +input vccl_aibnd, vssl_aibnd; + +/* +specify + specparam CDS_LIBNAME = "aibnd_lib"; + specparam CDS_CELLNAME = "aibnd_d8xsesdd2"; + specparam CDS_VIEWNAME = "schematic"; +endspecify +*/ + + + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_data_buf.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_data_buf.v new file mode 100644 index 0000000..bfd3f9d --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_data_buf.v @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_data_buf, View - schematic +// LAST TIME SAVED: Apr 20 19:57:06 2015 +// NETLIST TIME: May 12 17:53:11 2015 +// `timescale 1ns / 1ns + +module aibnd_data_buf ( sig_out, sig_in, vccl_aibnd, vssl_aibnd ); + +output sig_out; + +input sig_in, vccl_aibnd, vssl_aibnd; + +wire sig_in, sig_out; // Conversion Sript Generated + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_data_buf"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +assign sig_out = sig_in; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_3bcnt.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_3bcnt.v new file mode 100644 index 0000000..64de162 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_3bcnt.v @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_3bcnt, View - schematic +// LAST TIME SAVED: Jan 14 13:08:14 2015 +// NETLIST TIME: Jan 20 13:37:51 2015 + +module aibnd_dcc_3bcnt ( dir_flip, overflow, ovrflow_check, scan_out, + vcc_pl, vss_pl, clk, clk_coding, dir, nrst, overflow_opp, + scan_clk_in, scan_in, scan_mode_n, scan_rst_n ); + +output dir_flip, overflow, ovrflow_check, scan_out; + +inout vcc_pl, vss_pl; + +input clk, clk_coding, dir, nrst, overflow_opp, scan_clk_in, scan_in, + scan_mode_n, scan_rst_n; + +wire net095, dly_vcc, nrst, dir_flipb, ovrflow_check, limit_inc, net099, q0b, dir_buf, net063, net0103, net084, q2, net032, net083, dir_flip, overflow, net070, net037, q1, q1b, nrst_dlyed, net040, q2b, net098, net0104, dir, q0, overflow_mux, scan_mode_n, scan_clk_in, overflowb_mux, overflow_opp, nrst_dlyed_mux, scan_rst_n, net0102, net0101, net085, net086; // Conversion Sript Generated + + + +assign net095 = !(dly_vcc & nrst); +assign dir_flipb = !(ovrflow_check & limit_inc); +assign net099 = !(q0b & dir_buf); +assign net063 = !(net0103 & net084); +assign net0103 = !(q2 & dir_buf); +assign net032 = !(net099 & net083); +assign dir_flip = !dir_flipb; +assign overflow = !net070; +assign q0b = !net037; +assign q1 = !q1b; +assign nrst_dlyed = !net095; +assign q1b = !net040; +assign q2b = !net098; +assign q2 = !q2b; +assign net0104 = !dir; +assign q0 = !q0b; +assign dir_buf = !net0104; +aibnd_dcc_ff x163 ( .so(so6), .se_n(scan_mode_n), .si(so5), .q(net064), + .vcc_pl(vcc_pl), .rb(nrst_dlyed_mux), .clk(clk_coding), + .d(net046), .vss_pl(vss_pl)); +aibnd_dcc_ff x149 ( .so(so7), .se_n(scan_mode_n), .si(so3), .q(net037), + .vcc_pl(vcc_pl), .rb(nrst_dlyed_mux), .clk(clk), .d(net032), + .vss_pl(vss_pl)); +aibnd_dcc_ff x148 ( .so(so8), .se_n(scan_mode_n), .si(so7), .q(net040), + .vcc_pl(vcc_pl), .rb(nrst_dlyed_mux), .clk(clk), .d(net0101), + .vss_pl(vss_pl)); +aibnd_dcc_ff x152 ( .so(so2), .se_n(scan_mode_n), .si(so1), + .q(ovrflow_check), .vcc_pl(vcc_pl), .rb(nrst_dlyed_mux), + .clk(overflow_mux), .d(dly_vcc), .vss_pl(vss_pl)); +aibnd_dcc_ff x153 ( .so(so3), .se_n(scan_mode_n), .si(so2), + .q(limit_inc), .vcc_pl(vcc_pl), .rb(nrst_dlyed_mux), + .clk(overflowb_mux), .d(dly_vcc), .vss_pl(vss_pl)); +aibnd_dcc_ff x162 ( .so(so5), .se_n(scan_mode_n), .si(so4), .q(net046), + .vcc_pl(vcc_pl), .rb(nrst_dlyed_mux), .clk(clk_coding), + .d(net049), .vss_pl(vss_pl)); +aibnd_dcc_ff x161 ( .so(so4), .se_n(scan_mode_n), .si(vss_pl), + .q(net049), .vcc_pl(vcc_pl), .rb(nrst_dlyed_mux), + .clk(clk_coding), .d(vss_pl), .vss_pl(vss_pl)); +aibnd_dcc_ff x147 ( .so(scan_out), .se_n(scan_mode_n), .si(so8), + .q(net098), .vcc_pl(vcc_pl), .rb(nrst_dlyed_mux), .clk(clk), + .d(net063), .vss_pl(vss_pl)); +aibnd_dcc_ff x151 ( .so(so1), .se_n(scan_mode_n), .si(so0), + .q(dly_vcc), .vcc_pl(vcc_pl), .rb(nrst), .clk(clk_coding), + .d(net035), .vss_pl(vss_pl)); +aibnd_dcc_ff x150 ( .so(so0), .se_n(scan_mode_n), .si(scan_in), + .q(net035), .vcc_pl(vcc_pl), .rb(nrst), .clk(clk_coding), + .d(vcc_pl), .vss_pl(vss_pl)); +assign overflow_mux = scan_mode_n ? overflow : scan_clk_in; +assign overflowb_mux = scan_mode_n ? overflow_opp : scan_clk_in; +assign nrst_dlyed_mux = scan_mode_n ? nrst_dlyed : scan_rst_n; +assign net0102 = !(q2 & q1 & dir_buf); +assign net083 = !(q2 & q1 & dir_buf); +assign net0101 = !(net085 & net0102 & net086); +assign net086 = !(q1b & q0 & dir_buf); +assign net085 = !(q1 & q0b & dir_buf); +assign net070 = !(q2 & q1 & q0); +assign net084 = !(q1 & q0 & dir_buf); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_4b_b2tc.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_4b_b2tc.v new file mode 100644 index 0000000..a953403 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_4b_b2tc.v @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_4b_b2tc, View - schematic +// LAST TIME SAVED: Oct 28 09:54:35 2014 +// NETLIST TIME: Oct 29 14:53:12 2014 + +module aibnd_dcc_4b_b2tc ( therm, thermb, vcc_pl, vss_pl, q0, q1, q2, + q3, rb_dcc_manual, rb_dcc_manual_mode ); + + +inout vcc_pl, vss_pl; + +input q0, q1, q2, q3, rb_dcc_manual_mode; + +output [14:0] thermb; +output [14:0] therm; + +input [3:0] rb_dcc_manual; + +wire b0b, b1b, b2b, b3b, net045, net046, net057, net058, net088, net089, b3, rb_dcc_manual_mode, q3, b1, q1, b0, q0, b2, q2, net086, net066, net087, net067, net072, net042, net075; // Conversion Sript Generated + + +assign therm[14] = !(b0b | b1b | b2b | b3b ); +assign therm[3] = !(b2b & b3b); +assign therm[5] = !(net045 & b3b); +assign therm[6] = !(net046 & b3b); +assign therm[12] = !(net057 & net058); +assign therm[10] = !(net088 & net089); +assign b3 = rb_dcc_manual_mode ? rb_dcc_manual[3] : q3; +assign b1 = rb_dcc_manual_mode ? rb_dcc_manual[1] : q1; +assign b0 = rb_dcc_manual_mode ? rb_dcc_manual[0] : q0; +assign b2 = rb_dcc_manual_mode ? rb_dcc_manual[2] : q2; +assign b3b = !b3; +assign therm[7] = !thermb[7]; +assign thermb[7] = !b3; +assign thermb[8] = !therm[8]; +assign thermb[9] = !therm[9]; +assign b0b = !b0; +assign b1b = !b1; +assign thermb[10] = !therm[10]; +assign b2b = !b2; +assign thermb[0] = !therm[0]; +assign thermb[1] = !therm[1]; +assign thermb[2] = !therm[2]; +assign thermb[3] = !therm[3]; +assign thermb[4] = !therm[4]; +assign thermb[5] = !therm[5]; +assign thermb[6] = !therm[6]; +assign net086 = !net066; +assign thermb[11] = !therm[11]; +assign thermb[12] = !therm[12]; +assign net087 = !net067; +assign thermb[13] = !therm[13]; +assign thermb[14] = !therm[14]; +assign therm[0] = !(b0b & b1b & b2b & b2b); +assign net089 = !(b2 & b3); +assign net045 = !(b1 & b2); +assign net072 = !(b0 & b1); +assign net042 = !(b1 & b2); +assign net075 = !(b0 & b2); +assign net067 = !(b1b & b2b); +assign therm[1] = !(b1b & b2b & b3b); +assign net057 = !(b0 & b2 & b3); +assign net066 = !(b0b & b1b & b2b); +assign net046 = !(b0 & b1 & b2); +assign therm[2] = !(net072 & b2b & b3b); +assign therm[4] = !(net075 & net042 & b3b); +assign net088 = !(b0 & b1 & b3); +assign net058 = !(b1 & b2 & b3); +assign therm[8] = !(net086 | b3b); +assign therm[9] = !(net087 | b3b); +assign therm[11] = !(b2b | b3b); +assign therm[13] = !(b1b | b2b | b3b); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_4bdncnt.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_4bdncnt.v new file mode 100644 index 0000000..18e4434 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_4bdncnt.v @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_4bdncnt, View - schematic +// LAST TIME SAVED: Oct 27 19:03:25 2014 +// NETLIST TIME: Oct 29 14:53:12 2014 + +module aibnd_dcc_4bdncnt ( full, q0, q1, q2, q3, vcc_pl, vss_pl, clk, + dir, hold, nrst ); + +output full, q0, q1, q2, q3; + +inout vcc_pl, vss_pl; + +input clk, dir, hold, nrst; + +wire net066, q1, q0b, net035, q3, q0, net071, net042, q2, net063, net070, net039, net057, net034, q1b, net036, net092, net089, net065, net064, net090, net040, net062, q3b, q2b, ck, dir, clk, hld, holdb, net087, net059, net017, full, hold, net072, net060, net018, net099, net091; // Conversion Sript Generated + + +assign net066 = !(q1 & q0b); +assign net035 = !(q3 & q0); +assign net071 = !(q3 & q1); +assign net042 = !(q2 & q0); +assign net063 = !(q1 & q0); +assign net070 = !(q3 & q2); +assign net039 = !(q2 & q1); +assign net057 = !(net070 & net035 & net071); +assign net034 = !(q2 & q1b & q0b); +assign net036 = !(q3 & q1b & q0b); +assign net092 = !(net063 & net034 & net036); +assign net089 = !(net066 & net065 & net064); +assign net064 = !(q3 & q1b & q0b); +assign net090 = !(net042 & net039 & net040); +assign net065 = !(q2 & q1b & q0b); +aibnd_dcc_ff_pst x104 ( .q(net017), .vcc_pl(vcc_pl), .rb(nrst), + .clk(ck), .d(net091), .vss_pl(vss_pl)); +aibnd_dcc_ff_pst x106 ( .q(net087), .vcc_pl(vcc_pl), .rb(nrst), + .clk(ck), .d(net018), .vss_pl(vss_pl)); +aibnd_dcc_ff_pst x105 ( .q(net072), .vcc_pl(vcc_pl), .rb(nrst), + .clk(ck), .d(net099), .vss_pl(vss_pl)); +aibnd_dcc_ff_pst x103 ( .q(net059), .vcc_pl(vcc_pl), .rb(nrst), + .clk(ck), .d(net060), .vss_pl(vss_pl)); +assign net062 = !(q3b & q2b & q1b & q1b); +assign net040 = !(q3 & q2b & q1b & q1b); +assign ck = !(dir & clk); +assign hld = !(dir & holdb); +assign q0b = !net087; +assign q3b = !net059; +assign q2b = !net017; +assign full = !net062; +assign holdb = !hold; +assign q1b = !net072; +assign q3 = !q3b; +assign q2 = !q2b; +assign q0 = !q0b; +assign q1 = !q1b; +assign net060 = hld ? q3 : net057; +assign net018 = hld ? q0 : net089; +assign net099 = hld ? q1 : net092; +assign net091 = hld ? q2 : net090; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_4bupcnt.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_4bupcnt.v new file mode 100644 index 0000000..2ee45d2 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_4bupcnt.v @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_4bupcnt, View - schematic +// LAST TIME SAVED: Oct 27 16:24:12 2014 +// NETLIST TIME: Oct 29 14:53:12 2014 + +module aibnd_dcc_4bupcnt ( full, q0, q1, q2, q3, vcc_pl, vss_pl, clk, + dir, hold, nrst ); + +output full, q0, q1, q2, q3; + +inout vcc_pl, vss_pl; + +input clk, dir, hold, nrst; + +wire net066, q1b, q0b, net057, q3b, net038, net034, q1, net042, q3, q2, net063, q0, net040, net039, net065, net036, net092, net089, net064, net048, q2b, net090, net062, ck, dir, clk, hld, holdb, net087, net059, net017, full, hold, net072, net060, net018, net099, net091; // Conversion Sript Generated + +assign net066 = !(q1b & q0b); +assign net057 = !(q3b & net038); +assign net034 = !(q1 & q0b); +assign net042 = !(q3 & q2); +assign net063 = !(q1b & q0); +assign net040 = !(q2 & q0b); +assign net039 = !(q2 & q1b); +assign net065 = !(q1 & q0b); +assign net038 = !(q2 & q1 & q0); +assign net036 = !(q3 & q2 & q1); +assign net092 = !(net063 & net034 & net036); +assign net089 = !(net066 & net065 & net064); +assign net064 = !(q3 & q2 & q1); +assign net048 = !(q2b & q1 & q0); +assign net090 = !(net042 & net039 & net040 & net040); +assign net062 = !(q3 & q2 & q1 & q1); +assign ck = !(dir & clk); +assign hld = !(dir & holdb); +assign q0b = !net087; +assign q3b = !net059; +assign q2b = !net017; +assign full = !net062; +assign holdb = !hold; +assign q1b = !net072; +assign q3 = !q3b; +assign q2 = !q2b; +assign q0 = !q0b; +assign q1 = !q1b; +aibnd_dcc_ff x102 ( .q(net059), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck), + .d(net060), .vss_pl(vss_pl)); +aibnd_dcc_ff xreg2 ( .q(net017), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck), + .d(net091), .vss_pl(vss_pl)); +aibnd_dcc_ff xreg0 ( .q(net087), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck), + .d(net018), .vss_pl(vss_pl)); +aibnd_dcc_ff xreg1 ( .q(net072), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck), + .d(net099), .vss_pl(vss_pl)); +assign net060 = hld ? q3 : net057; +assign net018 = hld ? q0 : net089; +assign net099 = hld ? q1 : net092; +assign net091 = hld ? q2 : net090; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_5b_b2tc.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_5b_b2tc.v new file mode 100644 index 0000000..0ecf1d0 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_5b_b2tc.v @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_5b_b2tc, View - schematic +// LAST TIME SAVED: Dec 16 14:16:33 2014 +// NETLIST TIME: Dec 17 10:24:03 2014 + +module aibnd_dcc_5b_b2tc ( scan_out, therm_ff, thermb_ff, vcc_pl, + vss_pl, clk, nrst_coding, q0, q1, q2, q3, q4, rb_dcc_manual, + rb_dcc_manual_mode, scan_in, scan_mode_n ); + +output scan_out; + +inout vcc_pl, vss_pl; + +input clk, nrst_coding, q0, q1, q2, q3, q4, rb_dcc_manual_mode, + scan_in, scan_mode_n; + +output [30:0] thermb_ff; +output [30:0] therm_ff; + +input [4:0] rb_dcc_manual; + +wire b3, rb_dcc_manual_mode, q3, b1, q1, b0, q0, b2, q2, b4, q4, b3b, b0b, b1b, b2b, b4b; // Conversion Sript Generated + +// Buses in the design + +wire [30:0] therm_prebuf; + +wire [30:0] thermb; + +wire [30:0] therm; + +wire [29:0] so; + + + +assign b3 = rb_dcc_manual_mode ? rb_dcc_manual[3] : q3; +assign b1 = rb_dcc_manual_mode ? rb_dcc_manual[1] : q1; +assign b0 = rb_dcc_manual_mode ? rb_dcc_manual[0] : q0; +assign b2 = rb_dcc_manual_mode ? rb_dcc_manual[2] : q2; +assign b4 = rb_dcc_manual_mode ? rb_dcc_manual[4] : q4; +aibnd_dcc_ff xreg1[30:0] ( therm_prebuf[30:0], {scan_out, so[29], + so[28], so[27], so[26], so[25], so[24], so[23], so[22], so[21], + so[20], so[19], so[18], so[17], so[16], so[15], so[14], so[13], + so[12], so[11], so[10], so[9], so[8], so[7], so[6], so[5], so[4], + so[3], so[2], so[1], so[0]}, vcc_pl, vss_pl, clk, therm[30:0], + nrst_coding, scan_mode_n, {so[29], so[28], so[27], so[26], so[25], + so[24], so[23], so[22], so[21], so[20], so[19], so[18], so[17], + so[16], so[15], so[14], so[13], so[12], so[11], so[10], so[9], + so[8], so[7], so[6], so[5], so[4], so[3], so[2], so[1], so[0], + scan_in}); +assign therm_ff[30:0] = !thermb_ff[30:0]; +assign thermb_ff[30:0] = !therm_prebuf[30:0]; +assign b3b = !b3; +assign b0b = !b0; +assign b1b = !b1; +assign b2b = !b2; +assign b4b = !b4; +aibnd_dcc_5b_b2tc_x1 x118 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[0]), .thermb(thermb[0]), .q4(b4b), .q3(b3b), + .q2(b2b), .q1(b1b), .q0(b0), .therm_p1(therm[1])); +aibnd_dcc_5b_b2tc_x1 x149 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[17]), .thermb(thermb[17]), .q4(b4), .q3(b3b), + .q2(b2b), .q1(b1), .q0(b0b), .therm_p1(therm[18])); +aibnd_dcc_5b_b2tc_x1 x148 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[18]), .thermb(thermb[18]), .q4(b4), .q3(b3b), + .q2(b2b), .q1(b1), .q0(b0), .therm_p1(therm[19])); +aibnd_dcc_5b_b2tc_x1 x147 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[19]), .thermb(thermb[19]), .q4(b4), .q3(b3b), + .q2(b2), .q1(b1b), .q0(b0b), .therm_p1(therm[20])); +aibnd_dcc_5b_b2tc_x1 x146 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[20]), .thermb(thermb[20]), .q4(b4), .q3(b3b), + .q2(b2), .q1(b1b), .q0(b0), .therm_p1(therm[21])); +aibnd_dcc_5b_b2tc_x1 x144 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[21]), .thermb(thermb[21]), .q4(b4), .q3(b3b), + .q2(b2), .q1(b1), .q0(b0b), .therm_p1(therm[22])); +aibnd_dcc_5b_b2tc_x1 x145 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[16]), .thermb(thermb[16]), .q4(b4), .q3(b3b), + .q2(b2b), .q1(b1b), .q0(b0), .therm_p1(therm[17])); +aibnd_dcc_5b_b2tc_x1 x127 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[8]), .thermb(thermb[8]), .q4(b4b), .q3(b3), .q2(b2b), + .q1(b1b), .q0(b0), .therm_p1(therm[9])); +aibnd_dcc_5b_b2tc_x1 x126 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[9]), .thermb(thermb[9]), .q4(b4b), .q3(b3), .q2(b2b), + .q1(b1), .q0(b0b), .therm_p1(therm[10])); +aibnd_dcc_5b_b2tc_x1 x125 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[7]), .thermb(thermb[7]), .q4(b4b), .q3(b3), .q2(b2b), + .q1(b1b), .q0(b0b), .therm_p1(therm[8])); +aibnd_dcc_5b_b2tc_x1 x124 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[6]), .thermb(thermb[6]), .q4(b4b), .q3(b3b), .q2(b2), + .q1(b1), .q0(b0), .therm_p1(therm[7])); +aibnd_dcc_5b_b2tc_x1 x143 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[23]), .thermb(thermb[23]), .q4(b4), .q3(b3), + .q2(b2b), .q1(b1b), .q0(b0b), .therm_p1(therm[24])); +aibnd_dcc_5b_b2tc_x1 x142 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[25]), .thermb(thermb[25]), .q4(b4), .q3(b3), + .q2(b2b), .q1(b1), .q0(b0b), .therm_p1(therm[26])); +aibnd_dcc_5b_b2tc_x1 x141 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[24]), .thermb(thermb[24]), .q4(b4), .q3(b3), + .q2(b2b), .q1(b1b), .q0(b0), .therm_p1(therm[25])); +aibnd_dcc_5b_b2tc_x1 x139 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[26]), .thermb(thermb[26]), .q4(b4), .q3(b3), + .q2(b2b), .q1(b1), .q0(b0), .therm_p1(therm[27])); +aibnd_dcc_5b_b2tc_x1 x140 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[22]), .thermb(thermb[22]), .q4(b4), .q3(b3b), + .q2(b2), .q1(b1), .q0(b0), .therm_p1(therm[23])); +aibnd_dcc_5b_b2tc_x1 x138 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[27]), .thermb(thermb[27]), .q4(b4), .q3(b3), .q2(b2), + .q1(b1b), .q0(b0b), .therm_p1(therm[28])); +aibnd_dcc_5b_b2tc_x1 x136 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[30]), .thermb(thermb[30]), .q4(b4), .q3(b3), .q2(b2), + .q1(b1), .q0(b0), .therm_p1(vss_pl)); +aibnd_dcc_5b_b2tc_x1 x134 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[29]), .thermb(thermb[29]), .q4(b4), .q3(b3), .q2(b2), + .q1(b1), .q0(b0b), .therm_p1(therm[30])); +aibnd_dcc_5b_b2tc_x1 x131 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[12]), .thermb(thermb[12]), .q4(b4b), .q3(b3), + .q2(b2), .q1(b1b), .q0(b0), .therm_p1(therm[13])); +aibnd_dcc_5b_b2tc_x1 x130 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[13]), .thermb(thermb[13]), .q4(b4b), .q3(b3), + .q2(b2), .q1(b1), .q0(b0b), .therm_p1(therm[14])); +aibnd_dcc_5b_b2tc_x1 x129 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[11]), .thermb(thermb[11]), .q4(b4b), .q3(b3), + .q2(b2), .q1(b1b), .q0(b0b), .therm_p1(therm[12])); +aibnd_dcc_5b_b2tc_x1 x123 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[4]), .thermb(thermb[4]), .q4(b4b), .q3(b3b), .q2(b2), + .q1(b1b), .q0(b0), .therm_p1(therm[5])); +aibnd_dcc_5b_b2tc_x1 x122 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[5]), .thermb(thermb[5]), .q4(b4b), .q3(b3b), .q2(b2), + .q1(b1), .q0(b0b), .therm_p1(therm[6])); +aibnd_dcc_5b_b2tc_x1 x121 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[3]), .thermb(thermb[3]), .q4(b4b), .q3(b3b), .q2(b2), + .q1(b1b), .q0(b0b), .therm_p1(therm[4])); +aibnd_dcc_5b_b2tc_x1 x119 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[1]), .thermb(thermb[1]), .q4(b4b), .q3(b3b), + .q2(b2b), .q1(b1), .q0(b0b), .therm_p1(therm[2])); +aibnd_dcc_5b_b2tc_x1 x120 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[2]), .thermb(thermb[2]), .q4(b4b), .q3(b3b), + .q2(b2b), .q1(b1), .q0(b0), .therm_p1(therm[3])); +aibnd_dcc_5b_b2tc_x1 x137 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[28]), .thermb(thermb[28]), .q4(b4), .q3(b3), .q2(b2), + .q1(b1b), .q0(b0), .therm_p1(therm[29])); +aibnd_dcc_5b_b2tc_x1 x133 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[15]), .thermb(thermb[15]), .q4(b4), .q3(b3b), + .q2(b2b), .q1(b1b), .q0(b0b), .therm_p1(therm[16])); +aibnd_dcc_5b_b2tc_x1 x132 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[14]), .thermb(thermb[14]), .q4(b4b), .q3(b3), + .q2(b2), .q1(b1), .q0(b0), .therm_p1(therm[15])); +aibnd_dcc_5b_b2tc_x1 x128 ( .vss_pl(vss_pl), .vcc_pl(vcc_pl), + .therm(therm[10]), .thermb(thermb[10]), .q4(b4b), .q3(b3), + .q2(b2b), .q1(b1), .q0(b0), .therm_p1(therm[11])); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_5b_b2tc_x1.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_5b_b2tc_x1.v new file mode 100644 index 0000000..4176b2f --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_5b_b2tc_x1.v @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_5b_b2tc_x1, View - schematic +// LAST TIME SAVED: Nov 17 13:12:10 2014 +// NETLIST TIME: Dec 17 10:24:03 2014 + +module aibnd_dcc_5b_b2tc_x1 ( therm, thermb, vcc_pl, vss_pl, q0, q1, + q2, q3, q4, therm_p1 ); + +output therm, thermb; + +inout vcc_pl, vss_pl; + +input q0, q1, q2, q3, q4, therm_p1; + +wire net0353, q1, q0, therm, thermb, net0369, q4, q3, q2, net0565, therm_p1; // Conversion Sript Generated + + + +assign net0353 = !(q1 & q0); +assign therm = !thermb; +assign net0369 = !(q4 & q3 & q2); +assign net0565 = !(net0369 | net0353); +assign thermb = !(net0565 | therm_p1); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_5bdncnt.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_5bdncnt.v new file mode 100644 index 0000000..e8f3ffb --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_5bdncnt.v @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_5bdncnt, View - schematic +// LAST TIME SAVED: Dec 16 14:18:22 2014 +// NETLIST TIME: Dec 17 10:24:04 2014 + +module aibnd_dcc_5bdncnt ( full, q0, q1, q2, q3, q4, scan_out, vcc_pl, + vss_pl, clk, dir, hold_state, nrst, scan_clk_in, scan_in, + scan_mode_n ); + +output full, q0, q1, q2, q3, q4, scan_out; + +inout vcc_pl, vss_pl; + +input clk, dir, hold_state, nrst, scan_clk_in, scan_in, scan_mode_n; + +wire net095, net048, net035, net041, q2b, net016, net089, q0, net0102, full, net069, net040, net045, q4, net036, net047, net090, net039, net042, net076, q1b, q0b, net078, net031, net085, net058, net057, net038, net034, net092, net063, net049, q1, net021, q3b, q4b, net084, net032, net068, net096, net097, net064, net075, net098, net079, net037, net056, dir, clk, hld, holdb, net087, net081, net059, net017, hold_state, ck, net072, q3, q2, ck_mux, scan_mode_n, scan_clk_in, net061, net060, net018, net099, net091; // Conversion Sript Generated + + + +assign net095 = !(net048 | net035); +assign net041 = !(q2b | net016); +assign net089 = !(q0 | net0102); +assign full = !(net069 | net040); +assign net045 = !(q4 & net036); +assign net047 = !(q4 & net045); +assign net090 = !(net039 & net042); +assign net076 = !(q1b & q0b); +assign net040 = !(q1b & q0b); +assign net078 = !(net031 & net085); +assign net058 = !(q1b & q0b); +assign net057 = !(net078 & net038); +assign net034 = !(q1b & q0b); +assign net092 = !(net063 & net049); +assign net063 = !(q1 & q0); +assign net021 = !(q3b & q4b); +assign net084 = !net047; +assign net036 = !net032; +assign net0102 = !net068; +assign net042 = !net095; +assign net085 = !net058; +assign net031 = !net096; +assign net016 = !net076; +assign net097 = !net064; +assign net039 = !net041; +assign net035 = !net021; +assign net064 = !(q4b & q3b & q2b); +assign net075 = !(q2b & q1b & q0b); +assign net069 = !(q4b & q3b & q2b); +assign net048 = !(q2b & q1b & q0b); +assign net096 = !(q4 & q3b & q2b); +assign net098 = !(net034 | net097); +assign net079 = !(q3b | net037); +assign net032 = !(q3b & q2b & q1b & q1b); +assign net068 = !(q4b & q3b & q2b & q2b); +assign net056 = !(dir & clk); +assign hld = !(dir & holdb); +assign q0b = !net087; +assign q4b = !net081; +assign net049 = !net098; +assign net038 = !net079; +assign net037 = !net075; +assign q3b = !net059; +assign q2b = !net017; +assign holdb = !hold_state; +assign ck = !net056; +assign q1b = !net072; +assign q4 = !q4b; +assign q3 = !q3b; +assign q2 = !q2b; +assign q0 = !q0b; +assign q1 = !q1b; +assign ck_mux = scan_mode_n ? ck : scan_clk_in; +assign net061 = hld ? q4 : net084; +assign net060 = hld ? q3 : net057; +assign net018 = hld ? q0 : net089; +assign net099 = hld ? q1 : net092; +assign net091 = hld ? q2 : net090; +aibnd_dcc_ff_pst x102 ( .se_n(scan_mode_n), .so(so3), .si(so2), + .q(net059), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck_mux), .d(net060), + .vss_pl(vss_pl)); +aibnd_dcc_ff_pst x103 ( .se_n(scan_mode_n), .so(scan_out), .si(so3), + .q(net081), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck_mux), .d(net061), + .vss_pl(vss_pl)); +aibnd_dcc_ff_pst xreg2 ( .se_n(scan_mode_n), .so(so2), .si(so1), + .q(net017), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck_mux), .d(net091), + .vss_pl(vss_pl)); +aibnd_dcc_ff_pst xreg0 ( .se_n(scan_mode_n), .so(so0), .si(scan_in), + .q(net087), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck_mux), .d(net018), + .vss_pl(vss_pl)); +aibnd_dcc_ff_pst xreg1 ( .se_n(scan_mode_n), .so(so1), .si(so0), + .q(net072), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck_mux), .d(net099), + .vss_pl(vss_pl)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_5bupcnt.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_5bupcnt.v new file mode 100644 index 0000000..cae17f1 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_5bupcnt.v @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_5bupcnt, View - schematic +// LAST TIME SAVED: Dec 16 14:20:54 2014 +// NETLIST TIME: Dec 17 10:24:03 2014 + +module aibnd_dcc_5bupcnt ( full, q0, q1, q2, q3, q4, scan_out, vcc_pl, + vss_pl, clk, dir, hold_state, nrst, scan_clk_in, scan_in, + scan_mode_n ); + +output full, q0, q1, q2, q3, q4, scan_out; + +inout vcc_pl, vss_pl; + +input clk, dir, hold_state, nrst, scan_clk_in, scan_in, scan_mode_n; + +wire net041, q2b, net016, full, net069, net040, net090, net039, net048, net024, q4, q3, net043, net078, q3b, net038, net020, q1, q0, net084, q4b, net032, net057, net034, q0b, net089, net068, net063, q1b, net031, net037, net076, q2, net092, net036, ck_mux, scan_mode_n, ck, scan_clk_in, net056, dir, clk, hld, holdb, net087, net081, net059, net017, hold_state, net072, net061, net060, net018, net099, net091; // Conversion Sript Generated + + + +assign net041 = !(q2b | net016); +assign full = !(net069 | net040); +assign net090 = !(net039 & net048); +assign net024 = !(q4 & q3); +assign net043 = !(net078 & q3b); +assign net038 = !(q3 & net020); +assign net040 = !(q1 & q0); +assign net084 = !(q4b & net032); +assign net057 = !(net043 & net038); +assign net034 = !(q1 & q0b); +assign net089 = !(q0 & net068); +assign net063 = !(q1b & q0); +assign net031 = !net057; +assign net020 = !net037; +assign net016 = !net076; +assign net039 = !net041; +assign net069 = !(q4 & q3 & q2); +assign net092 = !(net063 & net034 & net036); +assign net076 = !(net024 & q1 & q0); +assign net048 = !(q2b & q1 & q0); +assign ck_mux = scan_mode_n ? ck : scan_clk_in; +assign net032 = !(q3 & q2 & q1 & q1); +assign net037 = !(q4b & q2 & q1 & q1); +assign net036 = !(q4 & q3 & q2 & q2); +assign net078 = !(q3b & q2 & q1 & q1); +assign net068 = !(q4 & q3 & q2 & q2); +assign net056 = !(dir & clk); +assign hld = !(dir & holdb); +assign q0b = !net087; +assign q4b = !net081; +assign q3b = !net059; +assign q2b = !net017; +assign holdb = !hold_state; +assign ck = !net056; +assign q1b = !net072; +assign q4 = !q4b; +assign q3 = !q3b; +assign q2 = !q2b; +assign q0 = !q0b; +assign q1 = !q1b; +aibnd_dcc_ff x102 ( .so(so3), .se_n(scan_mode_n), .si(so2), .q(net059), + .vcc_pl(vcc_pl), .rb(nrst), .clk(ck_mux), .d(net060), + .vss_pl(vss_pl)); +aibnd_dcc_ff x103 ( .so(scan_out), .se_n(scan_mode_n), .si(so3), + .q(net081), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck_mux), .d(net061), + .vss_pl(vss_pl)); +aibnd_dcc_ff xreg2 ( .so(so2), .se_n(scan_mode_n), .si(so1), + .q(net017), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck_mux), .d(net091), + .vss_pl(vss_pl)); +aibnd_dcc_ff xreg0 ( .so(so0), .se_n(scan_mode_n), .si(scan_in), + .q(net087), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck_mux), .d(net018), + .vss_pl(vss_pl)); +aibnd_dcc_ff xreg1 ( .so(so1), .se_n(scan_mode_n), .si(so0), + .q(net072), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck_mux), .d(net099), + .vss_pl(vss_pl)); +assign net061 = hld ? q4 : net084; +assign net060 = hld ? q3 : net031; +assign net018 = hld ? q0 : net089; +assign net099 = hld ? q1 : net092; +assign net091 = hld ? q2 : net090; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_adjust.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_adjust.v new file mode 100644 index 0000000..72a05a1 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_adjust.v @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_adjust, View - schematic +// LAST TIME SAVED: Oct 29 15:22:27 2014 +// NETLIST TIME: Oct 29 17:05:14 2014 + + +module aibnd_dcc_adjust ( ckout, vcc_pl, vss_pl, ckin, init_up, + rb_dcc_byp, therm_dn, therm_up, thermb_dn, thermb_up ); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +output ckout; +inout vcc_pl, vss_pl; +input ckin, init_up, rb_dcc_byp; + +input [30:0] therm_dn; +input [30:0] thermb_up; +input [30:0] thermb_dn; +input [30:0] therm_up; + +time step, a_time,b_time; +integer pulse, total_delay,calc_delay_up, calc_delay_dn, calc_delay; +reg trig; +wire ckin_dcc; + +//-------------------------------------------------------------------------------------------------------------------------------------------- +//--- Calculate the delay of the dcc delay line +//-------------------------------------------------------------------------------------------------------------------------------------------- + + initial step = 5; // Supports 5 ps step size + + always @(posedge ckin) + case (therm_up) + 31'b0_00000_00000_00000_00000_00000_00000 : calc_delay_up <= (0 * step); + 31'b0_00000_00000_00000_00000_00000_00001 : calc_delay_up <= (1 * step); + 31'b0_00000_00000_00000_00000_00000_00011 : calc_delay_up <= (2 * step); + 31'b0_00000_00000_00000_00000_00000_00111 : calc_delay_up <= (3 * step); + 31'b0_00000_00000_00000_00000_00000_01111 : calc_delay_up <= (4 * step); + 31'b0_00000_00000_00000_00000_00000_11111 : calc_delay_up <= (5 * step); + 31'b0_00000_00000_00000_00000_00001_11111 : calc_delay_up <= (6 * step); + 31'b0_00000_00000_00000_00000_00011_11111 : calc_delay_up <= (7 * step); + 31'b0_00000_00000_00000_00000_00111_11111 : calc_delay_up <= (8 * step); + 31'b0_00000_00000_00000_00000_01111_11111 : calc_delay_up <= (9 * step); + 31'b0_00000_00000_00000_00000_11111_11111 : calc_delay_up <= (10 * step); + 31'b0_00000_00000_00000_00001_11111_11111 : calc_delay_up <= (11 * step); + 31'b0_00000_00000_00000_00011_11111_11111 : calc_delay_up <= (12 * step); + 31'b0_00000_00000_00000_00111_11111_11111 : calc_delay_up <= (13 * step); + 31'b0_00000_00000_00000_01111_11111_11111 : calc_delay_up <= (14 * step); + 31'b0_00000_00000_00000_11111_11111_11111 : calc_delay_up <= (15 * step); + 31'b0_00000_00000_00001_11111_11111_11111 : calc_delay_up <= (16 * step); + 31'b0_00000_00000_00011_11111_11111_11111 : calc_delay_up <= (17 * step); + 31'b0_00000_00000_00111_11111_11111_11111 : calc_delay_up <= (18 * step); + 31'b0_00000_00000_01111_11111_11111_11111 : calc_delay_up <= (19 * step); + 31'b0_00000_00000_11111_11111_11111_11111 : calc_delay_up <= (20 * step); + 31'b0_00000_00001_11111_11111_11111_11111 : calc_delay_up <= (21 * step); + 31'b0_00000_00011_11111_11111_11111_11111 : calc_delay_up <= (22 * step); + 31'b0_00000_00111_11111_11111_11111_11111 : calc_delay_up <= (23 * step); + 31'b0_00000_01111_11111_11111_11111_11111 : calc_delay_up <= (24 * step); + 31'b0_00000_11111_11111_11111_11111_11111 : calc_delay_up <= (25 * step); + 31'b0_00001_11111_11111_11111_11111_11111 : calc_delay_up <= (26 * step); + 31'b0_00011_11111_11111_11111_11111_11111 : calc_delay_up <= (27 * step); + 31'b0_00111_11111_11111_11111_11111_11111 : calc_delay_up <= (28 * step); + 31'b0_01111_11111_11111_11111_11111_11111 : calc_delay_up <= (29 * step); + 31'b0_11111_11111_11111_11111_11111_11111 : calc_delay_up <= (30 * step); + 31'b1_11111_11111_11111_11111_11111_11111 : calc_delay_up <= (31 * step); + default : calc_delay_up <= (0 * step); + endcase + + always @(posedge ckin) + case (therm_dn) + 31'b0_00000_00000_00000_00000_00000_00000 : calc_delay_dn <= (-31 * step); + 31'b0_00000_00000_00000_00000_00000_00001 : calc_delay_dn <= (-30 * step); + 31'b0_00000_00000_00000_00000_00000_00011 : calc_delay_dn <= (-29 * step); + 31'b0_00000_00000_00000_00000_00000_00111 : calc_delay_dn <= (-28 * step); + 31'b0_00000_00000_00000_00000_00000_01111 : calc_delay_dn <= (-27 * step); + 31'b0_00000_00000_00000_00000_00000_11111 : calc_delay_dn <= (-26 * step); + 31'b0_00000_00000_00000_00000_00001_11111 : calc_delay_dn <= (-25 * step); + 31'b0_00000_00000_00000_00000_00011_11111 : calc_delay_dn <= (-24 * step); + 31'b0_00000_00000_00000_00000_00111_11111 : calc_delay_dn <= (-23 * step); + 31'b0_00000_00000_00000_00000_01111_11111 : calc_delay_dn <= (-22 * step); + 31'b0_00000_00000_00000_00000_11111_11111 : calc_delay_dn <= (-21 * step); + 31'b0_00000_00000_00000_00001_11111_11111 : calc_delay_dn <= (-20 * step); + 31'b0_00000_00000_00000_00011_11111_11111 : calc_delay_dn <= (-19 * step); + 31'b0_00000_00000_00000_00111_11111_11111 : calc_delay_dn <= (-18 * step); + 31'b0_00000_00000_00000_01111_11111_11111 : calc_delay_dn <= (-17 * step); + 31'b0_00000_00000_00000_11111_11111_11111 : calc_delay_dn <= (-16 * step); + 31'b0_00000_00000_00001_11111_11111_11111 : calc_delay_dn <= (-15 * step); + 31'b0_00000_00000_00011_11111_11111_11111 : calc_delay_dn <= (-14 * step); + 31'b0_00000_00000_00111_11111_11111_11111 : calc_delay_dn <= (-13 * step); + 31'b0_00000_00000_01111_11111_11111_11111 : calc_delay_dn <= (-12 * step); + 31'b0_00000_00000_11111_11111_11111_11111 : calc_delay_dn <= (-11 * step); + 31'b0_00000_00001_11111_11111_11111_11111 : calc_delay_dn <= (-10 * step); + 31'b0_00000_00011_11111_11111_11111_11111 : calc_delay_dn <= (-9 * step); + 31'b0_00000_00111_11111_11111_11111_11111 : calc_delay_dn <= (-8 * step); + 31'b0_00000_01111_11111_11111_11111_11111 : calc_delay_dn <= (-7 * step); + 31'b0_00000_11111_11111_11111_11111_11111 : calc_delay_dn <= (-6 * step); + 31'b0_00001_11111_11111_11111_11111_11111 : calc_delay_dn <= (-5 * step); + 31'b0_00011_11111_11111_11111_11111_11111 : calc_delay_dn <= (-4 * step); + 31'b0_00111_11111_11111_11111_11111_11111 : calc_delay_dn <= (-3 * step); + 31'b0_01111_11111_11111_11111_11111_11111 : calc_delay_dn <= (-2 * step); + 31'b0_11111_11111_11111_11111_11111_11111 : calc_delay_dn <= (-1 * step); + 31'b1_11111_11111_11111_11111_11111_11111 : calc_delay_dn <= (0 * step); + default : calc_delay_dn <= (0 * step); + endcase + + always @(posedge ckin) calc_delay <= calc_delay_up + calc_delay_dn; + always @(posedge ckin) a_time <= $time; + always @(negedge ckin) b_time <= $time; + + always @(posedge ckin) begin + pulse <= b_time - a_time; + total_delay <= pulse + calc_delay; + end + + always @(posedge ckin) + if (ckin) begin + trig <= 1'b1; + #total_delay trig <= 1'b0; + end + + assign ckin_dcc = trig; + assign ckout = (rb_dcc_byp) ? ckin : ckin_dcc; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_clkrst.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_clkrst.v new file mode 100644 index 0000000..eb54d67 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_clkrst.v @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_clkrst, View - schematic +// LAST TIME SAVED: Dec 16 14:07:49 2014 +// NETLIST TIME: Dec 17 10:24:03 2014 + +module aibnd_dcc_clkrst ( clk_coding, nrst, nrst_coding, scan_out, + vcc_pl, vss_pl, clk, dcc_dft_nrst, dcc_dft_nrst_coding, dcc_done, + dcc_req, dll_lock, rb_dcc_dft, rb_dcc_en, scan_clk_in, scan_in, + scan_mode_n, scan_rst_n ); + +output clk_coding, nrst, nrst_coding, scan_out; + +inout vcc_pl, vss_pl; + +input clk, dcc_dft_nrst, dcc_dft_nrst_coding, dcc_done, dcc_req, + dll_lock, rb_dcc_dft, rb_dcc_en, scan_clk_in, scan_in, + scan_mode_n, scan_rst_n; + +wire net052, dcc_req, rb_dcc_en, net054, rb_dcc_dft, dcc_dft_nrst_coding, net051, nrst, dcc_dft_nrst, net021, dccen_dccreq, clkdiv_4_mux, scan_mode_n, clkdiv_4, scan_clk_in, dll_lock_mux, dll_lock, nrst_mux, scan_rst_n, clk_mux, clk, clkdiv_2_mux, clkdiv_2, dccen_dccreq_mux, clkdiv_8_mux, clkdiv_8, nrst_coding, clk_coding_mux, clk_coding_premux, net056, clkdiv_16, net050, net037, net026, clk_coding, net036, dcc_done; // Conversion Sript Generated + + + +assign net052 = !(dcc_req & rb_dcc_en); +assign net054 = rb_dcc_dft ? dcc_dft_nrst_coding : net051; +assign nrst = rb_dcc_dft ? dcc_dft_nrst : net021; +assign dccen_dccreq = !net052; +assign clkdiv_4_mux = scan_mode_n ? clkdiv_4 : scan_clk_in; +assign dll_lock_mux = scan_mode_n ? dll_lock : scan_clk_in; +assign nrst_mux = scan_mode_n ? nrst : scan_rst_n; +assign clk_mux = scan_mode_n ? clk : scan_clk_in; +assign clkdiv_2_mux = scan_mode_n ? clkdiv_2 : scan_clk_in; +assign dccen_dccreq_mux = scan_mode_n ? dccen_dccreq : scan_rst_n; +assign clkdiv_8_mux = scan_mode_n ? clkdiv_8 : scan_clk_in; +assign nrst_coding = scan_mode_n ? net054 : scan_rst_n; +assign clk_coding_mux = scan_mode_n ? clk_coding_premux : scan_clk_in; +assign net056 = !clkdiv_16; +assign net050 = !clkdiv_8; +assign net037 = !clkdiv_2; +assign net026 = !clkdiv_4; +assign clk_coding = clk_coding_mux; +assign net036 = !(dcc_req & dll_lock & rb_dcc_en); +assign net021 = !(net036 | dcc_done); +aibnd_dcc_ff xreg0 ( .so(so1), .se_n(scan_mode_n), .si(so0), + .q(clkdiv_2), .vcc_pl(vcc_pl), .rb(nrst_mux), .clk(clk_mux), + .d(net037), .vss_pl(vss_pl)); +aibnd_dcc_ff xreg2 ( .so(so3), .se_n(scan_mode_n), .si(so2), + .q(clkdiv_8), .vcc_pl(vcc_pl), .rb(nrst_mux), .clk(clkdiv_4_mux), + .d(net050), .vss_pl(vss_pl)); +aibnd_dcc_ff xreg3 ( .so(so4), .se_n(scan_mode_n), .si(so3), + .q(clkdiv_16), .vcc_pl(vcc_pl), .rb(nrst_mux), .clk(clkdiv_8_mux), + .d(net056), .vss_pl(vss_pl)); +aibnd_dcc_ff xreg4 ( .so(scan_out), .se_n(scan_mode_n), .si(so4), + .q(clk_coding_premux), .vcc_pl(vcc_pl), .rb(nrst_mux), + .clk(clk_mux), .d(clkdiv_16), .vss_pl(vss_pl)); +aibnd_dcc_ff x134 ( .so(so0), .se_n(scan_mode_n), .si(scan_in), + .q(net051), .vcc_pl(vcc_pl), .rb(dccen_dccreq_mux), + .clk(dll_lock_mux), .d(vcc_pl), .vss_pl(vss_pl)); +aibnd_dcc_ff xreg1 ( .so(so2), .se_n(scan_mode_n), .si(so1), + .q(clkdiv_4), .vcc_pl(vcc_pl), .rb(nrst_mux), .clk(clkdiv_2_mux), + .d(net026), .vss_pl(vss_pl)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_ctrl.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_ctrl.v new file mode 100644 index 0000000..5a56f9a --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_ctrl.v @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_ctrl, View - schematic +// LAST TIME SAVED: Dec 16 14:23:02 2014 +// NETLIST TIME: Dec 17 10:24:04 2014 + +module aibnd_dcc_ctrl ( dcc_done, dir_dncnt, dir_upcnt, full_dn, + full_up, init_up, nrst, q0_dn, q0_up, q1_dn, q1_up, q2_dn, q2_up, + q3_dn, q3_up, q4_dn, q4_up, scan_out, therm_dn, therm_up, + thermb_dn, thermb_up, vcc_pl, vss_pl, clk, dcc_dft_nrst, + dcc_dft_nrst_coding, dcc_req, dll_lock, rb_dcc_dft, rb_dcc_en, + rb_dcc_manual_dn, rb_dcc_manual_mode, rb_dcc_manual_up, + scan_clk_in, scan_in, scan_mode_n, scan_rst_n, up ); + +output dcc_done, dir_dncnt, dir_upcnt, full_dn, full_up, init_up, + nrst, q0_dn, q0_up, q1_dn, q1_up, q2_dn, q2_up, q3_dn, q3_up, + q4_dn, q4_up, scan_out; + +inout vcc_pl, vss_pl; + +input clk, dcc_dft_nrst, dcc_dft_nrst_coding, dcc_req, dll_lock, + rb_dcc_dft, rb_dcc_en, rb_dcc_manual_mode, scan_clk_in, scan_in, + scan_mode_n, scan_rst_n, up; + +output [30:0] thermb_dn; +output [30:0] thermb_up; +output [30:0] therm_up; +output [30:0] therm_dn; + +input [4:0] rb_dcc_manual_up; +input [4:0] rb_dcc_manual_dn; + + + +aibnd_dcc_clkrst xclkrst ( .scan_out(so_clkrst), + .scan_rst_n(scan_rst_n), .scan_mode_n(scan_mode_n), + .scan_clk_in(scan_clk_in), .scan_in(scan_in), + .dcc_dft_nrst(dcc_dft_nrst), + .dcc_dft_nrst_coding(dcc_dft_nrst_coding), + .rb_dcc_dft(rb_dcc_dft), .nrst(nrst), .nrst_coding(nrst_coding), + .dll_lock(dll_lock), .dcc_req(dcc_req), .vss_pl(vss_pl), + .vcc_pl(vcc_pl), .clk_coding(clk_coding), .rb_dcc_en(rb_dcc_en), + .clk(clk), .dcc_done(dcc_done)); +aibnd_dcc_5b_b2tc xb2t_up ( .scan_out(so_b2t_up), + .scan_mode_n(scan_mode_n), .scan_in(so_5bcnt_dn), + .nrst_coding(nrst_coding), .rb_dcc_manual(rb_dcc_manual_up[4:0]), + .q4(q4_up), .clk(clk_coding), .thermb_ff(thermb_up[30:0]), + .therm_ff(therm_up[30:0]), .q3(q3_up), .vss_pl(vss_pl), + .vcc_pl(vcc_pl), .q2(q2_up), .q1(q1_up), .q0(q0_up), + .rb_dcc_manual_mode(rb_dcc_manual_mode)); +aibnd_dcc_5b_b2tc xb2t_dn ( .scan_out(scan_out), + .scan_mode_n(scan_mode_n), .scan_in(so_b2t_up), + .nrst_coding(nrst_coding), .rb_dcc_manual(rb_dcc_manual_dn[4:0]), + .q4(q4_dn), .clk(clk_coding), .thermb_ff(thermb_dn[30:0]), + .therm_ff(therm_dn[30:0]), .q3(q3_dn), .vss_pl(vss_pl), + .vcc_pl(vcc_pl), .q2(q2_dn), .q1(q1_dn), .q0(q0_dn), + .rb_dcc_manual_mode(rb_dcc_manual_mode)); +aibnd_dcc_5bupcnt x5bcnt_up ( .scan_out(so_5bcnt_up), + .scan_mode_n(scan_mode_n), .scan_clk_in(scan_clk_in), + .scan_in(so_fltr), .hold_state(dcc_done), .q4(q4_up), .q3(q3_up), + .vss_pl(vss_pl), .vcc_pl(vcc_pl), .full(full_up), .q0(q0_up), + .q1(q1_up), .q2(q2_up), .clk(clk_coding), .dir(dir_upcnt), + .nrst(nrst_coding)); +aibnd_dcc_fltr xfltr ( .scan_out(so_fltr), .scan_rst_n(scan_rst_n), + .scan_mode_n(scan_mode_n), .scan_clk_in(scan_clk_in), + .scan_in(so_clkrst), .dcc_req(dcc_req), .init_up(init_up), + .vss_pl(vss_pl), .vcc_pl(vcc_pl), .dcc_done(dcc_done), + .dir_dncnt(dir_dncnt), .dir_upcnt(dir_upcnt), .clk(clk), + .clk_coding(clk_coding), .full_dn(full_dn), .full_up(full_up), + .nrst_coding(nrst_coding), .rb_dcc_en(rb_dcc_en), .up(up)); +aibnd_dcc_5bdncnt x5bcnt_dn ( .scan_out(so_5bcnt_dn), + .scan_mode_n(scan_mode_n), .scan_clk_in(scan_clk_in), + .scan_in(so_5bcnt_up), .hold_state(dcc_done), .q4(q4_dn), + .q3(q3_dn), .vss_pl(vss_pl), .vcc_pl(vcc_pl), .full(full_dn), + .q0(q0_dn), .q1(q1_dn), .q2(q2_dn), .clk(clk_coding), + .dir(dir_dncnt), .nrst(nrst_coding)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dll.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dll.v new file mode 100644 index 0000000..d9964fc --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dll.v @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_dll, View - schematic +// LAST TIME SAVED: Mar 27 14:37:41 2015 +// NETLIST TIME: May 12 17:53:11 2015 +// `timescale 1ns / 1ns + +module aibnd_dcc_dll ( clk_dcc, dcc_done, odll_dll2core, odll_lock, + pvt_ref_half_gry, scan_out, clk_dcd, clk_pll, csr_reg, + idll_core2dll, idll_entest, nfrzdrv, nrst, pipeline_global_en, + rb_clkdiv, rb_cont_cal, rb_dcc_byp, rb_half_code, rb_selflock, + reinit, scan_clk_in, scan_in, scan_mode_n, scan_rst_n, + scan_shift_n, test_clk_pll_en_n, vcc_aibnd, vss_aibnd ); + +output clk_dcc, dcc_done, odll_lock, scan_out; + +input clk_dcd, clk_pll, idll_entest, nfrzdrv, nrst, + pipeline_global_en, rb_cont_cal, rb_dcc_byp, rb_half_code, + rb_selflock, reinit, scan_clk_in, scan_in, scan_mode_n, + scan_rst_n, scan_shift_n, test_clk_pll_en_n, vcc_aibnd, vss_aibnd; + +output [9:0] pvt_ref_half_gry; +output [12:0] odll_dll2core; + +input [51:0] csr_reg; +input [2:0] rb_clkdiv; +input [2:0] idll_core2dll; + +// Buses in the design + +wire [6:0] f_gray; + +wire [0:6] net43; + +wire [9:0] pvt_ref_gry; + +wire [2:0] i_gray; + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_dcc_dll"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +aibnd_dll_custom xdll_custom ( .scan_shift_n(scan_shift_n), + .rb_cont_cal(rb_cont_cal), .vss_aibnd(vss_aibnd), + .vcc_aibnd(vcc_aibnd), .dcc_done(dcc_done), .clk_dcd(clk_dcd), + .rb_dcc_byp(rb_dcc_byp), .scan_out(so_dll_custom), + .scan_rst_n(scan_rst_n), .scan_mode_n(scan_mode_n), + .scan_clk_in(scan_clk_in), .dll_lock(odll_lock), + .scan_in(scan_in), .pvt_ref_half_gry(pvt_ref_half_gry[9:0]), + .clk_dcc(clk_dcc), .nrst(nrst), .launch(launch), + .measure(measure), .nfrzdrv(nfrzdrv), .t_down(t_down), + .t_up(t_up), .dll_reset_n(dll_phdet_reset_n), + .f_gray(f_gray[6:0]), .i_gray(i_gray[2:0])); +aibndpnr_dll_pnr xdll_pnr ( .scan_shift_n(scan_shift_n), + .rb_clkdiv(rb_clkdiv[2:0]), .gate_shf(net43[0:6]), + .scan_in(so_dll_custom), .scan_rst_n(scan_rst_n), + .scan_clk_in(scan_clk_in), .scan_mode_n(scan_mode_n), + .scan_out(scan_out), .pipeline_global_en(pipeline_global_en), + .dll_lock(odll_lock), .rb_half_code(rb_half_code), + .pvt_ref_half_gry(pvt_ref_half_gry[9:0]), //.vcc_io(vcc_aibnd), + //.vss_io(vss_aibnd), + .pvt_ref_gry(pvt_ref_gry[9:0]), + .dll_core(odll_dll2core[12:0]), .i_gray(i_gray[2:0]), + .f_gray(f_gray[6:0]), .core_dll(idll_core2dll[2:0]), + .test_clk_pll_en_n(test_clk_pll_en_n), + .dll_phdet_reset_n(dll_phdet_reset_n), .measure(measure), + .launch(launch), .t_down(t_down), .t_up(t_up), + .entest(idll_entest), .reinit(reinit), .csr_reg(csr_reg[51:0]), + .rb_selflock(rb_selflock), .clk_pll(clk_pll)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dly.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dly.v new file mode 100644 index 0000000..3092a2f --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dly.v @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_dly, View - schematic +// LAST TIME SAVED: Mar 26 07:56:48 2015 +// NETLIST TIME: May 12 17:53:11 2015 +// `timescale 1ns / 1ns + +module aibnd_dcc_dly ( clkn_dly, clkn_mindly, clkp_dly, clkp_mindly, + clk_dcd, dll_lock_reg, gray, launch, measure, nfrzdrv, vcc_aibnd, + vss_aibnd ); + +output clkn_dly, clkn_mindly, clkp_dly, clkp_mindly; + +input clk_dcd, dll_lock_reg, launch, measure, nfrzdrv, vcc_aibnd, + vss_aibnd; + +input [9:0] gray; + +wire clkn_dly, net048, clkn_mindly, net050, clkp_mindly, net049, clkp_dly, net047, net033, measure, vss_aibnd, net028, launch, net025, net024, net022, net023; // Conversion Sript Generated + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_dcc_dly"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +io_nand_delay_line_min xdelay_min ( //.vcc_io(vcc_aibnd), + //.vcc_regphy(vcc_aibnd), .vss_io(vss_aibnd), + .out_n(net023), + .out_p(net022), .in_n(clk_split_mindly_n), + .in_p(clk_split_mindly_p), .nfrzdrv(nfrzdrv)); +assign clkn_dly = !net048; +assign clkn_mindly = !net050; +assign clkp_mindly = !net049; +assign clkp_dly = !net047; +io_nand_x128_delay_line xdelay_line ( .f_gray(gray[9:3]), + //.vcc_io(vcc_aibnd), .vcc_regphy(vcc_aibnd), .vss_io(vss_aibnd), + .osc_out_n(net060), .osc_out_p(net061), .out_n(net025), + .out_p(net024), .i_gray(gray[2:0]), .in_n(clk_split_dlyline_n), + .in_p(clk_split_dlyline_p), .nfrzdrv(nfrzdrv), + .osc_in_n(vcc_aibnd), .osc_in_p(vss_aibnd), .osc_mode(vss_aibnd)); +io_split_align xsplit0 ( //.vcc_io(vcc_aibnd), .vss_io(vss_aibnd), + .dout_n(clk_split_mindly_n), .dout_p(clk_split_mindly_p), + .din(clkin_mindly)); +io_split_align xsplit1 ( //.vcc_io(vcc_aibnd), .vss_io(vss_aibnd), + .dout_n(clk_split_dlyline_n), .dout_p(clk_split_dlyline_p), + .din(clkin_dlyline)); +aibnd_dcc_mux xmux11 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .clk0(launch), .s(dll_lock_reg), .clkout(clkin_dlyline), + .clk1(clk_dcd)); +aibnd_dcc_mux xmux10 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .clk0(measure), .s(dll_lock_reg), .clkout(clkin_mindly), + .clk1(clk_dcd)); +assign net033 = !(measure & vss_aibnd); +assign net028 = !(launch & vss_aibnd); +assign net048 = !net025; +assign net047 = !net024; +assign net049 = !net022; +assign net050 = !net023; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dly_inv.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dly_inv.v new file mode 100644 index 0000000..7f811be --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dly_inv.v @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + + +module aibnd_dcc_dly_inv ( a, o1, vcc_io, vss_io ); + + input a; + output o1; + input vss_io; + input vcc_io; + + + assign o1 = ~a ; + +endmodule + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dly_rep.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dly_rep.v new file mode 100644 index 0000000..71845b7 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dly_rep.v @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_dly_rep, View - schematic +// LAST TIME SAVED: Jun 10 18:02:11 2015 +// NETLIST TIME: Jun 16 14:57:46 2015 +//`timescale 1ns / 1ns + +module aibnd_dcc_dly_rep ( clkrep0, clkrep1, idat0, idat1, rb_dcc_byp, + vcc_aibnd, vss_aibnd ); + +output clkrep0, clkrep1; + +input idat0, idat1, rb_dcc_byp, vcc_aibnd, vss_aibnd; + +/* +specify + specparam CDS_LIBNAME = "aibnd_lib"; + specparam CDS_CELLNAME = "aibnd_dcc_dly_rep"; + specparam CDS_VIEWNAME = "schematic"; +endspecify +*/ + +/* +d04gbf00nd0b0 xbuf2 ( .vss(vss_aibnd), .vcc(vcc_aibnd), + .clk(rb_dcc_byp), .clkout(dcc_byp_buf)); +d04inn00ld0o7 xinv3 ( .o1(clkrep1), .a(net22), .vcc(vcc_aibnd), + .vss(vss_aibnd)); +d04inn00ld0o7 xinv1 ( .o1(clkrep0), .a(net050), .vcc(vcc_aibnd), + .vss(vss_aibnd)); +*/ +wire dcc_byp_buf , idat0_buf , idat1_buf,net22 , net050; +assign dcc_byp_buf = rb_dcc_byp; +assign clkrep1 = ~net22; +assign clkrep0 = ~net050; + +aibnd_io_nand_delay_line_min_rep xdelay_min ( + .out_n(idat0_dly), .out_p(idat1_dly), .in_n(idat0_buf), + .in_p(idat1_buf), .nfrzdrv(vcc_aibnd)); +aibnd_dcc_mux xmux4 ( .clk0(idat1_mux0), .s(vss_aibnd), + .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), .clkout(idat1_mux1), + .clk1(vss_aibnd)); +aibnd_dcc_mux xmux3 ( .clk0(idat1_dly), .s(vss_aibnd), + .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), .clkout(idat1_mux0), + .clk1(vss_aibnd)); +aibnd_dcc_mux xmux1 ( .clk0(idat0_mux0), .s(vss_aibnd), + .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), .clkout(idat0_mux1), + .clk1(vss_aibnd)); +aibnd_dcc_mux xmux0 ( .clk0(idat0_dly), .s(vss_aibnd), + .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), .clkout(idat0_mux0), + .clk1(vss_aibnd)); +aibnd_dcc_mux xmux5 ( .clk0(idat1_mux1), .s(dcc_byp_buf), + .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), .clkout(idat1_mux2), + .clk1(idat1)); +aibnd_dcc_mux xmux2 ( .clk0(idat0_mux1), .s(dcc_byp_buf), + .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), .clkout(idat0_mux2), + .clk1(idat0)); +/* +d04gbf00ld0d0 xbuf0 ( .vss(vss_aibnd), .vcc(vcc_aibnd), .clk(idat0), + .clkout(idat0_buf)); +d04gbf00ld0d0 xbuf1 ( .vss(vss_aibnd), .vcc(vcc_aibnd), .clk(idat1), + .clkout(idat1_buf)); +d04inn00ld0c5 xinv2 ( .o1(net22), .a(idat1_mux2), .vcc(vcc_aibnd), + .vss(vss_aibnd)); +d04inn00ld0c5 xinv0 ( .o1(net050), .a(idat0_mux2), .vcc(vcc_aibnd), + .vss(vss_aibnd)); +*/ +assign idat0_buf = idat0 ; +assign idat1_buf = idat1 ; +assign net22 = ~idat1_mux2; +assign net050 = ~idat0_mux2; + + +endmodule diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_ff.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_ff.v new file mode 100644 index 0000000..d016ee0 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_ff.v @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_ff, View - schematic +// LAST TIME SAVED: Mar 27 14:37:41 2015 +// NETLIST TIME: May 12 17:53:11 2015 +// `timescale 1ns / 1ns + +module aibnd_dcc_ff ( q, so, clk, d, rb, se_n, si, vcc_aibnd, vss_aibnd + ); + +output q, so; + +input clk, d, rb, se_n, si, vcc_aibnd, vss_aibnd; + +wire so, q, net011, se_n, d, si; // Conversion Sript Generated + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_dcc_ff"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +assign so = q; +aibnd_ff_r xreg0 ( .o(q), .d(net011), .clk(clk) /*`ifndef INTCNOPWR , .vss(vss_aibnd) , .vcc(vcc_aibnd) `endif*/ , .rb(rb)); +assign net011 = se_n ? d : si; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_fine_dly.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_fine_dly.v new file mode 100644 index 0000000..d2bbb82 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_fine_dly.v @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_fine_dly, View - schematic +// LAST TIME SAVED: Oct 29 11:08:08 2014 +// NETLIST TIME: Oct 29 15:43:12 2014 + +module aibnd_dcc_fine_dly ( out_p, therm_dn, therm_up, thermb_dn, + thermb_up, vcc_pl, vss_pl, fout_p ); + +output out_p; + +inout vcc_pl, vss_pl; + +input fout_p; + +output [14:0] therm_dn; +output [14:0] thermb_dn; +output [14:0] thermb_up; +output [14:0] therm_up; + +// Buses in the design + +wire [0:2] net040; + +aibnd_dcc_dly_inv inn1[2:0] ( .o1(cap_node1), .a(cap_node), + .vcc_io(vcc_pl), .vss_io(vss_pl)); +aibnd_dcc_dly_inv inn3[2:0] ( .o1(out_p), .a(net040[0:2]), + .vcc_io(vcc_pl), .vss_io(vss_pl)); +aibnd_dcc_dly_inv inn2[2:0] ( .o1(cap_node2), .a(cap_node1), + .vcc_io(vcc_pl), .vss_io(vss_pl)); +aibnd_dcc_dly_inv inn5[2:0] ( .o1(cap_node3), .a(cap_node2), + .vcc_io(vcc_pl), .vss_io(vss_pl)); +aibnd_dcc_dly_inv inn4[2:0] ( .o1(net040[0:2]), .a(cap_node3), + .vcc_io(vcc_pl), .vss_io(vss_pl)); +aibnd_dcc_dly_inv inn0[2:0] ( .o1(cap_node), .a(fout_p), + .vcc_io(vcc_pl), .vss_io(vss_pl)); +aibnd_dcc_fine_dly_x1 x119[14:0] ( .dout(cap_node2), + .vcc_regphy(vcc_pl), .vss_io(vss_pl), .sn(therm_up[14:0]), + .sp(thermb_up[14:0])); +aibnd_dcc_fine_dly_x1 x118[14:0] ( .dout(cap_node2), + .vcc_regphy(vcc_pl), .vss_io(vss_pl), .sn(therm_dn[14:0]), + .sp(thermb_dn[14:0])); +aibnd_dcc_fine_dly_x1 x114[14:0] ( .dout(cap_node1), + .vcc_regphy(vcc_pl), .vss_io(vss_pl), .sn(therm_dn[14:0]), + .sp(thermb_dn[14:0])); +aibnd_dcc_fine_dly_x1 x116[14:0] ( .dout(cap_node3), + .vcc_regphy(vcc_pl), .vss_io(vss_pl), .sn(therm_up[14:0]), + .sp(thermb_up[14:0])); +aibnd_dcc_fine_dly_x1 x115[14:0] ( .dout(cap_node1), + .vcc_regphy(vcc_pl), .vss_io(vss_pl), .sn(therm_up[14:0]), + .sp(thermb_up[14:0])); +aibnd_dcc_fine_dly_x1 xup[14:0] ( .dout(cap_node), .vcc_regphy(vcc_pl), + .vss_io(vss_pl), .sn(therm_up[14:0]), .sp(thermb_up[14:0])); +aibnd_dcc_fine_dly_x1 xdn[14:0] ( .dout(cap_node), .vcc_regphy(vcc_pl), + .vss_io(vss_pl), .sn(therm_dn[14:0]), .sp(thermb_dn[14:0])); +aibnd_dcc_fine_dly_x1 x117[14:0] ( .dout(cap_node3), + .vcc_regphy(vcc_pl), .vss_io(vss_pl), .sn(therm_dn[14:0]), + .sp(thermb_dn[14:0])); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_fine_dly_x1.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_fine_dly_x1.v new file mode 100644 index 0000000..ad40780 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_fine_dly_x1.v @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + + +module aibnd_dcc_fine_dly_x1 ( sp,sn , dout, vcc_regphy, vss_io ); + + input sp,sn; + output dout; + input vss_io; + input vcc_regphy; + + + assign dout = 1'bz ; + +endmodule + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_fltr.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_fltr.v new file mode 100644 index 0000000..8fc2682 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_fltr.v @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_fltr, View - schematic +// LAST TIME SAVED: Jan 14 13:07:12 2015 +// NETLIST TIME: Jan 20 13:37:51 2015 + +module aibnd_dcc_fltr ( dcc_done, dir_dncnt, dir_upcnt, init_up, + scan_out, vcc_pl, vss_pl, clk, clk_coding, dcc_req, full_dn, + full_up, nrst_coding, rb_dcc_en, scan_clk_in, scan_in, + scan_mode_n, scan_rst_n, up ); + +output dcc_done, dir_dncnt, dir_upcnt, init_up, scan_out; + +inout vcc_pl, vss_pl; + +input clk, clk_coding, dcc_req, full_dn, full_up, nrst_coding, + rb_dcc_en, scan_clk_in, scan_in, scan_mode_n, scan_rst_n, up; + +wire net040, scan_mode_n, net0112, scan_clk_in, stuck_overflow_mux, stuck_overflow, dither_overflow_mux, dither_overflow, clk_mux, clk, dcc_req_mux, dcc_req, scan_rst_n, net0113, net97, vss_pl, net085, dither_full, stuck_full, net039, dir_flip_up, full_up, full_dn, dir_flip_dn, net0103, dn, up_ff, upbuf, dcc_done, rb_dcc_en, dummy_dcc_done, dir_upcnt, dir_dncnt; // Conversion Sript Generated + + +assign net040 = scan_mode_n ? net0112 : scan_clk_in; +assign stuck_overflow_mux = scan_mode_n ? stuck_overflow : scan_clk_in; +assign dither_overflow_mux = scan_mode_n ? dither_overflow : scan_clk_in; +assign clk_mux = scan_mode_n ? clk : scan_clk_in; +assign dcc_req_mux = scan_mode_n ? dcc_req : scan_rst_n; +aibnd_dcc_ff x148 ( .so(so10), .se_n(scan_mode_n), .q(dither_full), + .vcc_pl(vcc_pl), .rb(nrst_coding), .clk(dither_overflow_mux), + .si(so9), .d(vcc_pl), .vss_pl(vss_pl)); +aibnd_dcc_ff x145 ( .so(scan_out), .se_n(scan_mode_n), .q(stuck_full), + .vcc_pl(vcc_pl), .rb(nrst_coding), .clk(stuck_overflow_mux), + .si(so11), .d(vcc_pl), .vss_pl(vss_pl)); +aibnd_dcc_ff xff0 ( .so(so6), .se_n(scan_mode_n), .si(so5), + .q(dummy_dcc_done), .vcc_pl(vcc_pl), .rb(dcc_req_mux), + .clk(clk_mux), .d(dcc_req), .vss_pl(vss_pl)); +assign net0112 = !net0113; +aibnd_dcc_3bcnt x3bcnt_stuck ( .overflow_opp(vss_pl), .scan_out(so11), + .scan_rst_n(scan_rst_n), .scan_mode_n(scan_mode_n), + .scan_clk_in(scan_clk_in), .scan_in(so10), .ovrflow_check(net095), + .vss_pl(vss_pl), .vcc_pl(vcc_pl), .clk_coding(clk_coding), + .overflow(stuck_overflow), .dir_flip(net093), .clk(clk_coding), + .dir(net0113), .nrst(nrst_coding)); +aibnd_dcc_3bcnt x3bcnt_dither ( .overflow_opp(vss_pl), .scan_out(so9), + .scan_rst_n(scan_rst_n), .scan_mode_n(scan_mode_n), + .scan_clk_in(scan_clk_in), .scan_in(so8), .ovrflow_check(net0108), + .vss_pl(vss_pl), .vcc_pl(vcc_pl), .clk_coding(clk_coding), + .overflow(dither_overflow), .dir_flip(net0109), .clk(net040), + .dir(vcc_pl), .nrst(nrst_coding)); +aibnd_dcc_3bcnt x3bcnt_dn ( .overflow_opp(dir_upcnt), .scan_out(so8), + .scan_rst_n(scan_rst_n), .scan_mode_n(scan_mode_n), + .scan_clk_in(scan_clk_in), .scan_in(so7), .ovrflow_check(net026), + .vss_pl(vss_pl), .vcc_pl(vcc_pl), .clk_coding(clk_coding), + .overflow(dir_dncnt), .dir_flip(dir_flip_dn), .clk(clk_mux), + .dir(dn), .nrst(nrst_coding)); +aibnd_dcc_3bcnt x3bcnt_up ( .overflow_opp(dir_dncnt), .scan_out(so7), + .scan_rst_n(scan_rst_n), .scan_mode_n(scan_mode_n), + .scan_clk_in(scan_clk_in), .scan_in(so6), .ovrflow_check(init_up), + .vss_pl(vss_pl), .vcc_pl(vcc_pl), .clk_coding(clk_coding), + .overflow(dir_upcnt), .dir_flip(dir_flip_up), .clk(clk_mux), + .dir(upbuf), .nrst(nrst_coding)); +assign net97 = !(vss_pl | net085 | dither_full | stuck_full ); +assign net039 = !(dir_flip_up | full_up | full_dn | dir_flip_dn ); +assign net0103 = !net97; +assign net085 = !net039; +assign dn = !up_ff; +assign upbuf = !dn; +assign dcc_done = rb_dcc_en ? net0103 : dummy_dcc_done; +aibnd_sync_ff xff1 ( .so(so5), .se_n(scan_mode_n), .si(scan_in), + .q(up_ff), //.vcc_pl(vcc_pl), + .rb(nrst_coding), .clk(clk_mux), + .d(up)); + //.vss_pl(vss_pl)); +assign net0113 = !(dir_upcnt | dir_dncnt); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_helper.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_helper.v new file mode 100644 index 0000000..02a95b1 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_helper.v @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_helper, View - schematic +// LAST TIME SAVED: May 7 14:55:59 2015 +// NETLIST TIME: May 12 17:53:11 2015 +// `timescale 1ns / 1ns + +module aibnd_dcc_helper ( clkout, clk_dcd, dcc_byp, launch, launchb, + measure, measureb, rstb, vcc_io, vss_io ); + +output clkout; + +input clk_dcd, dcc_byp, launch, launchb, measure, measureb, rstb, + vcc_io, vss_io; + +wire clk, sel, measure, launch, net074, clkout, datab, data, rb, reset, q, rstb, dcc_byp, net073; // Conversion Sript Generated + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_dcc_helper"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +assign clk = sel ? measure : launch; +aibnd_dcc_mux mbn2 ( .vcc_aibnd(vcc_io), .vss_aibnd(vss_io), .clk0(q), + .s(net073), .clkout(net074), .clk1(clk_dcd)); +assign clkout = net074; +an_io_phdet_ff_ln x2 ( /*`ifndef INTCNOPWR .vcc(vcc_io), .vss(vss_io), `endif*/ .q(q), .clk_p(clk), + .dn(datab), .dp(data), .rst_n(syncrstb)); +assign datab = !data; +assign rb = !reset; +assign data = !q; +assign sel = !data; +assign reset = !rstb; +aibnd_2ff_scan fyn1 ( .si(vss_io), .so(net035), .ssb(vcc_io), .o(syncrstb), .d(vcc_io), .clk(launch) /*`ifndef INTCNOPWR , .vss(vss_io) , .vcc(vcc_io) `endif*/ , .rb(rb)); +aibnd_2ff_scan hgy0 ( .d(vss_io), .clk(measure), .o(net038) /*`ifndef INTCNOPWR , .vcc(vcc_io) `endif*/ , .rb(vss_io), .si(vss_io) /*`ifndef INTCNOPWR , .vss(vss_io) `endif*/ , .so(net036), .ssb(vcc_io)); +assign net073 = dcc_byp; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_mux.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_mux.v new file mode 100644 index 0000000..c105b40 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_mux.v @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_mux, View - schematic +// LAST TIME SAVED: Mar 27 14:37:40 2015 +// NETLIST TIME: May 12 17:53:11 2015 +// `timescale 1ns / 1ns + +module aibnd_dcc_mux ( clkout, clk0, clk1, s, vcc_aibnd, vss_aibnd ); + +output clkout; + +input clk0, clk1, s, vcc_aibnd, vss_aibnd; + +wire net011, s, net013, clk1, net012, clk0, clkout; // Conversion Sript Generated + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_dcc_mux"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +assign net011 = !s; +assign net013 = !(clk1 & s); +assign net012 = !(clk0 & net011); +assign clkout = !(net012 & net013); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_sense.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_sense.v new file mode 100644 index 0000000..71588dc --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_sense.v @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_sense, View - schematic +// LAST TIME SAVED: Nov 27 11:09:50 2014 +// NETLIST TIME: Dec 8 13:43:49 2014 + +module aibnd_dcc_sense ( up, vcc_io, vcc_regphy, vss_io, clk_dcc, + dll_reset_n, nfrzdrv, pvt_ref_half_gry ); + +output up; + +inout vcc_io, vcc_regphy, vss_io; + +input clk_dcc, dll_reset_n, nfrzdrv; + +input [9:0] pvt_ref_half_gry; + +wire up, net018, net022, net025; // Conversion Sript Generated + + + +io_split_align xsplit_align_0 ( + //.vcc_io(vcc_regphy), .vss_io(vss_io), + .dout_n(clk_dcd_split_n), .dout_p(clk_dcd_split_p), + .din(clk_dcc)); +assign up = !net018; +assign net022 = !net025; +io_nand_delay_line_min xdelay_line_match ( .nfrzdrv(nfrzdrv), + //.vcc_regphy(vcc_regphy), .vcc_io(vcc_io), .vss_io(vss_io), + .out_n(clkn_mindly), .out_p(clkp_mindly), .in_n(clk_dcd_split_n), + .in_p(clk_dcd_split_p)); +an_io_phdet_ff xsampling ( /*`ifndef INTCNOPWR .vcc(vcc_io), .vss(vss_io), `endif*/ + .q(net018), + .clk_p(clkp_dly), .dn(clkn_mindly), .dp(clkp_mindly), + .rst_n(dll_reset_n)); +an_io_phdet_ff xload_match ( /*`ifndef INTCNOPWR .vcc(vcc_io), .vss(vss_io), `endif*/ + .q(net025), + .clk_p(clkp_mindly), .dn(clkn_dly), .dp(clkp_dly), + .rst_n(dll_reset_n)); +io_nand_x128_delay_line xdelay_line ( + //.vcc_io(vcc_io), + //.vcc_regphy(vcc_regphy), .vss_io(vss_io), + .i_gray(pvt_ref_half_gry[2:0]), .f_gray(pvt_ref_half_gry[9:3]), + .out_n(clkn_dly), .out_p(clkp_dly), .osc_out_n(net014), + .osc_out_p(net015), .osc_in_n(vcc_io), .osc_in_p(vss_io), + .osc_mode(vss_io), .in_n(clk_dcd_split_n), .in_p(clk_dcd_split_p), + .nfrzdrv(nfrzdrv)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_top.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_top.v new file mode 100644 index 0000000..358bdb1 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_top.v @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dcc_top, View - schematic +// LAST TIME SAVED: Apr 14 10:39:46 2015 +// NETLIST TIME: May 12 17:53:11 2015 +// `timescale 1ns / 1ns + +module aibnd_dcc_top ( clk_dcc, dcc_done, odll_dll2core, scan_out, + clk_dcd, clktree_out, csr_reg, dcc_dft_nrst, dcc_dft_nrst_coding, + dcc_dft_up, dcc_req, idll_core2dll, idll_entest, nfrzdrv, + pipeline_global_en, rb_clkdiv, rb_cont_cal, rb_dcc_byp, + rb_dcc_dft, rb_dcc_dft_sel, rb_dcc_en, rb_dcc_manual_dn, + rb_dcc_manual_up, rb_half_code, rb_selflock, scan_clk_in, scan_in, + scan_mode_n, scan_rst_n, scan_shift_n, test_clk_pll_en_n, + vcc_aibnd, vcc_io, vss_aibnd ); + +output clk_dcc, dcc_done, scan_out; + +input clk_dcd, clktree_out, dcc_dft_nrst, dcc_dft_nrst_coding, + dcc_dft_up, dcc_req, idll_entest, nfrzdrv, pipeline_global_en, + rb_cont_cal, rb_dcc_byp, rb_dcc_dft, rb_dcc_dft_sel, rb_dcc_en, + rb_half_code, rb_selflock, scan_clk_in, scan_in, scan_mode_n, + scan_rst_n, scan_shift_n, test_clk_pll_en_n, vcc_aibnd, vcc_io, + vss_aibnd; + +output [12:0] odll_dll2core; + +input [4:0] rb_dcc_manual_up; +input [4:0] rb_dcc_manual_dn; +input [51:0] csr_reg; +input [2:0] rb_clkdiv; +input [2:0] idll_core2dll; + +wire net088, nrst_coding, dcc_done, rb_dcc_byp_b, dcc_done_nonbyp, dcc_done_byp, dcc_byp_mux, csr_reg6, buf_rb_dcc_byp, buf_rb_dcc_dft_sel, odll_lock, vss_aibnd, dcc_req_mux, dcc_req, rb_dcc_dft_sel, scan_shift_n, scan_shift_n_buf, clk_dcd, clk_dcd_buf, scan_clk_in, scan_clk_in_buf, net081, net080, scan_in, scan_in_buf, scan_mode_n, scan_mode_n_buf, clk_dcd_mux, clk_buf0, scan_rst_n, scan_rst_n_buf, net96, dll_lock_mux, dccen_dccreq_mux, dccen_dccreq, dcc_req_synced_mux, dcc_req_synced, net61, buf_rb_dcc_en, reinit, nfrzdrv_nrst_b, nfrzdrv, nfrzdrv_nrst, rb_dcc_byp, rb_dcc_en_b, rb_dcc_en; // Conversion Sript Generated + +// Buses in the design + +wire [9:0] pvt_ref_half_gry; + +wire [12:0] dll2core; + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_dcc_top"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +assign nrst_coding = net088; +assign dcc_done = rb_dcc_byp_b ? dcc_done_nonbyp : dcc_done_byp; +assign dcc_byp_mux = csr_reg6 ? idll_core2dll[1] : buf_rb_dcc_byp; +assign odll_dll2core[0] = buf_rb_dcc_dft_sel ? odll_lock : dll2core[0]; +assign odll_dll2core[1] = buf_rb_dcc_dft_sel ? dcc_done : dll2core[1]; +assign odll_dll2core[2] = buf_rb_dcc_dft_sel ? vss_aibnd : dll2core[2]; +assign odll_dll2core[4] = buf_rb_dcc_dft_sel ? vss_aibnd : dll2core[4]; +assign odll_dll2core[3] = buf_rb_dcc_dft_sel ? vss_aibnd : dll2core[3]; +assign odll_dll2core[6] = buf_rb_dcc_dft_sel ? vss_aibnd : dll2core[6]; +assign odll_dll2core[5] = buf_rb_dcc_dft_sel ? vss_aibnd : dll2core[5]; +assign odll_dll2core[7] = buf_rb_dcc_dft_sel ? vss_aibnd : dll2core[7]; +assign odll_dll2core[8] = buf_rb_dcc_dft_sel ? vss_aibnd : dll2core[8]; +assign odll_dll2core[10] = buf_rb_dcc_dft_sel ? vss_aibnd : dll2core[10]; +assign odll_dll2core[9] = buf_rb_dcc_dft_sel ? vss_aibnd : dll2core[9]; +assign dcc_req_mux = csr_reg6 ? idll_core2dll[2] : dcc_req; +assign odll_dll2core[12] = buf_rb_dcc_dft_sel ? vss_aibnd : dll2core[12]; +assign odll_dll2core[11] = buf_rb_dcc_dft_sel ? vss_aibnd : dll2core[11]; +assign buf_rb_dcc_dft_sel = rb_dcc_dft_sel; +assign scan_shift_n_buf = scan_shift_n; +assign clk_dcd_buf = clk_dcd; +assign scan_clk_in_buf = scan_clk_in; +assign net080 = net081; +assign scan_in_buf = scan_in; +assign scan_mode_n_buf = scan_mode_n; +assign clk_buf0 = clk_dcd_mux; +assign scan_rst_n_buf = scan_rst_n; +assign net088 = scan_mode_n_buf ? net96 : scan_rst_n_buf; +assign dll_lock_mux = scan_mode_n_buf ? odll_lock : scan_clk_in_buf; +assign dccen_dccreq_mux = scan_mode_n_buf ? dccen_dccreq : scan_rst_n_buf; +assign dcc_req_synced_mux = scan_mode_n_buf ? dcc_req_synced : scan_rst_n_buf; +assign clk_dcd_mux = scan_mode_n_buf ? clk_dcd_buf : scan_clk_in_buf; +assign net081 = scan_mode_n_buf ? dcc_req_mux : scan_rst_n_buf; +assign net61 = !(dcc_req_mux & buf_rb_dcc_en); +assign reinit = !(dcc_req_synced & buf_rb_dcc_en); +assign nfrzdrv_nrst_b = !(nfrzdrv & buf_rb_dcc_en); +assign nfrzdrv_nrst = !nfrzdrv_nrst_b; +assign csr_reg6 = csr_reg[6]; +assign rb_dcc_byp_b = !rb_dcc_byp; +assign dccen_dccreq = !net61; +assign rb_dcc_en_b = !rb_dcc_en; +assign buf_rb_dcc_en = !rb_dcc_en_b; +assign buf_rb_dcc_byp = !rb_dcc_byp_b; +aibnd_dcc_dll xdll ( .rb_cont_cal(rb_cont_cal), .vcc_aibnd(vcc_aibnd), + .vss_aibnd(vss_aibnd), .scan_shift_n(scan_shift_n_buf), + .dcc_done(dcc_done_nonbyp), .rb_dcc_byp(dcc_byp_mux), + .clk_dcd(clk_buf0), .rb_clkdiv(rb_clkdiv[2:0]), + .pipeline_global_en(pipeline_global_en), .scan_out(scan_out), + .scan_mode_n(scan_mode_n_buf), .scan_clk_in(scan_clk_in_buf), + .scan_rst_n(scan_rst_n_buf), .scan_in(so_dcc_done), + .nfrzdrv(nfrzdrv_nrst), .clk_dcc(clk_dcc), .nrst(nrst_coding), + .odll_dll2core(dll2core[12:0]), .odll_lock(odll_lock), + .pvt_ref_half_gry(pvt_ref_half_gry[9:0]), .clk_pll(clk_buf0), + .csr_reg(csr_reg[51:0]), .idll_core2dll(idll_core2dll[2:0]), + .idll_entest(idll_entest), .rb_half_code(rb_half_code), + .rb_selflock(rb_selflock), .reinit(reinit), + .test_clk_pll_en_n(test_clk_pll_en_n)); +aibnd_2ff_scan xsync ( .d(vcc_aibnd), .clk(clk_buf0), .o(dcc_req_synced) /*`ifndef INTCNOPWR , .vcc(vcc_aibnd) `endif*/ , .rb(net080), .si(scan_in_buf) /*`ifndef INTCNOPWR , .vss(vss_aibnd) `endif*/ , .so(so_sync), .ssb(scan_shift_n_buf)); +aibnd_dcc_ff xff0 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .so(so_nrst), .se_n(scan_shift_n_buf), .q(net96), + .rb(dccen_dccreq_mux), .clk(dll_lock_mux), .si(so_sync), + .d(vcc_aibnd)); +aibnd_dcc_ff xff1 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .so(so_dcc_done), .se_n(scan_shift_n_buf), .q(dcc_done_byp), + .rb(dcc_req_synced_mux), .clk(clk_buf0), .si(so_nrst), + .d(dcc_req_synced)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_digital.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_digital.v new file mode 100644 index 0000000..05ab288 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_digital.v @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_digital, View - schematic +// LAST TIME SAVED: Dec 1 16:31:14 2014 +// NETLIST TIME: Dec 17 10:24:02 2014 + +module aibnd_digital ( clkbuf_en, datbuf_en, ndrv_sel0, ndrv_sel1, + ndrv_sel2, ndrv_sel3, odat0, odat1, pd_dataout, pdrv_sel0, + pdrv_sel1, pdrv_sel2, pdrv_sel3, rx_disable, sync_datbuf_en0, + sync_datbuf_en1, tx_dat, weak_pulld_en, weak_pullu_enb, + async_data, clkdr, iclkin_dist, idat0, idat1, idataselb, iddrctrl, + ilaunch_clk, ilpbk_dat, ilpbk_en, indrv, ipadrstb, ipdrv, irstb, + irxen, istrbclk, itx_en, rx_idat, test_weakpd, test_weakpu, + testmode_en, vccl_aibnd, vssl_aibnd ); + +output clkbuf_en, datbuf_en, ndrv_sel0, ndrv_sel1, ndrv_sel2, + ndrv_sel3, odat0, odat1, pd_dataout, pdrv_sel0, pdrv_sel1, + pdrv_sel2, pdrv_sel3, rx_disable, sync_datbuf_en0, + sync_datbuf_en1, tx_dat, weak_pulld_en, weak_pullu_enb; + +input async_data, clkdr, iclkin_dist, idat0, idat1, idataselb, + iddrctrl, ilaunch_clk, ilpbk_dat, ilpbk_en, ipadrstb, irstb, + istrbclk, itx_en, rx_idat, test_weakpd, test_weakpu, testmode_en, + vccl_aibnd, vssl_aibnd; + +input [1:0] indrv; +input [1:0] ipdrv; +input [2:0] irxen; + + + +aibnd_txdig xtxdig ( .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .ipadrstb(ipadrstb), .testmode_en(testmode_en), .clkdr(clkdr), + .ndrv_sel0b(ndrv_sel0), .test_weakpd(test_weakpd), + .test_weakpu(test_weakpu), .ndrv_sel1b(ndrv_sel1), + .ndrv_sel2b(ndrv_sel2), .ndrv_sel3b(ndrv_sel3), + .weak_pullu_enb(weak_pullu_enb), .async_data(async_data), + .weak_pulld_en(weak_pulld_en), .rx_enb(rx_disable), + .idataselb(idataselb), .iddrctrl(iddrctrl), .itx_en(itx_en), + .irstb(irstb), .ilpbk_en(ilpbk_en), .pdrv_sel0(pdrv_sel0), + .pdrv_sel1(pdrv_sel1), .pdrv_sel2(pdrv_sel2), + .pdrv_sel3(pdrv_sel3), .tx_dat_out(tx_dat), .idat0(idat0), + .idat1(idat1), .ilaunch_clk(ilaunch_clk), .ilpbk_dat(ilpbk_dat), + .indrv(indrv[1:0]), .ipdrv(ipdrv[1:0])); +aibnd_rxdig xrxdig ( .ipadrstb(ipadrstb), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd), .datbuf_en(datbuf_en), + .rx_idat_buf(pd_dataout), .rx_idat(rx_idat), + .clkbuf_en(clkbuf_en), .rx_disable(rx_disable), + .sync_datbuf_en0(sync_datbuf_en0), + .sync_datbuf_en1(sync_datbuf_en1), .irxen(irxen[2:0]), + .odat0(odat0), .odat1(odat1), .iclkin_dist(iclkin_dist), + .irstb(irstb), .istrbclk(istrbclk)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dll_custom.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dll_custom.v new file mode 100644 index 0000000..3331754 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dll_custom.v @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dll_custom, View - schematic +// LAST TIME SAVED: Mar 27 14:37:40 2015 +// NETLIST TIME: May 12 17:53:11 2015 +// `timescale 1ns / 1ns + +module aibnd_dll_custom ( clk_dcc, dcc_done, scan_out, t_down, t_up, + clk_dcd, dll_lock, dll_reset_n, f_gray, i_gray, launch, measure, + nfrzdrv, nrst, pvt_ref_half_gry, rb_cont_cal, rb_dcc_byp, + scan_clk_in, scan_in, scan_mode_n, scan_rst_n, scan_shift_n, + vcc_aibnd, vss_aibnd ); + +output clk_dcc, dcc_done, scan_out, t_down, t_up; + +input clk_dcd, dll_lock, dll_reset_n, launch, measure, nfrzdrv, nrst, + rb_cont_cal, rb_dcc_byp, scan_clk_in, scan_in, scan_mode_n, + scan_rst_n, scan_shift_n, vcc_aibnd, vss_aibnd; + +input [2:0] i_gray; +input [6:0] f_gray; +input [9:0] pvt_ref_half_gry; + +wire dll_lock_reg, rb_cont_cal, vss_aibnd, dll_lock_reg_premux, net080, scan_mode_n, net0109, scan_rst_n, net081, net075, scan_clk_in, dll_lock_reg_prebuf, dll_lock_mux, dll_reset_n_mux, clk_dcd, clk_dcd_buf; // Conversion Sript Generated + +// Buses in the design + +wire [9:0] gray; + +wire [9:0] pvt_ref_half_gry_ff; + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_dll_custom"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +assign gray[0] = dll_lock_reg ? pvt_ref_half_gry_ff[0] : i_gray[0]; +assign gray[1] = dll_lock_reg ? pvt_ref_half_gry_ff[1] : i_gray[1]; +assign dll_lock_reg = rb_cont_cal ? vss_aibnd : dll_lock_reg_premux; +assign gray[9] = dll_lock_reg ? pvt_ref_half_gry_ff[9] : f_gray[6]; +assign gray[8] = dll_lock_reg ? pvt_ref_half_gry_ff[8] : f_gray[5]; +assign gray[7] = dll_lock_reg ? pvt_ref_half_gry_ff[7] : f_gray[4]; +assign gray[6] = dll_lock_reg ? pvt_ref_half_gry_ff[6] : f_gray[3]; +assign gray[3] = dll_lock_reg ? pvt_ref_half_gry_ff[3] : f_gray[0]; +assign gray[2] = dll_lock_reg ? pvt_ref_half_gry_ff[2] : i_gray[2]; +assign gray[4] = dll_lock_reg ? pvt_ref_half_gry_ff[4] : f_gray[1]; +assign gray[5] = dll_lock_reg ? pvt_ref_half_gry_ff[5] : f_gray[2]; +aibnd_dcc_dly xdly1 ( .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkp_mindly(clkp_mindly_cont), .clkn_mindly(clkn_mindly_cont), + .clkp_dly(clkp_dly_cont), .clkn_dly(clkn_dly_cont), + .launch(vss_aibnd), .measure(vss_aibnd), .clk_dcd(clk_dcd_buf), + .nfrzdrv(nfrzdrv), .dll_lock_reg(rb_cont_cal), + .gray(pvt_ref_half_gry_ff[9:0])); +aibnd_dcc_dly xdly0 ( .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkp_mindly(clkp_mindly_1time), .clkn_mindly(clkn_mindly_1time), + .clkp_dly(clkp_dly_1time), .clkn_dly(clkn_dly_1time), + .launch(launch), .measure(measure), .clk_dcd(clk_dcd_buf), + .nfrzdrv(nfrzdrv), .dll_lock_reg(dll_lock_reg), .gray(gray[9:0])); +io_dll_phdet xdll_phdet ( //.vcc_io(vcc_aibnd), .vss_io(vss_aibnd), + .t_down(t_down), .t_up(t_up), .dll_reset_n(dll_reset_n), + .i_del_n(clkn_dly_1time), .i_del_p(clkp_dly_1time), + .phase_clk(clkp_mindly_1time), .phase_clkb(clkn_mindly_1time)); +io_dll_phdet xdll_phdet_load ( //.vcc_io(vcc_aibnd), .vss_io(vss_aibnd), + .t_down(net092), .t_up(net091), .dll_reset_n(vss_aibnd), + .i_del_n(clkn_dly_cont), .i_del_p(clkp_dly_cont), + .phase_clk(clkp_mindly_cont), .phase_clkb(clkn_mindly_cont)); +aibnd_dcc_mux gmx10 ( .clk0(clkn_dly_1time), .s(rb_cont_cal), + .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), .clkout(clkn_dly), + .clk1(clkn_dly_cont)); +aibnd_dcc_mux gmx9 ( .clk0(clkp_dly_1time), .s(rb_cont_cal), + .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), .clkout(clkp_dly), + .clk1(clkp_dly_cont)); +aibnd_dcc_mux gmx8 ( .clk0(clkn_mindly_1time), .s(rb_cont_cal), + .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .clkout(clkn_mindly), .clk1(clkn_mindly_cont)); +aibnd_dcc_mux gmx7 ( .clk0(clkp_mindly_1time), .s(rb_cont_cal), + .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .clkout(clkp_mindly), .clk1(clkp_mindly_cont)); +aibnd_dcc_mux gmx11 ( .clk0(dll_lock), .s(rb_cont_cal), + .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), .clkout(net075), + .clk1(clk_dcd)); +aibnd_dcc_mux gmx12 ( .clk0(dll_reset_n), .s(rb_cont_cal), + .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), .clkout(net0109), + .clk1(dll_lock)); +assign net080 = scan_mode_n ? net0109 : scan_rst_n; +assign net081 = scan_mode_n ? net075 : scan_clk_in; +aibnd_dcc_ff xff12 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .so(net119), .se_n(scan_shift_n), .q(net118), + .rb(dll_reset_n_mux), .clk(clk_dcd), .si(net111), .d(net112)); +aibnd_dcc_ff xff11 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .so(net111), .se_n(scan_shift_n), .q(net112), + .rb(dll_reset_n_mux), .clk(clk_dcd), .si(so0aa), + .d(dll_lock_reg_prebuf)); +aibnd_dcc_ff xff10 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .so(so0aa), .se_n(scan_shift_n), .q(dll_lock_reg_prebuf), + .rb(dll_reset_n_mux), .clk(dll_lock_mux), .si(scan_in), + .d(vcc_aibnd)); +aibnd_dcc_ff xff13 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .so(net115), .se_n(scan_shift_n), .q(net114), + .rb(dll_reset_n_mux), .clk(clk_dcd), .si(net119), .d(net118)); +aibnd_dcc_ff xff0 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .so(so0), .se_n(scan_shift_n), .si(so0a), + .q(pvt_ref_half_gry_ff[0]), .rb(dll_reset_n_mux), + .clk(dll_lock_mux), .d(pvt_ref_half_gry[0])); +aibnd_dcc_ff xff1 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .so(so1), .se_n(scan_shift_n), .si(so0), + .q(pvt_ref_half_gry_ff[1]), .rb(dll_reset_n_mux), + .clk(dll_lock_mux), .d(pvt_ref_half_gry[1])); +aibnd_dcc_ff xff2 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .so(so2), .se_n(scan_shift_n), .si(so1), + .q(pvt_ref_half_gry_ff[2]), .rb(dll_reset_n_mux), + .clk(dll_lock_mux), .d(pvt_ref_half_gry[2])); +aibnd_dcc_ff xff15 ( .vcc_aibnd(vcc_aibnd), .so(net0113), + .se_n(scan_shift_n), .q(net0112), .vss_aibnd(vss_aibnd), + .rb(dll_reset_n_mux), .clk(clk_dcd), .si(net098), .d(net097)); +aibnd_dcc_ff xff8 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .so(so8), .se_n(scan_shift_n), .si(so7), + .q(pvt_ref_half_gry_ff[8]), .rb(dll_reset_n_mux), + .clk(dll_lock_mux), .d(pvt_ref_half_gry[8])); +aibnd_dcc_ff xff4 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .so(so4), .se_n(scan_shift_n), .si(so3), + .q(pvt_ref_half_gry_ff[4]), .rb(dll_reset_n_mux), + .clk(dll_lock_mux), .d(pvt_ref_half_gry[4])); +aibnd_dcc_ff xff16 ( .vcc_aibnd(vcc_aibnd), .so(net127), + .se_n(scan_shift_n), .q(net126), .vss_aibnd(vss_aibnd), + .rb(dll_reset_n_mux), .clk(clk_dcd), .si(net0113), .d(net0112)); +aibnd_dcc_ff xff18 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .so(so0a), .se_n(scan_shift_n), .q(dcc_done), + .rb(dll_reset_n_mux), .clk(clk_dcd), .si(net0126), .d(net0108)); +aibnd_dcc_ff xff3 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .so(so3), .se_n(scan_shift_n), .si(so2), + .q(pvt_ref_half_gry_ff[3]), .rb(dll_reset_n_mux), + .clk(dll_lock_mux), .d(pvt_ref_half_gry[3])); +aibnd_dcc_ff xff17 ( .vcc_aibnd(vcc_aibnd), .so(net0126), + .se_n(scan_shift_n), .q(net0108), .vss_aibnd(vss_aibnd), + .rb(dll_reset_n_mux), .clk(clk_dcd), .si(net127), .d(net126)); +aibnd_dcc_ff xff9 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .so(scan_out), .se_n(scan_shift_n), .si(so8), + .q(pvt_ref_half_gry_ff[9]), .rb(dll_reset_n_mux), + .clk(dll_lock_mux), .d(pvt_ref_half_gry[9])); +aibnd_dcc_ff xff14 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .so(net098), .se_n(scan_shift_n), .q(net097), + .rb(dll_reset_n_mux), .clk(clk_dcd), .si(net115), .d(net114)); +aibnd_dcc_ff xff5 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .so(so5), .se_n(scan_shift_n), .si(so4), + .q(pvt_ref_half_gry_ff[5]), .rb(dll_reset_n_mux), + .clk(dll_lock_mux), .d(pvt_ref_half_gry[5])); +aibnd_dcc_ff xff6 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .so(so6), .se_n(scan_shift_n), .si(so5), + .q(pvt_ref_half_gry_ff[6]), .rb(dll_reset_n_mux), + .clk(dll_lock_mux), .d(pvt_ref_half_gry[6])); +aibnd_dcc_ff xff7 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), + .so(so7), .se_n(scan_shift_n), .si(so6), + .q(pvt_ref_half_gry_ff[7]), .rb(dll_reset_n_mux), + .clk(dll_lock_mux), .d(pvt_ref_half_gry[7])); +assign dll_lock_reg_premux = dll_lock_reg_prebuf; +assign dll_lock_mux = net081; +assign dll_reset_n_mux = net080; +assign clk_dcd_buf = clk_dcd; +aibnd_dcc_helper xdcc_helper ( .launchb(clkn_mindly), + .measureb(clkn_dly), .vcc_io(vcc_aibnd), .dcc_byp(rb_dcc_byp), + .clk_dcd(clk_dcd), .vss_io(vss_aibnd), .clkout(clk_dcc), + .launch(clkp_mindly), .measure(clkp_dly), .rstb(nrst)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dll_phdet.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dll_phdet.v new file mode 100644 index 0000000..f3a51ff --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dll_phdet.v @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dll_phdet, View - schematic +// LAST TIME SAVED: Mar 25 07:54:22 2015 +// NETLIST TIME: May 12 17:53:10 2015 +// `timescale 1ns / 1ns + +module aibnd_dll_phdet ( t_down, t_up, dll_reset_n, i_del_p, phase_clk, + vcc_io, vss_io ); + +output t_down, t_up; + +input dll_reset_n, i_del_p, phase_clk, vcc_io, vss_io; + +wire net034, t_down, net021, t_up; // Conversion Sript Generated + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_dll_phdet"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +assign t_down = net034; +assign t_up = net021; +aibnd_ff_r xsampling_dn ( .o(net034), .d(phase_clk), .clk(i_del_p) /*`ifndef INTCNOPWR , .vss(vss_io) , .vcc(vcc_io) `endif*/ , .rb(dll_reset_n)); +aibnd_ff_r xsampling_up ( .o(net021), .d(i_del_p), .clk(phase_clk) /*`ifndef INTCNOPWR , .vss(vss_io) , .vcc(vcc_io) `endif*/ , .rb(dll_reset_n)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dly_mimic.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dly_mimic.v new file mode 100644 index 0000000..b8905f1 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_dly_mimic.v @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_dly_mimic, View - schematic +// LAST TIME SAVED: Jun 16 14:16:32 2015 +// NETLIST TIME: Jun 16 14:57:46 2015 +//`timescale 1ns / 1ns + +module aibnd_dly_mimic ( ihssi_tx_data_out_dly, csr_reg6, + idll_core2dll_1, ihssi_tx_data_out, rb_dcc_byp, rb_dcc_byp_dprio, vcc_aibnd, + vss_aibnd ); + + +input csr_reg6, idll_core2dll_1, rb_dcc_byp, rb_dcc_byp_dprio, vcc_aibnd, vss_aibnd; + +output [39:0] ihssi_tx_data_out_dly; + +input [39:0] ihssi_tx_data_out; + +wire csr_reg6_buf , idll_core2dll_1_buf, dcc_byp_mux_buf, dcc_byp_mux; + +wire rb_dcc_byp_inv, rb_dcc_byp_inv_buf; +assign rb_dcc_byp_inv = ~rb_dcc_byp_dprio; + +assign csr_reg6_buf = csr_reg6; +assign rb_dcc_byp_inv_buf = rb_dcc_byp_inv; +assign idll_core2dll_1_buf = idll_core2dll_1 ; +assign dcc_byp_mux = csr_reg6_buf ? idll_core2dll_1_buf : rb_dcc_byp_inv_buf; +assign dcc_byp_mux_buf = dcc_byp_mux; + + + + +/* +specify + specparam CDS_LIBNAME = "aibnd_lib"; + specparam CDS_CELLNAME = "aibnd_dly_mimic"; + specparam CDS_VIEWNAME = "schematic"; +endspecify +*/ + +aibnd_dcc_dly_rep x19 ( .idat0(ihssi_tx_data_out[38]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[39]), + .idat1(ihssi_tx_data_out[39]), .rb_dcc_byp(dcc_byp_mux_buf), + .clkrep0(ihssi_tx_data_out_dly[38])); +aibnd_dcc_dly_rep x18 ( .idat0(ihssi_tx_data_out[36]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[37]), + .idat1(ihssi_tx_data_out[37]), .rb_dcc_byp(dcc_byp_mux_buf), + .clkrep0(ihssi_tx_data_out_dly[36])); +aibnd_dcc_dly_rep x17 ( .idat0(ihssi_tx_data_out[34]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[35]), + .idat1(ihssi_tx_data_out[35]), .rb_dcc_byp(dcc_byp_mux_buf), + .clkrep0(ihssi_tx_data_out_dly[34])); +aibnd_dcc_dly_rep x16 ( .idat0(ihssi_tx_data_out[32]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[33]), + .idat1(ihssi_tx_data_out[33]), .rb_dcc_byp(dcc_byp_mux_buf), + .clkrep0(ihssi_tx_data_out_dly[32])); +aibnd_dcc_dly_rep x15 ( .idat0(ihssi_tx_data_out[30]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[31]), + .idat1(ihssi_tx_data_out[31]), .rb_dcc_byp(dcc_byp_mux_buf), + .clkrep0(ihssi_tx_data_out_dly[30])); +aibnd_dcc_dly_rep x14 ( .idat0(ihssi_tx_data_out[28]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[29]), + .idat1(ihssi_tx_data_out[29]), .rb_dcc_byp(dcc_byp_mux_buf), + .clkrep0(ihssi_tx_data_out_dly[28])); +aibnd_dcc_dly_rep x13 ( .idat0(ihssi_tx_data_out[26]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[27]), + .idat1(ihssi_tx_data_out[27]), .rb_dcc_byp(dcc_byp_mux_buf), + .clkrep0(ihssi_tx_data_out_dly[26])); +aibnd_dcc_dly_rep x12 ( .idat0(ihssi_tx_data_out[24]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[25]), + .idat1(ihssi_tx_data_out[25]), .rb_dcc_byp(dcc_byp_mux_buf), + .clkrep0(ihssi_tx_data_out_dly[24])); +aibnd_dcc_dly_rep x11 ( .idat0(ihssi_tx_data_out[22]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[23]), + .idat1(ihssi_tx_data_out[23]), .rb_dcc_byp(dcc_byp_mux_buf), + .clkrep0(ihssi_tx_data_out_dly[22])); +aibnd_dcc_dly_rep x10 ( .idat0(ihssi_tx_data_out[20]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[21]), + .idat1(ihssi_tx_data_out[21]), .rb_dcc_byp(dcc_byp_mux_buf), + .clkrep0(ihssi_tx_data_out_dly[20])); +aibnd_dcc_dly_rep x9 ( .idat0(ihssi_tx_data_out[18]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[19]), + .idat1(ihssi_tx_data_out[19]), .rb_dcc_byp(dcc_byp_mux_buf), + .clkrep0(ihssi_tx_data_out_dly[18])); +aibnd_dcc_dly_rep x8 ( .idat0(ihssi_tx_data_out[16]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[17]), + .idat1(ihssi_tx_data_out[17]), .rb_dcc_byp(dcc_byp_mux_buf), + .clkrep0(ihssi_tx_data_out_dly[16])); +aibnd_dcc_dly_rep x7 ( .idat0(ihssi_tx_data_out[14]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[15]), + .idat1(ihssi_tx_data_out[15]), .rb_dcc_byp(dcc_byp_mux_buf), + .clkrep0(ihssi_tx_data_out_dly[14])); +aibnd_dcc_dly_rep x6 ( .idat0(ihssi_tx_data_out[12]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[13]), + .idat1(ihssi_tx_data_out[13]), .rb_dcc_byp(dcc_byp_mux_buf), + .clkrep0(ihssi_tx_data_out_dly[12])); +aibnd_dcc_dly_rep x5 ( .idat0(ihssi_tx_data_out[10]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[11]), + .idat1(ihssi_tx_data_out[11]), .rb_dcc_byp(dcc_byp_mux_buf), + .clkrep0(ihssi_tx_data_out_dly[10])); +aibnd_dcc_dly_rep x4 ( .idat0(ihssi_tx_data_out[8]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[9]), .idat1(ihssi_tx_data_out[9]), + .rb_dcc_byp(dcc_byp_mux_buf), .clkrep0(ihssi_tx_data_out_dly[8])); +aibnd_dcc_dly_rep x3 ( .idat0(ihssi_tx_data_out[6]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[7]), .idat1(ihssi_tx_data_out[7]), + .rb_dcc_byp(dcc_byp_mux_buf), .clkrep0(ihssi_tx_data_out_dly[6])); +aibnd_dcc_dly_rep x2 ( .idat0(ihssi_tx_data_out[4]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[5]), .idat1(ihssi_tx_data_out[5]), + .rb_dcc_byp(dcc_byp_mux_buf), .clkrep0(ihssi_tx_data_out_dly[4])); +aibnd_dcc_dly_rep x1 ( .idat0(ihssi_tx_data_out[2]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[3]), .idat1(ihssi_tx_data_out[3]), + .rb_dcc_byp(dcc_byp_mux_buf), .clkrep0(ihssi_tx_data_out_dly[2])); +aibnd_dcc_dly_rep x0 ( .idat0(ihssi_tx_data_out[0]), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .clkrep1(ihssi_tx_data_out_dly[1]), .idat1(ihssi_tx_data_out[1]), + .rb_dcc_byp(dcc_byp_mux_buf), .clkrep0(ihssi_tx_data_out_dly[0])); +/* +d04mbn22ld0i0 mbn17 ( .s(csr_reg6_buf), .vss(vss_aibnd), + .d2(rb_dcc_byp_buf), .o(dcc_byp_mux), .vcc(vcc_aibnd), + .d1(idll_core2dll_1_buf)); +d04bfn00wn0d5 bfn2 ( .a(csr_reg6), .o(csr_reg6_buf), .vcc(vcc_aibnd), + .vss(vss_aibnd)); +d04bfn00wn0d5 bfn1 ( .a(rb_dcc_byp), .o(rb_dcc_byp_buf), + .vcc(vcc_aibnd), .vss(vss_aibnd)); +d04bfn00wn0d5 bfn0 ( .a(idll_core2dll_1), .o(idll_core2dll_1_buf), + .vcc(vcc_aibnd), .vss(vss_aibnd)); +d04bfn00wn0d5 bf1 ( .a(dcc_byp_mux), .o(dcc_byp_mux_buf), + .vcc(vcc_aibnd), .vss(vss_aibnd)); +*/ + + +endmodule diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_ff_r.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_ff_r.v new file mode 100644 index 0000000..277eaa0 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_ff_r.v @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module aibnd_ff_r ( + input wire clk, + input wire rb, + input wire d, + //input wire vss, + //input wire vcc, + output reg o +); + +always@(posedge clk or negedge rb) begin + if (!rb) begin + o <= 1'b0; + end + else begin + o <= d; + end +end +endmodule + + + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_ff_rp.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_ff_rp.v new file mode 100644 index 0000000..73e6585 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_ff_rp.v @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module aibnd_ff_rp ( + input wire clk, + input wire rb, + input wire psb, + input wire d, + //input wire vss, + //input wire vcc, + output reg o +); + +always@(posedge clk or negedge rb or negedge psb) begin + if (!rb) begin + o <= 1'b0; + end + else if (!psb) begin + o <= 1'b1; + end + else begin + o <= d; + end +end +endmodule + + + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_fine_dly_inv.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_fine_dly_inv.v new file mode 100644 index 0000000..18241fb --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_fine_dly_inv.v @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + + +module aibnd_fine_dly_inv ( a, o1, vcc_io, vss_io ); + + input a; + output o1; + input vss_io; + input vcc_io; + + + assign o1 = ~a ; + +endmodule + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_fine_dly_x1.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_fine_dly_x1.v new file mode 100644 index 0000000..c94d79f --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_fine_dly_x1.v @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + + +module aibnd_fine_dly_x1 ( sp,sn , dout); // vcc_regphy, vss_io ); + + input sp,sn; + output dout; +// input vss_io; +// input vcc_regphy; + + + assign dout = 1'bz ; + +endmodule + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_hgy_latch.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_hgy_latch.v new file mode 100644 index 0000000..7c3b79f --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_hgy_latch.v @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module aibnd_hgy_latch ( + input wire set, + input wire preset, + input wire clk, + input wire d, + output reg q +); + +always@(*) begin + if (set && !preset) begin + q <= 0; + end + else if (!set && preset) begin + q <= 1; + end + else begin + if (clk) + q <= d; + end +end +endmodule + + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_interface.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_interface.v new file mode 100644 index 0000000..4673ce0 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_interface.v @@ -0,0 +1,699 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_interface, View - schematic +// LAST TIME SAVED: May 12 19:43:37 2015 +// NETLIST TIME: May 12 19:44:01 2015 +// `timescale 1ns / 1ns + +module aibnd_interface ( iasyncdata_out, iatpg_pipeline_global_en_out, + iatpg_scan_clk_in0_out, iatpg_scan_clk_in1_out, + iatpg_scan_in0_out, iatpg_scan_in1_out, iatpg_scan_mode_n_out, + iatpg_scan_rst_n_out, iatpg_scan_shift_n_out, + iavm1_sr_clk_out_out, iavm1in_en0_out, iavm1in_en1_out, + iavm1in_en2_out, iavm1out_dataselb_out, iavm1out_en_out, + iavm2in_en0_out, iavm2out_dataselb_out, iavm2out_en_out, + ihssi_adapter_rx_pld_rst_n_out, ihssi_adapter_tx_pld_rst_n_out, + ihssi_avmm1_data_out_out, ihssi_avmm2_data_out_out, + ihssi_dcc_dft_nrst_coding_out, ihssi_dcc_dft_nrst_out, + ihssi_dcc_dft_up_out, ihssi_dcc_dll_core2dll_str_out, + ihssi_dcc_dll_csr_reg_out, ihssi_dcc_dll_entest_out, + ihssi_dcc_req_out, ihssi_fsr_data_out_out, ihssi_fsr_load_out_out, + ihssi_pcs_rx_pld_rst_n_out, ihssi_pcs_tx_pld_rst_n_out, + ihssi_pld_pma_coreclkin_out, ihssi_pld_pma_rxpma_rstb_out, + ihssi_pld_pma_txdetectrx_out, ihssi_pld_pma_txpma_rstb_out, + ihssi_pld_sclk_out, ihssi_rb_clkdiv_out, ihssi_rb_dcc_byp_out, + ihssi_rb_dcc_dft_out, ihssi_rb_dcc_dft_sel_out, + ihssi_rb_dcc_dll_dft_sel_out, ihssi_rb_dcc_en_out, + ihssi_rb_dcc_manual_dn_out, ihssi_rb_dcc_manual_mode_out, + ihssi_rb_dcc_manual_up_out, ihssi_rb_dcc_test_clk_pll_en_n_out, + ihssi_rb_dll_test_clk_pll_en_n_out, ihssi_rb_half_code_out, + ihssi_rb_selflock_out, ihssi_ssr_data_out_out, + ihssi_ssr_load_out_out, ihssi_tx_data_in_out, + ihssi_tx_dll_lock_req_out, ihssi_tx_transfer_clk_out, + ihssirx_async_en_out, ihssirx_clk_en_out, + ihssirx_out_dataselb_out, ihssirx_out_ddren_out, + ihssirx_out_en_out, ihssitx_in_en0_out, ihssitx_in_en1_out, + ihssitx_in_en2_out, ihssitx_in_en3_out, ihssitx_out_dataselb_out, + ihssitx_out_en_out, ihssitxdll_rb_clkdiv_str_out, + ihssitxdll_rb_half_code_str_out, ihssitxdll_rb_selflock_str_out, + ihssitxdll_str_align_dly_pst_out, + ihssitxdll_str_align_dyconfig_ctl_static_out, + ihssitxdll_str_align_dyconfig_ctlsel_out, + ihssitxdll_str_align_entest_out, + ihssitxdll_str_align_stconfig_core_dn_prgmnvrt_out, + ihssitxdll_str_align_stconfig_core_up_prgmnvrt_out, + ihssitxdll_str_align_stconfig_core_updnen_out, + ihssitxdll_str_align_stconfig_dftmuxsel_out, + ihssitxdll_str_align_stconfig_dll_en_out, + ihssitxdll_str_align_stconfig_dll_rst_en_out, + ihssitxdll_str_align_stconfig_hps_ctrl_en_out, + ihssitxdll_str_align_stconfig_ndllrst_prgmnvrt_out, + ihssitxdll_str_align_stconfig_new_dll_out, + ihssitxdll_str_align_stconfig_spare_out, indrv_r12_out, + indrv_r34_out, indrv_r56_out, indrv_r78_out, ipdrv_r12_out, + ipdrv_r34_out, ipdrv_r56_out, ipdrv_r78_out, + ired_avm1_shift_en_out, ired_rshift_en_rx_avmm2_out, + ired_rshift_en_tx_avmm2_out, ired_rx_shift_en_out, irstb_out, + oatpg_scan_out0, oatpg_scan_out1, odat_async, ohssi_avmm1_data_in, + ohssi_avmm2_data_in, ohssi_fsr_data_in, ohssi_fsr_load_in, + ohssi_pld_8g_rxelecidle, ohssi_pld_pcs_rx_clk_out, + ohssi_pld_pcs_tx_clk_out, ohssi_pld_pma_clkdiv_rx_user, + ohssi_pld_pma_clkdiv_tx_user, ohssi_pld_pma_hclk, + ohssi_pld_pma_internal_clk1, ohssi_pld_pma_internal_clk2, + ohssi_pld_pma_pfdmode_lock, ohssi_pld_pma_rxpll_lock, + ohssi_pld_rx_hssi_fifo_latency_pulse, + ohssi_pld_tx_hssi_fifo_latency_pulse, ohssi_pma_aib_tx_clk, + ohssi_rx_data_out, ohssi_rx_transfer_clk, ohssi_sr_clk_in, + ohssi_sr_clk_n_in, ohssi_ssr_data_in, ohssi_ssr_load_in, + ohssi_tx_dll_lock, ohssitx_dcc_done, ohssitx_odcc_dll2core, + iasyncdata, iatpg_pipeline_global_en, iatpg_scan_clk_in0, + iatpg_scan_clk_in1, iatpg_scan_in0, iatpg_scan_in1, + iatpg_scan_mode_n, iatpg_scan_rst_n, iatpg_scan_shift_n, + iavm1_sr_clk_out, iavm1in_en0, iavm1in_en1, iavm1in_en2, + iavm1out_dataselb, iavm1out_en, iavm2in_en0, iavm2out_dataselb, + iavm2out_en, ihssi_adapter_rx_pld_rst_n, + ihssi_adapter_tx_pld_rst_n, ihssi_avmm1_data_out, + ihssi_avmm2_data_out, ihssi_dcc_dft_nrst, + ihssi_dcc_dft_nrst_coding, ihssi_dcc_dft_up, + ihssi_dcc_dll_core2dll_str, ihssi_dcc_dll_csr_reg, + ihssi_dcc_dll_entest, ihssi_dcc_req, ihssi_fsr_data_out, + ihssi_fsr_load_out, ihssi_pcs_rx_pld_rst_n, + ihssi_pcs_tx_pld_rst_n, ihssi_pld_pma_coreclkin, + ihssi_pld_pma_rxpma_rstb, ihssi_pld_pma_txdetectrx, + ihssi_pld_pma_txpma_rstb, ihssi_pld_sclk, ihssi_rb_clkdiv, + ihssi_rb_dcc_byp, ihssi_rb_dcc_dft, ihssi_rb_dcc_dft_sel, + ihssi_rb_dcc_dll_dft_sel, ihssi_rb_dcc_en, ihssi_rb_dcc_manual_dn, + ihssi_rb_dcc_manual_mode, ihssi_rb_dcc_manual_up, + ihssi_rb_dcc_test_clk_pll_en_n, ihssi_rb_dll_test_clk_pll_en_n, + ihssi_rb_half_code, ihssi_rb_selflock, ihssi_ssr_data_out, + ihssi_ssr_load_out, ihssi_tx_data_in, ihssi_tx_dll_lock_req, + ihssi_tx_transfer_clk, ihssirx_async_en, ihssirx_clk_en, + ihssirx_out_dataselb, ihssirx_out_ddren, ihssirx_out_en, + ihssitx_in_en0, ihssitx_in_en1, ihssitx_in_en2, ihssitx_in_en3, + ihssitx_out_dataselb, ihssitx_out_en, ihssitxdll_rb_clkdiv_str, + ihssitxdll_rb_half_code_str, ihssitxdll_rb_selflock_str, + ihssitxdll_str_align_dly_pst, + ihssitxdll_str_align_dyconfig_ctl_static, + ihssitxdll_str_align_dyconfig_ctlsel, ihssitxdll_str_align_entest, + ihssitxdll_str_align_stconfig_core_dn_prgmnvrt, + ihssitxdll_str_align_stconfig_core_up_prgmnvrt, + ihssitxdll_str_align_stconfig_core_updnen, + ihssitxdll_str_align_stconfig_dftmuxsel, + ihssitxdll_str_align_stconfig_dll_en, + ihssitxdll_str_align_stconfig_dll_rst_en, + ihssitxdll_str_align_stconfig_hps_ctrl_en, + ihssitxdll_str_align_stconfig_ndllrst_prgmnvrt, + ihssitxdll_str_align_stconfig_new_dll, + ihssitxdll_str_align_stconfig_spare, indrv_r12, indrv_r34, + indrv_r56, indrv_r78, ipdrv_r12, ipdrv_r34, ipdrv_r56, ipdrv_r78, + ired_avm1_shift_en, ired_rshift_en_rx_avmm2, + ired_rshift_en_tx_avmm2, ired_rx_shift_en, irstb, + oatpg_scan_out0_in, oatpg_scan_out1_in, odat_async_in, + ohssi_avmm1_data_in_in, ohssi_avmm2_data_in_in, + ohssi_fsr_data_in_in, ohssi_fsr_load_in_in, + ohssi_pld_8g_rxelecidle_in, ohssi_pld_pcs_rx_clk_out_in, + ohssi_pld_pcs_tx_clk_out_in, ohssi_pld_pma_clkdiv_rx_user_in, + ohssi_pld_pma_clkdiv_tx_user_in, ohssi_pld_pma_hclk_in, + ohssi_pld_pma_internal_clk1_in, ohssi_pld_pma_internal_clk2_in, + ohssi_pld_pma_pfdmode_lock_in, ohssi_pld_pma_rxpll_lock_in, + ohssi_pld_rx_hssi_fifo_latency_pulse_in, + ohssi_pld_tx_hssi_fifo_latency_pulse_in, ohssi_pma_aib_tx_clk_in, + ohssi_rx_data_out_in, ohssi_rx_transfer_clk_in, + ohssi_sr_clk_in_in, ohssi_sr_clk_n_in_in, ohssi_ssr_data_in_in, + ohssi_ssr_load_in_in, ohssi_tx_dll_lock_in, ohssitx_dcc_done_in, + ohssitx_odcc_dll2core_in, vccl_aibnd, vssl_aibnd ); + +output iatpg_pipeline_global_en_out, iatpg_scan_clk_in0_out, + iatpg_scan_clk_in1_out, iatpg_scan_in0_out, iatpg_scan_in1_out, + iatpg_scan_mode_n_out, iatpg_scan_rst_n_out, + iatpg_scan_shift_n_out, iavm1_sr_clk_out_out, + iavm2out_dataselb_out, iavm2out_en_out, + ihssi_adapter_rx_pld_rst_n_out, ihssi_adapter_tx_pld_rst_n_out, + ihssi_dcc_dft_nrst_coding_out, ihssi_dcc_dft_nrst_out, + ihssi_dcc_dft_up_out, ihssi_dcc_dll_entest_out, ihssi_dcc_req_out, + ihssi_fsr_data_out_out, ihssi_fsr_load_out_out, + ihssi_pcs_rx_pld_rst_n_out, ihssi_pcs_tx_pld_rst_n_out, + ihssi_pld_pma_coreclkin_out, ihssi_pld_pma_rxpma_rstb_out, + ihssi_pld_pma_txdetectrx_out, ihssi_pld_pma_txpma_rstb_out, + ihssi_pld_sclk_out, ihssi_rb_dcc_byp_out, ihssi_rb_dcc_dft_out, + ihssi_rb_dcc_dft_sel_out, ihssi_rb_dcc_dll_dft_sel_out, + ihssi_rb_dcc_en_out, ihssi_rb_dcc_manual_mode_out, + ihssi_rb_dcc_test_clk_pll_en_n_out, + ihssi_rb_dll_test_clk_pll_en_n_out, ihssi_rb_half_code_out, + ihssi_rb_selflock_out, ihssi_ssr_data_out_out, + ihssi_ssr_load_out_out, ihssi_tx_dll_lock_req_out, + ihssi_tx_transfer_clk_out, ihssirx_out_ddren_out, + ihssitxdll_rb_half_code_str_out, ihssitxdll_rb_selflock_str_out, + ihssitxdll_str_align_dyconfig_ctlsel_out, + ihssitxdll_str_align_entest_out, + ihssitxdll_str_align_stconfig_core_dn_prgmnvrt_out, + ihssitxdll_str_align_stconfig_core_up_prgmnvrt_out, + ihssitxdll_str_align_stconfig_core_updnen_out, + ihssitxdll_str_align_stconfig_dll_en_out, + ihssitxdll_str_align_stconfig_dll_rst_en_out, + ihssitxdll_str_align_stconfig_hps_ctrl_en_out, + ihssitxdll_str_align_stconfig_ndllrst_prgmnvrt_out, + ihssitxdll_str_align_stconfig_spare_out, + ired_rshift_en_rx_avmm2_out, irstb_out, oatpg_scan_out0, + oatpg_scan_out1, ohssi_avmm1_data_in, ohssi_avmm2_data_in, + ohssi_fsr_data_in, ohssi_fsr_load_in, ohssi_pld_8g_rxelecidle, + ohssi_pld_pcs_rx_clk_out, ohssi_pld_pcs_tx_clk_out, + ohssi_pld_pma_clkdiv_rx_user, ohssi_pld_pma_clkdiv_tx_user, + ohssi_pld_pma_hclk, ohssi_pld_pma_internal_clk1, + ohssi_pld_pma_internal_clk2, ohssi_pld_pma_pfdmode_lock, + ohssi_pld_pma_rxpll_lock, ohssi_pld_rx_hssi_fifo_latency_pulse, + ohssi_pld_tx_hssi_fifo_latency_pulse, ohssi_pma_aib_tx_clk, + ohssi_rx_transfer_clk, ohssi_sr_clk_in, ohssi_sr_clk_n_in, + ohssi_ssr_data_in, ohssi_ssr_load_in, ohssi_tx_dll_lock, + ohssitx_dcc_done; + +input iatpg_pipeline_global_en, iatpg_scan_clk_in0, + iatpg_scan_clk_in1, iatpg_scan_in0, iatpg_scan_in1, + iatpg_scan_mode_n, iatpg_scan_rst_n, iatpg_scan_shift_n, + iavm1_sr_clk_out, iavm2out_dataselb, iavm2out_en, + ihssi_adapter_rx_pld_rst_n, ihssi_adapter_tx_pld_rst_n, + ihssi_dcc_dft_nrst, ihssi_dcc_dft_nrst_coding, ihssi_dcc_dft_up, + ihssi_dcc_dll_entest, ihssi_dcc_req, ihssi_fsr_data_out, + ihssi_fsr_load_out, ihssi_pcs_rx_pld_rst_n, + ihssi_pcs_tx_pld_rst_n, ihssi_pld_pma_coreclkin, + ihssi_pld_pma_rxpma_rstb, ihssi_pld_pma_txdetectrx, + ihssi_pld_pma_txpma_rstb, ihssi_pld_sclk, ihssi_rb_dcc_byp, + ihssi_rb_dcc_dft, ihssi_rb_dcc_dft_sel, ihssi_rb_dcc_dll_dft_sel, + ihssi_rb_dcc_en, ihssi_rb_dcc_manual_mode, + ihssi_rb_dcc_test_clk_pll_en_n, ihssi_rb_dll_test_clk_pll_en_n, + ihssi_rb_half_code, ihssi_rb_selflock, ihssi_ssr_data_out, + ihssi_ssr_load_out, ihssi_tx_dll_lock_req, ihssi_tx_transfer_clk, + ihssirx_out_ddren, ihssitxdll_rb_half_code_str, + ihssitxdll_rb_selflock_str, ihssitxdll_str_align_dyconfig_ctlsel, + ihssitxdll_str_align_entest, + ihssitxdll_str_align_stconfig_core_dn_prgmnvrt, + ihssitxdll_str_align_stconfig_core_up_prgmnvrt, + ihssitxdll_str_align_stconfig_core_updnen, + ihssitxdll_str_align_stconfig_dll_en, + ihssitxdll_str_align_stconfig_dll_rst_en, + ihssitxdll_str_align_stconfig_hps_ctrl_en, + ihssitxdll_str_align_stconfig_ndllrst_prgmnvrt, + ihssitxdll_str_align_stconfig_spare, ired_rshift_en_rx_avmm2, + irstb, oatpg_scan_out0_in, oatpg_scan_out1_in, + ohssi_avmm1_data_in_in, ohssi_avmm2_data_in_in, + ohssi_fsr_data_in_in, ohssi_fsr_load_in_in, + ohssi_pld_8g_rxelecidle_in, ohssi_pld_pcs_rx_clk_out_in, + ohssi_pld_pcs_tx_clk_out_in, ohssi_pld_pma_clkdiv_rx_user_in, + ohssi_pld_pma_clkdiv_tx_user_in, ohssi_pld_pma_hclk_in, + ohssi_pld_pma_internal_clk1_in, ohssi_pld_pma_internal_clk2_in, + ohssi_pld_pma_pfdmode_lock_in, ohssi_pld_pma_rxpll_lock_in, + ohssi_pld_rx_hssi_fifo_latency_pulse_in, + ohssi_pld_tx_hssi_fifo_latency_pulse_in, ohssi_pma_aib_tx_clk_in, + ohssi_rx_transfer_clk_in, ohssi_sr_clk_in_in, + ohssi_sr_clk_n_in_in, ohssi_ssr_data_in_in, ohssi_ssr_load_in_in, + ohssi_tx_dll_lock_in, ohssitx_dcc_done_in, vccl_aibnd, vssl_aibnd; + +output [39:0] ohssi_rx_data_out; +output [51:0] ihssi_dcc_dll_csr_reg_out; +output [2:0] iasyncdata_out; +output [4:0] ihssi_rb_dcc_manual_up_out; +output [2:0] ihssitx_in_en3_out; +output [2:0] ihssitx_in_en2_out; +output [2:0] ihssitx_out_en_out; +output [2:0] ihssirx_clk_en_out; +output [2:0] ihssi_dcc_dll_core2dll_str_out; +output [2:0] iavm1out_dataselb_out; +output [36:0] ired_rx_shift_en_out; +output [4:0] ihssi_rb_dcc_manual_dn_out; +output [14:0] ired_avm1_shift_en_out; +output [19:0] ihssitxdll_str_align_stconfig_dftmuxsel_out; +output [1:0] ipdrv_r56_out; +output [2:0] ihssitxdll_str_align_stconfig_new_dll_out; +output [1:0] ipdrv_r12_out; +output [1:0] ihssi_avmm2_data_out_out; +output [1:0] ihssi_avmm1_data_out_out; +output [2:0] ihssirx_async_en_out; +output [1:0] indrv_r78_out; +output [3:0] ihssirx_out_en_out; +output [1:0] ired_rshift_en_tx_avmm2_out; +output [1:0] ipdrv_r34_out; +output [2:0] iavm1in_en1_out; +output [1:0] ipdrv_r78_out; +output [9:0] ihssitxdll_str_align_dly_pst_out; +output [1:0] indrv_r12_out; +output [2:0] ihssitx_in_en1_out; +output [9:0] ihssitxdll_str_align_dyconfig_ctl_static_out; +output [3:0] ihssirx_out_dataselb_out; +output [1:0] indrv_r56_out; +output [2:0] iavm1in_en2_out; +output [2:0] ihssi_rb_clkdiv_out; +output [39:0] ihssi_tx_data_in_out; +output [2:0] iavm1out_en_out; +output [2:0] iavm2in_en0_out; +output [2:0] ihssitx_in_en0_out; +output [2:0] iavm1in_en0_out; +output [1:0] indrv_r34_out; +output [12:0] ohssitx_odcc_dll2core; +output [2:0] ihssitx_out_dataselb_out; +output [4:0] odat_async; +output [2:0] ihssitxdll_rb_clkdiv_str_out; + +input [3:0] ihssirx_out_dataselb; +input [14:0] ired_avm1_shift_en; +input [12:0] ohssitx_odcc_dll2core_in; +input [2:0] ihssitxdll_rb_clkdiv_str; +input [19:0] ihssitxdll_str_align_stconfig_dftmuxsel; +input [1:0] ipdrv_r78; +input [1:0] ired_rshift_en_tx_avmm2; +input [2:0] ihssirx_clk_en; +input [2:0] ihssi_rb_clkdiv; +input [2:0] iavm1in_en1; +input [51:0] ihssi_dcc_dll_csr_reg; +input [4:0] ihssi_rb_dcc_manual_dn; +input [2:0] ihssitx_in_en2; +input [2:0] iavm1in_en2; +input [1:0] ihssi_avmm2_data_out; +input [9:0] ihssitxdll_str_align_dly_pst; +input [39:0] ohssi_rx_data_out_in; +input [1:0] ipdrv_r34; +input [3:0] ihssirx_out_en; +input [9:0] ihssitxdll_str_align_dyconfig_ctl_static; +input [1:0] indrv_r78; +input [1:0] indrv_r12; +input [2:0] ihssitx_in_en0; +input [1:0] ihssi_avmm1_data_out; +input [1:0] indrv_r34; +input [2:0] iavm2in_en0; +input [1:0] ipdrv_r12; +input [2:0] ihssitxdll_str_align_stconfig_new_dll; +input [1:0] indrv_r56; +input [2:0] ihssi_dcc_dll_core2dll_str; +input [2:0] iavm1in_en0; +input [2:0] ihssitx_out_en; +input [4:0] odat_async_in; +input [2:0] ihssitx_in_en3; +input [2:0] ihssirx_async_en; +input [36:0] ired_rx_shift_en; +input [2:0] ihssitx_out_dataselb; +input [2:0] iavm1out_en; +input [39:0] ihssi_tx_data_in; +input [4:0] ihssi_rb_dcc_manual_up; +input [2:0] ihssitx_in_en1; +input [1:0] ipdrv_r56; +input [2:0] iavm1out_dataselb; +input [2:0] iasyncdata; + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_interface"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +aibnd_rambit_buf x121[2:0] ( .sig_out(iavm2in_en0_out[2:0]), + .sig_in(iavm2in_en0[2:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x125 ( .sig_out(ired_rshift_en_rx_avmm2_out), + .sig_in(ired_rshift_en_rx_avmm2), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x122 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(iavm2out_en), + .sig_out(iavm2out_en_out)); +aibnd_rambit_buf x126[1:0] ( + .sig_out(ired_rshift_en_tx_avmm2_out[1:0]), + .sig_in(ired_rshift_en_tx_avmm2[1:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x120 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(iavm2out_dataselb), + .sig_out(iavm2out_dataselb_out)); +aibnd_rambit_buf x5[2:0] ( .sig_out(iavm1in_en0_out[2:0]), + .sig_in(iavm1in_en0[2:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x107[14:0] ( .sig_out(ired_avm1_shift_en_out[14:0]), + .sig_in(ired_avm1_shift_en[14:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x106[2:0] ( .sig_out(iavm1out_en_out[2:0]), + .sig_in(iavm1out_en[2:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x105[2:0] ( .sig_out(iavm1out_dataselb_out[2:0]), + .sig_in(iavm1out_dataselb[2:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x104[2:0] ( .sig_out(iavm1in_en2_out[2:0]), + .sig_in(iavm1in_en2[2:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x103[2:0] ( .sig_out(iavm1in_en1_out[2:0]), + .sig_in(iavm1in_en1[2:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x66[9:0] ( + .sig_out(ihssitxdll_str_align_dyconfig_ctl_static_out[9:0]), + .sig_in(ihssitxdll_str_align_dyconfig_ctl_static[9:0]), + .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x89[36:0] ( .sig_out(ired_rx_shift_en_out[36:0]), + .sig_in(ired_rx_shift_en[36:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x88[2:0] ( .sig_out(ihssitx_out_en_out[2:0]), + .sig_in(ihssitx_out_en[2:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x87[2:0] ( .sig_out(ihssitx_out_dataselb_out[2:0]), + .sig_in(ihssitx_out_dataselb[2:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x86[2:0] ( .sig_out(ihssitx_in_en3_out[2:0]), + .sig_in(ihssitx_in_en3[2:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x85[2:0] ( .sig_out(ihssitx_in_en2_out[2:0]), + .sig_in(ihssitx_in_en2[2:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x84[2:0] ( .sig_out(ihssitx_in_en1_out[2:0]), + .sig_in(ihssitx_in_en1[2:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x82 ( .sig_out(ihssi_rb_dll_test_clk_pll_en_n_out), + .sig_in(ihssi_rb_dll_test_clk_pll_en_n), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x81 ( .sig_out(ihssitxdll_rb_selflock_str_out), + .sig_in(ihssitxdll_rb_selflock_str), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x80 ( .sig_out(ihssitxdll_rb_half_code_str_out), + .sig_in(ihssitxdll_rb_half_code_str), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x83[2:0] ( .sig_out(ihssitx_in_en0_out[2:0]), + .sig_in(ihssitx_in_en0[2:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x79[2:0] ( + .sig_out(ihssitxdll_rb_clkdiv_str_out[2:0]), + .sig_in(ihssitxdll_rb_clkdiv_str[2:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x77 ( + .sig_out(ihssitxdll_str_align_stconfig_spare_out), + .sig_in(ihssitxdll_str_align_stconfig_spare), + .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x78[9:0] ( + .sig_out(ihssitxdll_str_align_dly_pst_out[9:0]), + .sig_in(ihssitxdll_str_align_dly_pst[9:0]), + .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x75 ( + .sig_out(ihssitxdll_str_align_stconfig_ndllrst_prgmnvrt_out), + .sig_in(ihssitxdll_str_align_stconfig_ndllrst_prgmnvrt), + .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x74 ( + .sig_out(ihssitxdll_str_align_stconfig_hps_ctrl_en_out), + .sig_in(ihssitxdll_str_align_stconfig_hps_ctrl_en), + .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x73 ( + .sig_out(ihssitxdll_str_align_stconfig_dll_rst_en_out), + .sig_in(ihssitxdll_str_align_stconfig_dll_rst_en), + .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x72 ( + .sig_out(ihssitxdll_str_align_stconfig_dll_en_out), + .sig_in(ihssitxdll_str_align_stconfig_dll_en), + .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x76[2:0] ( + .sig_out(ihssitxdll_str_align_stconfig_new_dll_out[2:0]), + .sig_in(ihssitxdll_str_align_stconfig_new_dll[2:0]), + .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x70 ( + .sig_out(ihssitxdll_str_align_stconfig_core_updnen_out), + .sig_in(ihssitxdll_str_align_stconfig_core_updnen), + .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x69 ( + .sig_out(ihssitxdll_str_align_stconfig_core_up_prgmnvrt_out), + .sig_in(ihssitxdll_str_align_stconfig_core_up_prgmnvrt), + .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x45 ( .sig_out(ihssi_rb_dcc_dll_dft_sel_out), + .sig_in(ihssi_rb_dcc_dll_dft_sel), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x44 ( .sig_out(ihssi_rb_dcc_test_clk_pll_en_n_out), + .sig_in(ihssi_rb_dcc_test_clk_pll_en_n), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x43 ( .sig_out(ihssi_rb_selflock_out), + .sig_in(ihssi_rb_selflock), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x42 ( .sig_out(ihssi_rb_half_code_out), + .sig_in(ihssi_rb_half_code), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x34[51:0] ( .sig_out(ihssi_dcc_dll_csr_reg_out[51:0]), + .sig_in(ihssi_dcc_dll_csr_reg[51:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x40 ( .sig_out(ihssi_rb_dcc_manual_mode_out), + .sig_in(ihssi_rb_dcc_manual_mode), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x68 ( + .sig_out(ihssitxdll_str_align_stconfig_core_dn_prgmnvrt_out), + .sig_in(ihssitxdll_str_align_stconfig_core_dn_prgmnvrt), + .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x38 ( .sig_out(ihssi_rb_dcc_en_out), + .sig_in(ihssi_rb_dcc_en), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x37 ( .sig_out(ihssi_rb_dcc_dft_sel_out), + .sig_in(ihssi_rb_dcc_dft_sel), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x36 ( .sig_out(ihssi_rb_dcc_dft_out), + .sig_in(ihssi_rb_dcc_dft), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x35 ( .sig_out(ihssi_rb_dcc_byp_out), + .sig_in(ihssi_rb_dcc_byp), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x39[4:0] ( .sig_out(ihssi_rb_dcc_manual_dn_out[4:0]), + .sig_in(ihssi_rb_dcc_manual_dn[4:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x32[3:0] ( .sig_out(ihssirx_out_en_out[3:0]), + .sig_in(ihssirx_out_en[3:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x4[2:0] ( .sig_out(ihssirx_clk_en_out[2:0]), + .sig_in(ihssirx_clk_en[2:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x31 ( .sig_out(ihssirx_out_ddren_out), + .sig_in(ihssirx_out_ddren), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x41[4:0] ( .sig_out(ihssi_rb_dcc_manual_up_out[4:0]), + .sig_in(ihssi_rb_dcc_manual_up[4:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x33[2:0] ( .sig_out(ihssi_rb_clkdiv_out[2:0]), + .sig_in(ihssi_rb_clkdiv[2:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x30[3:0] ( .sig_out(ihssirx_out_dataselb_out[3:0]), + .sig_in(ihssirx_out_dataselb[3:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x67 ( + .sig_out(ihssitxdll_str_align_dyconfig_ctlsel_out), + .sig_in(ihssitxdll_str_align_dyconfig_ctlsel), + .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x71[19:0] ( + .sig_out(ihssitxdll_str_align_stconfig_dftmuxsel_out[19:0]), + .sig_in(ihssitxdll_str_align_stconfig_dftmuxsel[19:0]), + .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd)); +aibnd_rambit_buf x29[2:0] ( .sig_out(ihssirx_async_en_out[2:0]), + .sig_in(ihssirx_async_en[2:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_signal_buf x141[4:0] ( .sig_out(odat_async[4:0]), + .sig_in(odat_async_in[4:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_signal_buf x140[2:0] ( .sig_out(iasyncdata_out[2:0]), + .sig_in(iasyncdata[2:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_signal_buf x138 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ihssi_pld_pma_rxpma_rstb), + .sig_out(ihssi_pld_pma_rxpma_rstb_out)); +aibnd_signal_buf x137 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ihssi_adapter_rx_pld_rst_n), + .sig_out(ihssi_adapter_rx_pld_rst_n_out)); +aibnd_signal_buf x136 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ihssi_pcs_rx_pld_rst_n), + .sig_out(ihssi_pcs_rx_pld_rst_n_out)); +aibnd_signal_buf x135[1:0] ( .sig_out(ipdrv_r78_out[1:0]), + .sig_in(ipdrv_r78[1:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_signal_buf x134[1:0] ( .sig_out(ipdrv_r56_out[1:0]), + .sig_in(ipdrv_r56[1:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_signal_buf x133[1:0] ( .sig_out(ipdrv_r34_out[1:0]), + .sig_in(ipdrv_r34[1:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_signal_buf x132[1:0] ( .sig_out(ipdrv_r12_out[1:0]), + .sig_in(ipdrv_r12[1:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_signal_buf x131[1:0] ( .sig_out(indrv_r78_out[1:0]), + .sig_in(indrv_r78[1:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_signal_buf x130[1:0] ( .sig_out(indrv_r56_out[1:0]), + .sig_in(indrv_r56[1:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_signal_buf x128[1:0] ( .sig_out(indrv_r12_out[1:0]), + .sig_in(indrv_r12[1:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_signal_buf x129[1:0] ( .sig_out(indrv_r34_out[1:0]), + .sig_in(indrv_r34[1:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_signal_buf x127 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(irstb), .sig_out(irstb_out)); +aibnd_signal_buf x124 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_avmm2_data_in_in), + .sig_out(ohssi_avmm2_data_in)); +aibnd_signal_buf x10[1:0] ( .sig_out(ihssi_avmm2_data_out_out[1:0]), + .sig_in(ihssi_avmm2_data_out[1:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_signal_buf x119 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_ssr_load_in_in), + .sig_out(ohssi_ssr_load_in)); +aibnd_signal_buf x118 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_ssr_data_in_in), + .sig_out(ohssi_ssr_data_in)); +aibnd_signal_buf x117 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_fsr_load_in_in), + .sig_out(ohssi_fsr_load_in)); +aibnd_signal_buf x116 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_fsr_data_in_in), + .sig_out(ohssi_fsr_data_in)); +aibnd_signal_buf x115 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_avmm1_data_in_in), + .sig_out(ohssi_avmm1_data_in)); +aibnd_signal_buf x114 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_sr_clk_n_in_in), + .sig_out(ohssi_sr_clk_n_in)); +aibnd_signal_buf x113 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_sr_clk_in_in), + .sig_out(ohssi_sr_clk_in)); +aibnd_signal_buf x112 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ihssi_ssr_load_out), + .sig_out(ihssi_ssr_load_out_out)); +aibnd_signal_buf x111 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ihssi_ssr_data_out), + .sig_out(ihssi_ssr_data_out_out)); +aibnd_signal_buf x110 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ihssi_fsr_load_out), + .sig_out(ihssi_fsr_load_out_out)); +aibnd_signal_buf x109 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ihssi_fsr_data_out), + .sig_out(ihssi_fsr_data_out_out)); +aibnd_signal_buf x108[1:0] ( .sig_out(ihssi_avmm1_data_out_out[1:0]), + .sig_in(ihssi_avmm1_data_out[1:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_signal_buf x102 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(oatpg_scan_out0_in), + .sig_out(oatpg_scan_out0)); +aibnd_signal_buf x92 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ihssi_tx_dll_lock_req), + .sig_out(ihssi_tx_dll_lock_req_out)); +aibnd_signal_buf x54[39:0] ( .sig_out(ohssi_rx_data_out[39:0]), + .sig_in(ohssi_rx_data_out_in[39:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_signal_buf x28[12:0] ( .sig_out(ohssitx_odcc_dll2core[12:0]), + .sig_in(ohssitx_odcc_dll2core_in[12:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_signal_buf x96 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(iatpg_scan_rst_n), + .sig_out(iatpg_scan_rst_n_out)); +aibnd_signal_buf x99 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(iatpg_scan_mode_n), + .sig_out(iatpg_scan_mode_n_out)); +aibnd_signal_buf x100 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(oatpg_scan_out1_in), + .sig_out(oatpg_scan_out1)); +aibnd_signal_buf x47 ( .sig_out(iatpg_scan_shift_n_out), + .sig_in(iatpg_scan_shift_n), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_signal_buf x95 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(iatpg_pipeline_global_en), + .sig_out(iatpg_pipeline_global_en_out)); +aibnd_signal_buf x20[2:0] ( + .sig_out(ihssi_dcc_dll_core2dll_str_out[2:0]), + .sig_in(ihssi_dcc_dll_core2dll_str[2:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_signal_buf x27 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssitx_dcc_done_in), + .sig_out(ohssitx_dcc_done)); +aibnd_signal_buf x26 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_pld_pcs_tx_clk_out_in), + .sig_out(ohssi_pld_pcs_tx_clk_out)); +aibnd_signal_buf x25 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_pma_aib_tx_clk_in), + .sig_out(ohssi_pma_aib_tx_clk)); +aibnd_signal_buf x24 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), + .sig_in(ohssi_pld_tx_hssi_fifo_latency_pulse_in), + .sig_out(ohssi_pld_tx_hssi_fifo_latency_pulse)); +aibnd_signal_buf x23 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_pld_pma_pfdmode_lock_in), + .sig_out(ohssi_pld_pma_pfdmode_lock)); +aibnd_signal_buf x21 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ihssi_dcc_dll_entest), + .sig_out(ihssi_dcc_dll_entest_out)); +aibnd_signal_buf x19 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ihssi_dcc_req), + .sig_out(ihssi_dcc_req_out)); +aibnd_signal_buf x18 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ihssi_dcc_dft_up), + .sig_out(ihssi_dcc_dft_up_out)); +aibnd_signal_buf x17 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ihssi_dcc_dft_nrst_coding), + .sig_out(ihssi_dcc_dft_nrst_coding_out)); +aibnd_signal_buf x63 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), + .sig_in(ohssi_pld_rx_hssi_fifo_latency_pulse_in), + .sig_out(ohssi_pld_rx_hssi_fifo_latency_pulse)); +aibnd_signal_buf x62 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_pld_pma_rxpll_lock_in), + .sig_out(ohssi_pld_pma_rxpll_lock)); +aibnd_signal_buf x61 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_pld_8g_rxelecidle_in), + .sig_out(ohssi_pld_8g_rxelecidle)); +aibnd_signal_buf x60 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_pld_pma_hclk_in), + .sig_out(ohssi_pld_pma_hclk)); +aibnd_signal_buf x59 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_pld_pma_internal_clk2_in), + .sig_out(ohssi_pld_pma_internal_clk2)); +aibnd_signal_buf x58 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_pld_pma_internal_clk1_in), + .sig_out(ohssi_pld_pma_internal_clk1)); +aibnd_signal_buf x57 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_pld_pma_clkdiv_rx_user_in), + .sig_out(ohssi_pld_pma_clkdiv_rx_user)); +aibnd_signal_buf x56 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_pld_pcs_rx_clk_out_in), + .sig_out(ohssi_pld_pcs_rx_clk_out)); +aibnd_signal_buf x55 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_rx_transfer_clk_in), + .sig_out(ohssi_rx_transfer_clk)); +aibnd_signal_buf x101 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_tx_dll_lock_in), + .sig_out(ohssi_tx_dll_lock)); +aibnd_signal_buf x8 ( .sig_out(ihssitxdll_str_align_entest_out), + .sig_in(ihssitxdll_str_align_entest), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_signal_buf x16 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ihssi_dcc_dft_nrst), + .sig_out(ihssi_dcc_dft_nrst_out)); +aibnd_signal_buf x22 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ohssi_pld_pma_clkdiv_tx_user_in), + .sig_out(ohssi_pld_pma_clkdiv_tx_user)); +aibnd_signal_buf x13 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ihssi_pld_pma_txpma_rstb), + .sig_out(ihssi_pld_pma_txpma_rstb_out)); +aibnd_signal_buf x12 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ihssi_pld_pma_txdetectrx), + .sig_out(ihssi_pld_pma_txdetectrx_out)); +aibnd_signal_buf x11 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .sig_in(ihssi_pcs_tx_pld_rst_n), + .sig_out(ihssi_pcs_tx_pld_rst_n_out)); +aibnd_signal_buf x1 ( .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .sig_in(ihssi_adapter_tx_pld_rst_n), + .sig_out(ihssi_adapter_tx_pld_rst_n_out)); +aibnd_data_buf x139 ( .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .sig_in(ihssi_pld_sclk), .sig_out(ihssi_pld_sclk_out)); +aibnd_data_buf x6 ( .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .sig_in(iavm1_sr_clk_out), .sig_out(iavm1_sr_clk_out_out)); +aibnd_data_buf x94 ( .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .sig_in(iatpg_scan_in0), .sig_out(iatpg_scan_in0_out)); +aibnd_data_buf x93 ( .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .sig_in(iatpg_scan_clk_in0), .sig_out(iatpg_scan_clk_in0_out)); +aibnd_data_buf x97 ( .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .sig_in(iatpg_scan_clk_in1), .sig_out(iatpg_scan_clk_in1_out)); +aibnd_data_buf x98 ( .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .sig_in(iatpg_scan_in1), .sig_out(iatpg_scan_in1_out)); +aibnd_data_buf x14[39:0] ( .sig_out(ihssi_tx_data_in_out[39:0]), + .sig_in(ihssi_tx_data_in[39:0]), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd)); +aibnd_data_buf x7 ( .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .sig_in(ihssi_pld_pma_coreclkin), + .sig_out(ihssi_pld_pma_coreclkin_out)); +aibnd_data_buf x15 ( .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .sig_in(ihssi_tx_transfer_clk), + .sig_out(ihssi_tx_transfer_clk_out)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_inv.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_inv.v new file mode 100644 index 0000000..3c0d3d1 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_inv.v @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Verilog HDL and netlist files of +// "aibnd_lib aibnd_inv schematic" + +// Netlisted models + +// Library - aibnd_lib, Cell - aibnd_inv, View - schematic +// LAST TIME SAVED: Apr 22 17:45:05 2015 +// NETLIST TIME: May 11 08:38:23 2015 +//`timescale 1ns / 1ns + +module aibnd_inv ( clkout, clk, vccl_aibnd, vssl_aibnd ); + +output clkout; + +input clk, vccl_aibnd, vssl_aibnd; + +// List of primary aliased buses + +/* +specify + specparam CDS_LIBNAME = "aibnd_lib"; + specparam CDS_CELLNAME = "aibnd_inv"; + specparam CDS_VIEWNAME = "schematic"; +endspecify +*/ + +assign clkout = ~clk ; + +endmodule + + +// End HDL models + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_inv_split_align.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_inv_split_align.v new file mode 100644 index 0000000..7a3d049 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_inv_split_align.v @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + + +module aibnd_inv_split_align ( din, dout, vccl, vssl ); + + input din; + output dout; + input vssl; + input vccl; + + + assign dout = ~din ; + +endmodule + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_io_dly_interpolator_rep.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_io_dly_interpolator_rep.v new file mode 100644 index 0000000..167ca36 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_io_dly_interpolator_rep.v @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// io_dly_interpolator +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module aibnd_io_dly_interpolator_rep ( +input nfrzdrv, +input fout_p, +input fout_n, +input [2:0] gray, +output out_p, +output out_n, +output osc_out_p, +output osc_out_n +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter NAND_DELAY = 20; + +wire a_in_p; +wire b_in_p; +wire c_in_p; +wire a_in_n; +wire b_in_n; +wire c_in_n; +wire out_pb; +wire out_nb; +wire x_p; +wire x_n; +wire x_pb; +wire x_nb; +wire [6:0] sn; +reg [6:0] sp; + +io_dly_interpclk xio_dly_interpclk ( +.nfrzdrv (nfrzdrv ), +.fout_p (fout_p ), +.fout_n (fout_n ), +.a_in_p (a_in_p ), +.b_in_p (b_in_p ), +.c_in_p (c_in_p ), +.a_in_n (a_in_n ), +.b_in_n (b_in_n ), +.c_in_n (c_in_n ) +); + +always @(*) + case (gray[2:0]) + 3'b000 : sp[6:0] = 7'b000_0000; + 3'b001 : sp[6:0] = 7'b000_0001; + 3'b011 : sp[6:0] = 7'b000_0011; + 3'b010 : sp[6:0] = 7'b000_0111; + 3'b110 : sp[6:0] = 7'b000_1111; + 3'b111 : sp[6:0] = 7'b001_1111; + 3'b101 : sp[6:0] = 7'b011_1111; + 3'b100 : sp[6:0] = 7'b111_1111; + endcase + +assign sn[6:0] = ~sp[6:0]; + +io_ip8phs_3in xio_ip8phs_3in_n ( +.a_in ( a_in_n ), +.b_in ( b_in_n ), +.c_in ( c_in_n ), +.svcc ( 1'b1 ), +.sp ( sp[6:0] ), +.sn ( sn[6:0] ), +.clk_outb ( out_nb ) +); + +io_ip8phs_3in xio_ip8phs_3in_p ( +.a_in ( a_in_p ), +.b_in ( b_in_p ), +.c_in ( c_in_p ), +.svcc ( 1'b1 ), +.sp ( sp[6:0] ), +.sn ( sn[6:0] ), +.clk_outb ( out_pb ) +); + +assign x_p = ~out_pb; +assign x_n = ~out_nb; +//cross couple +assign x_pb = ~x_p; +assign x_nb = ~x_n; +assign out_p = ~x_pb; +assign out_n = ~x_nb; +assign osc_out_p = ~x_pb; +assign osc_out_n = ~x_nb; + +/* +`ifdef LEC +assign x_p = ~x_n; +assign x_n = ~x_p; +`endif +*/ + +endmodule + + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_io_nand_delay_line_min_rep.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_io_nand_delay_line_min_rep.v new file mode 100644 index 0000000..c35fa20 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_io_nand_delay_line_min_rep.v @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// io_nand_delay_line_min +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module aibnd_io_nand_delay_line_min_rep( +input nfrzdrv, +input in_p, +input in_n, +output out_p, +output out_n +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter NAND_DELAY = 20; + +wire fout_p; +wire fout_n; +wire osc_out_p; +wire osc_out_n; + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// +//--------------------------------------------------------------------------------------------------------------------------------------------- + +io_cmos_nand_x1 xnandx1 ( +.in_p ( in_p ), +.in_n ( in_n ), +.bk ( 1'b0 ), +.ci_p ( 1'b1 ), +.ci_n ( 1'b1 ), +.out_p ( fout_p ), +.out_n ( fout_n ), +.co_p ( ), +.co_n ( ) +); + +aibnd_io_dly_interpolator_rep xinterp ( +.nfrzdrv ( nfrzdrv ), +.fout_p ( fout_p ), +.fout_n ( fout_n ), +.gray ( 3'b000 ), +.out_p ( out_p ), +.out_n ( out_n ), +.osc_out_p ( osc_out_p ), +.osc_out_n ( osc_out_n ) +); + +endmodule + + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_jtag_bscan.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_jtag_bscan.v new file mode 100644 index 0000000..f43392a --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_jtag_bscan.v @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + + +module aibnd_jtag_bscan ( + input odat0_aib, //sync data0 RX from AIB + input odat1_aib, //sync data1 RX from AIB + input odat_asyn_aib, //async data RX from AIB + input oclk_aib, //diff clk RX from AIB + input itxen_adap, //OE TX from HSSI Adapter + input idat0_adap, //SDR dat0 TX from HSSI Adapter + input idat1_adap, //SDR dat1 TX from HSSI Adapter + input async_data_adap, //async data TX from HSSI Adapter + input jtag_tx_scanen_in, //JTAG shift DR, active high + input jtag_rx_scanen_in, //JTAG shift DR, active high + input jtag_clkdr_in, //JTAG boundary scan clock + input jtag_tx_scan_in, //JTAG TX data scan in + input jtag_rx_scan_in, //JTAG TX data scan in + input jtag_mode_in, //JTAG mode select + input last_bs_in, //scan-out loopback feedthru back to SSM + input anlg_rstb_adap, //IRSTB from Adaptor + input dig_rstb_adap, //IRSTB from Adaptor + input jtag_rstb_en, //reset_en from TAP + input jtag_rstb, //reset signal from TAP + + output jtag_clkdr_out, //CLKDR to remaining BSR + output jtag_tx_scan_out, //JTAG TX scan chain output + output jtag_rx_scan_out, //JTAG TX scan chain output +// output jtag_tx_scanen_out, +// output jtag_rx_scanen_out, + output odat0_adap, //sync data0 RX to HSSI Adapter + output odat1_adap, //sync data1 RX to HSSI Adapter + output oclk_adap, //sync data1 RX to HSSI Adapter + output odat_asyn_adap, //async data RX to HSSI Adapter + output itxen_aib, //OE TX to AIB + output idat0_aib, //SDR dat0 TX to AIB + output idat1_aib, //SDR dat1 TX to AIB + output async_data_aib, //async data TX to AIB + output anlg_rstb_aib, //irstb to AIB + output dig_rstb_aib, //irstb to AIB +// output tx_clk, +// output rx_clk, + output last_bs_out //scan-out loopback feedthru back to SSM +// output weakpu, //Weak Pull-up control for leakage test to AIB +// output weakpdn //Weak Pull-down control for leakage test to AIB +// output jtag_bsdout //Replaced with separate TX and RX Scan out + +); + +reg [3:0] tx_reg; +reg [3:0] rx_reg; +reg tx_nreg; +reg rx_nreg; +//wire tx_clk; +//wire tx_clk; +wire [3:0] tx_shift; +wire [3:0] rx_shift; + +assign jtag_rx_scan_out = rx_nreg; +assign jtag_tx_scan_out = tx_nreg; +assign idat0_aib = (jtag_mode_in)? tx_reg[3] : idat0_adap; +assign idat1_aib = (jtag_mode_in)? tx_reg[2] : idat1_adap; +assign async_data_aib = (jtag_mode_in)? tx_reg[1] : async_data_adap; +assign itxen_aib = (jtag_mode_in)? tx_reg[0] : itxen_adap; +assign odat0_adap = odat0_aib; +assign odat1_adap = odat1_aib; +assign oclk_adap = oclk_aib; +assign odat_asyn_adap = odat_asyn_aib; +assign last_bs_out = last_bs_in; +//assign jtag_tx_scanen_out = jtag_tx_scanen_in; +//assign jtag_rx_scanen_out = jtag_rx_scanen_in; +assign anlg_rstb_aib = (jtag_rstb_en)? jtag_rstb : anlg_rstb_adap; +assign dig_rstb_aib = (jtag_rstb_en)? jtag_rstb : dig_rstb_adap; +//assign jtag_loopbacken_out = jtag_loopbacken_in; +//assign jtag_mode_out = jtag_mode_in; + +assign jtag_clkdr_out = jtag_clkdr_in; + +//assign tx_clk = ( burst_en )? pma_ref_clk : jtag_clkdr_in; //Need to force tools to use CKMUX for this CLK Muxing to prevent glitch +//assign rx_clk = ( jtag_loopbacken_in )? tx_clk : istrbclk_aib; //Need to force tools to use CKMUX for this CLK Muxing to prevent glitch +//assign ilaunch_clk_aib = ( jtag_mode_in )? tx_clk : ilaunch_clk_adap; //Need to force tools to use CKMUX for this CLK Muxing to prevent glitch + +assign tx_shift = (jtag_tx_scanen_in) ? {jtag_tx_scan_in,tx_reg[3:1]} : tx_reg; + +//always @( posedge tx_clk ) +always @( posedge jtag_clkdr_in ) +begin + tx_reg <= #1 tx_shift; +end + +//always @( negedge tx_clk ) +always @( negedge jtag_clkdr_in ) +begin + tx_nreg <= tx_reg[0]; +end + +assign rx_shift = (jtag_rx_scanen_in) ? {jtag_rx_scan_in,rx_reg[3:1]} : {odat0_aib,odat1_aib,oclk_aib,odat_asyn_aib}; + +//always @( posedge rx_clk ) +always @( posedge jtag_clkdr_in ) +begin + rx_reg <= rx_shift; +end + +//always @ ( negedge rx_clk ) +always @ ( negedge jtag_clkdr_in ) +begin + rx_nreg <= rx_reg[0]; +end + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_latch.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_latch.v new file mode 100644 index 0000000..8476fb7 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_latch.v @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module aibnd_latch ( + input wire clk, + input wire rb, + //input wire vcc, + //input wire vss, + input wire d, + output reg o +); + +always@(*) begin + if (!rb) begin + o <= 0; + end + else begin + if (clk) + o <= d; + end +end +endmodule + + + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_nand2.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_nand2.v new file mode 100644 index 0000000..f245746 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_nand2.v @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Verilog HDL and netlist files of +// "aibnd_lib aibnd_nand2 schematic" + +// Netlisted models + +// Library - aibnd_lib, Cell - aibnd_nand2, View - schematic +// LAST TIME SAVED: May 4 08:41:42 2015 +// NETLIST TIME: May 11 08:41:16 2015 +//`timescale 1ns / 1ns + +module aibnd_nand2 ( clkout, clk, en, vccl_aibnd, vssl_aibnd ); + +output clkout; + +input clk, en, vccl_aibnd, vssl_aibnd; + +// List of primary aliased buses + +/* +specify + specparam CDS_LIBNAME = "aibnd_lib"; + specparam CDS_CELLNAME = "aibnd_nand2"; + specparam CDS_VIEWNAME = "schematic"; +endspecify +*/ + +assign clkout = ~(clk & en) ; + + + +endmodule + + +// End HDL models + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_nand_x128_delay_line.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_nand_x128_delay_line.v new file mode 100644 index 0000000..06c88c3 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_nand_x128_delay_line.v @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_nand_x128_delay_line, View - +//schematic +// LAST TIME SAVED: Nov 11 07:23:04 2014 +// NETLIST TIME: Dec 17 10:24:03 2014 + +module aibnd_nand_x128_delay_line ( out_p, vcc_io, vcc_regphy, vss_io, + f_gray, i_gray, in_p ); + +output out_p; + +inout vcc_io, vcc_regphy, vss_io; + +input in_p; + +input [2:0] i_gray; +input [6:0] f_gray; + + + +aibnd_cmos_nand_x128 xnand128 ( .vcc_io(vcc_io), + .vcc_regphy(vcc_regphy), .vss_io(vss_io), .out_p(fout_p), + .in_p(in_p), .gray(f_gray[6:0])); +aibnd_cmos_fine_dly xfine ( //.vcc_io(vcc_io), .vss_io(vss_io), + .gray(i_gray[2:0]), .out_p(out_p), .fout_p(fout_p) + //.vcc_regphy(vcc_regphy) + ); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_nand_x64_delay_line.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_nand_x64_delay_line.v new file mode 100644 index 0000000..d0dbd5f --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_nand_x64_delay_line.v @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_nand_x64_delay_line, View - +//schematic +// LAST TIME SAVED: Mar 26 07:33:47 2015 +// NETLIST TIME: May 12 17:53:10 2015 +// `timescale 1ns / 1ns + +module aibnd_nand_x64_delay_line ( out_p, so, code_valid, dll_reset_n, + f_gray, i_gray, in_p, scan_rst_n, sck_in, se_n, si, sm_n, + vcc_aibnd, vcc_io, vss_aibnd ); + +output out_p, so; + +input code_valid, dll_reset_n, in_p, scan_rst_n, sck_in, se_n, si, + sm_n, vcc_aibnd, vcc_io, vss_aibnd; + +input [2:0] i_gray; +input [6:0] f_gray; + +wire clk_buf0, clk_buf1, clk_prebuf, sm_n_buf, out_p, sck_in, nrst_mux, dll_reset_n, scan_rst_n, code_valid_sync, code_valid_buf, nrst, ck, se_n, se_n_buf, sm_n; // Conversion Sript Generated + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_nand_x64_delay_line"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +assign clk_buf1 = clk_buf0; +assign clk_buf0 = clk_prebuf; +assign clk_prebuf = sm_n_buf ? out_p : sck_in; +assign nrst_mux = sm_n_buf ? dll_reset_n : scan_rst_n; +aibnd_sync_ff xsync ( .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .so(so_sync), .se_n(se_n_buf), .q(code_valid_sync), .rb(nrst), + .clk(ck), .si(si), .d(code_valid)); +aibnd_cmos_nand_x64 xcoarse ( .vss_aibnd(vss_aibnd), + .vcc_aibnd(vcc_aibnd), .code_valid(code_valid_buf), .nrst(nrst), + .ck(ck), .so(so_nand_x64), .se_n(se_n_buf), .si(so_sync), + .vcc_io(vcc_io), .out_p(fout_p), .in_p(in_p), .gray(f_gray[6:0])); +assign code_valid_buf = code_valid_sync; +assign nrst = nrst_mux; +assign ck = clk_buf1; +assign se_n_buf = se_n; +assign sm_n_buf = sm_n; +aibnd_cmos_fine_dly xfine (.vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), .vcc_io(vcc_io), + .code_valid(code_valid_buf), .so(so), + .ck(ck), .nrst(nrst), .se_n(se_n_buf), .si(so_nand_x64), + .gray(i_gray[2:0]), .out_p(out_p), + .fout_p(fout_p)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_nor2.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_nor2.v new file mode 100644 index 0000000..2254487 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_nor2.v @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Verilog HDL and netlist files of +// "aibnd_lib aibnd_nor2 schematic" + +// Netlisted models + +// Library - aibnd_lib, Cell - aibnd_nor2, View - schematic +// LAST TIME SAVED: May 4 15:13:02 2015 +// NETLIST TIME: May 11 08:42:44 2015 +//`timescale 1ns / 1ns + +module aibnd_nor2 ( clkout, clk, en, vccl_aibnd, vssl_aibnd ); + +output clkout; + +input clk, en, vccl_aibnd, vssl_aibnd; + +// List of primary aliased buses + +/* +specify + specparam CDS_LIBNAME = "aibnd_lib"; + specparam CDS_CELLNAME = "aibnd_nor2"; + specparam CDS_VIEWNAME = "schematic"; +endspecify +*/ + +assign clkout = ~( clk | en ) ; + +endmodule + + +// End HDL models + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_preclkbuf.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_preclkbuf.v new file mode 100644 index 0000000..2d648f1 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_preclkbuf.v @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_preclkbuf, View - schematic +// LAST TIME SAVED: Nov 27 15:01:54 2014 +// NETLIST TIME: Dec 17 10:24:03 2014 + +module aibnd_preclkbuf ( clkout, vccl, vssl, clkin ); + +output clkout; + +inout vccl, vssl; + +input clkin; + +wire clkin, clkout; // Conversion Sript Generated + + + +assign clkout = !clkin; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_quadph_code_gen.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_quadph_code_gen.v new file mode 100644 index 0000000..a6e6ed0 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_quadph_code_gen.v @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #6 $ +// Date: $DateTime: 2015/07/27 23:57:02 $ +//------------------------------------------------------------------------ +// Description: quadrature phase delay code generation logics +//------------------------------------------------------------------------ + +//------------------------------------------------------------------------ +// To be considered : +// 1. any potential glitch between code switching? +//------------------------------------------------------------------------ +module aibnd_quadph_code_gen +#( +parameter FF_DELAY = 200 +) +( + input wire clk, //reference clock from pll + input wire reset_n, //output for dll reset + input wire [9:0] pvt_ref_binary, //output binary pvt value for delay chain + input wire rb_quad_code, //select between original or quadrature codes + output reg [9:0] pvt_ref_quad_binary //quadrature code (binary) for delay chain +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +wire [6:0] coarse_bin; +reg [2:0] fint_bin; +wire [2:0] fine_bin; + +reg [8:0] coarse_divided_bin; +reg [4:0] fine_divided_bin, coarse_frac_bin; + + always @(*) + begin + if(~reset_n) begin + coarse_divided_bin = 9'b0_0000_0000; + fine_divided_bin = 5'b0_0000; + coarse_frac_bin = 5'b0_0000; + fint_bin = 3'b000; + end + else begin + coarse_divided_bin = {2'b00,pvt_ref_binary[9:3]}; + fine_divided_bin = {2'b00,pvt_ref_binary[2:0]}; +// coarse_frac_bin = {1'b0,coarse_divided_bin[1:0],2'b00}; //****need to finalize what's the ratio between coarse/fine steps. current coding assumes 20ps/5ps=4 + coarse_frac_bin = {coarse_divided_bin[1:0],3'b000}; + fint_bin = coarse_frac_bin[4:2] + fine_divided_bin[4:2]; + if ((fine_divided_bin[1:0] >= 2'd2)) begin + fint_bin = fint_bin + 3'b001; + end + else begin + fint_bin = fint_bin; + end + end + end + + assign coarse_bin = coarse_divided_bin[8:2]; + assign fine_bin = fint_bin; + + always @(posedge clk or negedge reset_n) + begin + if(~reset_n) begin + pvt_ref_quad_binary <= #FF_DELAY 10'b00_0000_0000; + end + else case (rb_quad_code) + 1'b0 : pvt_ref_quad_binary <= #FF_DELAY pvt_ref_binary; + 1'b1 : pvt_ref_quad_binary <= #FF_DELAY {coarse_bin,fine_bin}; + default : pvt_ref_quad_binary <= #FF_DELAY {coarse_bin,fine_bin}; + endcase + end + +endmodule // aibnd_quadph_code_gen + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_rambit_buf.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_rambit_buf.v new file mode 100644 index 0000000..e9df3e5 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_rambit_buf.v @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_rambit_buf, View - schematic +// LAST TIME SAVED: Apr 19 23:56:59 2015 +// NETLIST TIME: May 12 17:53:11 2015 +// `timescale 1ns / 1ns + +module aibnd_rambit_buf ( sig_out, sig_in, vccl_aibnd, vssl_aibnd ); + +output sig_out; + +input sig_in, vccl_aibnd, vssl_aibnd; + +wire sig_out, sig_in; // Conversion Sript Generated + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_rambit_buf"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +assign sig_out = sig_in; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_clkmux2.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_clkmux2.v new file mode 100644 index 0000000..e8b630f --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_clkmux2.v @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_red_clkmux2, View - schematic +// LAST TIME SAVED: Apr 27 12:38:24 2015 +// NETLIST TIME: May 11 08:44:04 2015 +//`timescale 1ns / 1ns + +module aibnd_red_clkmux2 ( clkout, clk1, clk2, s, vccl_aibnd, + vssl_aibnd ); + +output clkout; + +input clk1, clk2, s, vccl_aibnd, vssl_aibnd; + +// List of primary aliased buses + +/* +specify + specparam CDS_LIBNAME = "aibnd_lib"; + specparam CDS_CELLNAME = "aibnd_red_clkmux2"; + specparam CDS_VIEWNAME = "schematic"; +endspecify +*/ + +assign clkout = s ? clk1 : clk2 ; + + +endmodule + + +// End HDL models + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_clkmux3.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_clkmux3.v new file mode 100644 index 0000000..533e228 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_clkmux3.v @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_red_clkmux3, View - schematic +// LAST TIME SAVED: Apr 22 13:17:46 2015 +// NETLIST TIME: May 11 08:48:38 2015 +//`timescale 1ns / 1ns + +module aibnd_red_clkmux3 ( clkout, clk1, clk2, clk3, s1, s2, s3, + vccl_aibnd, vssl_aibnd ); + +output clkout; + +input clk1, clk2, clk3, s1, s2, s3, vccl_aibnd, vssl_aibnd; + +reg clkout; + +// List of primary aliased buses + +/* +specify + specparam CDS_LIBNAME = "aibnd_lib"; + specparam CDS_CELLNAME = "aibnd_red_clkmux3"; + specparam CDS_VIEWNAME = "schematic"; +endspecify +*/ + +always @ ( s1 or s2 or s3 or clk1 or clk2 or clk3 ) + case ( {s3,s2,s1} ) + 3'b001 : clkout = clk1 ; + 3'b010 : clkout = clk2 ; + 3'b100 : clkout = clk3 ; + default : clkout = 1'bx ; + endcase +endmodule + + +// End HDL models + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_custom_dig.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_custom_dig.v new file mode 100644 index 0000000..e84ac3e --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_custom_dig.v @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_red_custom_dig, View - schematic +// LAST TIME SAVED: Apr 22 15:41:59 2015 +// NETLIST TIME: May 12 17:53:10 2015 +// `timescale 1ns / 1ns + +module aibnd_red_custom_dig ( anlg_rstb_out, anlg_rstb, + prev_io_shift_en, shift_en, vccl_aibnd, vssl_aibnd ); + +output anlg_rstb_out; + +input anlg_rstb, prev_io_shift_en, shift_en, vccl_aibnd, vssl_aibnd; + +wire anlg_rstb_out, io_disable_b, anlg_rstb, prev_io_shenb, shift_en, prev_io_shift_en; // Conversion Sript Generated + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_red_custom_dig"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +assign anlg_rstb_out = io_disable_b & anlg_rstb; +assign io_disable_b = !(prev_io_shenb & shift_en); +assign prev_io_shenb = !prev_io_shift_en; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_custom_dig2.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_custom_dig2.v new file mode 100644 index 0000000..4c425dc --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_custom_dig2.v @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_red_custom_dig2, View - schematic +// LAST TIME SAVED: Apr 22 17:47:49 2015 +// NETLIST TIME: May 12 17:53:10 2015 +// `timescale 1ns / 1ns + +module aibnd_red_custom_dig2 ( iclkin_dist_aib, ilaunch_clk_aib, + istrbclk_aib, oclk_out, oclkb_out, clkdr_in, iclkin_dist_in0, + iclkin_dist_in1, ilaunch_clk_in0, ilaunch_clk_in1, istrbclk_in0, + istrbclk_in1, jtag_clksel, oclk_aib, oclk_in1, oclkb_aib, + oclkb_in1, shift_en, vccl_aibnd, vssl_aibnd ); + +output iclkin_dist_aib, ilaunch_clk_aib, istrbclk_aib, oclk_out, + oclkb_out; + +input clkdr_in, iclkin_dist_in0, iclkin_dist_in1, ilaunch_clk_in0, + ilaunch_clk_in1, istrbclk_in0, istrbclk_in1, jtag_clksel, + oclk_aib, oclk_in1, oclkb_aib, oclkb_in1, shift_en, vccl_aibnd, + vssl_aibnd; + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_red_custom_dig2"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +aibnd_red_clkmux2 gmx4 ( .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd), .s(shift_enbuf), .clk2(iclkin_dist_in0), + .clkout(iclkin_dist_mux), .clk1(iclkin_dist_in1)); +aibnd_red_clkmux2 gmx2 ( .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd), .s(shift_enbuf), .clk2(istrbclk_in0), + .clkout(istrbclk_mux), .clk1(istrbclk_in1)); +aibnd_red_clkmux2 gmx1 ( .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd), .s(shift_enbuf), .clk2(oclk_aib), + .clkout(oclk_mux), .clk1(oclk_in1)); +aibnd_red_clkmux2 gmx0 ( .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd), .s(shift_enbuf), .clk2(oclkb_aib), + .clkout(oclkb_mux), .clk1(oclkb_in1)); +aibnd_inv gin10 ( .clkout(oclk_out), .clk(oclk_mux_inv), + .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd)); +aibnd_inv gin6 ( .vssl_aibnd(vssl_aibnd), .clk(istrbclk_mux), + .vccl_aibnd(vccl_aibnd), .clkout(istrbclk_mux_inv)); +aibnd_inv gin13 ( .vssl_aibnd(vssl_aibnd), .clk(shift_en_b), + .vccl_aibnd(vccl_aibnd), .clkout(shift_enbuf)); +aibnd_inv gin11 ( .vssl_aibnd(vssl_aibnd), .clk(oclk_mux), + .vccl_aibnd(vccl_aibnd), .clkout(oclk_mux_inv)); +aibnd_inv gin8 ( .vssl_aibnd(vssl_aibnd), .clk(oclkb_mux), + .vccl_aibnd(vccl_aibnd), .clkout(oclkb_mux_inv)); +aibnd_inv gin0 ( .vssl_aibnd(vssl_aibnd), .clk(jtag_clksel_b), + .vccl_aibnd(vccl_aibnd), .clkout(jtag_clksel_buf)); +aibnd_inv gin9 ( .clkout(oclkb_out), .clk(oclkb_mux_inv), + .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd)); +aibnd_inv gin3 ( .vssl_aibnd(vssl_aibnd), .clk(iclkin_dist_mux_inv), + .vccl_aibnd(vccl_aibnd), .clkout(iclkin_dist_aib)); +aibnd_inv gna1 ( .vssl_aibnd(vssl_aibnd), .clk(lclk_s1b), + .vccl_aibnd(vccl_aibnd), .clkout(lclk_s1)); +aibnd_inv gin5 ( .vssl_aibnd(vssl_aibnd), .clk(ilaunch_clk_mux_inv), + .vccl_aibnd(vccl_aibnd), .clkout(ilaunch_clk_aib)); +aibnd_inv gin2 ( .vssl_aibnd(vssl_aibnd), .clk(iclkin_dist_mux), + .vccl_aibnd(vccl_aibnd), .clkout(iclkin_dist_mux_inv)); +aibnd_inv gin4 ( .vssl_aibnd(vssl_aibnd), .clk(ilaunch_clk_mux), + .vccl_aibnd(vccl_aibnd), .clkout(ilaunch_clk_mux_inv)); +aibnd_inv gin12 ( .vssl_aibnd(vssl_aibnd), .clk(shift_en), + .vccl_aibnd(vccl_aibnd), .clkout(shift_en_b)); +aibnd_inv gin1 ( .vssl_aibnd(vssl_aibnd), .clk(jtag_clksel), + .vccl_aibnd(vccl_aibnd), .clkout(jtag_clksel_b)); +aibnd_inv gin7 ( .vssl_aibnd(vssl_aibnd), .clk(istrbclk_mux_inv), + .vccl_aibnd(vccl_aibnd), .clkout(istrbclk_aib)); +aibnd_nand2 gna0 ( .clk(shift_enbuf), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .en(jtag_clksel_b), .clkout(lclk_s1b)); +aibnd_red_clkmux3 gmx3 ( .clk3(clkdr_in), .s1(lclk_s1), + .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd), + .s3(jtag_clksel_buf), .s2(lclk_s2), .clk2(ilaunch_clk_in0), + .clkout(ilaunch_clk_mux), .clk1(ilaunch_clk_in1)); +aibnd_nor2 gna2 ( .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd), + .en(jtag_clksel_buf), .clk(shift_enbuf), .clkout(lclk_s2)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_redundancy.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_redundancy.v new file mode 100644 index 0000000..09072af --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_redundancy.v @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module aibnd_redundancy ( //input of input mux +pd_data_in1, pd_data_in0, iclkin_dist_in1, iclkin_dist_in0, idata0_in1, idata0_in0, idata1_in1, idata1_in0, +idataselb_in1, idataselb_in0, iddren_in1, iddren_in0, ilaunch_clk_in1, ilaunch_clk_in0, ilpbk_dat_in1, ilpbk_dat_in0, ilpbk_en_in1, ilpbk_en_in0, +irxen_in1, irxen_in0, istrbclk_in1, istrbclk_in0, itxen_in1, itxen_in0, indrv_in1, indrv_in0, ipdrv_in1, ipdrv_in0, async_dat_in1, async_dat_in0, +//Output of input mux +iclkin_dist_out, idata0_out, idata1_out, idataselb_out, iddren_out, ilaunch_clk_out, ilpbk_dat_out, ilpbk_en_out, +irxen_out, istrbclk_out, itxen_out, indrv_out, ipdrv_out, async_dat_out, + +//input of output mux +oclkb_in1, oclkb_in0, oclk_in1, oclk_in0, odat0_in1, odat0_in0, odat1_in1, odat1_in0, odat_async_in1, odat_async_in0, + +//Output of output mux +pd_data_out, oclkb_out, oclk_out, odat0_out, odat1_out, odat_async_out, + +//Mux selection signal +shift_en //Removed VCCL & VSS port + +); + +//Power Supply +//input vccl, vssl; + +//Mux selection signal +input shift_en; + +//input of input mux +input iclkin_dist_in1, iclkin_dist_in0; +input idata0_in1, idata0_in0; +input idata1_in1, idata1_in0; +input idataselb_in1, idataselb_in0; +input iddren_in1, iddren_in0; +input ilaunch_clk_in1, ilaunch_clk_in0; +input ilpbk_dat_in1, ilpbk_dat_in0; +input ilpbk_en_in1, ilpbk_en_in0; +input [2:0] irxen_in1, irxen_in0; +input istrbclk_in1, istrbclk_in0; +input itxen_in1, itxen_in0; +input [1:0] indrv_in1, indrv_in0; +input [1:0] ipdrv_in1, ipdrv_in0; +input async_dat_in1, async_dat_in0; + +//output of input mux +output iclkin_dist_out; +output idata0_out; +output idata1_out; +output idataselb_out; +output iddren_out; +output ilaunch_clk_out; +output ilpbk_dat_out; +output ilpbk_en_out; +output [2:0] irxen_out; +output istrbclk_out; +output itxen_out; +output [1:0] indrv_out; +output [1:0] ipdrv_out; +output async_dat_out; + + +//input of output mux +input pd_data_in1, pd_data_in0; +input oclkb_in1, oclkb_in0; +input oclk_in1, oclk_in0; +input odat0_in1, odat0_in0; +input odat1_in1, odat1_in0; +input odat_async_in1, odat_async_in0; + +//output of output mux +output pd_data_out; +output oclkb_out; +output oclk_out; +output odat0_out; +output odat1_out; +output odat_async_out; + +// Buses in the design + + +//input mux +assign iclkin_dist_out = shift_en? iclkin_dist_in1 : iclkin_dist_in0 ; +assign idata0_out = shift_en? idata0_in1 : idata0_in0; +assign idata1_out = shift_en? idata1_in1 : idata1_in0; +assign idataselb_out = shift_en? idataselb_in1 : idataselb_in0 ; +assign iddren_out = shift_en? iddren_in1 : iddren_in0; +assign ilaunch_clk_out = shift_en? ilaunch_clk_in1 : ilaunch_clk_in0 ; +assign ilpbk_dat_out = shift_en? ilpbk_dat_in1 : ilpbk_dat_in0 ; +assign ilpbk_en_out = shift_en? ilpbk_en_in1 : ilpbk_en_in0 ; +assign irxen_out[2] = shift_en? irxen_in1[2] : irxen_in0[2]; +assign irxen_out[1] = shift_en? irxen_in1[1] : irxen_in0[1]; +assign irxen_out[0] = shift_en? irxen_in1[0] : irxen_in0[0]; +assign istrbclk_out = shift_en? istrbclk_in1 : istrbclk_in0; +assign itxen_out = shift_en? itxen_in1 : itxen_in0; +assign indrv_out[1] = shift_en? indrv_in1[1] : indrv_in0[1]; +assign indrv_out[0] = shift_en? indrv_in1[0] : indrv_in0[0]; +assign ipdrv_out[1] = shift_en? ipdrv_in1[1] : ipdrv_in0[1]; +assign ipdrv_out[0] = shift_en? ipdrv_in1[0] : ipdrv_in0[0]; +assign async_dat_out = shift_en? async_dat_in1 : async_dat_in0; + +//output mux +assign pd_data_out = shift_en? pd_data_in1 : pd_data_in0; +assign oclkb_out = shift_en? oclkb_in1 : oclkb_in0; +assign oclk_out = shift_en? oclk_in1 : oclk_in0; +assign odat0_out = shift_en? odat0_in1 : odat0_in0; +assign odat1_out = shift_en? odat1_in1 : odat1_in0; +assign odat_async_out = shift_en? odat_async_in1 : odat_async_in0; + +endmodule + + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxanlg.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxanlg.v new file mode 100644 index 0000000..080a6c0 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxanlg.v @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Verilog HDL and netlist files of +// "aibnd_lib aibnd_rxanlg schematic" + + +// alias module. For internal use only. +//hdlFilesDir/cds_alias.v + +// Netlisted models + +// Library - aibnd_lib, Cell - aibnd_rxinv, View - schematic +// LAST TIME SAVED: Oct 1 14:27:50 2014 +// NETLIST TIME: Oct 27 17:27:56 2014 +//`timescale 1ns / 1ns + +module aibnd_rxanlg ( oclkn, oclkp, odat, odat_async, iopad, vccl_aibnd, + vssl_aibnd, clk_en, data_en, iclkn ); + +output oclkn, oclkp, odat, odat_async; + +inout iopad; +input vccl_aibnd, vssl_aibnd; +input clk_en, data_en, iclkn; + +wire clk_enb, clk_en_buf, preoclkpb, preoclkpbb, preoclkpbbb, preoclkp, oclkpb; +wire preoclknb, preoclknbb, preoclknbbb, preoclkn, oclknb; +wire data_enb, data_en_buf, preodatb, preodatbb, preodatbbb, preodat, odatb, preodatn, odat_inv_b, odat_inv; +//specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_rxanlg"; +// specparam CDS_VIEWNAME = "schematic"; +//endspecify +assign clk_enb = ~clk_en; +assign clk_en_buf = ~clk_enb; + +assign preoclkpb = ~iopad; +assign preoclkpbb = ~preoclkpb; +assign preoclkpbbb = ~preoclkpbb; +assign preoclkp = ~preoclkpbbb; +assign oclkpb = ~(preoclkp & clk_en_buf); +assign oclkp = ~oclkpb; +//assign oclkp = (clk_en_buf == 1'b1) ? iopad : ((clk_en_buf == 1'b0)? 1'b0: 1'bx); + +assign preoclknb = ~iclkn; +assign preoclknbb = ~preoclknb; +assign preoclknbbb = ~preoclknbb; +assign preoclkn = ~ preoclknbbb; +assign oclknb = ~(clk_enb | preoclkn); +assign oclkn = ~oclknb; +//assign oclkn = (clk_enb == 1'b0) ? iclkn : ((clk_enb == 1'b1)? 1'b1: 1'bx); +// REMARK: oclkp and oclkn should be mutually exclusive when clk_en = 1 or 0; Need assertion to check. +// Need to gate VCCL power supply in future. +assign data_enb = ~data_en; +assign data_en_buf = ~data_enb; +assign preodatb = ~iopad; +assign preodatbb = ~preodatb; +assign preodatbbb = ~preodatbb; +assign preodat = ~preodatbbb; +assign odatb = ~( preodat & data_en_buf); +assign odat = ~odatb; +//assign odat = (data_en_buf == 1'b1)? iopad : (data_en_buf == 1'b0)? 1'b0: 1'bx; +//Need to gate VCCL power supply in future. + +assign preodatn = preodatbbb; +assign odat_inv_b = ~(preodatn | data_enb); +assign odat_inv = ~odat_inv_b; +assign odat_async = ~odat_inv; +//assign odat_async = (data_enb == 1'b0)? iopad : (data_enb == 1'b1)? 1'b0:1'bx; +//Need to gate VCCL power supply in future +endmodule + + +// End HDL models + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxdat_mimic.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxdat_mimic.v new file mode 100644 index 0000000..8e705ab --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxdat_mimic.v @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module aibnd_rxdat_mimic ( + input wire vccl_aibnd, + input wire vssl_aibnd, + input wire odat_in, + output wire odat_out +); + +assign odat_out = odat_in; + +endmodule diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxdatapath_rx.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxdatapath_rx.v new file mode 100644 index 0000000..504a564 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxdatapath_rx.v @@ -0,0 +1,2054 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_rxdatapath_rx, View - schematic +// LAST TIME SAVED: Jul 7 14:09:46 2015 +// NETLIST TIME: Jul 8 13:09:51 2015 +// `timescale 1ns / 1ns + +module aibnd_rxdatapath_rx ( async_dat_outpclk1_1, + async_dat_outpdir0_1, idat0_in0_dout_clkp, idat1_in0_dout_clkp, + idataselb_in0_directout2, idataselb_in0_dout_clkp, + idataselb_outpclk1_1, idataselb_outpdir0_1, + idirectout_data_outpdir2_1, idlkin_dist_pinp0, + ilaunch_clk_in0_dout_clkp, irxen_chain1, irxen_inpclk6, + irxen_inpdir2, irxen_pinp0, istrbclk_pinp0, itxen_in0_directout2, + itxen_in0_dout_clkp, itxen_outpclk1_1, itxen_outpdir0_1, + jtag_clkdr_inpclk1n, jtag_clkdr_inpclk6, jtag_clkdr_out_chain1, + jtag_clkdr_out_diin_clkp, jtag_clkdr_out_directin2, + jtag_clkdr_out_dirout2, jtag_clkdr_outpclk1_1, + jtag_clkdr_outpdir0_1, jtag_clkdr_pinp0, jtag_rx_scan_inpclk1n, + jtag_rx_scan_inpclk6, jtag_rx_scan_out_diin_clkp, + jtag_rx_scan_out_directin2, jtag_rx_scan_out_dirout2, + jtag_rx_scan_outpclk1_1, jtag_rx_scan_outpdir0_1, + jtag_scan_out_chain1, jtag_scan_pinp0, last_bs_out_chain1, + oclk_inpdir2, oclkb_inpdir2, oclkn_inpdir4, odat0_outpclk1_1, + odat0_outpdir0_1, odat1_outpclk1_1, odat1_outpdir0_1, + odat_async_inpclk1, odat_async_inpclk4, odirectin_data, + odirectin_data_out0_chain1, odll_dll2core_str, odll_lock, + out_rx_fast_clk, pcs_clk, pcs_data_out0, pcs_data_out1, scan_out, + shift_en_directout2, shift_en_dout_clkp, shift_en_inpclk1n, + shift_en_inpclk6, shift_en_inpdir2, shift_en_out_chain1, + shift_en_outpclk1_1, shift_en_outpdir0_1, shift_en_pinp0, + iopad_direct_input, iopad_directinclkn, iopad_directinclkp, + iopad_directout, iopad_directoutclkn, iopad_directoutclkp, + iopad_inclkn, iopad_inclkp, iopad_indat, avmm_sync_rstb, + clkdr_xr1l, clkdr_xr1r, clkdr_xr2l, clkdr_xr2r, clkdr_xr3l, + clkdr_xr3r, clkdr_xr4l, clkdr_xr4r, clkdr_xr5l, clkdr_xr5r, + clkdr_xr6l, clkdr_xr6r, clkdr_xr7l, clkdr_xr7r, clkdr_xr8l, + clkdr_xr8r, dft_rx_clk, iasync_dat_outpdir6, iclkin_dist_vinp0, + iclkin_dist_vinp1, idat0_directoutclkn, idat0_directoutclkp, + idat0_poutp18, idat1_directoutclkn, idat1_directoutclkp, + idat1_poutp18, idataselb, idataselb_outpdir6, idataselb_poutp18, + idatdll_entest_str, idatdll_pipeline_global_en, + idatdll_rb_clkdiv_str, idatdll_rb_half_code_str, + idatdll_rb_selflock_str, idatdll_scan_clk_in, idatdll_scan_in, + idatdll_scan_mode_n, idatdll_scan_rst_n, idatdll_scan_shift_n, + idatdll_str_align_dyconfig_ctl_static, + idatdll_str_align_dyconfig_ctlsel, + idatdll_str_align_stconfig_core_dn_prgmnvrt, + idatdll_str_align_stconfig_core_up_prgmnvrt, + idatdll_str_align_stconfig_core_updnen, + idatdll_str_align_stconfig_dftmuxsel, + idatdll_str_align_stconfig_dll_en, + idatdll_str_align_stconfig_dll_rst_en, + idatdll_str_align_stconfig_hps_ctrl_en, + idatdll_str_align_stconfig_ndllrst_prgmnvrt, + idatdll_str_align_stconfig_new_dll, + idatdll_str_align_stconfig_spare, idatdll_test_clk_pll_en_n, + iddren_poutp18, idirectout_data, idll_core2dll_str, idll_lock_req, + ilaunch_clk_poutp18, indrv_r12, indrv_r34, indrv_r56, indrv_r78, + input_rstb, ipdrv_r12, ipdrv_r34, ipdrv_r56, ipdrv_r78, + irxen_in_chain1, irxen_inpclk3, irxen_inpdir3, irxen_inpshared0, + irxen_r0, irxen_r1, irxen_r2, irxen_r3, irxen_vinp0, irxen_vinp1, + istrbclk_vinp0, istrbclk_vinp1, itxen, itxen_outpdir6, + itxen_poutp18, jtag_clkdr_in_chain1, jtag_clkdr_inpclk0n, + jtag_clkdr_inpshared0, jtag_clkdr_out_inpclk3, + jtag_clkdr_out_inpdir3, jtag_clkdr_out_outpdir6, + jtag_clkdr_out_poutp18, jtag_clkdr_vinp0, jtag_clkdr_vinp1, + jtag_clksel, jtag_intest, jtag_mode_in, jtag_rstb, jtag_rstb_en, + jtag_rx_scan_inpclk0n, jtag_rx_scan_inpshared0, + jtag_rx_scan_out_inpclk3, jtag_rx_scan_out_inpdir3, + jtag_rx_scan_out_outpdir6, jtag_rx_scan_out_poutp18, + jtag_rx_scan_vinp0, jtag_rx_scan_vinp1, jtag_scan_in_chain1, + jtag_tx_scanen_in, jtag_weakpdn, jtag_weakpu, oclk_inpclk3, + oclkb_inpclk3, oclkn_inpclk3, oclkn_outpdir4_1, odat0_inpdir0, + odat1_inpdir0, odat_async_oshared1, odat_async_poutp0, + odirectin_data_in_chain1, poutp_dig_rstb, rx_shift_en, + shift_en_in_chain1, shift_en_inpclk0n, shift_en_inpclk3, + shift_en_inpdir3, shift_en_inpshared0, shift_en_outpdir6, + shift_en_poutp18, shift_en_vinp0, shift_en_vinp1, + txdirclk_fast_clkn, txdirclk_fast_clkp, txpma_dig_rstb, + vccl_aibnd, vssl_aibnd ); + +output async_dat_outpclk1_1, async_dat_outpdir0_1, + idat0_in0_dout_clkp, idat1_in0_dout_clkp, + idataselb_in0_directout2, idataselb_in0_dout_clkp, + idataselb_outpclk1_1, idataselb_outpdir0_1, + idirectout_data_outpdir2_1, idlkin_dist_pinp0, + ilaunch_clk_in0_dout_clkp, istrbclk_pinp0, itxen_in0_directout2, + itxen_in0_dout_clkp, itxen_outpclk1_1, itxen_outpdir0_1, + jtag_clkdr_inpclk1n, jtag_clkdr_inpclk6, jtag_clkdr_out_chain1, + jtag_clkdr_out_diin_clkp, jtag_clkdr_out_directin2, + jtag_clkdr_out_dirout2, jtag_clkdr_outpclk1_1, + jtag_clkdr_outpdir0_1, jtag_clkdr_pinp0, jtag_rx_scan_inpclk1n, + jtag_rx_scan_inpclk6, jtag_rx_scan_out_diin_clkp, + jtag_rx_scan_out_directin2, jtag_rx_scan_out_dirout2, + jtag_rx_scan_outpclk1_1, jtag_rx_scan_outpdir0_1, + jtag_scan_out_chain1, jtag_scan_pinp0, last_bs_out_chain1, + oclk_inpdir2, oclkb_inpdir2, oclkn_inpdir4, odat0_outpclk1_1, + odat0_outpdir0_1, odat1_outpclk1_1, odat1_outpdir0_1, + odat_async_inpclk1, odat_async_inpclk4, + odirectin_data_out0_chain1, odll_lock, out_rx_fast_clk, pcs_clk, + scan_out, shift_en_directout2, shift_en_dout_clkp, + shift_en_inpclk1n, shift_en_inpclk6, shift_en_inpdir2, + shift_en_out_chain1, shift_en_outpclk1_1, shift_en_outpdir0_1, + shift_en_pinp0; + +inout iopad_directinclkn, iopad_directinclkp, iopad_directoutclkn, + iopad_directoutclkp, iopad_inclkn, iopad_inclkp; + +input avmm_sync_rstb, clkdr_xr1l, clkdr_xr1r, clkdr_xr2l, clkdr_xr2r, + clkdr_xr3l, clkdr_xr3r, clkdr_xr4l, clkdr_xr4r, clkdr_xr5l, + clkdr_xr5r, clkdr_xr6l, clkdr_xr6r, clkdr_xr7l, clkdr_xr7r, + clkdr_xr8l, clkdr_xr8r, dft_rx_clk, iasync_dat_outpdir6, + iclkin_dist_vinp0, iclkin_dist_vinp1, idat0_directoutclkn, + idat0_directoutclkp, idat0_poutp18, idat1_directoutclkn, + idat1_directoutclkp, idat1_poutp18, idataselb_outpdir6, + idataselb_poutp18, idatdll_entest_str, idatdll_pipeline_global_en, + idatdll_rb_half_code_str, idatdll_rb_selflock_str, + idatdll_scan_clk_in, idatdll_scan_in, idatdll_scan_mode_n, + idatdll_scan_rst_n, idatdll_scan_shift_n, + idatdll_str_align_dyconfig_ctlsel, + idatdll_str_align_stconfig_core_dn_prgmnvrt, + idatdll_str_align_stconfig_core_up_prgmnvrt, + idatdll_str_align_stconfig_core_updnen, + idatdll_str_align_stconfig_dll_en, + idatdll_str_align_stconfig_dll_rst_en, + idatdll_str_align_stconfig_hps_ctrl_en, + idatdll_str_align_stconfig_ndllrst_prgmnvrt, + idatdll_test_clk_pll_en_n, iddren_poutp18, idll_lock_req, + ilaunch_clk_poutp18, input_rstb, istrbclk_vinp0, istrbclk_vinp1, + itxen_outpdir6, itxen_poutp18, jtag_clkdr_in_chain1, + jtag_clkdr_inpclk0n, jtag_clkdr_inpshared0, + jtag_clkdr_out_inpclk3, jtag_clkdr_out_inpdir3, + jtag_clkdr_out_outpdir6, jtag_clkdr_out_poutp18, jtag_clkdr_vinp0, + jtag_clkdr_vinp1, jtag_clksel, jtag_intest, jtag_mode_in, + jtag_rstb, jtag_rstb_en, jtag_rx_scan_inpclk0n, + jtag_rx_scan_inpshared0, jtag_rx_scan_out_inpclk3, + jtag_rx_scan_out_inpdir3, jtag_rx_scan_out_outpdir6, + jtag_rx_scan_out_poutp18, jtag_rx_scan_vinp0, jtag_rx_scan_vinp1, + jtag_scan_in_chain1, jtag_tx_scanen_in, jtag_weakpdn, jtag_weakpu, + oclk_inpclk3, oclkb_inpclk3, oclkn_inpclk3, oclkn_outpdir4_1, + odat0_inpdir0, odat1_inpdir0, odat_async_oshared1, + odat_async_poutp0, odirectin_data_in_chain1, poutp_dig_rstb, + shift_en_in_chain1, shift_en_inpclk0n, shift_en_inpclk3, + shift_en_inpdir3, shift_en_inpshared0, shift_en_outpdir6, + shift_en_poutp18, shift_en_vinp0, shift_en_vinp1, + txdirclk_fast_clkn, txdirclk_fast_clkp, txpma_dig_rstb, + vccl_aibnd, vssl_aibnd; + +output [2:0] irxen_pinp0; +output [2:0] irxen_inpclk6; +output [2:0] irxen_inpdir2; +output [2:0] irxen_chain1; +output [12:0] odll_dll2core_str; +output [6:0] odirectin_data; +output [19:0] pcs_data_out1; +output [19:0] pcs_data_out0; + +inout [19:0] iopad_indat; +inout [3:0] iopad_directout; +inout [6:0] iopad_direct_input; + +input [2:0] idll_core2dll_str; +input [2:0] irxen_inpshared0; +input [1:0] indrv_r34; +input [9:0] idatdll_str_align_dyconfig_ctl_static; +input [2:0] idatdll_rb_clkdiv_str; +input [2:0] irxen_inpclk3; +input [2:0] irxen_vinp0; +input [1:0] indrv_r56; +input [1:0] ipdrv_r56; +input [2:0] irxen_inpdir3; +input [1:0] ipdrv_r34; +input [1:0] ipdrv_r12; +input [2:0] irxen_r2; +input [2:0] itxen; +input [3:0] idirectout_data; +input [1:0] indrv_r12; +input [2:0] irxen_r1; +input [10:0] idatdll_str_align_stconfig_spare; +input [2:0] irxen_r0; +input [19:0] idatdll_str_align_stconfig_dftmuxsel; +input [1:0] ipdrv_r78; +input [1:0] indrv_r78; +input [2:0] idataselb; +input [2:0] irxen_vinp1; +input [2:0] irxen_in_chain1; +input [2:0] irxen_r3; +input [2:0] idatdll_str_align_stconfig_new_dll; +input [36:0] rx_shift_en; + +wire dll_scan_out, scan_out, pcs_clk_inv, lstrbclk_rep ; // Conversion Sript Generated + +// Buses in the design + +wire [1:2] nc_odat0_out0_directout; + +wire [1:1] nc_oclkn_out0_directin; + +wire [0:1] nc_oclk_out0_directin; + +wire [0:3] nc_pd_data_directout; + +wire [1:6] nc_odata0_out0_directin; + +wire [51:0] csr_reg_str; + +wire [0:19] pcs_data_out0_io; + +wire [0:6] nc_oclk_directin; + +wire [1:2] nc_odat1_out0_directout; + +wire [12:12] ncdrx_oclkb; + +wire [12:12] ncdrx_oclkn; + +wire [12:12] ncdrx_oclk; + +wire [0:11] rx_strbclk_l; + +wire [0:1] odirectin_data_out0; + +wire [0:1] nc_oclkb_out0_directin; + +wire [0:11] rx_distclk_l; + +wire [0:6] nc_pd_data_out0_directin; + +wire [0:6] nc_odata0_directin; + +wire [0:6] nc_oclkb_directin; + +wire [0:19] pcs_data_out1_io; + +wire [0:3] nc_odat1_directout; + +wire [0:3] nc_odat_async_directout; + +wire [0:3] nc_oclk_directout; + +wire [0:3] nc_oclkb_directout; + +wire [0:3] nc_pd_data_out0_directout; + +wire [0:11] rx_strbclk_r; + +wire [1:6] nc_odata1_out0_directin; + +wire [0:11] rx_distclk_r; + +wire [0:6] nc_odata1_directin; + +wire [0:3] nc_oclkb_out0_directout; + +wire [0:3] nc_oclk_out0_directout; + +wire [0:3] nc_odat_async_out0_directout; + +wire [0:6] nc_pd_data_directin; + +wire [0:3] nc_odat0_directout; + +wire [0:3] nc_oclkn_out0_directout; + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_rxdatapath_rx"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify +wire oclk_clkp_buf; +wire oclk_clkpb_buf; +wire oclk_clkp_io; +wire oclk_clkpb_io; + +aibnd_clktree_pcs clktree_pcs ( /*.vcc_aibnd(vccl_aibnd), + .vss_aibnd(vssl_aibnd),*/ .lstrbclk_mimic2(clk_distclk), + .lstrbclk_r_11(rx_distclk_r[11]), + .lstrbclk_r_10(rx_distclk_r[10]), .lstrbclk_r_9(rx_distclk_r[9]), + .lstrbclk_r_8(rx_distclk_r[8]), .lstrbclk_r_7(rx_distclk_r[7]), + .lstrbclk_r_6(rx_distclk_r[6]), .lstrbclk_r_5(rx_distclk_r[5]), + .lstrbclk_r_4(rx_distclk_r[4]), .lstrbclk_r_3(rx_distclk_r[3]), + .lstrbclk_r_2(rx_distclk_r[2]), .lstrbclk_r_1(rx_distclk_r[1]), + .lstrbclk_r_0(rx_distclk_r[0]), .lstrbclk_mimic1(nc_clk_mimic1), + .lstrbclk_mimic0(nc_clk_mimic0), .lstrbclk_l_0(rx_distclk_l[0]), + .lstrbclk_l_1(rx_distclk_l[1]), .lstrbclk_l_2(rx_distclk_l[2]), + .lstrbclk_l_3(rx_distclk_l[3]), .lstrbclk_l_4(rx_distclk_l[4]), + .lstrbclk_l_5(rx_distclk_l[5]), .lstrbclk_l_6(rx_distclk_l[6]), + .lstrbclk_l_7(rx_distclk_l[7]), .lstrbclk_l_8(rx_distclk_l[8]), + .lstrbclk_l_9(rx_distclk_l[9]), .lstrbclk_l_10(rx_distclk_l[10]), + .lstrbclk_l_11(rx_distclk_l[11]), .lstrbclk_rep(lstrbclk_rep), + .clkin(oclk_clkp_buf)); +aibnd_aliasd aliasd11 ( .MINUS(shift_en_inpclk6), .PLUS(rx_shift_en[3])); +aibnd_aliasd aliasv99[2:0] ( .MINUS(irxen_chain1[2:0]), .PLUS(irxen_r2[2:0])); +aibnd_aliasd aliasd4 ( .MINUS(shift_en_pinp0), .PLUS(rx_shift_en[33])); +aibnd_aliasd aliasd10 ( .MINUS(shift_en_inpclk1n), .PLUS(rx_shift_en[8])); +aibnd_aliasd aliasv55 ( .MINUS(idataselb_in0_directout2), .PLUS(idataselb[1])); +aibnd_aliasd aliasd3[2:0] ( .MINUS(irxen_inpclk6[2:0]), .PLUS(irxen_r2[2:0])); +aibnd_aliasd aliasd1[2:0] ( .MINUS(irxen_pinp0[2:0]), .PLUS(irxen_r0[2:0])); +aibnd_aliasd aliasd2 ( .MINUS(istrbclk_pinp0), .PLUS(rx_strbclk_r[11])); +aibnd_aliasd aliasv41 ( .MINUS(itxen_in0_dout_clkp), .PLUS(itxen[0])); +aibnd_aliasd aliasd0 ( .MINUS(idlkin_dist_pinp0), .PLUS(rx_distclk_r[11])); +aibnd_aliasd aliasv88 ( .MINUS(csr_reg_str[51]), .PLUS(idatdll_str_align_stconfig_hps_ctrl_en)); +aibnd_aliasd aliasv86 ( .MINUS(csr_reg_str[1]), .PLUS(idatdll_str_align_stconfig_dll_en)); +aibnd_aliasd aliasv85[2:0] ( .MINUS(csr_reg_str[50:48]), .PLUS(idatdll_str_align_stconfig_new_dll[2:0])); +aibnd_aliasd aliasv87 ( .MINUS(csr_reg_str[0]), .PLUS(idatdll_str_align_stconfig_dll_rst_en)); +aibnd_aliasd aliasv53 ( .MINUS(itxen_in0_directout2), .PLUS(itxen[1])); +aibnd_aliasd aliasv37 ( .MINUS(ilaunch_clk_in0_dout_clkp), .PLUS(txdirclk_fast_clkp)); +aibnd_aliasd aliasd5 ( .MINUS(shift_en_out_chain1), .PLUS(rx_shift_en[36])); +aibnd_aliasd aliasv28[2:0] ( .MINUS(irxen_inpdir2[2:0]), .PLUS(irxen_r2[2:0])); +aibnd_aliasd aliasd6 ( .MINUS(shift_en_directout2), .PLUS(rx_shift_en[9])); +aibnd_aliasd aliasv30 ( .MINUS(idataselb_outpclk1_1), .PLUS(idataselb[1])); +aibnd_aliasd aliasd7 ( .MINUS(shift_en_dout_clkp), .PLUS(rx_shift_en[4])); +aibnd_aliasd aliasd8 ( .MINUS(shift_en_outpdir0_1), .PLUS(rx_shift_en[11])); +aibnd_aliasd aliasv96[9:0] ( .MINUS(csr_reg_str[27:18]), .PLUS(idatdll_str_align_dyconfig_ctl_static[9:0])); +aibnd_aliasd aliasv95 ( .MINUS(csr_reg_str[17]), .PLUS(idatdll_str_align_dyconfig_ctlsel)); +aibnd_aliasd aliasv94[10:0] ( .MINUS(csr_reg_str[16:6]), .PLUS(idatdll_str_align_stconfig_spare[10:0])); +aibnd_aliasd aliasv93 ( .MINUS(csr_reg_str[5]), .PLUS(idatdll_str_align_stconfig_core_updnen)); +aibnd_aliasd aliasv92 ( .MINUS(csr_reg_str[4]), .PLUS(idatdll_str_align_stconfig_core_dn_prgmnvrt)); +aibnd_aliasd aliasv91 ( .MINUS(csr_reg_str[3]), .PLUS(idatdll_str_align_stconfig_core_up_prgmnvrt)); +aibnd_aliasd aliasd12 ( .MINUS(shift_en_inpdir2), .PLUS(rx_shift_en[0])); +aibnd_aliasd aliasv71 ( .MINUS(idataselb_outpdir0_1), .PLUS(idataselb[1])); +aibnd_aliasd aliasv66 ( .MINUS(itxen_outpdir0_1), .PLUS(itxen[1])); +aibnd_aliasd aliasv36 ( .MINUS(idataselb_in0_dout_clkp), .PLUS(idataselb[0])); +aibnd_aliasd aliasv89[19:0] ( .MINUS(csr_reg_str[47:28]), .PLUS(idatdll_str_align_stconfig_dftmuxsel[19:0])); +aibnd_aliasd aliasv90 ( .MINUS(csr_reg_str[2]), .PLUS(idatdll_str_align_stconfig_ndllrst_prgmnvrt)); +aibnd_aliasd aliasv35 ( .MINUS(itxen_outpclk1_1), .PLUS(itxen[1])); +aibnd_aliasd aliasd9 ( .MINUS(shift_en_outpclk1_1), .PLUS(rx_shift_en[10])); +aibnd_buffx1_top xdirect_in6 ( .idata1_in1_jtag_out(nc_idat1_inpclk2), + .async_dat_in1_jtag_out(nc_async_dat_inpclk2), + .idata0_in1_jtag_out(nc_idat0_inpclk2), + .jtag_clkdr_outn(jtag_clkdr_outn_inpclk2), + .prev_io_shift_en(rx_shift_en[7]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_directin[6]), + .oclk_out(nc_oclk_directin[6]), .oclkb_out(nc_oclkb_directin[6]), + .odat0_out(nc_odata0_directin[6]), + .odat1_out(nc_odata1_directin[6]), + .odat_async_out(odirectin_data[6]), + .pd_data_out(nc_pd_data_directin[6]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(vssl_aibnd), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vssl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r2[2:0]), .irxen_in1(irxen_r3[2:0]), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odata_async_out0_directin6), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(odat_async_inpclk5), + .shift_en(rx_shift_en[1]), .pd_data_in1(vssl_aibnd), + .dig_rstb(input_rstb), .jtag_clkdr_out(jtag_clkdr_out_inpclk2), + .odat1_aib(nc_odata1_out0_directin[6]), + .jtag_rx_scan_out(jtag_rx_scan_out_inpclk2), + .odat0_aib(nc_odata0_out0_directin[6]), + .oclk_aib(oclk_out0_directin6), + .last_bs_out(nc_last_bs_out_inpclk2), + .oclkb_aib(oclkb_out0_directin6), .jtag_clkdr_in(clkdr_xr1l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_inpclk1), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_direct_input[6]), .oclkn(nc_oclkn_out0_directin6), + .iclkn(oclkn_inpclk3), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdirect_out3 ( + .idata1_in1_jtag_out(nc_idat1_outpdir0_1), + .async_dat_in1_jtag_out(async_dat_outpdir0_1), + .idata0_in1_jtag_out(nc_idat0_outpdir0_1), + .jtag_clkdr_outn(jtag_clkdr_outn_outpdir0_1), + .prev_io_shift_en(shift_en_vinp1), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), + .pd_data_aib(nc_pd_data_out0_directout[3]), + .oclk_out(nc_oclk_directout[3]), + .oclkb_out(nc_oclkb_directout[3]), + .odat0_out(nc_odat0_directout[3]), + .odat1_out(nc_odat1_directout[3]), + .odat_async_out(nc_odat_async_directout[3]), + .pd_data_out(nc_pd_data_directout[3]), + .async_dat_in0(idirectout_data[3]), .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(iclkin_dist_vinp1), + .iclkin_dist_in1(iclkin_dist_vinp1), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(idataselb[1]), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r12[1:0]), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0(ipdrv_r12[1:0]), + .ipdrv_in1({vssl_aibnd, vssl_aibnd}), .irxen_in0({vssl_aibnd, + vccl_aibnd, vssl_aibnd}), .irxen_in1(irxen_vinp1[2:0]), + .istrbclk_in0(istrbclk_vinp1), .istrbclk_in1(istrbclk_vinp1), + .itxen_in0(itxen[1]), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_out0_directout[3]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[11]), .pd_data_in1(vssl_aibnd), + .dig_rstb(avmm_sync_rstb), .jtag_clkdr_out(jtag_clkdr_outpdir0_1), + .odat1_aib(odat1_outpdir0_1), + .jtag_rx_scan_out(jtag_rx_scan_outpdir0_1), + .odat0_aib(odat0_outpdir0_1), + .oclk_aib(nc_oclk_out0_directout[3]), + .last_bs_out(nc_last_bs_out_directout3), + .oclkb_aib(nc_oclkb_out0_directout[3]), + .jtag_clkdr_in(clkdr_xr2l), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_vinp1), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_directout[3]), .oclkn(nc_oclkn_out0_directout[3]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdirect_out1 ( + .idata1_in1_jtag_out(nc_idat1_directout1), + .async_dat_in1_jtag_out(async_dat_directout1), + .idata0_in1_jtag_out(nc_idat0_directout1), + .jtag_clkdr_outn(jtag_clkdr_outn_directout1), + .prev_io_shift_en(shift_en_poutp18), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), + .pd_data_aib(nc_pd_data_out0_directout[1]), + .oclk_out(nc_oclk_directout[1]), + .oclkb_out(nc_oclkb_directout[1]), + .odat0_out(nc_odat0_directout[1]), + .odat1_out(nc_odat1_directout[1]), + .odat_async_out(nc_odat_async_directout[1]), + .pd_data_out(nc_pd_data_directout[1]), + .async_dat_in0(idirectout_data[1]), .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(vssl_aibnd), .iclkin_dist_in1(vssl_aibnd), + .idata0_in0(vssl_aibnd), .idata0_in1(idat0_poutp18), + .idata1_in0(vssl_aibnd), .idata1_in1(idat1_poutp18), + .idataselb_in0(idataselb[1]), .idataselb_in1(idataselb_poutp18), + .iddren_in0(vssl_aibnd), .iddren_in1(iddren_poutp18), + .ilaunch_clk_in0(ilaunch_clk_poutp18), + .ilaunch_clk_in1(ilaunch_clk_poutp18), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[1]), .itxen_in1(itxen_poutp18), + .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_out0_directout[1]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[12]), .pd_data_in1(vssl_aibnd), + .dig_rstb(txpma_dig_rstb), + .jtag_clkdr_out(jtag_clkdr_out_directout1), + .odat1_aib(nc_odat1_out0_directout[1]), + .jtag_rx_scan_out(jtag_rx_scan_out_directout1), + .odat0_aib(nc_odat0_out0_directout[1]), + .oclk_aib(nc_oclk_out0_directout[1]), + .last_bs_out(nc_last_bs_out_directout1), + .oclkb_aib(nc_oclkb_out0_directout[1]), + .jtag_clkdr_in(clkdr_xr5l), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_out_poutp18), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_directout[1]), .oclkn(nc_oclkn_out0_directout[1]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp0 ( .idata1_in1_jtag_out(nc_idat1_pinp0), + .async_dat_in1_jtag_out(nc_async_dat_pinp0), + .idata0_in1_jtag_out(nc_idat0_pinp0), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp0), + .prev_io_shift_en(rx_shift_en[31]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(pd_data__out0_pinp0), + .oclk_out(nc_oclk_pinp0), .oclkb_out(nc_oclkb_pinp0), + .odat0_out(pcs_data_out0_io[0]), .odat1_out(pcs_data_out1_io[0]), + .odat_async_out(nc_odat_async_pinp0), + .pd_data_out(nc_pd_data_pinp0), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_r[7]), + .iclkin_dist_in1(rx_distclk_r[7]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(rx_strbclk_r[7]), .istrbclk_in1(rx_strbclk_r[7]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(odirectin_data_out0_pinp0), + .oclkb_in1(vssl_aibnd), .odat0_in1(odat0_inpdir0), + .odat1_in1(odat1_inpdir0), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[33]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_pinp0), + .odat1_aib(ncdrx_odat1_out0_pinp0), + .jtag_rx_scan_out(jtag_scan_pinp0), + .odat0_aib(ncdrx_odat0_out0_pinp0), + .oclk_aib(ncdrx_oclk_out0_pinp0), .last_bs_out(last_bs_out_pinp0), + .oclkb_aib(ncdrx_oclkb_out0_pinp0), .jtag_clkdr_in(clkdr_xr7r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_pinp2), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp2), .iopad(iopad_indat[0]), + .oclkn(ncdrx_oclkn_out0_pinp0), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp2 ( .idata1_in1_jtag_out(nc_idat1_pinp2), + .async_dat_in1_jtag_out(nc_async_dat_pinp2), + .idata0_in1_jtag_out(nc_idat0_pinp2), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp2), + .prev_io_shift_en(rx_shift_en[29]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(pd_data__out0_pinp2), + .oclk_out(nc_oclk_pinp2), .oclkb_out(nc_oclkb_pinp2), + .odat0_out(pcs_data_out0_io[2]), .odat1_out(pcs_data_out1_io[2]), + .odat_async_out(nc_odat_async_pinp2), + .pd_data_out(nc_pd_data_pinp2), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_r[3]), + .iclkin_dist_in1(rx_distclk_r[3]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(rx_strbclk_r[3]), .istrbclk_in1(rx_strbclk_r[3]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(odirectin_data_out0_pinp2), + .oclkb_in1(vssl_aibnd), .odat0_in1(ncdrx_odat0_out0_pinp0), + .odat1_in1(ncdrx_odat1_out0_pinp0), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[31]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_pinp2), + .odat1_aib(ncdrx_odat1_out0_pinp2), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp2), + .odat0_aib(ncdrx_odat0_out0_pinp2), + .oclk_aib(ncdrx_oclk_out0_pinp2), .last_bs_out(last_bs_out_pinp2), + .oclkb_aib(ncdrx_oclkb_out0_pinp2), .jtag_clkdr_in(clkdr_xr7r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_pinp4), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp4), .iopad(iopad_indat[2]), + .oclkn(ncdrx_oclkn_out0_pinp2), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp4 ( .idata1_in1_jtag_out(nc_idat1_pinp4), + .async_dat_in1_jtag_out(nc_async_dat_pinp4), + .idata0_in1_jtag_out(nc_idat0_pinp4), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp4), + .prev_io_shift_en(rx_shift_en[27]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_pinp4), + .oclk_out(nc_oclk_pinp4), .oclkb_out(nc_oclkb_pinp4), + .odat0_out(pcs_data_out0_io[4]), .odat1_out(pcs_data_out1_io[4]), + .odat_async_out(nc_odat_async_pinp4), + .pd_data_out(nc_pd_data_pinp4), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_r[1]), + .iclkin_dist_in1(rx_distclk_r[1]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(rx_strbclk_r[1]), .istrbclk_in1(rx_strbclk_r[1]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(nc_odat_async_out0_pinp4), + .oclkb_in1(vssl_aibnd), .odat0_in1(ncdrx_odat0_out0_pinp2), + .odat1_in1(ncdrx_odat1_out0_pinp2), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[29]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_pinp4), + .odat1_aib(ncdrx_odat1_pinp4), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp4), + .odat0_aib(ncdrx_odat0_pinp4), .oclk_aib(ncdrx_oclk_pinp4), + .last_bs_out(last_bs_out_pinp4), .oclkb_aib(ncdrx_oclkb_pinp4), + .jtag_clkdr_in(clkdr_xr7r), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_out_pinp6), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp6), .iopad(iopad_indat[4]), + .oclkn(ncdrx_oclkn_pinp4), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp6 ( .idata1_in1_jtag_out(nc_idat1_pinp6), + .async_dat_in1_jtag_out(nc_async_dat_pinp6), + .idata0_in1_jtag_out(nc_idat0_pinp6), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp6), + .prev_io_shift_en(rx_shift_en[25]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_pinp6), + .oclk_out(nc_oclk_pinp6), .oclkb_out(nc_oclkb_pinp6), + .odat0_out(pcs_data_out0_io[6]), .odat1_out(pcs_data_out1_io[6]), + .odat_async_out(nc_odat_async_pinp6), + .pd_data_out(nc_pd_data_pinp6), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_r[5]), + .iclkin_dist_in1(rx_distclk_r[5]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(rx_strbclk_r[5]), .istrbclk_in1(rx_strbclk_r[5]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(nc_odat_async_out0_pinp6), + .oclkb_in1(vssl_aibnd), .odat0_in1(ncdrx_odat0_pinp4), + .odat1_in1(ncdrx_odat1_pinp4), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[27]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_pinp6), + .odat1_aib(pcs_data_out1_pinp6), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp6), + .odat0_aib(pcs_data_out0_pinp6), .oclk_aib(nc_oclk_out0_pinp6), + .last_bs_out(last_bs_out_pinp6), .oclkb_aib(nc_oclkb_out0_pinp6), + .jtag_clkdr_in(clkdr_xr7r), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_out_pinp8), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp8), .iopad(iopad_indat[6]), + .oclkn(nc_oclkn_out0_pinp6), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp8 ( .idata1_in1_jtag_out(nc_idat1_pinp8), + .async_dat_in1_jtag_out(nc_async_dat_pinp8), + .idata0_in1_jtag_out(nc_idat0_pinp8), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp8), + .prev_io_shift_en(rx_shift_en[23]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_pinp8), + .oclk_out(nc_oclk_pinp8), .oclkb_out(nc_oclkb_pinp8), + .odat0_out(pcs_data_out0_io[8]), .odat1_out(pcs_data_out1_io[8]), + .odat_async_out(nc_odat_async_pinp8), + .pd_data_out(nc_pd_data_pinp8), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_r[9]), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(idat0_rx_clkp), .idata1_in0(vssl_aibnd), + .idata1_in1(idat1_rx_clkp), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vccl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vccl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(dft_rx_clk), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1(irxen_r1[2:0]), + .istrbclk_in0(rx_strbclk_r[9]), .istrbclk_in1(vssl_aibnd), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(nc_odat_async_out0_pinp8), + .oclkb_in1(vssl_aibnd), .odat0_in1(pcs_data_out0_pinp6), + .odat1_in1(pcs_data_out1_pinp6), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[25]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_pinp8), + .odat1_aib(ncdrx_odat1_pinp8), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp8), + .odat0_aib(ncdrx_odat0_pinp8), .oclk_aib(oclk_pinp8), + .last_bs_out(last_bs_out_pinp8), .oclkb_aib(oclkb_pinp8), + .jtag_clkdr_in(clkdr_xr7r), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(nc_jtag_rx_scan_out_rx_clkp), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(nc_last_bs_out_rx_clkp), .iopad(iopad_indat[8]), + .oclkn(ncdrx_oclkn_pinp8), .iclkn(oclkn_pinp9), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xrx_clkp ( .idata1_in1_jtag_out(idat1_rx_clkp), + .async_dat_in1_jtag_out(nc_async_dat_rx_clkp), + .idata0_in1_jtag_out(idat0_rx_clkp), + .jtag_clkdr_outn(jtag_clkdr_outn_rx_clkp), + .prev_io_shift_en(rx_shift_en[21]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(pd_data_out0_rx_clkp), + .oclk_out(oclk_clkp_io), .oclkb_out(oclk_clkpb_io), + .odat0_out(nc_odat0_rx_clkp), .odat1_out(nc_odat1__rx_clkp), + .odat_async_out(nc_odat_async_rx_clkp), + .pd_data_out(nc_pd_data_rx_clkp), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_l[11]), + .iclkin_dist_in1(rx_distclk_l[11]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vccl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(dft_rx_clk), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r1[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(rx_strbclk_l[11]), .istrbclk_in1(rx_strbclk_l[11]), + .itxen_in0(idatdll_str_align_stconfig_spare[0]), + .itxen_in1(vssl_aibnd), .oclk_in1(oclk_clkp_buf), + .odat_async_aib(ncdrx_odat_async_out0_rx_clkp), + .oclkb_in1(oclk_clkpb_buf), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[23]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), + .jtag_clkdr_out(nc_jtag_clkdr_out_rx_clkp), + .odat1_aib(drx_odat1_out0_rx_clkp), + .jtag_rx_scan_out(nc_jtag_rx_scan_out_rx_clkp), + .odat0_aib(drx_odat0_out0_rx_clkp), + .oclk_aib(drx_oclk_out0_rx_clkp), + .last_bs_out(nc_last_bs_out_rx_clkp), + .oclkb_aib(drx_oclkb_out0_rx_clkp), .jtag_clkdr_in(clkdr_xr7l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_pinp10), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp10), .iopad(iopad_inclkp), + .oclkn(ncdrx_oclkn_rx_clkp), .iclkn(oclkn_clkn), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp10 ( .idata1_in1_jtag_out(nc_idat1_pinp10), + .async_dat_in1_jtag_out(nc_async_dat_pinp10), + .idata0_in1_jtag_out(nc_idat0_pinp10), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp10), + .prev_io_shift_en(rx_shift_en[19]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(pd_data__out0_pinp10), + .oclk_out(nc_oclk_pinp10), .oclkb_out(nc_oclkb_pinp10), + .odat0_out(pcs_data_out0_io[10]), + .odat1_out(pcs_data_out1_io[10]), + .odat_async_out(nc_odat_async_pinp10), + .pd_data_out(nc_pd_data_pinp10), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_l[7]), + .iclkin_dist_in1(rx_distclk_l[7]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(rx_strbclk_l[7]), .istrbclk_in1(rx_strbclk_l[7]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), + .odat_async_aib(odirectin_data_out0_pinp10), + .oclkb_in1(vssl_aibnd), .odat0_in1(drx_odat0_out0_rx_clkp), + .odat1_in1(drx_odat1_out0_rx_clkp), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[21]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_pinp10), + .odat1_aib(odat1_pinp10), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp10), + .odat0_aib(odat0_pinp10), .oclk_aib(ncdrx_oclk_out0_pinp10), + .last_bs_out(last_bs_out_pinp10), + .oclkb_aib(ncdrx_oclkb_out0_pinp10), .jtag_clkdr_in(clkdr_xr7l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_pinp12), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp12), .iopad(iopad_indat[10]), + .oclkn(ncdrx_oclkn_out0_pinp10), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp12 ( .idata1_in1_jtag_out(nc_idat1_pinp12), + .async_dat_in1_jtag_out(nc_async_dat_pinp12), + .idata0_in1_jtag_out(nc_idat0_pinp12), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp12), + .prev_io_shift_en(rx_shift_en[17]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(pd_data__out0_pinp12), + .oclk_out(nc_oclk_pinp12), .oclkb_out(nc_oclkb_pinp12), + .odat0_out(pcs_data_out0_io[12]), + .odat1_out(pcs_data_out1_io[12]), + .odat_async_out(nc_odat_async_pinp12), + .pd_data_out(nc_pd_data_pinp12), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_l[3]), + .iclkin_dist_in1(rx_distclk_l[3]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(rx_strbclk_l[3]), .istrbclk_in1(rx_strbclk_l[3]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), + .odat_async_aib(odirectin_data_out0_pinp12), + .oclkb_in1(vssl_aibnd), .odat0_in1(odat0_pinp10), + .odat1_in1(odat1_pinp10), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[19]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_pinp12), + .odat1_aib(odat1_pinp12), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp12), + .odat0_aib(odat0_pinp12), .oclk_aib(ncdrx_oclk[12]), + .last_bs_out(last_bs_out_pinp12), .oclkb_aib(ncdrx_oclkb[12]), + .jtag_clkdr_in(clkdr_xr7l), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_out_pinp14), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp14), .iopad(iopad_indat[12]), + .oclkn(ncdrx_oclkn[12]), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp14 ( .idata1_in1_jtag_out(nc_idat1_pinp14), + .async_dat_in1_jtag_out(nc_async_dat_pinp14), + .idata0_in1_jtag_out(nc_idat0_pinp14), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp14), + .prev_io_shift_en(rx_shift_en[15]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(pd_data__out0_pinp14), + .oclk_out(nc_oclk_pinp14), .oclkb_out(nc_oclkb_pinp14), + .odat0_out(pcs_data_out0_io[14]), + .odat1_out(pcs_data_out1_io[14]), + .odat_async_out(nc_odat_async_pinp14), + .pd_data_out(nc_pd_data_pinp14), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_l[1]), + .iclkin_dist_in1(rx_distclk_l[1]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(rx_strbclk_l[1]), .istrbclk_in1(rx_strbclk_l[1]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), + .odat_async_aib(odirectin_data_out0_pinp14), + .oclkb_in1(vssl_aibnd), .odat0_in1(odat0_pinp12), + .odat1_in1(odat1_pinp12), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[17]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_pinp14), + .odat1_aib(odat1_pinp14), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp14), + .odat0_aib(odat0_pinp14), .oclk_aib(ncdrx_oclk_pinp14), + .last_bs_out(last_bs_out_pinp14), .oclkb_aib(ncdrx_oclkb_pinp14), + .jtag_clkdr_in(clkdr_xr7l), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_out_pinp16), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp16), .iopad(iopad_indat[14]), + .oclkn(ncdrx_oclkn_pinp14), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp16 ( .idata1_in1_jtag_out(nc_idat1_pinp16), + .async_dat_in1_jtag_out(nc_async_dat_pinp16), + .idata0_in1_jtag_out(nc_idat0_pinp16), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp16), + .prev_io_shift_en(rx_shift_en[13]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_pinp16), + .oclk_out(nc_oclk_pinp16), .oclkb_out(nc_oclkb_pinp16), + .odat0_out(pcs_data_out0_io[16]), + .odat1_out(pcs_data_out1_io[16]), + .odat_async_out(nc_odat_async_pinp16), + .pd_data_out(nc_pd_data_pinp16), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_l[5]), + .iclkin_dist_in1(rx_distclk_l[5]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(rx_strbclk_l[5]), .istrbclk_in1(rx_strbclk_l[5]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(nc_odat_async_out0_pinp16), + .oclkb_in1(vssl_aibnd), .odat0_in1(odat0_pinp14), + .odat1_in1(odat1_pinp14), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[15]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_pinp16), + .odat1_aib(pcs_data_out1_pinp16), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp16), + .odat0_aib(pcs_data_out0_pinp16), .oclk_aib(nc_oclk_out0_pinp16), + .last_bs_out(last_bs_out_pinp16), + .oclkb_aib(nc_oclkb_out0_pinp16), .jtag_clkdr_in(clkdr_xr7l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_pinp18), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp18), .iopad(iopad_indat[16]), + .oclkn(nc_oclkn_out0_pinp16), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp18 ( .idata1_in1_jtag_out(nc_idat1_pinp18), + .async_dat_in1_jtag_out(nc_async_dat_pinp18), + .idata0_in1_jtag_out(nc_idat0_pinp18), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp18), + .prev_io_shift_en(rx_shift_en[12]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(pd_data_pinp18), + .oclk_out(nc_oclk_pinp18), .oclkb_out(nc_oclkb_pinp18), + .odat0_out(pcs_data_out0_io[18]), + .odat1_out(pcs_data_out1_io[18]), + .odat_async_out(nc_odat_async_pinp18), + .pd_data_out(nc_pd_data_pinp18), .async_dat_in0(vssl_aibnd), + .async_dat_in1(async_dat_directout1), + .iclkin_dist_in0(rx_distclk_l[9]), .iclkin_dist_in1(vssl_aibnd), + .idata0_in0(vssl_aibnd), .idata0_in1(vssl_aibnd), + .idata1_in0(vssl_aibnd), .idata1_in1(vssl_aibnd), + .idataselb_in0(vccl_aibnd), .idataselb_in1(idataselb[1]), + .iddren_in0(vccl_aibnd), .iddren_in1(vssl_aibnd), + .ilaunch_clk_in0(vssl_aibnd), .ilaunch_clk_in1(vssl_aibnd), + .ilpbk_dat_in0(vssl_aibnd), .ilpbk_dat_in1(vssl_aibnd), + .ilpbk_en_in0(vssl_aibnd), .ilpbk_en_in1(vssl_aibnd), + .indrv_in0({vssl_aibnd, vssl_aibnd}), .indrv_in1(indrv_r78[1:0]), + .ipdrv_in0({vssl_aibnd, vssl_aibnd}), .ipdrv_in1(ipdrv_r78[1:0]), + .irxen_in0(irxen_r0[2:0]), .irxen_in1({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .istrbclk_in0(rx_strbclk_l[9]), + .istrbclk_in1(vssl_aibnd), .itxen_in0(vssl_aibnd), + .itxen_in1(itxen[1]), .oclk_in1(vssl_aibnd), + .odat_async_aib(odirectin_data_pinp18), .oclkb_in1(vssl_aibnd), + .odat0_in1(pcs_data_out0_pinp16), + .odat1_in1(pcs_data_out1_pinp16), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[13]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_pinp18), + .odat1_aib(odat1_pinp18), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp18), + .odat0_aib(odat0_pinp18), .oclk_aib(ncdrx_oclk_pinp18), + .last_bs_out(last_bs_out_pinp18), .oclkb_aib(ncdrx_oclkb_pinp18), + .jtag_clkdr_in(clkdr_xr7l), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_directout1), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_indat[18]), .oclkn(ncdrx_oclkn_pinp18), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xrx_clkn ( .idata1_in1_jtag_out(idat1_rx_clkn), + .async_dat_in1_jtag_out(nc_async_dat_rx_clkn), + .idata0_in1_jtag_out(idat0_rx_clkn), + .jtag_clkdr_outn(jtag_clkdr_outn_rx_clkn), + .prev_io_shift_en(rx_shift_en[22]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_rx_clkn), + .oclk_out(nc_oclk_rx_clkn), .oclkb_out(nc_oclkb_rx_clkn), + .odat0_out(nc_odat0_out1_rx_clkn), + .odat1_out(nc_odat1_out1_rx_clkn), + .odat_async_out(nc_odat_async_out1_rx_clkn), + .pd_data_out(nc_pd_data_out_rx_clkn), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_l[10]), + .iclkin_dist_in1(rx_distclk_l[10]), .idata0_in0(vccl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(dft_rx_clk), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .irxen_in1(irxen_r0[2:0]), .istrbclk_in0(rx_strbclk_l[10]), + .istrbclk_in1(rx_strbclk_l[10]), + .itxen_in0(idatdll_str_align_stconfig_spare[0]), + .itxen_in1(vssl_aibnd), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_out0_rx_clkn), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[24]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), + .jtag_clkdr_out(nc_jtag_clkdr_out1_rx_clkn), + .odat1_aib(nc_odat1_out0_rx_clkn), + .jtag_rx_scan_out(nc_jtag_rx_scan_out1_rx_clkn), + .odat0_aib(nc_odat0_out0_rx_clkn), + .oclk_aib(nc_oclk_out0_rx_clkn), + .last_bs_out(nc_last_bs_out1_rx_clkn), + .oclkb_aib(nc_oclkb_out0_rx_clkn), .jtag_clkdr_in(clkdr_xr8l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_pinp11), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp11), .iopad(iopad_inclkn), + .oclkn(oclkn_clkn), .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp11 ( .idata1_in1_jtag_out(nc_idat1_pinp11), + .async_dat_in1_jtag_out(nc_async_dat_pinp11), + .idata0_in1_jtag_out(nc_idat0_pinp11), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp11), + .prev_io_shift_en(rx_shift_en[20]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_pinp11), + .oclk_out(nc_oclk_pinp11), .oclkb_out(nc_oclkb_pinp11), + .odat0_out(pcs_data_out0_io[11]), + .odat1_out(pcs_data_out1_io[11]), + .odat_async_out(nc_odat_async_pinp11), + .pd_data_out(nc_pd_data_pinp11), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_l[6]), + .iclkin_dist_in1(rx_distclk_l[6]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(rx_strbclk_l[6]), .istrbclk_in1(rx_strbclk_l[6]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(nc_odat_async_out0_pinp11), + .oclkb_in1(vssl_aibnd), .odat0_in1(nc_odat0_out0_rx_clkn), + .odat1_in1(nc_odat1_out0_rx_clkn), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[22]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_pinp11), + .odat1_aib(pcs_data_out1_pinp11), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp11), + .odat0_aib(pcs_data_out0_pinp11), .oclk_aib(nc_oclk_out0_pinp11), + .last_bs_out(last_bs_out_pinp11), + .oclkb_aib(nc_oclkb_out0_pinp11), .jtag_clkdr_in(clkdr_xr8l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_pinp13), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp13), .iopad(iopad_indat[11]), + .oclkn(nc_oclkn_out0_pinp11), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp13 ( .idata1_in1_jtag_out(nc_idat1_pinp13), + .async_dat_in1_jtag_out(nc_async_dat_pinp13), + .idata0_in1_jtag_out(nc_idat0_pinp13), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp13), + .prev_io_shift_en(rx_shift_en[18]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_pinp13), + .oclk_out(nc_oclk_pinp13), .oclkb_out(nc_oclkb_pinp13), + .odat0_out(pcs_data_out0_io[13]), + .odat1_out(pcs_data_out1_io[13]), + .odat_async_out(nc_odat_async_pinp13), + .pd_data_out(nc_pd_data_pinp13), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_l[2]), + .iclkin_dist_in1(rx_distclk_l[2]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(rx_strbclk_l[2]), .istrbclk_in1(rx_strbclk_l[2]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(nc_odat_async_out0_pinp13), + .oclkb_in1(vssl_aibnd), .odat0_in1(pcs_data_out0_pinp11), + .odat1_in1(pcs_data_out1_pinp11), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[20]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_pinp13), + .odat1_aib(pcs_data_out1_pinp13), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp13), + .odat0_aib(pcs_data_out0_pinp13), .oclk_aib(nc_oclk_out0_pinp13), + .last_bs_out(last_bs_out_pinp13), + .oclkb_aib(nc_oclkb_out0_pinp13), .jtag_clkdr_in(clkdr_xr8l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_pinp15), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp15), .iopad(iopad_indat[13]), + .oclkn(nc_oclkn_out0_pinp13), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp15 ( .idata1_in1_jtag_out(nc_idat1_pinp15), + .async_dat_in1_jtag_out(nc_async_dat_pinp15), + .idata0_in1_jtag_out(nc_idat0_pinp15), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp15), + .prev_io_shift_en(rx_shift_en[16]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_pinp15), + .oclk_out(nc_oclk_pinp15), .oclkb_out(nc_oclkb_pinp15), + .odat0_out(pcs_data_out0_io[15]), + .odat1_out(pcs_data_out1_io[15]), + .odat_async_out(nc_odat_async_pinp15), + .pd_data_out(nc_pd_data_pinp15), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_l[0]), + .iclkin_dist_in1(rx_distclk_l[0]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(rx_strbclk_l[0]), .istrbclk_in1(rx_strbclk_l[0]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(nc_odat_async_out0_pinp15), + .oclkb_in1(vssl_aibnd), .odat0_in1(pcs_data_out0_pinp13), + .odat1_in1(pcs_data_out1_pinp13), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[18]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_pinp15), + .odat1_aib(ncdrx_odat1_pinp15), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp15), + .odat0_aib(ncdrx_odat0_pinp15), .oclk_aib(ncdrx_oclk_pinp15), + .last_bs_out(last_bs_out_pinp15), .oclkb_aib(ncdrx_oclkb_pinp15), + .jtag_clkdr_in(clkdr_xr8l), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_out_pinp17), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp17), .iopad(iopad_indat[15]), + .oclkn(ncdrx_oclkn_pinp15), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp17 ( .idata1_in1_jtag_out(nc_idat1_pinp17), + .async_dat_in1_jtag_out(nc_async_dat_pinp17), + .idata0_in1_jtag_out(nc_idat0_pinp17), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp17), + .prev_io_shift_en(rx_shift_en[14]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_pinp17), + .oclk_out(nc_oclk_pinp17), .oclkb_out(nc_oclkb_pinp17), + .odat0_out(pcs_data_out0_io[17]), + .odat1_out(pcs_data_out1_io[17]), + .odat_async_out(nc_odat_async_pinp17), + .pd_data_out(nc_pd_data_pinp17), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_l[4]), + .iclkin_dist_in1(rx_distclk_l[4]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(rx_strbclk_l[4]), .istrbclk_in1(rx_strbclk_l[4]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(nc_odat_async_out0_pinp17), + .oclkb_in1(vssl_aibnd), .odat0_in1(ncdrx_odat0_pinp15), + .odat1_in1(ncdrx_odat1_pinp15), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[16]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_pinp17), + .odat1_aib(pcs_data_out1_pinp17), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp17), + .odat0_aib(pcs_data_out0_pinp17), .oclk_aib(nc_oclk_out0_pinp17), + .last_bs_out(last_bs_out_pinp17), + .oclkb_aib(nc_oclkb_out0_pinp17), .jtag_clkdr_in(clkdr_xr8l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_pinp19), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp19), .iopad(iopad_indat[17]), + .oclkn(nc_oclkn_out0_pinp17), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp19 ( .idata1_in1_jtag_out(nc_idat1_pinp19), + .async_dat_in1_jtag_out(nc_async_dat_pinp19), + .idata0_in1_jtag_out(nc_idat0_pinp19), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp19), + .prev_io_shift_en(shift_en_outpdir6), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(pd_data_pinp19), + .oclk_out(nc_oclk_pinp19), .oclkb_out(nc_oclkb_pinp19), + .odat0_out(pcs_data_out0_io[19]), + .odat1_out(pcs_data_out1_io[19]), + .odat_async_out(nc_odat_async_pinp19), + .pd_data_out(nc_pd_data_pinp19), .async_dat_in0(vssl_aibnd), + .async_dat_in1(iasync_dat_outpdir6), + .iclkin_dist_in0(rx_distclk_l[8]), .iclkin_dist_in1(vssl_aibnd), + .idata0_in0(vssl_aibnd), .idata0_in1(vssl_aibnd), + .idata1_in0(vssl_aibnd), .idata1_in1(vssl_aibnd), + .idataselb_in0(vccl_aibnd), .idataselb_in1(idataselb_outpdir6), + .iddren_in0(vccl_aibnd), .iddren_in1(vssl_aibnd), + .ilaunch_clk_in0(vssl_aibnd), .ilaunch_clk_in1(vssl_aibnd), + .ilpbk_dat_in0(vssl_aibnd), .ilpbk_dat_in1(vssl_aibnd), + .ilpbk_en_in0(vssl_aibnd), .ilpbk_en_in1(vssl_aibnd), + .indrv_in0({vssl_aibnd, vssl_aibnd}), .indrv_in1(indrv_r78[1:0]), + .ipdrv_in0({vssl_aibnd, vssl_aibnd}), .ipdrv_in1(ipdrv_r78[1:0]), + .irxen_in0(irxen_r0[2:0]), .irxen_in1({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .istrbclk_in0(rx_strbclk_l[8]), + .istrbclk_in1(vssl_aibnd), .itxen_in0(vssl_aibnd), + .itxen_in1(itxen_outpdir6), .oclk_in1(vssl_aibnd), + .odat_async_aib(odirectin_data_pinp19), .oclkb_in1(vssl_aibnd), + .odat0_in1(pcs_data_out0_pinp17), + .odat1_in1(pcs_data_out1_pinp17), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[14]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_pinp19), + .odat1_aib(ncdrx_odat1_pinp19), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp19), + .odat0_aib(ncdrx_odat0_pinp19), .oclk_aib(ncdrx_oclk_pinp19), + .last_bs_out(last_bs_out_pinp19), .oclkb_aib(ncdrx_oclkb_pinp19), + .jtag_clkdr_in(clkdr_xr8l), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_outpdir6), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_indat[19]), .oclkn(ncdrx_oclkn_pinp19), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp7 ( .idata1_in1_jtag_out(nc_idat1_pinp7), + .async_dat_in1_jtag_out(nc_async_dat_pinp7), + .idata0_in1_jtag_out(nc_idat0_pinp7), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp7), + .prev_io_shift_en(rx_shift_en[26]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_pinp7), + .oclk_out(nc_oclk_pinp7), .oclkb_out(nc_oclkb_pinp7), + .odat0_out(pcs_data_out0_io[7]), .odat1_out(pcs_data_out1_io[7]), + .odat_async_out(nc_odat_async_pinp7), + .pd_data_out(nc_pd_data_pinp7), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_r[4]), + .iclkin_dist_in1(rx_distclk_r[4]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(rx_strbclk_r[4]), .istrbclk_in1(rx_strbclk_r[4]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(nc_odat_async_out0_pinp7), + .oclkb_in1(vssl_aibnd), .odat0_in1(ncdrx_odat0_pinp5), + .odat1_in1(ncdrx_odat1_pinp5), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[28]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_pinp7), + .odat1_aib(pcs_data_out1_pinp7), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp7), + .odat0_aib(pcs_data_out0_pinp7), .oclk_aib(nc_oclk_out0_pinp7), + .last_bs_out(last_bs_out_pinp7), .oclkb_aib(nc_oclkb_out0_pinp7), + .jtag_clkdr_in(clkdr_xr8r), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_out_pinp9), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp9), .iopad(iopad_indat[7]), + .oclkn(nc_oclkn_out0_pinp7), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp9 ( .idata1_in1_jtag_out(nc_idat1_pinp9), + .async_dat_in1_jtag_out(nc_async_dat_pinp9), + .idata0_in1_jtag_out(nc_idat0_pinp9), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp9), + .prev_io_shift_en(rx_shift_en[24]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_pinp9), + .oclk_out(nc_oclk_pinp9), .oclkb_out(nc_oclkb_pinp9), + .odat0_out(pcs_data_out0_io[9]), .odat1_out(pcs_data_out1_io[9]), + .odat_async_out(nc_odat_async_pinp9), + .pd_data_out(nc_pd_data_pinp9), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_r[8]), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(idat0_rx_clkn), .idata1_in0(vssl_aibnd), + .idata1_in1(idat1_rx_clkn), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vccl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vccl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(dft_rx_clk), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .istrbclk_in0(rx_strbclk_r[8]), + .istrbclk_in1(vssl_aibnd), .itxen_in0(vssl_aibnd), + .itxen_in1(vssl_aibnd), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_out0_pinp9), .oclkb_in1(vssl_aibnd), + .odat0_in1(pcs_data_out0_pinp7), .odat1_in1(pcs_data_out1_pinp7), + .odat_async_in1(vssl_aibnd), .shift_en(rx_shift_en[26]), + .pd_data_in1(vssl_aibnd), .dig_rstb(poutp_dig_rstb), + .jtag_clkdr_out(jtag_clkdr_out_pinp9), + .odat1_aib(ncdrx_odat1_pinp9), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp9), + .odat0_aib(ncdrx_odat0_pinp9), .oclk_aib(ncdrx_oclk_pinp9), + .last_bs_out(last_bs_out_pinp9), .oclkb_aib(ncdrx_oclkb_pinp9), + .jtag_clkdr_in(clkdr_xr8r), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(nc_jtag_rx_scan_out1_rx_clkn), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(nc_last_bs_out1_rx_clkn), .iopad(iopad_indat[9]), + .oclkn(oclkn_pinp9), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdirect_in2 ( + .idata1_in1_jtag_out(nc_idat1_directin2), + .async_dat_in1_jtag_out(nc_async_dat_directin2), + .idata0_in1_jtag_out(nc_idat0_directin2), + .jtag_clkdr_outn(jtag_clkdr_outn_directin2), + .prev_io_shift_en(shift_en_inpshared0), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(input_rstb), + .pd_data_aib(nc_pd_data_out0_directin[2]), + .oclk_out(nc_oclk_directin[2]), .oclkb_out(nc_oclkb_directin[2]), + .odat0_out(nc_odata0_directin[2]), + .odat1_out(nc_odata1_directin[2]), + .odat_async_out(odirectin_data[2]), + .pd_data_out(nc_pd_data_directin[2]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(vssl_aibnd), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vssl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r2[2:0]), .irxen_in1(irxen_inpshared0[2:0]), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odata_async_out0_directin2), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(odat_async_poutp0), + .shift_en(rx_shift_en[0]), .pd_data_in1(vssl_aibnd), + .dig_rstb(input_rstb), .jtag_clkdr_out(jtag_clkdr_out_directin2), + .odat1_aib(nc_odata1_out0_directin[2]), + .jtag_rx_scan_out(jtag_rx_scan_out_directin2), + .odat0_aib(nc_odata0_out0_directin[2]), .oclk_aib(oclk_inpdir2), + .last_bs_out(nc_last_bs_out_directin2), .oclkb_aib(oclkb_inpdir2), + .jtag_clkdr_in(clkdr_xr3r), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_inpshared0), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_direct_input[2]), .oclkn(nc_oclkn_out0_directin2), + .iclkn(oclkn_outpdir4_1), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdiin_clkp ( .idata1_in1_jtag_out(nc_idat1_inpclk1), + .async_dat_in1_jtag_out(nc_async_dat_inpclk1), + .idata0_in1_jtag_out(nc_idat0_inpclk1), + .jtag_clkdr_outn(jtag_clkdr_outn_inpclk1), + .prev_io_shift_en(shift_en_inpdir3), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_diin_clkp), + .oclk_out(out_rx_fast_clk), .oclkb_out(out_rx_fast_clkb), + .odat0_out(nc_odat0_diin_clkp), .odat1_out(nc_odat1_diin_clkp), + .odat_async_out(nc_odat_async_diin_clkp), + .pd_data_out(nc_pd_data_diin_clkp), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(vssl_aibnd), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vssl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r3[2:0]), .irxen_in1(irxen_inpdir3[2:0]), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(oclk_out0_directin6), + .odat_async_aib(odat_async_inpclk1), + .oclkb_in1(oclkb_out0_directin6), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[7]), .pd_data_in1(vssl_aibnd), + .dig_rstb(input_rstb), .jtag_clkdr_out(jtag_clkdr_out_inpclk1), + .odat1_aib(nc_odat1_out0_diin_clkp), + .jtag_rx_scan_out(jtag_rx_scan_out_inpclk1), + .odat0_aib(nc_odat0_out0_diin_clkp), + .oclk_aib(nc_oclk_out0_diin_clkp), + .last_bs_out(nc_last_bs_out_inpclk1), + .oclkb_aib(nc_oclkb_out0_diin_clkp), .jtag_clkdr_in(clkdr_xr1l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_inpdir3), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_directinclkp), .oclkn(nc_oclkn_out0_diin_clkp), + .iclkn(rxoclkn_clkn), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdirect_in4 ( .idata1_in1_jtag_out(nc_idat1_inpclk5), + .async_dat_in1_jtag_out(nc_async_dat_inpclk5), + .idata0_in1_jtag_out(nc_idat0_inpclk5), + .jtag_clkdr_outn(jtag_clkdr_outn_inpclk5), + .prev_io_shift_en(rx_shift_en[1]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_directin[4]), + .oclk_out(nc_oclk_directin[4]), .oclkb_out(nc_oclkb_directin[4]), + .odat0_out(nc_odata0_directin[4]), + .odat1_out(nc_odata1_directin[4]), + .odat_async_out(odirectin_data[4]), + .pd_data_out(nc_pd_data_directin[4]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(vssl_aibnd), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vssl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r2[2:0]), .irxen_in1(irxen_r2[2:0]), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(odat_async_inpclk5), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(odat_async_outpclk0), + .shift_en(rx_shift_en[2]), .pd_data_in1(vssl_aibnd), + .dig_rstb(input_rstb), .jtag_clkdr_out(jtag_clkdr_out_inpclk5), + .odat1_aib(nc_odata1_out0_directin[4]), + .jtag_rx_scan_out(jtag_rx_scan_out_inpclk5), + .odat0_aib(nc_odata0_out0_directin[4]), + .oclk_aib(nc_oclk_out0_directin4), + .last_bs_out(nc_last_bs_out_inptclk5), + .oclkb_aib(nc_oclkb_out0_directin4), .jtag_clkdr_in(clkdr_xr3l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_inpclk2), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_direct_input[4]), .oclkn(nc_oclkn_out0_directin4), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdout_clkp ( + .idata1_in1_jtag_out(idat1_in0_dout_clkp), + .async_dat_in1_jtag_out(nc_async_dat_diin_clkp), + .idata0_in1_jtag_out(idat0_in0_dout_clkp), + .jtag_clkdr_outn(jtag_clkdr_outn_diin_clkp), + .prev_io_shift_en(rx_shift_en[2]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_dout_clkp), + .oclk_out(nc_oclk_dout_clkp), .oclkb_out(nc_oclkb_clkp), + .odat0_out(nc_odat0_dout_clkp), .odat1_out(nc_odat1_dout_clkp), + .odat_async_out(nc_odat_async_dout_clkp), + .pd_data_out(nc_pd_data_dout_clkp), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_diin_clkp), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0_directoutclkp), + .idata0_in1(vssl_aibnd), .idata1_in0(idat1_directoutclkp), + .idata1_in1(vssl_aibnd), .idataselb_in0(idataselb[0]), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(txdirclk_fast_clkp), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r34[1:0]), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0(ipdrv_r34[1:0]), + .ipdrv_in1({vssl_aibnd, vssl_aibnd}), .irxen_in0({vssl_aibnd, + vccl_aibnd, vssl_aibnd}), .irxen_in1(irxen_r2[2:0]), + .istrbclk_in0(jtag_clkdr_outn_diin_clkp), + .istrbclk_in1(vssl_aibnd), .itxen_in0(itxen[0]), + .itxen_in1(vssl_aibnd), .oclk_in1(oclk_inpclk3), + .odat_async_aib(odat_async_outpclk0), .oclkb_in1(oclkb_inpclk3), + .odat0_in1(vssl_aibnd), .odat1_in1(vssl_aibnd), + .odat_async_in1(vssl_aibnd), .shift_en(rx_shift_en[4]), + .pd_data_in1(vssl_aibnd), .dig_rstb(input_rstb), + .jtag_clkdr_out(jtag_clkdr_out_diin_clkp), + .odat1_aib(nc_odat1_out0_dout_clkp), + .jtag_rx_scan_out(jtag_rx_scan_out_diin_clkp), + .odat0_aib(nc_odat0_out0_dout_clkp), + .oclk_aib(nc_oclk_out0_dout_clkp), .last_bs_out(nc2), + .oclkb_aib(nc_oclkb_out0_dout_clkp), .jtag_clkdr_in(clkdr_xr3l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_inpclk5), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_directoutclkp), .oclkn(nc_oclkn_out0_dout_clkp), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdirect_in3 ( .idata1_in1_jtag_out(nc_idat1_inpclk6), + .async_dat_in1_jtag_out(nc_async_dat_inpclk6), + .idata0_in1_jtag_out(nc_idat0_inpclk6), + .jtag_clkdr_outn(jtag_clkdr_outn_inpclk6), + .prev_io_shift_en(shift_en_in_chain1), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(input_rstb), + .pd_data_aib(nc_pd_data_out0_directin[3]), + .oclk_out(nc_oclk_directin[3]), .oclkb_out(nc_oclkb_directin[3]), + .odat0_out(nc_odata0_directin[3]), + .odat1_out(nc_odata1_directin[3]), + .odat_async_out(odirectin_data[3]), + .pd_data_out(nc_pd_data_directin[3]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(vssl_aibnd), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vssl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r2[2:0]), .irxen_in1(irxen_in_chain1[2:0]), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), + .odat_async_aib(odirectin_data_out0_chain1), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(odat_async_oshared1), + .shift_en(rx_shift_en[3]), .pd_data_in1(vssl_aibnd), + .dig_rstb(input_rstb), .jtag_clkdr_out(jtag_clkdr_inpclk6), + .odat1_aib(nc_odata1_out0_directin[3]), + .jtag_rx_scan_out(jtag_rx_scan_inpclk6), + .odat0_aib(nc_odata0_out0_directin[3]), + .oclk_aib(nc_oclk_out0_directin3), + .last_bs_out(last_bs_out_inpclk6), + .oclkb_aib(nc_oclkb_out0_directin3), .jtag_clkdr_in(clkdr_xr2r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_scan_in_chain1), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_direct_input[3]), .oclkn(nc_oclkn_out0_directin3), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdirect_in5 ( + .idata1_in1_jtag_out(nc_idat1_directin5), + .async_dat_in1_jtag_out(nc_async_dat_directin5), + .idata0_in1_jtag_out(nc_idat0_directin5), + .jtag_clkdr_outn(jtag_clkdr_outn_directin5), + .prev_io_shift_en(shift_en_inpclk3), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_directin[5]), + .oclk_out(nc_oclk_directin[5]), .oclkb_out(nc_oclkb_directin[5]), + .odat0_out(nc_odata0_directin[5]), + .odat1_out(nc_odata1_directin[5]), + .odat_async_out(odirectin_data[5]), + .pd_data_out(nc_pd_data_directin[5]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(vssl_aibnd), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vssl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r2[2:0]), .irxen_in1(irxen_inpclk3[2:0]), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(odat_async_inpclk4), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), + .odat_async_in1(nc_odat_async_out0_dout_clkn), + .shift_en(rx_shift_en[6]), .pd_data_in1(vssl_aibnd), + .dig_rstb(input_rstb), .jtag_clkdr_out(jtag_clkdr_out_directin5), + .odat1_aib(nc_odata1_out0_directin[5]), + .jtag_rx_scan_out(jtag_rx_scan_out_directin5), + .odat0_aib(nc_odata0_out0_directin[5]), + .oclk_aib(nc_oclk_out0_directin5), + .last_bs_out(nc_last_bs_out_outpdir6_1), + .oclkb_aib(nc_oclkb_out0_directin5), .jtag_clkdr_in(clkdr_xr4l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_inpclk3), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_direct_input[5]), .oclkn(nc_oclkn_inpclk4), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdout_clkn ( .idata1_in1_jtag_out(idat1_dout_clkn), + .async_dat_in1_jtag_out(nc_async_dat_dout_clkn), + .idata0_in1_jtag_out(idat0_dout_clkn), + .jtag_clkdr_outn(jtag_clkdr_outn_dout_clkn), + .prev_io_shift_en(rx_shift_en[6]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_dout_clkn), + .oclk_out(nc_oclk_dout_clkn), .oclkb_out(nc_oclkb_clkn), + .odat0_out(nc_odat0_dout_clkn), .odat1_out(nc_odat1_dout_clkn), + .odat_async_out(nc_odat_async_dout_clkn), + .pd_data_out(nc_pd_data_dout_clkn), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_dout_clkn), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0_directoutclkn), + .idata0_in1(vssl_aibnd), .idata1_in0(idat1_directoutclkn), + .idata1_in1(vssl_aibnd), .idataselb_in0(idataselb[0]), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(txdirclk_fast_clkn), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r34[1:0]), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0(ipdrv_r34[1:0]), + .ipdrv_in1({vssl_aibnd, vssl_aibnd}), .irxen_in0({vssl_aibnd, + vccl_aibnd, vssl_aibnd}), .irxen_in1(irxen_r2[2:0]), + .istrbclk_in0(jtag_clkdr_outn_dout_clkn), + .istrbclk_in1(vssl_aibnd), .itxen_in0(itxen[0]), + .itxen_in1(vssl_aibnd), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_out0_dout_clkn), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[5]), .pd_data_in1(vssl_aibnd), + .dig_rstb(input_rstb), .jtag_clkdr_out(jtag_clkdr_out_dout_clkn), + .odat1_aib(nc_odat1_out0_dout_clkn), + .jtag_rx_scan_out(jtag_rx_scan_out_dout_clkn), + .odat0_aib(nc_odat0_out0_dout_clkn), + .oclk_aib(nc_oclk_out0_dout_clkn), + .last_bs_out(nc_last_bs_out_dout_clkn), + .oclkb_aib(nc_oclkb_out0_dout_clkn), .jtag_clkdr_in(clkdr_xr4l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_directin5), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_directoutclkn), .oclkn(nc_oclkn_out0_dout_clkn), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdirect_out0 ( + .idata1_in1_jtag_out(nc_idat1_outpclk1_1), + .async_dat_in1_jtag_out(async_dat_outpclk1_1), + .idata0_in1_jtag_out(nc_idat0_outpclk1_1), + .jtag_clkdr_outn(jtag_clkdr_outn_outpclk1_1), + .prev_io_shift_en(shift_en_vinp0), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), + .pd_data_aib(nc_pd_data_out0_directout[0]), + .oclk_out(nc_oclk_directout[0]), + .oclkb_out(nc_oclkb_directout[0]), + .odat0_out(nc_odat0_directout[0]), + .odat1_out(nc_odat1_directout[0]), + .odat_async_out(nc_odat_async_directout[0]), + .pd_data_out(nc_pd_data_directout[0]), + .async_dat_in0(idirectout_data[0]), .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(iclkin_dist_vinp0), + .iclkin_dist_in1(iclkin_dist_vinp0), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(idataselb[1]), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r12[1:0]), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0(ipdrv_r12[1:0]), + .ipdrv_in1({vssl_aibnd, vssl_aibnd}), .irxen_in0({vssl_aibnd, + vccl_aibnd, vssl_aibnd}), .irxen_in1(irxen_vinp0[2:0]), + .istrbclk_in0(istrbclk_vinp0), .istrbclk_in1(istrbclk_vinp0), + .itxen_in0(itxen[1]), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_out0_directout[0]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[10]), .pd_data_in1(vssl_aibnd), + .dig_rstb(avmm_sync_rstb), .jtag_clkdr_out(jtag_clkdr_outpclk1_1), + .odat1_aib(odat1_outpclk1_1), + .jtag_rx_scan_out(jtag_rx_scan_outpclk1_1), + .odat0_aib(odat0_outpclk1_1), + .oclk_aib(nc_oclk_out0_directout[0]), + .last_bs_out(nc_last_bs_out_directout0), + .oclkb_aib(nc_oclkb_out0_directout[0]), + .jtag_clkdr_in(clkdr_xr1l), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_vinp0), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_directout[0]), .oclkn(nc_oclkn_out0_directout[0]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp5 ( .idata1_in1_jtag_out(nc_idat1_pinp5), + .async_dat_in1_jtag_out(nc_async_dat_pinp5), + .idata0_in1_jtag_out(nc_idat0_pinp5), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp5), + .prev_io_shift_en(rx_shift_en[28]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_pinp5), + .oclk_out(nc_oclk_pinp5), .oclkb_out(nc_oclkb_pinp5), + .odat0_out(pcs_data_out0_io[5]), .odat1_out(pcs_data_out1_io[5]), + .odat_async_out(nc_odat_async_pinp5), + .pd_data_out(nc_pd_data_pinp5), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_r[0]), + .iclkin_dist_in1(rx_distclk_r[0]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(rx_strbclk_r[0]), .istrbclk_in1(rx_strbclk_r[0]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(nc_odat_async_out0_pinp5), + .oclkb_in1(vssl_aibnd), .odat0_in1(pcs_data_out0_pinp3), + .odat1_in1(pcs_data_out1_pinp3), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[30]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_pinp5), + .odat1_aib(ncdrx_odat1_pinp5), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp5), + .odat0_aib(ncdrx_odat0_pinp5), .oclk_aib(ncdrx_oclk_pinp5), + .last_bs_out(last_bs_out_pinp5), .oclkb_aib(ncdrx_oclkb_pinp5), + .jtag_clkdr_in(clkdr_xr8r), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_out_pinp7), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp7), .test_weakpd(jtag_weakpdn), + .test_weakpu(jtag_weakpu), .iopad(iopad_indat[5]), + .oclkn(ncdrx_oclkn_pinp5), .iclkn(vssl_aibnd)); +aibnd_buffx1_top xdirect_out2 ( .idata1_in1_jtag_out(nc_idat1_dirout2), + .async_dat_in1_jtag_out(idirectout_data_outpdir2_1), + .idata0_in1_jtag_out(nc_idat0_dirout2), + .jtag_clkdr_outn(jtag_clkdr_outn_dirout2), + .prev_io_shift_en(rx_shift_en[5]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), + .pd_data_aib(nc_pd_data_out0_directout[2]), + .oclk_out(nc_oclk_directout[2]), + .oclkb_out(nc_oclkb_directout[2]), + .odat0_out(nc_odat0_directout[2]), + .odat1_out(nc_odat1_directout[2]), + .odat_async_out(nc_odat_async_directout[2]), + .pd_data_out(nc_pd_data_directout[2]), + .async_dat_in0(idirectout_data[2]), .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(vssl_aibnd), .iclkin_dist_in1(vssl_aibnd), + .idata0_in0(vssl_aibnd), .idata0_in1(idat0_dout_clkn), + .idata1_in0(vssl_aibnd), .idata1_in1(idat1_dout_clkn), + .idataselb_in0(idataselb[1]), .idataselb_in1(idataselb[0]), + .iddren_in0(vssl_aibnd), .iddren_in1(vccl_aibnd), + .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(txdirclk_fast_clkn), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r34[1:0]), + .indrv_in1(indrv_r34[1:0]), .ipdrv_in0(ipdrv_r34[1:0]), + .ipdrv_in1(ipdrv_r34[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[1]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_out0_directout[2]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[9]), .pd_data_in1(vssl_aibnd), + .dig_rstb(input_rstb), .jtag_clkdr_out(jtag_clkdr_out_dirout2), + .odat1_aib(nc_odat1_out0_directout[2]), + .jtag_rx_scan_out(jtag_rx_scan_out_dirout2), + .odat0_aib(nc_odat0_out0_directout[2]), + .oclk_aib(nc_oclk_out0_directout[2]), + .last_bs_out(nc_last_bs_out_dirout2), + .oclkb_aib(nc_oclkb_out0_directout[2]), + .jtag_clkdr_in(clkdr_xr4l), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_dout_clkn), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_directout[2]), .oclkn(nc_oclkn_out0_directout[2]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdiin_clkn ( .idata1_in1_jtag_out(nc_idat1_inpclk1n), + .async_dat_in1_jtag_out(nc_async_dat_inpclk1n), + .idata0_in1_jtag_out(nc_idat0_inpclk1n), + .jtag_clkdr_outn(jtag_clkdr_outn_inpclk1n), + .prev_io_shift_en(rx_shift_en[35]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_diin_clkn), + .oclk_out(nc_oclk_diin_clkn), .oclkb_out(nc_oclkb_diin_clkn), + .odat0_out(nc_odat0_diin_clkn), .odat1_out(nc_odat1_diin_clkn), + .odat_async_out(nc_odat_async_diin_clkn), + .pd_data_out(nc_pd_data_diin_clkn), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(vssl_aibnd), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vssl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .irxen_in1(irxen_r2[2:0]), .istrbclk_in0(vssl_aibnd), + .istrbclk_in1(vssl_aibnd), .itxen_in0(vssl_aibnd), + .itxen_in1(vssl_aibnd), .oclk_in1(vssl_aibnd), + .odat_async_aib(odat_async_out_inpclk1n), .oclkb_in1(vssl_aibnd), + .odat0_in1(vssl_aibnd), .odat1_in1(vssl_aibnd), + .odat_async_in1(vssl_aibnd), .shift_en(rx_shift_en[8]), + .pd_data_in1(vssl_aibnd), .dig_rstb(input_rstb), + .jtag_clkdr_out(jtag_clkdr_inpclk1n), + .odat1_aib(nc_odat1_out0_diin_clkn), + .jtag_rx_scan_out(jtag_rx_scan_inpclk1n), + .odat0_aib(nc_odat0_out0_diin_clkn), + .oclk_aib(nc_oclk_out0_diin_clkn), + .last_bs_out(last_bs_out_inpclk1n), + .oclkb_aib(nc_oclkb_out0_diin_clkn), .jtag_clkdr_in(clkdr_xr2l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_inpdir4), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_directinclkn), .oclkn(rxoclkn_clkn), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp3 ( .idata1_in1_jtag_out(nc_idat1_pinp3), + .async_dat_in1_jtag_out(nc_async_dat_pinp3), + .idata0_in1_jtag_out(nc_idat0_pinp3), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp3), + .prev_io_shift_en(rx_shift_en[30]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_pinp3), + .oclk_out(nc_oclk_pinp3), .oclkb_out(nc_oclkb_pinp3), + .odat0_out(pcs_data_out0_io[3]), .odat1_out(pcs_data_out1_io[3]), + .odat_async_out(nc_odat_async_pinp3), + .pd_data_out(nc_pd_data_pinp3), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_r[2]), + .iclkin_dist_in1(rx_distclk_r[2]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(rx_strbclk_r[2]), .istrbclk_in1(rx_strbclk_r[2]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(nc_odat_async_out0_pinp3), + .oclkb_in1(vssl_aibnd), .odat0_in1(pcs_data_out0_pinp1), + .odat1_in1(pcs_data_out1_pinp1), .odat_async_in1(vssl_aibnd), + .shift_en(rx_shift_en[32]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_pinp3), + .odat1_aib(pcs_data_out1_pinp3), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp3), + .odat0_aib(pcs_data_out0_pinp3), .oclk_aib(nc_oclk_out0_pinp3), + .last_bs_out(last_bs_out_pinp3), .oclkb_aib(nc_oclkb_out0_pinp3), + .jtag_clkdr_in(clkdr_xr8r), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_out_pinp5), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp5), .iopad(iopad_indat[3]), + .oclkn(nc_oclkn_out0_pinp3), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpinp1 ( .idata1_in1_jtag_out(nc_idat1_pinp1), + .async_dat_in1_jtag_out(nc_async_dat_pinp1), + .idata0_in1_jtag_out(nc_idat0_pinp1), + .jtag_clkdr_outn(jtag_clkdr_outn_pinp1), + .prev_io_shift_en(rx_shift_en[32]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_pinp1), + .oclk_out(nc_oclk_pinp1), .oclkb_out(nc_oclkb_pinp1), + .odat0_out(pcs_data_out0_io[1]), .odat1_out(pcs_data_out1_io[1]), + .odat_async_out(nc_odat_async_pinp1), + .pd_data_out(nc_pd_data_pinp1), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_r[6]), + .iclkin_dist_in1(rx_distclk_r[6]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vccl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vccl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(rx_strbclk_r[6]), .istrbclk_in1(rx_strbclk_r[6]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(nc_odat_async_out0_pinp1), + .oclkb_in1(vssl_aibnd), .odat0_in1(nc_odata0_out0_directin[1]), + .odat1_in1(nc_odata1_out0_directin[1]), + .odat_async_in1(vssl_aibnd), .shift_en(rx_shift_en[34]), + .pd_data_in1(vssl_aibnd), .dig_rstb(poutp_dig_rstb), + .jtag_clkdr_out(jtag_clkdr_out_pinp1), + .odat1_aib(pcs_data_out1_pinp1), + .jtag_rx_scan_out(jtag_rx_scan_out_pinp1), + .odat0_aib(pcs_data_out0_pinp1), .oclk_aib(nc_oclk_out0_pinp1), + .last_bs_out(last_bs_out_pinp1), .oclkb_aib(nc_oclkb_out0_pinp1), + .jtag_clkdr_in(clkdr_xr8r), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_out_pinp3), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp3), .test_weakpd(jtag_weakpdn), + .test_weakpu(jtag_weakpu), .iopad(iopad_indat[1]), + .oclkn(nc_oclkn_out0_pinp1), .iclkn(vssl_aibnd)); +aibnd_buffx1_top xdirect_in0 ( .idata1_in1_jtag_out(nc_idat1_inpdir4), + .async_dat_in1_jtag_out(nc_async_dat_inpdir4), + .idata0_in1_jtag_out(nc_idat0_inpdir4), + .jtag_clkdr_outn(jtag_clkdr_outn_inpdir4), + .prev_io_shift_en(shift_en_inpclk0n), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_directin[0]), + .oclk_out(nc_oclk_directin[0]), .oclkb_out(nc_oclkb_directin[0]), + .odat0_out(nc_odata0_directin[0]), + .odat1_out(nc_odata1_directin[0]), + .odat_async_out(odirectin_data[0]), + .pd_data_out(nc_pd_data_directin[0]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(vssl_aibnd), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vssl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r2[2:0]), .irxen_in1({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .istrbclk_in0(vssl_aibnd), + .istrbclk_in1(vssl_aibnd), .itxen_in0(vssl_aibnd), + .itxen_in1(vssl_aibnd), .oclk_in1(vssl_aibnd), + .odat_async_aib(odirectin_data_out0[0]), .oclkb_in1(vssl_aibnd), + .odat0_in1(vssl_aibnd), .odat1_in1(vssl_aibnd), + .odat_async_in1(odat_async_out_inpclk1n), + .shift_en(rx_shift_en[35]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), + .jtag_clkdr_out(jtag_clkdr_out_inpdir4), + .odat1_aib(nc_odat1_directin0), + .jtag_rx_scan_out(jtag_rx_scan_out_inpdir4), + .odat0_aib(nc_odat0_directin0), + .oclk_aib(nc_oclk_out0_directin[0]), + .last_bs_out(last_bs_out_inpdir4), + .oclkb_aib(nc_oclkb_out0_directin[0]), .jtag_clkdr_in(clkdr_xr2l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_inpclk0n), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_direct_input[0]), .oclkn(oclkn_inpdir4), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdirect_in1 ( .idata1_in1_jtag_out(nc_idat1_inpdir1), + .async_dat_in1_jtag_out(nc_async_dat_inpdir1), + .idata0_in1_jtag_out(nc_idat0_inpdir1), + .jtag_clkdr_outn(jtag_clkdr_outn_inpdir1), + .prev_io_shift_en(rx_shift_en[34]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(input_rstb), .pd_data_aib(nc_pd_data_out0_directin[1]), + .oclk_out(nc_oclk_directin[1]), .oclkb_out(nc_oclkb_directin[1]), + .odat0_out(nc_odata0_directin[1]), + .odat1_out(nc_odata1_directin[1]), + .odat_async_out(odirectin_data[1]), + .pd_data_out(nc_pd_data_directin[1]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(rx_distclk_r[10]), + .iclkin_dist_in1(rx_distclk_r[10]), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vssl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r2[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(rx_strbclk_r[10]), .istrbclk_in1(rx_strbclk_r[10]), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(odirectin_data_out0[1]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(odirectin_data_in_chain1), + .shift_en(rx_shift_en[36]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_chain1), + .odat1_aib(nc_odata1_out0_directin[1]), + .jtag_rx_scan_out(jtag_scan_out_chain1), + .odat0_aib(nc_odata0_out0_directin[1]), + .oclk_aib(nc_oclk_out0_directin[1]), + .last_bs_out(last_bs_out_chain1), + .oclkb_aib(nc_oclkb_out0_directin[1]), .jtag_clkdr_in(clkdr_xr8r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_pinp1), + .jtag_tx_scanen_in(jtag_tx_scanen_in), + .last_bs_in(last_bs_out_pinp1), .iopad(iopad_direct_input[1]), + .oclkn(nc_oclkn_out0_directin[1]), .iclkn(vssl_aibnd), + .test_weakpu(jtag_weakpu), .test_weakpd(jtag_weakpdn)); +aibnd_str_align x982 ( .vcc_aibnd(vccl_aibnd), .vss_aibnd(vssl_aibnd), + .scan_shift_n(idatdll_scan_shift_n), + .rb_clkdiv_str(idatdll_rb_clkdiv_str[2:0]), + .scan_rst_n(idatdll_scan_rst_n), .ref_clk_p(oclk_clkp), + .lstrbclk_l_11(rx_strbclk_l[11]), .vcc_io(vccl_aibnd), + .lstrbclk_l_10(rx_strbclk_l[10]), + .odll_dll2core_str(odll_dll2core_str[12:0]), + .lstrbclk_l_9(rx_strbclk_l[9]), .lstrbclk_l_8(rx_strbclk_l[8]), + .lstrbclk_l_7(rx_strbclk_l[7]), .lstrbclk_l_6(rx_strbclk_l[6]), + .lstrbclk_l_5(rx_strbclk_l[5]), .lstrbclk_l_4(rx_strbclk_l[4]), + .lstrbclk_l_3(rx_strbclk_l[3]), .lstrbclk_l_2(rx_strbclk_l[2]), + .lstrbclk_l_1(rx_strbclk_l[1]), .lstrbclk_l_0(rx_strbclk_l[0]), + .lstrbclk_r_0(rx_strbclk_r[0]), .lstrbclk_r_1(rx_strbclk_r[1]), + .lstrbclk_r_2(rx_strbclk_r[2]), + .idll_core2dll_str(idll_core2dll_str[2:0]), + .lstrbclk_r_3(rx_strbclk_r[3]), .idll_lock_req(idll_lock_req), + .idll_entest_str(idatdll_entest_str), + .lstrbclk_r_4(rx_strbclk_r[4]), .lstrbclk_r_5(rx_strbclk_r[5]), + .lstrbclk_r_6(rx_strbclk_r[6]), .lstrbclk_r_7(rx_strbclk_r[7]), + .lstrbclk_r_8(rx_strbclk_r[8]), .lstrbclk_r_9(rx_strbclk_r[9]), + .lstrbclk_r_10(rx_strbclk_r[10]), + .lstrbclk_r_11(rx_strbclk_r[11]), + .scan_mode_n(idatdll_scan_mode_n), + .pipeline_global_en(idatdll_pipeline_global_en), + .scan_clk_in(idatdll_scan_clk_in), .scan_in(idatdll_scan_in), + .scan_out(dll_scan_out), .csr_reg_str(csr_reg_str[51:0]), + .odll_lock(odll_lock), + .rb_half_code_str(idatdll_rb_half_code_str), + .rb_selflock_str(idatdll_rb_selflock_str), .ref_clk_n(oclk_clkpb), + .test_clk_pll_en_n(idatdll_test_clk_pll_en_n)); + +aibnd_clkmux2 xrx_clkp_mux ( + .oclk_out(oclk_clkp), + .mux_sel(rx_shift_en[23]), .oclk_in0(drx_oclk_out0_rx_clkp), + .oclk_in1(oclk_pinp8)); + +aibnd_clkmux2 xrx_clkn_mux ( + .oclk_out(oclk_clkpb), + .mux_sel(rx_shift_en[23]), .oclk_in0(drx_oclkb_out0_rx_clkp), + .oclk_in1(oclkb_pinp8)); + +assign oclk_clkp_buf = oclk_clkp; +assign oclk_clkpb_buf = oclk_clkpb; + +assign scan_out = dll_scan_out; +assign pcs_data_out0[3] = pcs_data_out0_io[3]; +assign pcs_data_out0[5] = pcs_data_out0_io[5]; +assign pcs_data_out1[5] = pcs_data_out1_io[5]; +assign pcs_data_out1[7] = pcs_data_out1_io[7]; +assign pcs_data_out0[7] = pcs_data_out0_io[7]; +assign pcs_data_out0[9] = pcs_data_out0_io[9]; +assign pcs_data_out1[9] = pcs_data_out1_io[9]; +assign pcs_data_out0[11] = pcs_data_out0_io[11]; +assign pcs_data_out1[11] = pcs_data_out1_io[11]; +assign pcs_data_out1[13] = pcs_data_out1_io[13]; +assign pcs_data_out0[13] = pcs_data_out0_io[13]; +assign pcs_data_out0[15] = pcs_data_out0_io[15]; +assign pcs_data_out1[15] = pcs_data_out1_io[15]; +assign pcs_data_out1[17] = pcs_data_out1_io[17]; +assign pcs_data_out0[17] = pcs_data_out0_io[17]; +assign pcs_data_out0[19] = pcs_data_out0_io[19]; +assign pcs_data_out1[19] = pcs_data_out1_io[19]; +assign pcs_data_out0[0] = pcs_data_out0_io[0]; +assign pcs_data_out1[0] = pcs_data_out1_io[0]; +assign pcs_data_out1[2] = pcs_data_out1_io[2]; +assign pcs_data_out0[2] = pcs_data_out0_io[2]; +assign pcs_data_out0[4] = pcs_data_out0_io[4]; +assign pcs_data_out1[4] = pcs_data_out1_io[4]; +assign pcs_data_out1[6] = pcs_data_out1_io[6]; +assign pcs_data_out0[6] = pcs_data_out0_io[6]; +assign pcs_data_out0[8] = pcs_data_out0_io[8]; +assign pcs_data_out1[8] = pcs_data_out1_io[8]; +assign pcs_data_out1[10] = pcs_data_out1_io[10]; +assign pcs_data_out0[10] = pcs_data_out0_io[10]; +assign pcs_data_out0[12] = pcs_data_out0_io[12]; +assign pcs_data_out1[12] = pcs_data_out1_io[12]; +assign pcs_data_out1[14] = pcs_data_out1_io[14]; +assign pcs_data_out0[14] = pcs_data_out0_io[14]; +assign pcs_data_out0[16] = pcs_data_out0_io[16]; +assign pcs_data_out1[16] = pcs_data_out1_io[16]; +assign pcs_data_out0[18] = pcs_data_out0_io[18]; +assign pcs_data_out1[18] = pcs_data_out1_io[18]; +assign pcs_data_out0[1] = pcs_data_out0_io[1]; +assign pcs_data_out1[3] = pcs_data_out1_io[3]; +assign pcs_data_out1[1] = pcs_data_out1_io[1]; + +assign pre_pcs_clk = pcs_clk_inv; + +assign pcs_clk_inv = lstrbclk_rep; +aibnd_rxdat_mimic x1231 ( .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .odat_out(pcs_clk), + .odat_in(pre_pcs_clk)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxdig.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxdig.v new file mode 100644 index 0000000..b21d0e2 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxdig.v @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_rxdig, View - schematic +// LAST TIME SAVED: Dec 1 16:18:35 2014 +// NETLIST TIME: Dec 17 10:24:02 2014 + +module aibnd_rxdig ( clkbuf_en, datbuf_en, odat0, odat1, rx_disable, + rx_idat_buf, sync_datbuf_en0, sync_datbuf_en1, iclkin_dist, + ipadrstb, irstb, irxen, istrbclk, rx_idat, vccl_aibnd, vssl_aibnd + ); + +output clkbuf_en, datbuf_en, odat0, odat1, rx_disable, rx_idat_buf, + sync_datbuf_en0, sync_datbuf_en1; + +input iclkin_dist, ipadrstb, irstb, istrbclk, rx_idat, vccl_aibnd, + vssl_aibnd; + +input [2:0] irxen; + +wire irxen1_b, rst, iclkin_dist, iclkin_distb, iclkin_dist_buf, istrbclkb, istrbclk_buf, istrbclk, ipadrstb, irxen0, irxen0_b, irxen1, irxen2, irxen2_b, sdr_mode, clkbuf_en, sync_datbuf_en1, asyn_data_en, rx_disable, sync_datbuf_en0, pre_databuf_en_out, pre_databuf_en, datbuf_en, odat1_int, odat1, odat0_int, odat0, gt_sync_datbuf_en1, irstb, gt_sync_datbuf_en0, rx_idat, rx_idat_buf; // Conversion Sript Generated + + + +assign irxen1_b = !(irxen[1] | rst); +assign iclkin_distb = !iclkin_dist; +assign iclkin_dist_buf = !iclkin_distb; +assign istrbclk_buf = !istrbclkb; +assign istrbclkb = !istrbclk; +aibnd_latch lyn0 ( .clk(istrbclk_buf), .rb(gt_sync_datbuf_en0) /*`ifndef INTCNOPWR , .vcc(vccl_aibnd) , .vss(vssl_aibnd) `endif*/ , .d(idat0_sync1), .o(idat0_latch)); +aibnd_ff_r fyn0 ( .o(odat0_int), .d(idat0_latch), .clk(iclkin_dist_buf) /*`ifndef INTCNOPWR , .vss(vssl_aibnd) , .vcc(vccl_aibnd) `endif*/ , .rb(gt_sync_datbuf_en0)); +aibnd_ff_r fyn1 ( .o(odat1_int), .d(idat1_sync), .clk(iclkin_dist_buf) /*`ifndef INTCNOPWR , .vss(vssl_aibnd) , .vcc(vccl_aibnd) `endif*/ , .rb(gt_sync_datbuf_en1)); +assign rst = !ipadrstb; +assign irxen0 = !irxen0_b; +assign irxen1 = !irxen1_b; +assign irxen2 = !irxen2_b; +assign sdr_mode = irxen0_b & irxen1_b & irxen2; +assign clkbuf_en = irxen0 & irxen1 & irxen2_b; +assign sync_datbuf_en1 = irxen0 & irxen1_b & irxen2_b; +assign asyn_data_en = irxen0_b & irxen1_b & irxen2_b; +assign rx_disable = irxen0_b & irxen1 & irxen2_b; +assign sync_datbuf_en0 = sync_datbuf_en1 | sdr_mode; +//KSCHIA hack. WW21. Disconnect clkbuf_en to vss. +//assign pre_databuf_en_out = pre_databuf_en | clkbuf_en; +assign pre_databuf_en_out = pre_databuf_en | 1'b0; +assign pre_databuf_en = sync_datbuf_en1 | asyn_data_en; +assign datbuf_en = pre_databuf_en_out | sdr_mode; +assign odat1 = odat1_int; +assign odat0 = odat0_int; +assign gt_sync_datbuf_en1 = irstb & sync_datbuf_en1; +assign gt_sync_datbuf_en0 = irstb & sync_datbuf_en0; +assign irxen2_b = !(irxen[2] & ipadrstb); +assign irxen0_b = !(irxen[0] & ipadrstb); + +//TWTAN : Update the RTL to match with the timing fix , adding inverter before , after fyn3 datapath . +//TWTAN : revert the change to invert the data before/after fyn3 . No invertion before/after fyn3 now +//wire idat_sync1_inv, rx_idat_buf_inv; +//assign idat1_sync = !idat_sync1_inv; +//assign rx_idat_buf_inv = !rx_idat_buf; + +aibnd_ff_r fyn3 ( .o(idat1_sync), .d(rx_idat_buf), .clk(istrbclk_buf) /*`ifndef INTCNOPWR , .vss(vssl_aibnd) , .vcc(vccl_aibnd) `endif*/ , .rb(gt_sync_datbuf_en1)); +aibnd_ff_r fyn2 ( .o(idat0_sync1), .d(rx_idat_buf), .clk(istrbclkb) /*`ifndef INTCNOPWR , .vss(vssl_aibnd) , .vcc(vccl_aibnd) `endif*/ , .rb(gt_sync_datbuf_en0)); +assign rx_idat_buf = rx_idat; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_signal_buf.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_signal_buf.v new file mode 100644 index 0000000..559751a --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_signal_buf.v @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_signal_buf, View - schematic +// LAST TIME SAVED: Apr 19 23:59:52 2015 +// NETLIST TIME: May 12 17:53:11 2015 +// `timescale 1ns / 1ns + +module aibnd_signal_buf ( sig_out, sig_in, vccl_aibnd, vssl_aibnd ); + +output sig_out; + +input sig_in, vccl_aibnd, vssl_aibnd; + +wire sig_in, sig_out; // Conversion Sript Generated + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_signal_buf"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +assign sig_out = sig_in; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_align.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_align.v new file mode 100644 index 0000000..43dad42 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_align.v @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_str_align, View - schematic +// LAST TIME SAVED: May 7 14:46:58 2015 +// NETLIST TIME: May 12 17:53:11 2015 +// `timescale 1ns / 1ns + +module aibnd_str_align ( lstrbclk_l_0, lstrbclk_l_1, lstrbclk_l_2, + lstrbclk_l_3, lstrbclk_l_4, lstrbclk_l_5, lstrbclk_l_6, + lstrbclk_l_7, lstrbclk_l_8, lstrbclk_l_9, lstrbclk_l_10, + lstrbclk_l_11, lstrbclk_r_0, lstrbclk_r_1, lstrbclk_r_2, + lstrbclk_r_3, lstrbclk_r_4, lstrbclk_r_5, lstrbclk_r_6, + lstrbclk_r_7, lstrbclk_r_8, lstrbclk_r_9, lstrbclk_r_10, + lstrbclk_r_11, odll_dll2core_str, odll_lock, scan_out, + csr_reg_str, idll_core2dll_str, idll_entest_str, idll_lock_req, + pipeline_global_en, rb_clkdiv_str, rb_half_code_str, + rb_selflock_str, ref_clk_n, ref_clk_p, scan_clk_in, scan_in, + scan_mode_n, scan_rst_n, scan_shift_n, test_clk_pll_en_n, + vcc_aibnd, vcc_io, vss_aibnd ); + +output lstrbclk_l_0, lstrbclk_l_1, lstrbclk_l_2, lstrbclk_l_3, + lstrbclk_l_4, lstrbclk_l_5, lstrbclk_l_6, lstrbclk_l_7, + lstrbclk_l_8, lstrbclk_l_9, lstrbclk_l_10, lstrbclk_l_11, + lstrbclk_r_0, lstrbclk_r_1, lstrbclk_r_2, lstrbclk_r_3, + lstrbclk_r_4, lstrbclk_r_5, lstrbclk_r_6, lstrbclk_r_7, + lstrbclk_r_8, lstrbclk_r_9, lstrbclk_r_10, lstrbclk_r_11, + odll_lock, scan_out; + +input idll_entest_str, idll_lock_req, pipeline_global_en, + rb_half_code_str, rb_selflock_str, ref_clk_n, ref_clk_p, + scan_clk_in, scan_in, scan_mode_n, scan_rst_n, scan_shift_n, + test_clk_pll_en_n, vcc_aibnd, vcc_io, vss_aibnd; + +output [12:0] odll_dll2core_str; + +input [2:0] rb_clkdiv_str; +input [2:0] idll_core2dll_str; +input [51:0] csr_reg_str; + +wire scan_shift_n, scan_shift_n_buf, scan_clk_in, scan_clk_in_buf, net_0112, net_0111, scan_rst_n, scan_rst_n_buf, scan_mode_n, scan_mode_n_buf, scan_in, scan_in_buf, dll_lock, odll_lock, ref_clk_p, buf_refclk_p, ref_clk_n, buf_refclk_n, lock_req_mux, csr_reg_str6, idll_lock_req, reinit_b, reinit, net106, lstrbclk_mimic0, vss_aibnd, net107, net105, net103, net114, lstrbclk_mimic0_quadph, net115, net112, lstrbclk_rep, net108, net110, lstrbclk_mimic2, net119, net104, lstrbclk_mimic1, net120, net_0113, clk_buf0, code_valid; // Conversion Sript Generated + +// Buses in the design + +wire [9:0] pvt_ref_gry_str; + +wire [9:0] pvt_ref_half_gry_str; + +wire [6:0] f_gray_str; + +wire [6:0] gate_shf; + +wire [2:0] i_gray_str; + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_str_align"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +aibnd_2ff_scan xsync ( .si(scan_in_buf), .so(so_sync), .ssb(scan_shift_n_buf), .o(reinit_b), .d(vcc_aibnd), .clk(clk_buf0) /*`ifndef INTCNOPWR , .vss(vss_aibnd) , .vcc(vcc_aibnd) `endif*/ , .rb(net_0111)); +aibndpnr_dll_pnr xaibnd_str_pnr ( .scan_shift_n(scan_shift_n_buf), + .rb_clkdiv(rb_clkdiv_str[2:0]), .gate_shf(gate_shf[6:0]), + .scan_in(so_sync), .scan_rst_n(scan_rst_n_buf), + .scan_clk_in(scan_clk_in_buf), .scan_mode_n(scan_mode_n_buf), + .scan_out(so_str_pnr), .pipeline_global_en(pipeline_global_en), + .rb_half_code(rb_half_code_str), + .pvt_ref_half_gry(pvt_ref_half_gry_str[9:0]), .dll_lock(dll_lock), + //.vcc_io(vcc_aibnd), .vss_io(vss_aibnd), + .pvt_ref_gry(pvt_ref_gry_str[9:0]), + .dll_core(odll_dll2core_str[12:0]), .i_gray(i_gray_str[2:0]), + .f_gray(f_gray_str[6:0]), .core_dll(idll_core2dll_str[2:0]), + .test_clk_pll_en_n(test_clk_pll_en_n), + .dll_phdet_reset_n(str_rst_n), .measure(measure_str), + .launch(launch_str), .t_down(t_down_str), .t_up(t_up_str), + .entest(idll_entest_str), .reinit(reinit), + .csr_reg(csr_reg_str[51:0]), .rb_selflock(rb_selflock_str), + .clk_pll(buf_refclk_p)); +aibnd_str_clktree_mimic xclktree_quadph ( //.vcc_aibnd(vcc_aibnd), + //.vss_aibnd(vss_aibnd), + .lstrbclk_mimic0(lstrbclk_mimic0_quadph), + .lstrbclk_l_0(lstrbclk_l_0_quadph), + .lstrbclk_l_1(lstrbclk_l_1_quadph), + .lstrbclk_l_2(lstrbclk_l_2_quadph), + .lstrbclk_l_3(lstrbclk_l_3_quadph), + .lstrbclk_l_4(lstrbclk_l_4_quadph), + .lstrbclk_l_5(lstrbclk_l_5_quadph), + .lstrbclk_l_6(lstrbclk_l_6_quadph), + .lstrbclk_l_7(lstrbclk_l_7_quadph), + .lstrbclk_l_8(lstrbclk_l_8_quadph), + .lstrbclk_l_9(lstrbclk_l_9_quadph), + .lstrbclk_l_10(lstrbclk_l_10_quadph), + .lstrbclk_l_11(lstrbclk_l_11_quadph), .lstrbclk_rep(lstrbclk), + .clkin(lstrbclk_rep)); +assign scan_shift_n_buf = scan_shift_n; +assign scan_clk_in_buf = scan_clk_in; +assign net_0111 = net_0112; +assign scan_rst_n_buf = scan_rst_n; +assign scan_mode_n_buf = scan_mode_n; +assign scan_in_buf = scan_in; +aibnd_ff_r fyn0 ( .o(net121), .d(i_del_str), .clk(ref_clk_p) /*`ifndef INTCNOPWR , .vss(vss_aibnd) , .vcc(vcc_aibnd) `endif*/ , .rb(vss_aibnd)); +aibnd_ff_r xsampling_dn ( .o(net102), .d(ref_clk_p), .clk(i_del_str) /*`ifndef INTCNOPWR , .vss(vss_aibnd) , .vcc(vcc_aibnd) `endif*/ , .rb(vss_aibnd)); +assign odll_lock = dll_lock; +assign buf_refclk_p = ref_clk_p; +assign buf_refclk_n = ref_clk_n; +aibnd_str_preclkbuf x211 ( .vcc_aibnd(vcc_aibnd), + .vss_aibnd(vss_aibnd), .clkin(lstrbclk_mimic0), .clkout(net111)); +aibnd_str_preclkbuf x212 ( .vcc_aibnd(vcc_aibnd), + .vss_aibnd(vss_aibnd), .clkin(lstrbclk_mimic1), .clkout(net117)); +aibnd_str_preclkbuf x215 ( .vcc_aibnd(vcc_aibnd), + .vss_aibnd(vss_aibnd), .clkin(lstrbclk_mimic2), .clkout(net101)); +aibnd_str_preclkbuf x216 ( .vcc_aibnd(vcc_aibnd), + .vss_aibnd(vss_aibnd), .clkin(lstrbclk), .clkout(net118)); +aibnd_str_preclkbuf x219 ( .vcc_aibnd(vcc_aibnd), + .vss_aibnd(vss_aibnd), .clkin(lstrbclk_mimic0_quadph), + .clkout(net109)); +aibnd_str_preclkbuf x220 ( .vcc_aibnd(vcc_aibnd), + .vss_aibnd(vss_aibnd), .clkin(clkout_quadph), .clkout(net116)); +assign lock_req_mux = csr_reg_str6 ? idll_core2dll_str[2] : idll_lock_req; +assign reinit = !reinit_b; +aibnd_nand_x64_delay_line xdly_line_quadph ( .sm_n(scan_mode_n_buf), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .code_valid(code_valid), .sck_in(scan_clk_in_buf), + .scan_rst_n(scan_rst_n_buf), .dll_reset_n(str_rst_n), + .se_n(scan_shift_n_buf), .so(scan_out), .si(so_dly_line_str), + .vcc_io(vcc_aibnd), .i_gray(i_gray_str[2:0]), + .f_gray(f_gray_str[6:0]), .out_p(clkout_quadph), .in_p(lstrbclk)); +aibnd_nand_x64_delay_line xdly_line_str ( .sm_n(scan_mode_n_buf), + .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), + .code_valid(code_valid), .sck_in(scan_clk_in_buf), + .scan_rst_n(scan_rst_n_buf), .dll_reset_n(str_rst_n), + .se_n(scan_shift_n_buf), .so(so_dly_line_str), .si(vss_aibnd), + .vcc_io(vcc_aibnd), .i_gray(i_gray_str[2:0]), + .f_gray(f_gray_str[6:0]), .out_p(i_del_str), .in_p(ref_clk_p)); +aibnd_dll_phdet xdll_phdet ( .vss_io(vss_aibnd), .vcc_io(vcc_aibnd), + .t_down(t_down_str), .t_up(t_up_str), .dll_reset_n(str_rst_n), + .phase_clk(ref_clk_n), .i_del_p(clkout_quadph)); +assign csr_reg_str6 = csr_reg_str[6]; +assign net106 = !(lstrbclk_mimic0 & vss_aibnd); +assign net107 = !(vss_aibnd & lstrbclk_mimic0); +assign net105 = !(ref_clk_n & vss_aibnd); +assign net103 = !(vss_aibnd & ref_clk_n); +assign net114 = !(lstrbclk_mimic0_quadph & vss_aibnd); +assign net115 = !(vss_aibnd & lstrbclk_mimic0_quadph); +assign net112 = !(lstrbclk_rep & vss_aibnd); +assign net108 = !(vss_aibnd & lstrbclk_rep); +assign net110 = !(vss_aibnd & lstrbclk_mimic2); +assign net119 = !(lstrbclk_mimic2 & vss_aibnd); +assign net104 = !(lstrbclk_mimic1 & vss_aibnd); +assign net120 = !(vss_aibnd & lstrbclk_mimic1); +//pdecap xdecap0 ( .g(vss_aibnd), .b(vcc_aibnd)); +assign net_0113 = scan_mode_n_buf ? buf_refclk_p : scan_clk_in_buf; +assign net_0112 = scan_mode_n_buf ? lock_req_mux : scan_rst_n_buf; +assign clk_buf0 = net_0113; +//assign code_valid = !gate_shf[6]; +assign code_valid = gate_shf[6]; +aibnd_str_clktree xclktree ( //.vcc_aibnd(vcc_aibnd), + //.vss_aibnd(vss_aibnd), + .lstrbclk_mimic2(lstrbclk_mimic2), + .lstrbclk_r_11(lstrbclk_r_11), .lstrbclk_r_10(lstrbclk_r_10), + .lstrbclk_r_9(lstrbclk_r_9), .lstrbclk_r_8(lstrbclk_r_8), + .lstrbclk_r_7(lstrbclk_r_7), .lstrbclk_r_6(lstrbclk_r_6), + .lstrbclk_r_5(lstrbclk_r_5), .lstrbclk_r_4(lstrbclk_r_4), + .lstrbclk_r_3(lstrbclk_r_3), .lstrbclk_r_2(lstrbclk_r_2), + .lstrbclk_r_1(lstrbclk_r_1), .lstrbclk_r_0(lstrbclk_r_0), + .lstrbclk_mimic1(lstrbclk_mimic1), + .lstrbclk_mimic0(lstrbclk_mimic0), .lstrbclk_l_0(lstrbclk_l_0), + .lstrbclk_l_1(lstrbclk_l_1), .lstrbclk_l_2(lstrbclk_l_2), + .lstrbclk_l_3(lstrbclk_l_3), .lstrbclk_l_4(lstrbclk_l_4), + .lstrbclk_l_5(lstrbclk_l_5), .lstrbclk_l_6(lstrbclk_l_6), + .lstrbclk_l_7(lstrbclk_l_7), .lstrbclk_l_8(lstrbclk_l_8), + .lstrbclk_l_9(lstrbclk_l_9), .lstrbclk_l_10(lstrbclk_l_10), + .lstrbclk_l_11(lstrbclk_l_11), .lstrbclk_rep(lstrbclk_rep), + .clkin(i_del_str)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_align_avmm.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_align_avmm.v new file mode 100644 index 0000000..04690e6 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_align_avmm.v @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_str_align_avmm, View - schematic +// LAST TIME SAVED: Oct 28 17:42:05 2014 +// NETLIST TIME: Oct 29 15:43:13 2014 + +module aibnd_str_align_avmm ( lstrbclk_l_0, lstrbclk_l_1, lstrbclk_l_2, + lstrbclk_l_3, lstrbclk_l_4, lstrbclk_l_5, lstrbclk_l_6, + lstrbclk_l_7, lstrbclk_r_0, lstrbclk_r_1, lstrbclk_r_2, + lstrbclk_r_3, lstrbclk_r_4, lstrbclk_r_5, lstrbclk_r_6, + lstrbclk_r_7, odll_dll2core_str, odll_lock, scan_out, atpg_en_n, + csr_reg_str, idll_core2dll_str, idll_entest_str, idll_lock_req, + pipeline_global_en, rb_clkdiv_str, rb_half_code_str, + rb_selflock_str, ref_clk_n, ref_clk_p, scan_clk_in, scan_in, + scan_mode_n, scan_shift, test_clk, test_clk_pll_en_n, test_clr_n, + vcc_io, vcc_regphy, vss_io ); + +output lstrbclk_l_0, lstrbclk_l_1, lstrbclk_l_2, lstrbclk_l_3, + lstrbclk_l_4, lstrbclk_l_5, lstrbclk_l_6, lstrbclk_l_7, + lstrbclk_r_0, lstrbclk_r_1, lstrbclk_r_2, lstrbclk_r_3, + lstrbclk_r_4, lstrbclk_r_5, lstrbclk_r_6, lstrbclk_r_7, odll_lock, + scan_out; + +input atpg_en_n, idll_entest_str, idll_lock_req, pipeline_global_en, + rb_half_code_str, rb_selflock_str, ref_clk_n, ref_clk_p, + scan_clk_in, scan_in, scan_mode_n, scan_shift, test_clk, + test_clk_pll_en_n, test_clr_n, vcc_io, vcc_regphy, vss_io; + +output [12:0] odll_dll2core_str; + +input [51:0] csr_reg_str; +input [1:0] rb_clkdiv_str; +input [2:0] idll_core2dll_str; + +wire ref_clk_p, buf_refclk_p, ref_clk_n, buf_refclk_n, idll_lock_req, reinit, net0135, lstrbclk_mimic0, vss_io, net098, net095, net0129, net0115, lstrbclk_mimic0_quadph, net0114, net0117, lstrbclk_rep, net0116, net0110, lstrbclk_mimic2, net0144, net0112, lstrbclk_mimic1, net0113; // Conversion Sript Generated + +// Buses in the design + +wire [2:0] i_gray_str; + +wire [9:0] pvt_ref_half_gry_str; + +wire [9:0] pvt_ref_gry_str; + +wire [6:0] f_gray_str; + +aibnd_dll_pnr xaibnd_str_pnr ( .rb_half_code(rb_half_code_str), + .pvt_ref_half_gry(pvt_ref_half_gry_str[9:0]), + .dll_lock(odll_lock), .rb_clkdiv(rb_clkdiv_str[1:0]), +// .vcc_io(vcc_io), .vss_io(vss_io), + .pvt_ref_gry(pvt_ref_gry_str[9:0]), + .dll_core(odll_dll2core_str[12:0]), .i_gray(i_gray_str[2:0]), + .f_gray(f_gray_str[6:0]), .core_dll(idll_core2dll_str[2:0]), + .test_clk_pll_en_n(test_clk_pll_en_n), .test_clr_n(test_clr_n), + .test_clk(test_clk), .dll_phdet_reset_n(str_rst_n), + .measure(measure_str), .launch(launch_str), .t_down(t_down_str), + .t_up(t_up_str), .entest(idll_entest_str), .reinit(reinit), + .atpg_en_n(atpg_en_n), .csr_reg(csr_reg_str[51:0]), + .rb_selflock(rb_selflock_str), .clk_pll(buf_refclk_p)); +aibnd_clktree_avmm_mimic xclktree_quadph ( + .lstrbclk_mimic0(lstrbclk_mimic0_quadph), + .lstrbclk_l_0(lstrbclk_l_0_quadph), + .lstrbclk_l_1(lstrbclk_l_1_quadph), + .lstrbclk_l_2(lstrbclk_l_2_quadph), + .lstrbclk_l_3(lstrbclk_l_3_quadph), + .lstrbclk_l_4(lstrbclk_l_4_quadph), + .lstrbclk_l_5(lstrbclk_l_5_quadph), + .lstrbclk_l_6(lstrbclk_l_6_quadph), + .lstrbclk_l_7(lstrbclk_l_7_quadph), .lstrbclk_rep(lstrbclk), + .clkin(lstrbclk_rep) + //, .vssl(vss_io), .vccl(vcc_regphy) +); +aibnd_ff_r fyn0 ( .o(net185), .d(i_del_str), .clk(ref_clk_p) /*`ifndef INTCNOPWR , .vss(vss_io) , .vcc(vcc_io) `endif*/ , .rb(vss_io)); +aibnd_ff_r xsampling_dn ( .o(net0111), .d(ref_clk_p), .clk(i_del_str) /*`ifndef INTCNOPWR , .vss(vss_io) , .vcc(vcc_io) `endif*/ , .rb(vss_io)); +assign buf_refclk_p = ref_clk_p; +assign buf_refclk_n = ref_clk_n; +aibnd_aliasv aliasv11 ( scan_out, vss_io); +assign reinit = !idll_lock_req; +aibnd_nand_x128_delay_line xdly_line_quadph ( .vcc_io(vcc_io), + .vcc_regphy(vcc_regphy), .vss_io(vss_io), + .i_gray(i_gray_str[2:0]), .f_gray(f_gray_str[6:0]), + .out_p(clkout_quadph), .in_p(lstrbclk)); +aibnd_nand_x128_delay_line xdly_line_str ( .vcc_io(vcc_io), + .vcc_regphy(vcc_regphy), .vss_io(vss_io), + .i_gray(i_gray_str[2:0]), .f_gray(f_gray_str[6:0]), + .out_p(i_del_str), .in_p(ref_clk_p)); +aibnd_dll_phdet xdll_phdet ( + .vss_io(vss_io), .vcc_io(vcc_regphy), + .t_down(t_down_str), .t_up(t_up_str), .dll_reset_n(str_rst_n), + .phase_clk(ref_clk_n), .i_del_p(clkout_quadph)); +aibnd_clktree_avmm xclktree ( .lstrbclk_mimic2(lstrbclk_mimic2), + .lstrbclk_r_7(lstrbclk_r_7), .lstrbclk_r_6(lstrbclk_r_6), + .lstrbclk_r_5(lstrbclk_r_5), .lstrbclk_r_4(lstrbclk_r_4), + .lstrbclk_r_3(lstrbclk_r_3), .lstrbclk_r_2(lstrbclk_r_2), + .lstrbclk_r_1(lstrbclk_r_1), .lstrbclk_r_0(lstrbclk_r_0), + .lstrbclk_mimic1(lstrbclk_mimic1), + .lstrbclk_mimic0(lstrbclk_mimic0), .lstrbclk_l_0(lstrbclk_l_0), + .lstrbclk_l_1(lstrbclk_l_1), .lstrbclk_l_2(lstrbclk_l_2), + .lstrbclk_l_3(lstrbclk_l_3), .lstrbclk_l_4(lstrbclk_l_4), + .lstrbclk_l_5(lstrbclk_l_5), .lstrbclk_l_6(lstrbclk_l_6), + .lstrbclk_l_7(lstrbclk_l_7), .lstrbclk_rep(lstrbclk_rep), + .clkin(i_del_str) + //, .vssl(vss_io), .vccl(vcc_regphy) +); +assign net0135 = !(lstrbclk_mimic0 & vss_io); +assign net098 = !(vss_io & lstrbclk_mimic0); +assign net095 = !(ref_clk_n & vss_io); +assign net0129 = !(vss_io & ref_clk_n); +assign net0115 = !(lstrbclk_mimic0_quadph & vss_io); +assign net0114 = !(vss_io & lstrbclk_mimic0_quadph); +assign net0117 = !(lstrbclk_rep & vss_io); +assign net0116 = !(vss_io & lstrbclk_rep); +assign net0110 = !(vss_io & lstrbclk_mimic2); +assign net0144 = !(lstrbclk_mimic2 & vss_io); +assign net0112 = !(lstrbclk_mimic1 & vss_io); +assign net0113 = !(vss_io & lstrbclk_mimic1); +aibnd_preclkbuf x211 ( .clkin(lstrbclk_mimic0), .vssl(vss_io), + .vccl(vcc_regphy), .clkout(net0103)); +aibnd_preclkbuf x212 ( .clkin(lstrbclk_mimic1), .vssl(vss_io), + .vccl(vcc_regphy), .clkout(net090)); +aibnd_preclkbuf x215 ( .clkin(lstrbclk_mimic2), .vssl(vss_io), + .vccl(vcc_regphy), .clkout(net0101)); +aibnd_preclkbuf x216 ( .clkin(lstrbclk), .vssl(vss_io), + .vccl(vcc_regphy), .clkout(net0100)); +aibnd_preclkbuf x219 ( .clkin(lstrbclk_mimic0_quadph), .vssl(vss_io), + .vccl(vcc_regphy), .clkout(net099)); +aibnd_preclkbuf x220 ( .clkin(clkout_quadph), .vssl(vss_io), + .vccl(vcc_regphy), .clkout(net0136)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_clktree.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_clktree.v new file mode 100644 index 0000000..fce11d6 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_clktree.v @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #5 $ +// Date: $DateTime: 2015/07/27 23:57:02 $ +//------------------------------------------------------------------------ +// Description: skew-matched clock distribution network +//------------------------------------------------------------------------ + +module aibnd_str_clktree +#( +parameter SKEW_DELAY = 60 //min:20ps; typ :60ps; max:100ps +) +( + input wire clkin, //clock source + output wire lstrbclk_l_0, //buffered clock + output wire lstrbclk_l_1, //buffered clock + output wire lstrbclk_l_2, //buffered clock + output wire lstrbclk_l_3, //buffered clock + output wire lstrbclk_l_4, //buffered clock + output wire lstrbclk_l_5, //buffered clock + output wire lstrbclk_l_6, //buffered clock + output wire lstrbclk_l_7, //buffered clock + output wire lstrbclk_l_8, //buffered clock + output wire lstrbclk_l_9, //buffered clock + output wire lstrbclk_l_10, //buffered clock + output wire lstrbclk_l_11, //buffered clock + output wire lstrbclk_r_0, //buffered clock + output wire lstrbclk_r_1, //buffered clock + output wire lstrbclk_r_2, //buffered clock + output wire lstrbclk_r_3, //buffered clock + output wire lstrbclk_r_4, //buffered clock + output wire lstrbclk_r_5, //buffered clock + output wire lstrbclk_r_6, //buffered clock + output wire lstrbclk_r_7, //buffered clock + output wire lstrbclk_r_8, //buffered clock + output wire lstrbclk_r_9, //buffered clock + output wire lstrbclk_r_10, //buffered clock + output wire lstrbclk_r_11, //buffered clock + output wire lstrbclk_rep, //replica for DLL + output wire lstrbclk_mimic0, //mimic path for load matching + output wire lstrbclk_mimic1, //mimic path for load matching + output wire lstrbclk_mimic2 //mimic path for load matching +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + + assign #SKEW_DELAY lstrbclk_l_0 = clkin; + assign #SKEW_DELAY lstrbclk_l_1 = clkin; + assign #SKEW_DELAY lstrbclk_l_2 = clkin; + assign #SKEW_DELAY lstrbclk_l_3 = clkin; + assign #SKEW_DELAY lstrbclk_l_4 = clkin; + assign #SKEW_DELAY lstrbclk_l_5 = clkin; + assign #SKEW_DELAY lstrbclk_l_6 = clkin; + assign #SKEW_DELAY lstrbclk_l_7 = clkin; + assign #SKEW_DELAY lstrbclk_l_8 = clkin; + assign #SKEW_DELAY lstrbclk_l_9 = clkin; + assign #SKEW_DELAY lstrbclk_l_10 = clkin; + assign #SKEW_DELAY lstrbclk_l_11 = clkin; + assign #SKEW_DELAY lstrbclk_r_0 = clkin; + assign #SKEW_DELAY lstrbclk_r_1 = clkin; + assign #SKEW_DELAY lstrbclk_r_2 = clkin; + assign #SKEW_DELAY lstrbclk_r_3 = clkin; + assign #SKEW_DELAY lstrbclk_r_4 = clkin; + assign #SKEW_DELAY lstrbclk_r_5 = clkin; + assign #SKEW_DELAY lstrbclk_r_6 = clkin; + assign #SKEW_DELAY lstrbclk_r_7 = clkin; + assign #SKEW_DELAY lstrbclk_r_8 = clkin; + assign #SKEW_DELAY lstrbclk_r_9 = clkin; + assign #SKEW_DELAY lstrbclk_r_10 = clkin; + assign #SKEW_DELAY lstrbclk_r_11 = clkin; + assign #SKEW_DELAY lstrbclk_rep = clkin; + assign #SKEW_DELAY lstrbclk_mimic0 = clkin; + assign #SKEW_DELAY lstrbclk_mimic1 = clkin; + assign #SKEW_DELAY lstrbclk_mimic2 = clkin; + +endmodule // aibnd_str_clktree + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_clktree_mimic.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_clktree_mimic.v new file mode 100644 index 0000000..c827923 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_clktree_mimic.v @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #5 $ +// Date: $DateTime: 2015/07/27 23:57:02 $ +//------------------------------------------------------------------------ +// Description: skew-matched clock distribution network +//------------------------------------------------------------------------ + +module aibnd_str_clktree_mimic +#( +parameter SKEW_DELAY = 60 //min:20ps; typ :60ps; max:100ps +) +( + input wire clkin, //clock source + output wire lstrbclk_l_0, //buffered clock + output wire lstrbclk_l_1, //buffered clock + output wire lstrbclk_l_2, //buffered clock + output wire lstrbclk_l_3, //buffered clock + output wire lstrbclk_l_4, //buffered clock + output wire lstrbclk_l_5, //buffered clock + output wire lstrbclk_l_6, //buffered clock + output wire lstrbclk_l_7, //buffered clock + output wire lstrbclk_l_8, //buffered clock + output wire lstrbclk_l_9, //buffered clock + output wire lstrbclk_l_10, //buffered clock + output wire lstrbclk_l_11, //buffered clock + output wire lstrbclk_rep, //replica for DLL + output wire lstrbclk_mimic0 //mimic path for load matching +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + + assign #SKEW_DELAY lstrbclk_l_0 = clkin; + assign #SKEW_DELAY lstrbclk_l_1 = clkin; + assign #SKEW_DELAY lstrbclk_l_2 = clkin; + assign #SKEW_DELAY lstrbclk_l_3 = clkin; + assign #SKEW_DELAY lstrbclk_l_4 = clkin; + assign #SKEW_DELAY lstrbclk_l_5 = clkin; + assign #SKEW_DELAY lstrbclk_l_6 = clkin; + assign #SKEW_DELAY lstrbclk_l_7 = clkin; + assign #SKEW_DELAY lstrbclk_l_8 = clkin; + assign #SKEW_DELAY lstrbclk_l_9 = clkin; + assign #SKEW_DELAY lstrbclk_l_10 = clkin; + assign #SKEW_DELAY lstrbclk_l_11 = clkin; + assign #SKEW_DELAY lstrbclk_rep = clkin; + assign #SKEW_DELAY lstrbclk_mimic0 = clkin; + +endmodule // aibnd_str_clktree_mimic + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_ff.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_ff.v new file mode 100644 index 0000000..b7cee6a --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_ff.v @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_str_ff, View - schematic +// LAST TIME SAVED: Mar 26 07:33:48 2015 +// NETLIST TIME: May 12 17:53:10 2015 +// `timescale 1ns / 1ns + +module aibnd_str_ff ( q, so, clk, code_valid, d, rb, se_n, si ); + +output q, so; + +input clk, code_valid, d, rb, se_n, si; + +wire so, q, net010, code_valid, d, net011, se_n, si; // Conversion Sript Generated + +assign vcc_aibnd = 1'b1; +assign vss_aibnd = 1'b0; + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_str_ff"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +assign q = so; +aibnd_ff_r xreg0 ( .o(so), .d(net011), .clk(clk) /*`ifndef INTCNOPWR , .vss(vss_aibnd) , .vcc(vcc_aibnd) `endif*/ , .rb(rb)); +assign net010 = code_valid ? d : so; +assign net011 = se_n ? net010 : si; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_ioload.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_ioload.v new file mode 100644 index 0000000..d136962 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_ioload.v @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_str_ioload, View - schematic +// LAST TIME SAVED: May 19 10:56:07 2015 +// NETLIST TIME: May 19 12:48:22 2015 +//`timescale 1ns / 1ns + +module aibnd_str_ioload ( inp); + +input inp; + +// Buses in the design + +wire net07; + +assign vcc_aibnd = 1'b1; +assign vss_aibnd = 1'b0; + + +//specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_str_ioload"; +// specparam CDS_VIEWNAME = "schematic"; +//endspecify + +assign net07 = ~inp ; + +endmodule diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_preclkbuf.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_preclkbuf.v new file mode 100644 index 0000000..841cf5a --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_preclkbuf.v @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_str_preclkbuf, View - schematic +// LAST TIME SAVED: Mar 25 07:54:22 2015 +// NETLIST TIME: May 12 17:53:10 2015 +// `timescale 1ns / 1ns + +module aibnd_str_preclkbuf ( clkout, clkin, vcc_aibnd, vss_aibnd ); + +output clkout; + +input clkin, vcc_aibnd, vss_aibnd; + +wire clkin, clkout; // Conversion Sript Generated + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_str_preclkbuf"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +assign clkout = !clkin; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_sync_ff.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_sync_ff.v new file mode 100644 index 0000000..09c98f2 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_sync_ff.v @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_sync_ff, View - schematic +// LAST TIME SAVED: Mar 26 07:33:50 2015 +// NETLIST TIME: May 12 17:53:10 2015 +// `timescale 1ns / 1ns + +module aibnd_sync_ff ( q, so, clk, d, rb, se_n, si, vcc_aibnd, + vss_aibnd ); + +output q, so; + +input clk, d, rb, se_n, si, vcc_aibnd, vss_aibnd; + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_sync_ff"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +aibnd_2ff_scan xsync0 ( .d(d), .clk(clk), .o(net016) /*`ifndef INTCNOPWR , .vcc(vcc_aibnd) `endif*/ , .rb(rb), .si(si) /*`ifndef INTCNOPWR , .vss(vss_aibnd) `endif*/ , .so(so0), .ssb(se_n)); +aibnd_2ff_scan xsync1 ( .d(net016), .clk(clk), .o(q) /*`ifndef INTCNOPWR , .vcc(vcc_aibnd) `endif*/ , .rb(rb), .si(so0) /*`ifndef INTCNOPWR , .vss(vss_aibnd) `endif*/ , .so(so), .ssb(se_n)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_top.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_top.v new file mode 100644 index 0000000..35b0606 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_top.v @@ -0,0 +1,1279 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_top, View - schematic +// LAST TIME SAVED: May 12 19:18:16 2015 +// NETLIST TIME: May 12 19:44:01 2015 +// `timescale 1ns / 1ns + +module aibnd_top ( jtag_clksel_out, jtag_intest_out, jtag_mode_out, + jtag_rstb_en_out, jtag_rstb_out, jtag_tx_scanen_out, + jtag_weakpdn_out, jtag_weakpu_out, oatpg_scan_out0, + oatpg_scan_out1, ohssi_avmm1_data_in, ohssi_avmm2_data_in, + ohssi_fsr_data_in, ohssi_fsr_load_in, ohssi_pld_8g_rxelecidle, + ohssi_pld_pcs_rx_clk_out, ohssi_pld_pcs_tx_clk_out, + ohssi_pld_pma_clkdiv_rx_user, ohssi_pld_pma_clkdiv_tx_user, + ohssi_pld_pma_hclk, ohssi_pld_pma_internal_clk1, + ohssi_pld_pma_internal_clk2, ohssi_pld_pma_pfdmode_lock, + ohssi_pld_pma_rxpll_lock, ohssi_pld_rx_hssi_fifo_latency_pulse, + ohssi_pld_tx_hssi_fifo_latency_pulse, ohssi_pma_aib_tx_clk, + ohssi_rx_data_out, ohssi_rx_transfer_clk, ohssi_sr_clk_in, + ohssi_sr_clk_n_in, ohssi_ssr_data_in, ohssi_ssr_load_in, + ohssi_tx_dll_lock, ohssitx_dcc_done, ohssitx_odcc_dll2core, + ojtag_clkdr_out_chain, ojtag_last_bs_out_chain, + ojtag_rx_scan_out_chain, ored_directin_data_out0_chain1, + ored_directin_data_out0_chain2, ored_rxen_out_chain1, + ored_rxen_out_chain2, ored_shift_en_out_chain1, + ored_shift_en_out_chain2, aib_hssi_adapter_rx_pld_rst_n, + aib_hssi_adapter_tx_pld_rst_n, aib_hssi_avmm1_data_in, + aib_hssi_avmm1_data_out, aib_hssi_avmm2_data_in, + aib_hssi_avmm2_data_out, aib_hssi_fsr_data_in, + aib_hssi_fsr_data_out, aib_hssi_fsr_load_in, + aib_hssi_fsr_load_out, aib_hssi_pcs_rx_pld_rst_n, + aib_hssi_pcs_tx_pld_rst_n, aib_hssi_pld_8g_rxelecidle, + aib_hssi_pld_pcs_rx_clk_out, aib_hssi_pld_pcs_rx_clk_out_n, + aib_hssi_pld_pcs_tx_clk_out, aib_hssi_pld_pcs_tx_clk_out_n, + aib_hssi_pld_pma_clkdiv_rx_user, aib_hssi_pld_pma_clkdiv_tx_user, + aib_hssi_pld_pma_coreclkin, aib_hssi_pld_pma_coreclkin_n, + aib_hssi_pld_pma_hclk, aib_hssi_pld_pma_internal_clk1, + aib_hssi_pld_pma_internal_clk2, aib_hssi_pld_pma_pfdmode_lock, + aib_hssi_pld_pma_rxpll_lock, aib_hssi_pld_pma_rxpma_rstb, + aib_hssi_pld_pma_txdetectrx, aib_hssi_pld_pma_txpma_rstb, + aib_hssi_pld_rx_hssi_fifo_latency_pulse, aib_hssi_pld_sclk, + aib_hssi_pld_tx_hssi_fifo_latency_pulse, aib_hssi_pma_aib_tx_clk, + aib_hssi_pma_aib_tx_clk_n, aib_hssi_rx_data_out, + aib_hssi_rx_transfer_clk, aib_hssi_rx_transfer_clk_n, + aib_hssi_sr_clk_in, aib_hssi_sr_clk_n_in, aib_hssi_sr_clk_n_out, + aib_hssi_sr_clk_out, aib_hssi_ssr_data_in, aib_hssi_ssr_data_out, + aib_hssi_ssr_load_in, aib_hssi_ssr_load_out, aib_hssi_tx_data_in, + aib_hssi_tx_transfer_clk, aib_hssi_tx_transfer_clk_n, + aib_shared_direct_async, oshared_direct_async, + iatpg_pipeline_global_en, iatpg_scan_clk_in0, iatpg_scan_clk_in1, + iatpg_scan_in0, iatpg_scan_in1, iatpg_scan_mode_n, + iatpg_scan_rst_n, iatpg_scan_shift_n, iavm1_sr_clk_out, + iavm1in_en0, iavm1in_en1, iavm1in_en2, iavm1out_dataselb, + iavm1out_en, iavm2in_en0, iavm2out_dataselb, iavm2out_en, + ihssi_adapter_rx_pld_rst_n, ihssi_adapter_tx_pld_rst_n, + ihssi_avmm1_data_out, ihssi_avmm2_data_out, ihssi_dcc_dft_nrst, + ihssi_dcc_dft_nrst_coding, ihssi_dcc_dft_up, + ihssi_dcc_dll_core2dll_str, ihssi_dcc_dll_csr_reg, + ihssi_dcc_dll_entest, ihssi_dcc_req, ihssi_fsr_data_out, + ihssi_fsr_load_out, ihssi_pcs_rx_pld_rst_n, + ihssi_pcs_tx_pld_rst_n, ihssi_pld_pma_coreclkin, + ihssi_pld_pma_rxpma_rstb, ihssi_pld_pma_txdetectrx, + ihssi_pld_pma_txpma_rstb, ihssi_pld_sclk, ihssi_rb_clkdiv, + ihssi_rb_dcc_byp, ihssi_rb_dcc_byp_dprio, // Mod : Add dprio rambit + ihssi_rb_dcc_dft, ihssi_rb_dcc_dft_sel, + ihssi_rb_dcc_dll_dft_sel, ihssi_rb_dcc_en, ihssi_rb_dcc_en_dprio, // Mod : Add dprio rambit + ihssi_rb_dcc_manual_dn, + ihssi_rb_dcc_manual_mode, ihssi_rb_dcc_manual_mode_dprio, // Mod : Added dprio rambit + ihssi_rb_dcc_manual_up, + ihssi_rb_dcc_test_clk_pll_en_n, ihssi_rb_dll_test_clk_pll_en_n, + ihssi_rb_half_code, ihssi_rb_selflock, ihssi_ssr_data_out, + ihssi_ssr_load_out, ihssi_tx_data_in, ihssi_tx_dll_lock_req, + ihssi_tx_transfer_clk, ihssirx_async_en, ihssirx_clk_en, + ihssirx_out_dataselb, ihssirx_out_ddren, ihssirx_out_en, + ihssitx_in_en0, ihssitx_in_en1, ihssitx_in_en2, ihssitx_in_en3, + ihssitx_out_dataselb, ihssitx_out_en, ihssitxdll_rb_clkdiv_str, + ihssitxdll_rb_half_code_str, ihssitxdll_rb_selflock_str, + ihssitxdll_str_align_dly_pst, + ihssitxdll_str_align_dyconfig_ctl_static, + ihssitxdll_str_align_dyconfig_ctlsel, ihssitxdll_str_align_entest, + ihssitxdll_str_align_stconfig_core_dn_prgmnvrt, + ihssitxdll_str_align_stconfig_core_up_prgmnvrt, + ihssitxdll_str_align_stconfig_core_updnen, + ihssitxdll_str_align_stconfig_dftmuxsel, + ihssitxdll_str_align_stconfig_dll_en, + ihssitxdll_str_align_stconfig_dll_rst_en, + ihssitxdll_str_align_stconfig_hps_ctrl_en, + ihssitxdll_str_align_stconfig_ndllrst_prgmnvrt, + ihssitxdll_str_align_stconfig_new_dll, + ihssitxdll_str_align_stconfig_spare, ijtag_clkdr_in_chain, + ijtag_last_bs_in_chain, ijtag_tx_scan_in_chain, indrv_r12, + indrv_r34, indrv_r56, indrv_r78, ipdrv_r12, ipdrv_r34, ipdrv_r56, + ipdrv_r78, ired_avm1_shift_en, ired_directin_data_in_chain1, + ired_directin_data_in_chain2, ired_irxen_in_chain1, + ired_irxen_in_chain2, ired_rshift_en_dirclkn, + ired_rshift_en_dirclkp, ired_rshift_en_drx, ired_rshift_en_dtx, + ired_rshift_en_poutp, ired_rshift_en_rx, ired_rshift_en_rx_avmm2, + ired_rshift_en_tx, ired_rshift_en_tx_avmm2, + ired_rshift_en_txferclkout, ired_rshift_en_txferclkoutn, + ired_rx_shift_en, ired_shift_en_in_chain1, + ired_shift_en_in_chain2, irstb, jtag_clksel, jtag_intest, + jtag_mode_in, jtag_rstb, jtag_rstb_en, jtag_tx_scanen_in, + jtag_weakpdn, jtag_weakpu, vccl_aibnd, vssl_aibnd ); + +output jtag_clksel_out, jtag_intest_out, jtag_mode_out, + jtag_rstb_en_out, jtag_rstb_out, jtag_tx_scanen_out, + jtag_weakpdn_out, jtag_weakpu_out, oatpg_scan_out0, + oatpg_scan_out1, ohssi_avmm1_data_in, ohssi_avmm2_data_in, + ohssi_fsr_data_in, ohssi_fsr_load_in, ohssi_pld_8g_rxelecidle, + ohssi_pld_pcs_rx_clk_out, ohssi_pld_pcs_tx_clk_out, + ohssi_pld_pma_clkdiv_rx_user, ohssi_pld_pma_clkdiv_tx_user, + ohssi_pld_pma_hclk, ohssi_pld_pma_internal_clk1, + ohssi_pld_pma_internal_clk2, ohssi_pld_pma_pfdmode_lock, + ohssi_pld_pma_rxpll_lock, ohssi_pld_rx_hssi_fifo_latency_pulse, + ohssi_pld_tx_hssi_fifo_latency_pulse, ohssi_pma_aib_tx_clk, + ohssi_rx_transfer_clk, ohssi_sr_clk_in, ohssi_sr_clk_n_in, + ohssi_ssr_data_in, ohssi_ssr_load_in, ohssi_tx_dll_lock, + ohssitx_dcc_done, ojtag_clkdr_out_chain, ojtag_last_bs_out_chain, + ojtag_rx_scan_out_chain, ored_directin_data_out0_chain1, + ored_directin_data_out0_chain2, ored_shift_en_out_chain1, + ored_shift_en_out_chain2; + +inout aib_hssi_adapter_rx_pld_rst_n, aib_hssi_adapter_tx_pld_rst_n, + aib_hssi_avmm1_data_in, aib_hssi_avmm2_data_in, + aib_hssi_fsr_data_in, aib_hssi_fsr_data_out, aib_hssi_fsr_load_in, + aib_hssi_fsr_load_out, aib_hssi_pcs_rx_pld_rst_n, + aib_hssi_pcs_tx_pld_rst_n, aib_hssi_pld_8g_rxelecidle, + aib_hssi_pld_pcs_rx_clk_out, aib_hssi_pld_pcs_rx_clk_out_n, + aib_hssi_pld_pcs_tx_clk_out, aib_hssi_pld_pcs_tx_clk_out_n, + aib_hssi_pld_pma_clkdiv_rx_user, aib_hssi_pld_pma_clkdiv_tx_user, + aib_hssi_pld_pma_coreclkin, aib_hssi_pld_pma_coreclkin_n, + aib_hssi_pld_pma_hclk, aib_hssi_pld_pma_internal_clk1, + aib_hssi_pld_pma_internal_clk2, aib_hssi_pld_pma_pfdmode_lock, + aib_hssi_pld_pma_rxpll_lock, aib_hssi_pld_pma_rxpma_rstb, + aib_hssi_pld_pma_txdetectrx, aib_hssi_pld_pma_txpma_rstb, + aib_hssi_pld_rx_hssi_fifo_latency_pulse, aib_hssi_pld_sclk, + aib_hssi_pld_tx_hssi_fifo_latency_pulse, aib_hssi_pma_aib_tx_clk, + aib_hssi_pma_aib_tx_clk_n, aib_hssi_rx_transfer_clk, + aib_hssi_rx_transfer_clk_n, aib_hssi_sr_clk_in, + aib_hssi_sr_clk_n_in, aib_hssi_sr_clk_n_out, aib_hssi_sr_clk_out, + aib_hssi_ssr_data_in, aib_hssi_ssr_data_out, aib_hssi_ssr_load_in, + aib_hssi_ssr_load_out, aib_hssi_tx_transfer_clk, + aib_hssi_tx_transfer_clk_n; + +input iatpg_pipeline_global_en, iatpg_scan_clk_in0, + iatpg_scan_clk_in1, iatpg_scan_in0, iatpg_scan_in1, + iatpg_scan_mode_n, iatpg_scan_rst_n, iatpg_scan_shift_n, + iavm1_sr_clk_out, iavm2out_dataselb, iavm2out_en, + ihssi_adapter_rx_pld_rst_n, ihssi_adapter_tx_pld_rst_n, + ihssi_dcc_dft_nrst, ihssi_dcc_dft_nrst_coding, ihssi_dcc_dft_up, + ihssi_dcc_dll_entest, ihssi_dcc_req, ihssi_fsr_data_out, + ihssi_fsr_load_out, ihssi_pcs_rx_pld_rst_n, + ihssi_pcs_tx_pld_rst_n, ihssi_pld_pma_coreclkin, + ihssi_pld_pma_rxpma_rstb, ihssi_pld_pma_txdetectrx, + ihssi_pld_pma_txpma_rstb, ihssi_pld_sclk, ihssi_rb_dcc_byp, ihssi_rb_dcc_byp_dprio, // Mod : Added dprio rambit + ihssi_rb_dcc_dft, ihssi_rb_dcc_dft_sel, ihssi_rb_dcc_dll_dft_sel, + ihssi_rb_dcc_en, ihssi_rb_dcc_en_dprio, // Mod : added dprio rambit + ihssi_rb_dcc_manual_mode, ihssi_rb_dcc_manual_mode_dprio , // Mod : Added dprio rambit + ihssi_rb_dcc_test_clk_pll_en_n, ihssi_rb_dll_test_clk_pll_en_n, + ihssi_rb_half_code, ihssi_rb_selflock, ihssi_ssr_data_out, + ihssi_ssr_load_out, ihssi_tx_dll_lock_req, ihssi_tx_transfer_clk, + ihssirx_out_ddren, ihssitxdll_rb_half_code_str, + ihssitxdll_rb_selflock_str, ihssitxdll_str_align_dyconfig_ctlsel, + ihssitxdll_str_align_entest, + ihssitxdll_str_align_stconfig_core_dn_prgmnvrt, + ihssitxdll_str_align_stconfig_core_up_prgmnvrt, + ihssitxdll_str_align_stconfig_core_updnen, + ihssitxdll_str_align_stconfig_dll_en, + ihssitxdll_str_align_stconfig_dll_rst_en, + ihssitxdll_str_align_stconfig_hps_ctrl_en, + ihssitxdll_str_align_stconfig_ndllrst_prgmnvrt, + ihssitxdll_str_align_stconfig_spare, ijtag_clkdr_in_chain, + ijtag_last_bs_in_chain, ijtag_tx_scan_in_chain, + ired_directin_data_in_chain1, ired_directin_data_in_chain2, + ired_rshift_en_rx_avmm2, ired_rshift_en_txferclkout, + ired_rshift_en_txferclkoutn, ired_shift_en_in_chain1, + ired_shift_en_in_chain2, irstb, jtag_clksel, jtag_intest, + jtag_mode_in, jtag_rstb, jtag_rstb_en, jtag_tx_scanen_in, + jtag_weakpdn, jtag_weakpu, vccl_aibnd, vssl_aibnd; + +output [2:0] ored_rxen_out_chain2; +output [39:0] ohssi_rx_data_out; +output [12:0] ohssitx_odcc_dll2core; +output [2:0] ored_rxen_out_chain1; + +inout [1:0] aib_hssi_avmm2_data_out; +inout [19:0] aib_hssi_tx_data_in; +inout [7:0] aib_shared_direct_async; +inout [19:0] aib_hssi_rx_data_out; +inout [7:0] oshared_direct_async; +inout [1:0] aib_hssi_avmm1_data_out; + +input [2:0] iavm1out_en; +input [2:0] ihssi_dcc_dll_core2dll_str; +input [1:0] indrv_r78; +input [2:0] ihssitx_in_en3; +input [3:0] ihssirx_out_en; +input [2:0] ihssirx_clk_en; +input [2:0] ired_rshift_en_drx; +input [1:0] ipdrv_r78; +input [9:0] ihssitxdll_str_align_dly_pst; +input [36:0] ired_rx_shift_en; +input [51:0] ihssi_dcc_dll_csr_reg; +input [2:0] ihssitx_in_en0; +input [2:0] iavm1out_dataselb; +input [1:0] ipdrv_r34; +input [2:0] ihssitxdll_rb_clkdiv_str; +input [1:0] indrv_r12; +input [2:0] ired_irxen_in_chain2; +input [39:0] ihssi_tx_data_in; +input [3:0] ired_rshift_en_tx; +input [1:0] ihssi_avmm2_data_out; +input [1:0] ired_rshift_en_dirclkp; +input [2:0] iavm1in_en1; +input [2:0] ihssitx_in_en2; +input [1:0] ihssi_avmm1_data_out; +input [2:0] ihssi_rb_clkdiv; +input [14:0] ired_avm1_shift_en; +input [1:0] ipdrv_r12; +input [3:0] ihssirx_out_dataselb; +input [2:0] iavm1in_en2; +input [2:0] ihssirx_async_en; +input [2:0] iavm1in_en0; +input [4:0] ihssi_rb_dcc_manual_up; +input [1:0] ipdrv_r56; +input [1:0] ired_rshift_en_tx_avmm2; +input [9:0] ihssitxdll_str_align_dyconfig_ctl_static; +input [2:0] ired_irxen_in_chain1; +input [2:0] ihssitx_out_en; +input [1:0] indrv_r56; +input [2:0] ihssitxdll_str_align_stconfig_new_dll; +input [2:0] iavm2in_en0; +input [3:0] ired_rshift_en_dtx; +input [1:0] indrv_r34; +input [1:0] ired_rshift_en_dirclkn; +input [19:0] ihssitxdll_str_align_stconfig_dftmuxsel; +input [3:0] ired_rshift_en_rx; +input [2:0] ihssitx_in_en1; +input [2:0] ihssitx_out_dataselb; +input [4:0] ihssi_rb_dcc_manual_dn; +input [19:0] ired_rshift_en_poutp; + +wire jtag_clkdr_mid, ojtag_clkdr_out_chain, ijtag_clkdr_in_chain, clkdr_xr1r, clkdr_xr2r, clkdr_xr2l, clkdr_xr3l, clkdr_xr5r, clkdr_xr6r, clkdr_xr7r, clkdr_xr5l, clkdr_xr6l, clkdr_xr7l, clkdr_xr8r, clkdr_xr4l, clkdr_xr8l, clkdr_xr4r, clkdr_xr3r, clkdr_xr1l, ojtag_last_bs_out_chain, ijtag_last_bs_in_chain, jtag_clksel_out, jtag_clksel, jtag_mode_out, jtag_mode_in, jtag_rstb_en_out, jtag_rstb_en, jtag_rstb_out, jtag_rstb, jtag_weakpdn_out, jtag_weakpdn, jtag_intest_out, jtag_intest, jtag_weakpu_out, jtag_weakpu, jtag_tx_scanen_out, jtag_tx_scanen_in; // Conversion Sript Generated + +wire iatpg_pipeline_global_en_inv; +assign iatpg_pipeline_global_en_inv = !iatpg_pipeline_global_en; + +// Buses in the design + +wire [2:0] irxen_inpdir2; + +wire [2:0] ihssitxdll_str_align_dll_core2dll_str; + +wire [2:0] rxen_inpclk3; + +wire [2:0] rxen_inpdir3; + +wire [2:0] ihssirx_clk_en_buf; + +wire [3:0] ihssirx_out_dataselb_buf; + +wire [1:0] ired_rshift_en_tx_avmm2_buf; + +wire [3:0] avmm1_nc2; + +wire [36:0] ired_rx_shift_en_buf; + +wire [2:0] irxen_pinp0; + +wire [2:0] iavm1in_en2_buf; + +wire [2:0] iavm1in_en1_buf; + +wire [2:0] ihssitx_in_en1_buf; + +wire [14:0] ired_avm1_shift_en_buf; + +wire [2:0] iavm1in_en0_buf; + +wire [2:0] ihssitx_out_en_buf; + +wire [2:0] ihssitx_in_en3_buf; + +wire [2:0] ihssitx_in_en0_buf; + +wire [9:0] ihssitxdll_str_align_dly_pst_buf; + +wire [9:0] ihssitxdll_str_align_dyconfig_ctl_static_buf; + +wire [2:0] ihssitxdll_str_align_stconfig_new_dll_buf; + +wire [19:0] ihssitxdll_str_align_stconfig_dftmuxsel_buf; + +wire [51:0] ihssi_dcc_dll_csr_reg_buf; + +wire [2:0] ihssi_dcc_dll_core2dll_str_buf; + +wire [12:0] ohssitx_odcc_dll2core_in; + +wire [1:0] indrv_r12_buf; + +wire [2:0] irxen_ptxclkin; + +wire [4:0] ihssi_rb_dcc_manual_up_buf; + +wire [4:0] ihssi_rb_dcc_manual_dn_buf; + +wire [2:0] ihssi_rb_clkdiv_buf; + +wire [2:0] ihssitx_out_dataselb_buf; + +wire [1:0] ipdrv_r12_buf; + +wire [1:0] ipdrv_r34_buf; + +wire [1:0] ipdrv_r78_buf; + +wire [1:0] indrv_r78_buf; + +wire [1:0] indrv_r56_buf; + +wire [2:0] ihssitx_in_en2_buf; + +wire [1:0] ipdrv_r56_buf; + +wire [1:0] indrv_r34_buf; + +wire [2:0] ihssirx_async_en_buf; + +wire [3:0] ihssirx_out_en_buf; + +wire [2:0] irxen_inpshared0; + +wire [2:0] ihssitxdll_rb_clkdiv_str_buf; + +wire [2:0] iasyncdata_out; + +wire [12:0] ohssirx_odll_dll2core; + +wire [4:0] odat_async_in; + +wire [2:0] irxen_vinp1; + +wire [2:0] irxen_inpshared4; + +wire [2:0] irxen_vinp0; + +wire [2:0] iavm2in_en0_buf; + +wire [2:0] irxen_inpclk6; + +wire [39:0] ihssi_tx_data_in_buf; + +wire [1:0] ihssi_avmm1_data_out_buf; + +wire [39:0] ohssi_rx_data_out_in; + +wire [2:0] iavm1out_en_buf; + +wire [2:0] iavm1out_dataselb_buf; + +wire [1:0] ihssi_avmm2_data_out_buf; + +wire [39:0] ihssi_tx_data_in_dly; +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_top"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +assign ojtag_clkdr_out_chain = jtag_clkdr_mid; +assign jtag_clkdr_mid = ijtag_clkdr_in_chain; +aibnd_avmm1 xavmm1 ( .clkdr_xr4l(clkdr_xr4l), .clkdr_xr4r(clkdr_xr4r), + .clkdr_xr2r(clkdr_xr2r), .clkdr_xr3l(clkdr_xr3l), + .clkdr_xr3r(clkdr_xr3r), .clkdr_xr1l(clkdr_xr1l), + .clkdr_xr1r(clkdr_xr1r), .clkdr_xr2l(clkdr_xr2l), + .istrbclk_vinp1(istrbclk_vinp1), + .iclkin_dist_vinp1(iclkin_dist_vinp1), + .resetb_sync_buf(avmm_sync_resetb), + .ipdrv_r12(ipdrv_r12_buf[1:0]), .indrv_r12(indrv_r12_buf[1:0]), + .shift_en_srcclkinn(shift_en_srcclkinn), + .shift_en_voutp11(shift_en_voutp11), + .shift_en_voutp10(shift_en_voutp10), + .shift_en_ssrldout(shift_en_ssrldout), + .shift_en_voutp00(shift_en_voutp00), + .shift_en_ptxclkinn(shift_en_ptxclkinn), + .shift_en_ptxclkin(shift_en_ptxclkin), + .shift_en_ssrdout(shift_en_ssrdout), + .shift_en_vinp0(shift_en_vinp0), + .shift_en_oshared2(shift_en_oshared2), + .shift_en_inpshared4(shift_en_inpshared4), + .shift_en_voutp01(shift_en_voutp01), + .itxen_oshared2(itxen_oshared2), + .irxen_inpshared4(irxen_inpshared4[2:0]), + .jtag_rx_scan_oshared2(jtag_rx_scan_oshared2), + .jtag_rx_scan_inpshared4(jtag_rx_scan_inpshared4), + .jtag_clkdr_oshared2(jtag_clkdr_oshared2), + .jtag_clkdr_inpshared4(jtag_clkdr_inpshared4), + .idataselb_oshared2(idataselb_oshared2), + .odat_async_fsrdin(odat_async_fsrdin), + .iasyncdata_oshared2(async_dat_oshared2), + .jtag_clksel(jtag_clksel_out), .jtag_intest(jtag_intest_out), + .jtag_rstb_en(jtag_rstb_en_out), + .odat1_outpclk1_1(odat1_outpclk1_1), + .odat0_outpclk1_1(odat0_outpclk1_1), + .jtag_rx_scan_ptxclkinn(jtag_rx_scan_ptxclkinn), + .jtag_rx_scan_ptxclkin(jtag_rx_scan_ptxclkin), + .jtag_clkdr_ptxclkin(jtag_clkdr_ptxclkin), + .jtag_clkdr_ptxclkinn(jtag_clkdr_ptxclkinn), + .oclk_srclkout(oclk_srclkout), .oclkb_srclkout(oclkb_srclkout), + .jtag_rx_scan_voutp01(jtag_rx_scan_voutp01), + .jtag_clkdr_voutp00(jtag_clkdr_voutp00), + .jtag_clkdr_voutp01(jtag_clkdr_voutp01), + .jtag_rx_scan_vinp0(jtag_rx_scan_vinp0), + .jtag_rx_scan_voutp00(jtag_rx_scan_voutp00), + .jtag_clkdr_vinp0(jtag_clkdr_vinp0), + .itxen_voutp01(itxen_voutp01), .itxen_voutp00(itxen_voutp00), + .istrbclk_vinp0(istrbclk_vinp0), .irxen_vinp0(irxen_vinp0[2:0]), + .ilaunch_clk_voutp01(ilaunch_clk_voutp01), + .ilaunch_clk_voutp00(ilaunch_clk_voutp00), + .idataselb_voutp01(idataselb_voutp01), + .idataselb_voutp00(idataselb_voutp00), + .idat1_voutp01(idat1_voutp01), .idat1_voutp00(idat1_voutp00), + .idat0_voutp01(idat0_voutp01), .idat0_voutp00(idat0_voutp00), + .iclkin_dist_vinp0(iclkin_dist_vinp0), + .pcs_clkb(ohssi_sr_clk_n_in_in), .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd), .oclkn_vinp1(oclkn_vinp1), + .avmm2_tx_launch_clk_l1(avmm2_tx_launch_clk_l1), + .avmm2_tx_launch_clk_l0(avmm2_tx_launch_clk_l0), + .avmm1_rstb(irstb_buf), .avmm_tx_clk_in(iavm1_sr_clk_out_buf), + .ipdrv_r34(ipdrv_r34_buf[1:0]), .indrv_r34(indrv_r34_buf[1:0]), + .idat1_clkn(vssl_aibnd), .idat0_clkn(vccl_aibnd), + .avmm2_rx_strbclk(rx_strbclk), .avmm1_idat1({vssl_aibnd, + vssl_aibnd}), .avmm1_idat0(ihssi_avmm1_data_out_buf[1:0]), + .iopad_avmm1_in(aib_hssi_avmm1_data_in), + .iopad_avmm1_out(aib_hssi_avmm1_data_out[1:0]), + .iopad_clkn(aib_hssi_sr_clk_n_out), + .iopad_clkp(aib_hssi_sr_clk_out), + .iopad_inclkn(aib_hssi_sr_clk_n_in), + .iopad_inclkp(aib_hssi_sr_clk_in), + .iopad_sdr_in({aib_hssi_fsr_data_in, aib_hssi_ssr_data_in, + aib_hssi_fsr_load_in, aib_hssi_ssr_load_in}), + .iopad_sdr_out({aib_hssi_fsr_data_out, aib_hssi_ssr_data_out, + aib_hssi_fsr_load_out, aib_hssi_ssr_load_out}), + .avmm1_odat0(ohssi_avmm1_data_in_in), + .avmm1_odat1(avmm1_odat1_nc), .avmm2_rx_distclk(rx_distclk), + .idata0_ssrdout(idata0_ssrdout), .idata0_ssrldout(data0_ssrldout), + .idata1_ssrdout(idata1_ssrdout), .idata1_ssrldout(data1_ssrldout), + .idataselb_ssrdout(dataselb_ssrdout), + .idataselb_ssrldout(dataselb_ssrldout), + .ilaunch_clk_ssrdout(launch_clk_ssrdout), + .ilaunch_clk_ssrldout(launch_clk_ssrldout), + .itxen_ssrdout(itxen_ssrdout), .itxen_ssrldout(itxen_ssrldout), + .jtag_clkdr_in_srcclkinn(jtag_clkdr_srcclkinn), + .jtag_clkdr_in_ssrdout(jtag_clkdr_in_ssrdout), + .jtag_clkdr_in_ssrldout(jtag_clkdr_in_ssrldout), + .jtag_rx_scan_in_srcclkinn(jtag_rx_scan_srcclkinn), + .jtag_rx_scan_in_ssrdout(jtag_rx_scan_in_ssrdout), + .jtag_rx_scan_in_ssrldout(jtag_rx_scan_in_ssrldout), + .osdrin_odat0({ohssi_fsr_data_in_in, ohssi_ssr_data_in_in, + ohssi_fsr_load_in_in, ohssi_ssr_load_in_in}), + .osdrin_odat1(avmm1_nc2[3:0]), .pcs_clk(ohssi_sr_clk_in_in), + .idat0_clkp(vssl_aibnd), .idat0_voutp10(idat0_voutp10), + .idat0_voutp11(idat0_voutp11), .idat1_clkp(vccl_aibnd), + .idat1_voutp10(idat1_voutp10), .idat1_voutp11(idat1_voutp11), + .idataselb(iavm1out_dataselb_buf[2:0]), + .idataselb_voutp10(idataselb_voutp10), + .idataselb_voutp11(idataselb_voutp11), + .irxen_ptxclkin(irxen_ptxclkin[2:0]), + .irxen_r0(iavm1in_en0_buf[2:0]), .irxen_r1(iavm1in_en1_buf[2:0]), + .irxen_r2(iavm1in_en2_buf[2:0]), + .isdrin_idat0({ihssi_fsr_data_out_buf, ihssi_ssr_data_out_buf, + ihssi_fsr_load_out_buf, ihssi_ssr_load_out_buf}), + .isdrin_idat1({vssl_aibnd, vssl_aibnd, vssl_aibnd, vssl_aibnd}), + .itxen(iavm1out_en_buf[2:0]), .itxen_voutp10(itxen_voutp10), + .itxen_voutp11(itxen_voutp11), + .jtag_clkdr_in_dirin5(jtag_clkdr_in_dirin5), + .jtag_clkdr_in_voutp10(jtag_clkdr_in_voutp10), + .jtag_mode_in(jtag_mode_out), .jtag_rstb(jtag_rstb_out), + .jtag_rx_scan_in_dirin5(jtag_rx_scan_in_dirin5), + .jtag_rx_scan_in_voutp10(jtag_rx_scan_in_voutp10), + .jtag_tx_scanen_in(jtag_tx_scanen_out), + .jtag_weakpdn(jtag_weakpdn_out), .jtag_weakpu(jtag_weakpu_out), + .rx_shift_en(ired_avm1_shift_en_buf[14:0])); +aibnd_avmm2 xavmm2 ( .clkdr_xr4l(clkdr_xr4l), .clkdr_xr3l(clkdr_xr3l), + .clkdr_xr2l(clkdr_xr2l), .avmm_sync_rstb(avmm_sync_resetb), + .shift_en_voutp10(shift_en_voutp10), + .shift_en_voutp11(shift_en_voutp11), + .shift_en_vinp1(shift_en_vinp1), + .shift_en_srcclkinn(shift_en_srcclkinn), + .shift_en_outpdir1_1(shift_en_outpdir1_1), + .shift_en_directout2(shift_en_directout2), + .jtag_clksel(jtag_clksel_out), .jtag_rstb_en(jtag_rstb_en_out), + .jtag_intest(jtag_intest_out), + .odat1_outpdir0_1(odat1_outpdir0_1), + .odat0_outpdir0_1(odat0_outpdir0_1), + .jtag_rx_scan_srcclkinn(jtag_rx_scan_srcclkinn), + .jtag_clkdr_srcclkinn(jtag_clkdr_srcclkinn), + .jtag_rx_scan_vinp1(jtag_rx_scan_vinp1), + .jtag_clkdr_vinp1(jtag_clkdr_vinp1), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), + .tx_launch_clk_l0(avmm2_tx_launch_clk_l0), + .tx_launch_clk_l1(avmm2_tx_launch_clk_l1), + .ipdrv_r34(ipdrv_r34_buf[1:0]), .indrv_r34(indrv_r34_buf[1:0]), + .jtag_clkdr_in_dirin5(jtag_clkdr_in_dirin5), + .idataselb_in0_directout2(idataselb_in0_directout2), + .jtag_rx_scan_out_dirout2(jtag_rx_scan_out_dirout2), + .jtag_rx_scan_out_outpdir1_1(jtag_rx_scan_out_outpdir1_1), + .itxen_in0_directout2(itxen_in0_directout2), + .jtag_rx_scan_in_dirin5(jtag_rx_scan_in_dirin5), + .jtag_clkdr_out_outpdir1_1(jtag_clkdr_out_outpdir1_1), + .jtag_clkdr_out_dirout2(jtag_clkdr_out_dirout2), + .jtag_rx_scan_in_voutp10(jtag_rx_scan_in_voutp10), + .async_dat_outpdir1_1(async_dat_outpdir1_1), + .jtag_clkdr_in_voutp10(jtag_clkdr_in_voutp10), + .irxen_vinp1(irxen_vinp1[2:0]), .idat0_voutp10(idat0_voutp10), + .idat0_voutp11(idat0_voutp11), .idat1_voutp10(idat1_voutp10), + .idat1_voutp11(idat1_voutp11), + .idataselb_voutp10(idataselb_voutp10), + .idirectout_data_outpdir2_1(idirectout_data_outpdir2_1), + .idataselb_outpdir1_1(dataselb_outpdir1_1), + .itxen_outpdir1_1(itxen_outpdir1_1), + .itxen_voutp10(itxen_voutp10), .itxen_voutp11(itxen_voutp11), + .idataselb_voutp11(idataselb_voutp11), + .jtag_mode_in(jtag_mode_out), .jtag_rstb(jtag_rstb_out), + .rx_distclk_vinp1(rx_distclk), + .iopad_avmm2_in(aib_hssi_avmm2_data_in), + .avmm2_odat0(ohssi_avmm2_data_in_in), + .iopad_avmm2_out(aib_hssi_avmm2_data_out[1:0]), + .avmm2_odat1(avmm2_odat1_nc), + .avmm2_idat0(ihssi_avmm2_data_out_buf[1:0]), + .rshift_en_rx(ired_rshift_en_rx_avmm2_buf), + .avmm2_rstb(irstb_buf), .avmm2_idat1({vssl_aibnd, vssl_aibnd}), + .jtag_weakpu(jtag_weakpu_out), .jtag_weakpdn(jtag_weakpdn_out), + .rshift_en_tx(ired_rshift_en_tx_avmm2_buf[1:0]), + .jtag_tx_scanen_in(jtag_tx_scanen_out), + .idataselb(iavm2out_dataselb_buf), + .irxen_r0(iavm2in_en0_buf[2:0]), .itxen(iavm2out_en_buf), + .rx_strbclk_vinp1(rx_strbclk), .oclkn_vinp1(oclkn_vinp1)); +aibnd_rxdatapath_rx xrxdatapath_rx ( + .idatdll_scan_shift_n(iatpg_scan_shift_n_buf), + .clkdr_xr7r(clkdr_xr7r), .clkdr_xr8l(clkdr_xr8l), + .clkdr_xr8r(clkdr_xr8r), .oclkb_inpdir2(oclkb_inpdir2), + .oclk_inpdir2(oclk_inpdir2), .clkdr_xr3l(clkdr_xr3l), + .clkdr_xr3r(clkdr_xr3r), .clkdr_xr4l(clkdr_xr4l), + .clkdr_xr1r(clkdr_xr1r), .clkdr_xr2l(clkdr_xr2l), + .clkdr_xr2r(clkdr_xr2r), .clkdr_xr6l(clkdr_xr6l), + .clkdr_xr6r(clkdr_xr6r), .clkdr_xr7l(clkdr_xr7l), + .clkdr_xr1l(clkdr_xr1l), .clkdr_xr4r(clkdr_xr4r), + .clkdr_xr5l(clkdr_xr5l), .clkdr_xr5r(clkdr_xr5r), + .avmm_sync_rstb(avmm_sync_resetb), + .shift_en_inpdir2(shift_en_inpdir2), + .oclkn_outpdir4_1(oclkn_outpdir4_1), + .odat_async_inpclk4(odat_async_inpclk4), + .odat1_inpdir0(odat1_inpdir0), .odat0_inpdir0(odat0_inpdir0), + .shift_en_inpshared0(shift_en_inpshared0), + .idatdll_rb_clkdiv_str(ihssitxdll_rb_clkdiv_str_buf[2:0]), + .jtag_clkdr_inpclk0n(jtag_clkdr_inpclk0n), + .jtag_rx_scan_inpclk0n(jtag_rx_scan_inpclk0n), + .oclkn_inpclk3(oclkn_inpclk3), + .odat_async_inpclk1(odat_async_inpclk1), + .oclkn_inpdir4(oclkn_inpdir4), .jtag_scan_pinp0(jtag_scan_pinp0), + .jtag_clkdr_pinp0(jtag_clkdr_pinp0), + .istrbclk_pinp0(istrbclk_pinp0), .irxen_pinp0(irxen_pinp0[2:0]), + .irxen_inpshared0(irxen_inpshared0[2:0]), + .idlkin_dist_pinp0(iclkin_dist_pinp0), + .shift_en_inpdir3(shift_en_inpdir3), + .shift_en_inpclk0n(shift_en_inpclk0n), + .shift_en_poutp18(shift_en_poutp18), + .jtag_clkdr_inpclk1n(jtag_clkdr_inpclk1n), + .jtag_rx_scan_inpclk1n(jtag_rx_scan_inpclk1n), + .odat_async_poutp0(odat_async_pout0), + .shift_en_pinp0(shift_en_pinp0), + .shift_en_outpdir0_1(shift_en_outpdir0_1), + .shift_en_outpclk1_1(shift_en_outpclk1_1), + .shift_en_out_chain1(ored_shift_en_out_chain1), + .shift_en_inpclk1n(shift_en_inpclk1n), + .shift_en_inpclk6(shift_en_inpclk6), + .shift_en_dout_clkp(shift_en_dout_clkp), + .shift_en_directout2(shift_en_directout2), + .jtag_scan_out_chain1(ojtag_rx_scan_out_chain), + .jtag_rx_scan_inpclk6(jtag_rx_scan_inpclk6), + .jtag_clkdr_inpclk6(jtag_clkdr_inpclk6), + .shift_en_outpdir6(shift_en_outpdir6), + .irxen_inpclk6(irxen_inpclk6[2:0]), + .jtag_rx_scan_inpshared0(jtag_rx_scan_inpshared0), + .jtag_clkdr_inpshared0(jtag_clkdr_inpshared0), + .jtag_scan_in_chain1(jtag_rx_scan_int), + .shift_en_in_chain1(ired_shift_en_in_chain1), + .shift_en_inpclk3(shift_en_inpclk3), + .shift_en_vinp1(shift_en_vinp1), .shift_en_vinp0(shift_en_vinp0), + .odat_async_oshared1(odat_async_oshared1), + .dft_rx_clk(dft_rx_clk), .jtag_clksel(jtag_clksel_out), + .jtag_intest(jtag_intest_out), .jtag_rstb_en(jtag_rstb_en_out), + .jtag_rx_scan_vinp1(jtag_rx_scan_vinp1), + .jtag_clkdr_vinp0(jtag_clkdr_vinp0), + .jtag_clkdr_vinp1(jtag_clkdr_vinp1), + .jtag_rx_scan_vinp0(jtag_rx_scan_vinp0), + .irxen_vinp1(irxen_vinp1[2:0]), .istrbclk_vinp0(istrbclk_vinp0), + .istrbclk_vinp1(istrbclk_vinp1), .irxen_vinp0(irxen_vinp0[2:0]), + .iclkin_dist_vinp1(iclkin_dist_vinp1), + .iclkin_dist_vinp0(iclkin_dist_vinp0), + .odat1_outpdir0_1(odat1_outpdir0_1), + .odat1_outpclk1_1(odat1_outpclk1_1), + .odat0_outpdir0_1(odat0_outpdir0_1), + .odat0_outpclk1_1(odat0_outpclk1_1), + .jtag_rx_scan_outpdir0_1(jtag_rx_scan_outpdir0_1), + .jtag_rx_scan_outpclk1_1(jtag_rx_scan_outpclk1_1), + .jtag_clkdr_outpdir0_1(jtag_clkdr_outpdir0_1), + .jtag_clkdr_outpclk1_1(jtag_clkdr_outpclk1_1), + .itxen_outpdir0_1(itxen_outpdir0_1), + .itxen_outpclk1_1(itxen_outpclk1_1), + .idataselb_outpclk1_1(idataselb_outpclk1_1), + .idataselb_outpdir0_1(idataselb_outpdir0_1), + .async_dat_outpdir0_1(async_dat_outpdir0_1), + .async_dat_outpclk1_1(async_dat_outpclk1_1), + .idatdll_test_clk_pll_en_n(ihssi_rb_dll_test_clk_pll_en_n_buf), + .idatdll_scan_rst_n(iatpg_scan_rst_n_buf), + .txpma_dig_rstb(irstb_buf), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .rx_shift_en(ired_rx_shift_en_buf[36:0]), + .jtag_clkdr_in_chain1(jtag_clkdr_int), + .odirectin_data_in_chain1(ired_directin_data_in_chain1), + .odirectin_data_out0_chain1(ored_directin_data_out0_chain1), + .last_bs_out_chain1(nc_last_bs_out_chain1), + .jtag_clkdr_out_chain1(nc_jtag_clkdr_out_chain1), + .irxen_in_chain1(ired_irxen_in_chain1[2:0]), + .irxen_chain1(ored_rxen_out_chain1[2:0]), + .iasync_dat_outpdir6(idat0_outpdir6), + .ipdrv_r78(ipdrv_r78_buf[1:0]), .indrv_r56(indrv_r56_buf[1:0]), + .indrv_r78(indrv_r78_buf[1:0]), .ipdrv_r12(ipdrv_r12_buf[1:0]), + .ipdrv_r34(ipdrv_r34_buf[1:0]), .ipdrv_r56(ipdrv_r56_buf[1:0]), + .indrv_r34(indrv_r34_buf[1:0]), .indrv_r12(indrv_r12_buf[1:0]), + .idatdll_entest_str(ihssitxdll_str_align_entest_buf), + .idatdll_scan_mode_n(iatpg_scan_mode_n_buf), + .idatdll_pipeline_global_en(iatpg_pipeline_global_en_buf), + .idatdll_rb_half_code_str(ihssitxdll_rb_half_code_str_buf), + .idatdll_rb_selflock_str(ihssitxdll_rb_selflock_str_buf), + .idatdll_scan_clk_in(iatpg_scan_clk_in0_buf), + .idatdll_scan_in(iatpg_scan_in0_buf), + .iopad_directinclkn(aib_hssi_pld_pcs_rx_clk_out_n), + .iopad_directinclkp(aib_hssi_pld_pcs_rx_clk_out), + .iopad_directoutclkn(aib_hssi_pld_pma_coreclkin_n), + .iopad_directoutclkp(aib_hssi_pld_pma_coreclkin), + .iopad_inclkn(aib_hssi_rx_transfer_clk_n), + .iopad_inclkp(aib_hssi_rx_transfer_clk), + .iopad_indat(aib_hssi_rx_data_out[19:0]), + .idat0_in0_dout_clkp(idat0_in0_dout_clkp), + .idat1_in0_dout_clkp(idat1_in0_dout_clkp), + .idataselb_in0_directout2(idataselb_in0_directout2), + .idataselb_in0_dout_clkp(idataselb_in0_dout_clkp), + .idirectout_data_outpdir2_1(idirectout_data_outpdir2_1), + .ilaunch_clk_in0_dout_clkp(ilaunch_clk_in0_dout_clkp), + .iopad_directout({aib_hssi_pcs_rx_pld_rst_n, + aib_hssi_adapter_rx_pld_rst_n, aib_hssi_pld_pma_rxpma_rstb, + aib_hssi_pld_sclk}), .irxen_inpdir2(irxen_inpdir2[2:0]), + .itxen_in0_directout2(itxen_in0_directout2), + .itxen_in0_dout_clkp(itxen_in0_dout_clkp), + .jtag_clkdr_out_diin_clkp(jtag_clkdr_out_diin_clkp), + .jtag_clkdr_out_directin2(jtag_clkdr_out_directin2), + .jtag_clkdr_out_dirout2(jtag_clkdr_out_dirout2), + .jtag_rx_scan_out_diin_clkp(jtag_rx_scan_out_diin_clkp), + .jtag_rx_scan_out_directin2(jtag_rx_scan_out_directin2), + .jtag_rx_scan_out_dirout2(jtag_rx_scan_out_dirout2), + .odirectin_data({ohssi_pld_pma_clkdiv_rx_user_in, + ohssi_pld_pma_internal_clk1_in, ohssi_pld_pma_internal_clk2_in, + ohssi_pld_pma_hclk_in, ohssi_pld_8g_rxelecidle_in, + ohssi_pld_pma_rxpll_lock_in, + ohssi_pld_rx_hssi_fifo_latency_pulse_in}), + .odll_dll2core_str(ohssirx_odll_dll2core[12:0]), + .odll_lock(ohssi_tx_dll_lock_in), + .out_rx_fast_clk(ohssi_pld_pcs_rx_clk_out_in), + .pcs_clk(ohssi_rx_transfer_clk_in), + .pcs_data_out0({ohssi_rx_data_out_in[38], + ohssi_rx_data_out_in[36], ohssi_rx_data_out_in[34], + ohssi_rx_data_out_in[32], ohssi_rx_data_out_in[30], + ohssi_rx_data_out_in[28], ohssi_rx_data_out_in[26], + ohssi_rx_data_out_in[24], ohssi_rx_data_out_in[22], + ohssi_rx_data_out_in[20], ohssi_rx_data_out_in[18], + ohssi_rx_data_out_in[16], ohssi_rx_data_out_in[14], + ohssi_rx_data_out_in[12], ohssi_rx_data_out_in[10], + ohssi_rx_data_out_in[8], ohssi_rx_data_out_in[6], + ohssi_rx_data_out_in[4], ohssi_rx_data_out_in[2], + ohssi_rx_data_out_in[0]}), + .pcs_data_out1({ohssi_rx_data_out_in[39], + ohssi_rx_data_out_in[37], ohssi_rx_data_out_in[35], + ohssi_rx_data_out_in[33], ohssi_rx_data_out_in[31], + ohssi_rx_data_out_in[29], ohssi_rx_data_out_in[27], + ohssi_rx_data_out_in[25], ohssi_rx_data_out_in[23], + ohssi_rx_data_out_in[21], ohssi_rx_data_out_in[19], + ohssi_rx_data_out_in[17], ohssi_rx_data_out_in[15], + ohssi_rx_data_out_in[13], ohssi_rx_data_out_in[11], + ohssi_rx_data_out_in[9], ohssi_rx_data_out_in[7], + ohssi_rx_data_out_in[5], ohssi_rx_data_out_in[3], + ohssi_rx_data_out_in[1]}), .scan_out(oatpg_scan_out0_in), + .idat0_directoutclkn(vccl_aibnd), + .idat0_directoutclkp(vssl_aibnd), .idat0_poutp18(idat0_poutp18), + .idat1_directoutclkn(vssl_aibnd), + .idat1_directoutclkp(vccl_aibnd), .idat1_poutp18(idat1_poutp18), + .idataselb(ihssitx_out_dataselb_buf[2:0]), + .idataselb_outpdir6(dataselb_outpdir6), + .idataselb_poutp18(dataselb_poutp18), + .idatdll_str_align_dyconfig_ctl_static(ihssitxdll_str_align_dyconfig_ctl_static_buf[9:0]), + .idatdll_str_align_dyconfig_ctlsel(ihssitxdll_str_align_dyconfig_ctlsel_buf), + .idatdll_str_align_stconfig_core_dn_prgmnvrt(ihssitxdll_str_align_stconfig_core_dn_prgmnvrt_buf), + .idatdll_str_align_stconfig_core_up_prgmnvrt(ihssitxdll_str_align_stconfig_core_up_prgmnvrt_buf), + .idatdll_str_align_stconfig_core_updnen(ihssitxdll_str_align_stconfig_core_updnen_buf), + .idatdll_str_align_stconfig_dftmuxsel(ihssitxdll_str_align_stconfig_dftmuxsel_buf[19:0]), + .idatdll_str_align_stconfig_dll_en(ihssitxdll_str_align_stconfig_dll_en_buf), + .idatdll_str_align_stconfig_dll_rst_en(ihssitxdll_str_align_stconfig_dll_rst_en_buf), + .idatdll_str_align_stconfig_hps_ctrl_en(ihssitxdll_str_align_stconfig_hps_ctrl_en_buf), + .idatdll_str_align_stconfig_ndllrst_prgmnvrt(ihssitxdll_str_align_stconfig_ndllrst_prgmnvrt_buf), + .idatdll_str_align_stconfig_new_dll(ihssitxdll_str_align_stconfig_new_dll_buf[2:0]), + .idatdll_str_align_stconfig_spare({ihssitxdll_str_align_stconfig_spare_buf, + ihssitxdll_str_align_dly_pst_buf[9:0]}), + .iddren_poutp18(ddren_poutp18), + .idirectout_data({ihssi_pcs_rx_pld_rst_n_buf, + ihssi_adapter_rx_pld_rst_n_buf, ihssi_pld_pma_rxpma_rstb_buf, + ihssi_pld_sclk_buf}), + .idll_core2dll_str(ihssitxdll_str_align_dll_core2dll_str[2:0]), + .idll_lock_req(ihssi_tx_dll_lock_req_buf), + .ilaunch_clk_poutp18(launch_clk_poutp18), .input_rstb(irstb_buf), + .iopad_direct_input({aib_hssi_pld_pma_clkdiv_rx_user, + aib_hssi_pld_pma_internal_clk1, aib_hssi_pld_pma_internal_clk2, + aib_hssi_pld_pma_hclk, aib_hssi_pld_8g_rxelecidle, + aib_hssi_pld_pma_rxpll_lock, + aib_hssi_pld_rx_hssi_fifo_latency_pulse}), + .irxen_inpclk3(rxen_inpclk3[2:0]), + .irxen_inpdir3(rxen_inpdir3[2:0]), + .irxen_r0(ihssitx_in_en0_buf[2:0]), + .irxen_r1(ihssitx_in_en1_buf[2:0]), + .irxen_r2(ihssitx_in_en2_buf[2:0]), + .irxen_r3(ihssitx_in_en3_buf[2:0]), + .itxen(ihssitx_out_en_buf[2:0]), .itxen_outpdir6(txen_outpdir6), + .itxen_poutp18(txen_poutp18), + .jtag_clkdr_out_inpclk3(jtag_clkdr_out_inpclk3), + .jtag_clkdr_out_inpdir3(jtag_clkdr_out_inpdir3), + .jtag_clkdr_out_outpdir6(jtag_clkdr_out_outpdir6), + .jtag_clkdr_out_poutp18(jtag_clkdr_out_poutp18), + .jtag_mode_in(jtag_mode_out), .jtag_rstb(jtag_rstb_out), + .jtag_rx_scan_out_inpclk3(jtag_rx_scan_out_inpclk3), + .jtag_rx_scan_out_inpdir3(jtag_rx_scan_out_inpdir3), + .jtag_rx_scan_out_outpdir6(jtag_rx_scan_out_outpdir6), + .jtag_rx_scan_out_poutp18(jtag_rx_scan_out_poutp18), + .jtag_tx_scanen_in(jtag_tx_scanen_out), + .jtag_weakpdn(jtag_weakpdn_out), .jtag_weakpu(jtag_weakpu_out), + .oclk_inpclk3(oclk_inpclk3), .oclkb_inpclk3(oclkb_inpclk3), + .poutp_dig_rstb(irstb_buf), + .txdirclk_fast_clkn(ihssi_pld_pma_coreclkin_buf), + .txdirclk_fast_clkp(ihssi_pld_pma_coreclkin_buf)); +aibnd_txdatapath_tx xtxdatapath_tx ( + .iddren(ihssirx_out_ddren_buf), .oclk_inpdir2(oclk_inpdir2), + .oclkb_inpdir2(oclkb_inpdir2), + .odirectin_data_out0_chain2(ored_directin_data_out0_chain2), + .clkdr_xr7r(clkdr_xr7r), .clkdr_xr8l(clkdr_xr8l), + .clkdr_xr8r(clkdr_xr8r), .clkdr_xr6l(clkdr_xr6l), + .clkdr_xr6r(clkdr_xr6r), .clkdr_xr7l(clkdr_xr7l), + .clkdr_xr4r(clkdr_xr4r), .clkdr_xr5l(clkdr_xr5l), + .clkdr_xr5r(clkdr_xr5r), .clkdr_xr3l(clkdr_xr3l), + .clkdr_xr3r(clkdr_xr3r), .clkdr_xr4l(clkdr_xr4l), + .clkdr_xr2r(clkdr_xr2r), .clkdr_xr2l(clkdr_xr2l), + .clkdr_xr1r(clkdr_xr1r), .clkdr_xr1l(clkdr_xr1l), + .jtag_clkdr_in_chain2(vssl_aibnd), + .avmm_sync_rstb(avmm_sync_resetb), + .shift_en_inpclk3(shift_en_inpclk3), + .shift_en_out_chain2(ored_shift_en_out_chain2), + .oclkn_inpdir4(oclkn_inpdir4), + .shift_en_ptxclkinn(shift_en_ptxclkinn), + .odat_async_pout0(odat_async_pout0), + .odat0_inpdir0(odat0_inpdir0), .odat1_inpdir0(odat1_inpdir0), + .odat_async_inpclk1(odat_async_inpclk1), + .odat_async_inpclk4(odat_async_inpclk4), + .oclkb_inpclk3(oclkb_inpclk3), .oclk_inpclk3(oclk_inpclk3), + .irxen_inpclk6(irxen_inpclk6[2:0]), + .jtag_clkdr_inpclk6(jtag_clkdr_inpclk6), + .jtag_rx_scan_inpclk6(jtag_rx_scan_inpclk6), + .shift_en_voutp01(shift_en_voutp01), + .shift_en_outpdir0_1(shift_en_outpdir0_1), + .shift_en_voutp00(shift_en_voutp00), + .rb_clkdiv(ihssi_rb_clkdiv_buf[2:0]), + .scan_shift_n(iatpg_scan_shift_n_buf), + .shift_en_in_chain2(ired_shift_en_in_chain2), + .shift_en_inpclk6(shift_en_inpclk6), + .odat_async_chain2(ired_directin_data_in_chain2), + .jtag_scan_pinp0(jtag_scan_pinp0), + .jtag_scan_in_chain2(ijtag_tx_scan_in_chain), + .shift_en_pinp0(shift_en_pinp0), + .shift_en_inpclk0n(shift_en_inpclk0n), + .shift_en_ssrldout(shift_en_ssrldout), + .oclkn_outpdir4_1(oclkn_outpdir4_1), + .shift_en_ssrdout(shift_en_ssrdout), + .shift_en_outpclk1_1(shift_en_outpclk1_1), + .jtag_clkdr_pinp0(jtag_clkdr_pinp0), + .shift_en_inpclk1n(shift_en_inpclk1n), + .shift_en_outpclk0(shift_en_dout_clkp), + .istrbclk_pinp0(istrbclk_pinp0), .irxen_pinp0(irxen_pinp0[2:0]), + .jtag_rx_scan_inpclk1n(jtag_rx_scan_inpclk1n), + .irxen_in_chain2(ired_irxen_in_chain2[2:0]), + .jtag_clkdr_inpclk1n(jtag_clkdr_inpclk1n), + .shift_en_outpdir6(shift_en_outpdir6), + .shift_en_ptxclkin(shift_en_ptxclkin), + .shift_en_outpdir1_1(shift_en_outpdir1_1), + .iclkin_dist_pinp0(iclkin_dist_pinp0), + .shift_en_poutp18(shift_en_poutp18), + .shift_en_inpdir3(shift_en_inpdir3), + .shift_en_oshared2(shift_en_oshared2), + .shift_en_inpshared4(shift_en_inpshared4), + .jtag_clkdr_inpclk0n(jtag_clkdr_inpclk0n), + .shift_en_inpshared0(shift_en_inpshared0), + .jtag_scan_out_chain2(jtag_rx_scan_int), + .oclkn_inpclk3(oclkn_inpclk3), + .jtag_rx_scan_inpclk0n(jtag_rx_scan_inpclk0n), + .shift_en_inpdir2(shift_en_inpdir2), + .jtag_rx_scan_inpshared0(jtag_rx_scan_inpshared0), + .irxen_inpshared0(irxen_inpshared0[2:0]), + .jtag_clkdr_inpshared0(jtag_clkdr_inpshared0), + .jtag_clkdr_out_chain2(jtag_clkdr_int), + .irxen_chain2(ored_rxen_out_chain2[2:0]), + .odat_async_oshared1(odat_async_oshared1), + .odat_async_fsrdin(odat_async_fsrdin), + .jtag_clkdr_oshared2(jtag_clkdr_oshared2), + .iopad_async_out(aib_shared_direct_async[2:0]), + .iopad_async_in(aib_shared_direct_async[7:3]), + .iasyncdata(iasyncdata_out[2:0]), .odat_async(odat_async_in[4:0]), + .jtag_rx_scan_oshared2(jtag_rx_scan_oshared2), + .jtag_rx_scan_inpshared4(jtag_rx_scan_inpshared4), + .irxen_inpshared4(irxen_inpshared4[2:0]), + .iasyncdata_oshared2(async_dat_oshared2), + .idataselb_oshared2(idataselb_oshared2), + .itxen_oshared2(itxen_oshared2), + .jtag_clkdr_inpshared4(jtag_clkdr_inpshared4), + .dll_csr_reg6(ihssitxdll_str_align_dly_pst_buf[0]), + .dft_rx_clk(dft_rx_clk), .jtag_rstb_en(jtag_rstb_en_out), + .jtag_clksel(jtag_clksel_out), .jtag_intest(jtag_intest_out), + .jtag_rx_scan_outpdir0_1(jtag_rx_scan_outpdir0_1), + .jtag_rx_scan_outpclk1_1(jtag_rx_scan_outpclk1_1), + .jtag_clkdr_outpdir0_1(jtag_clkdr_outpdir0_1), + .jtag_clkdr_outpclk1_1(jtag_clkdr_outpclk1_1), + .itxen_outpdir0_1(itxen_outpdir0_1), + .itxen_outpclk1_1(itxen_outpclk1_1), + .idataselb_outpclk1_1(idataselb_outpclk1_1), + .idataselb_outpdir0_1(idataselb_outpdir0_1), + .async_dat_outpclk1_1(async_dat_outpclk1_1), + .async_dat_outpdir0_1(async_dat_outpdir0_1), + .oclkb_srclkout(oclkb_srclkout), .oclk_srclkout(oclk_srclkout), + .jtag_rx_scan_voutp01(jtag_rx_scan_voutp01), + .jtag_rx_scan_voutp00(jtag_rx_scan_voutp00), + .jtag_clkdr_voutp01(jtag_clkdr_voutp01), + .jtag_clkdr_voutp00(jtag_clkdr_voutp00), + .itxen_voutp01(itxen_voutp01), .itxen_voutp00(itxen_voutp00), + .ipdrv_r12(ipdrv_r12_buf[1:0]), .indrv_r12(indrv_r12_buf[1:0]), + .ilaunch_clk_voutp00(ilaunch_clk_voutp00), + .ilaunch_clk_voutp01(ilaunch_clk_voutp01), + .idat1_voutp01(idat1_voutp01), + .idataselb_voutp00(idataselb_voutp00), + .idataselb_voutp01(idataselb_voutp01), + .idat0_voutp00(idat0_voutp00), .idat0_voutp01(idat0_voutp01), + .idat1_voutp00(idat1_voutp00), + .jtag_rx_scan_ptxclkinn(jtag_rx_scan_ptxclkinn), + .jtag_clkdr_ptxclkin(jtag_clkdr_ptxclkin), + .jtag_clkdr_ptxclkinn(jtag_clkdr_ptxclkinn), + .jtag_rx_scan_ptxclkin(jtag_rx_scan_ptxclkin), + .rb_dcc_test_clk_pll_en_n(ihssi_rb_dcc_test_clk_pll_en_n_buf), + .oaibdftcore2dll(ihssitxdll_str_align_dll_core2dll_str[2:0]), + .idll_dll2core(ohssirx_odll_dll2core[12:0]), + .rb_dcc_dll_dft_sel(ihssi_rb_dcc_dll_dft_sel_buf), + .scan_rst_n(iatpg_scan_rst_n_buf), + .rb_dcc_manual_up(ihssi_rb_dcc_manual_up_buf[4:0]), + .rb_dcc_manual_dn(ihssi_rb_dcc_manual_dn_buf[4:0]), + .iaibdftcore2dll(ihssi_dcc_dll_core2dll_str_buf[2:0]), + .oaibdftdll2core(ohssitx_odcc_dll2core_in[12:0]), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .ipdrv_r34(ipdrv_r34_buf[1:0]), .ipdrv_r56(ipdrv_r56_buf[1:0]), + .indrv_r34(indrv_r34_buf[1:0]), .indrv_r56(indrv_r56_buf[1:0]), + .idat0_in0_dout_clkp(idat0_in0_dout_clkp), + .idat1_in0_dout_clkp(idat1_in0_dout_clkp), + .idataselb_in0_dout_clkp(idataselb_in0_dout_clkp), + .ilaunch_clk_in0_dout_clkp(ilaunch_clk_in0_dout_clkp), + .itxen_in0_dout_clkp(itxen_in0_dout_clkp), + .jtag_clkdr_out_diin_clkp(jtag_clkdr_out_diin_clkp), + .jtag_clkdr_out_directin2(jtag_clkdr_out_directin2), + .jtag_rx_scan_out_diin_clkp(jtag_rx_scan_out_diin_clkp), + .jtag_rx_scan_out_directin2(jtag_rx_scan_out_directin2), + .rshift_en_txferclkout(ired_rshift_en_txferclkout), + .rshift_en_txferclkoutn(ired_rshift_en_txferclkoutn), + .async_dat_outpdir1_1(async_dat_outpdir1_1), + .dcc_done(ohssitx_dcc_done_in), .idat0_outpdir6(idat0_outpdir6), + .idat0_poutp18(idat0_poutp18), .idat1_poutp18(idat1_poutp18), + .idataselb_outpdir1_1(dataselb_outpdir1_1), + .idataselb_outpdir6(dataselb_outpdir6), + .idataselb_poutp18(dataselb_poutp18), + .iddren_poutp18(ddren_poutp18), + .ilaunch_clk_poutp18(launch_clk_poutp18), + .irxen_inpclk3(rxen_inpclk3[2:0]), + .irxen_inpdir3(rxen_inpdir3[2:0]), + .irxen_ptxclkin(irxen_ptxclkin[2:0]), + .itxen_outpdir1_1(itxen_outpdir1_1), + .itxen_outpdir6(txen_outpdir6), .itxen_poutp18(txen_poutp18), + .jtag_clkdr_out_inpclk3(jtag_clkdr_out_inpclk3), + .jtag_clkdr_out_inpdir3(jtag_clkdr_out_inpdir3), + .jtag_clkdr_out_outpdir1_1(jtag_clkdr_out_outpdir1_1), + .jtag_clkdr_out_outpdir6(jtag_clkdr_out_outpdir6), + .jtag_clkdr_out_poutp18(jtag_clkdr_out_poutp18), + .jtag_rx_scan_out_inpclk3(jtag_rx_scan_out_inpclk3), + .jtag_rx_scan_out_inpdir3(jtag_rx_scan_out_inpdir3), + .jtag_rx_scan_out_outpdir1_1(jtag_rx_scan_out_outpdir1_1), + .jtag_rx_scan_out_outpdir6(jtag_rx_scan_out_outpdir6), + .jtag_rx_scan_out_poutp18(jtag_rx_scan_out_poutp18), + .scan_out(oatpg_scan_out1_in), + .csr_reg(ihssi_dcc_dll_csr_reg_buf[51:0]), + .dcc_dft_nrst(ihssi_dcc_dft_nrst_buf), + .dcc_dft_nrst_coding(ihssi_dcc_dft_nrst_coding_buf), + .dcc_dft_up(ihssi_dcc_dft_up_buf), .dcc_req(ihssi_dcc_req_buf), + .idata0_ssrdout(idata0_ssrdout), .idata0_ssrldout(data0_ssrldout), + .idata1_ssrdout(idata1_ssrdout), .idata1_ssrldout(data1_ssrldout), + .idataselb_ssrdout(dataselb_ssrdout), + .idataselb_ssrldout(dataselb_ssrldout), + .idll_entest(ihssi_dcc_dll_entest_buf), + .ilaunch_clk_ssrdout(launch_clk_ssrdout), + .ilaunch_clk_ssrldout(launch_clk_ssrldout), + .irxen_inpdir2(irxen_inpdir2[2:0]), .itxen_ssrdout(itxen_ssrdout), + .itxen_ssrldout(itxen_ssrldout), + .jtag_clkdr_in_ssrdout(jtag_clkdr_in_ssrdout), + .jtag_clkdr_in_ssrldout(jtag_clkdr_in_ssrldout), + .jtag_mode_in(jtag_mode_out), .jtag_rstb(jtag_rstb_out), + .jtag_rx_scan_in_ssrdout(jtag_rx_scan_in_ssrdout), + .jtag_rx_scan_in_ssrldout(jtag_rx_scan_in_ssrldout), + .jtag_tx_scanen_in(jtag_tx_scanen_out), + .jtag_weakpdn(jtag_weakpdn_out), .jtag_weakpu(jtag_weakpu_out), + .pipeline_global_en(iatpg_pipeline_global_en_buf), + .poutp_dig_rstb(irstb_buf), .rb_dcc_byp(ihssi_rb_dcc_byp_buf), + .rb_dcc_byp_dprio(ihssi_rb_dcc_byp_dprio), //Mod : Add DPRIO rambit + .rb_dcc_dft(ihssi_rb_dcc_dft_buf), + .rb_dcc_dft_sel(ihssi_rb_dcc_dft_sel_buf), + .rb_dcc_en(ihssi_rb_dcc_en_buf), + .rb_dcc_en_dprio(ihssi_rb_dcc_en_dprio), + .rb_dcc_manual_mode(ihssi_rb_dcc_manual_mode_buf), + .rb_dcc_manual_mode_dprio(ihssi_rb_dcc_manual_mode_dprio), + .rb_half_code(ihssi_rb_half_code_buf), + .rb_selflock(ihssi_rb_selflock_buf), + .rshift_en_dirclkn(ired_rshift_en_dirclkn[1:0]), + .rshift_en_dirclkp(ired_rshift_en_dirclkp[1:0]), + .rshift_en_drx(ired_rshift_en_drx[2:0]), + .rshift_en_dtx(ired_rshift_en_dtx[3:0]), + .rshift_en_poutp(ired_rshift_en_poutp[19:0]), + .rshift_en_rx(ired_rshift_en_rx[3:0]), + .irxen_r0(ihssirx_clk_en_buf[2:0]), + .irxen_r1(ihssirx_async_en_buf[2:0]), + .scan_mode_n(iatpg_scan_mode_n_buf), + .odirectin_data({ohssi_pld_pma_clkdiv_tx_user_in, + ohssi_pld_pma_pfdmode_lock_in, + ohssi_pld_tx_hssi_fifo_latency_pulse_in}), + .idirectout_data({ihssi_pcs_tx_pld_rst_n_buf, + ihssi_adapter_tx_pld_rst_n_buf, ihssi_pld_pma_txdetectrx_buf, + ihssi_pld_pma_txpma_rstb_buf}), + .out_rx_fast_clk({ohssi_pld_pcs_tx_clk_out_in, + ohssi_pma_aib_tx_clk_in}), .scan_in(iatpg_scan_in1_buf), + .scan_clk_in(iatpg_scan_clk_in1_buf), + .rshift_en_tx(ired_rshift_en_tx[3:0]), + .iopad_direct_input({aib_hssi_pld_pma_clkdiv_tx_user, + aib_hssi_pld_pma_pfdmode_lock, + aib_hssi_pld_tx_hssi_fifo_latency_pulse}), + .output_buffer_clk(ihssi_tx_transfer_clk_buf), + .output_rstb(irstb_buf), .irxen_r2(ihssirx_async_en_buf[2:0]), + .iopad_directinclkn({aib_hssi_pld_pcs_tx_clk_out_n, + aib_hssi_pma_aib_tx_clk_n}), + .iopad_directinclkp({aib_hssi_pld_pcs_tx_clk_out, + aib_hssi_pma_aib_tx_clk}), .iopad_dat(aib_hssi_tx_data_in[19:0]), + .iopad_clkp(aib_hssi_tx_transfer_clk), + .iopad_clkn(aib_hssi_tx_transfer_clk_n), + .iopad_directout({aib_hssi_pcs_tx_pld_rst_n, + aib_hssi_adapter_tx_pld_rst_n, aib_hssi_pld_pma_txdetectrx, + aib_hssi_pld_pma_txpma_rstb}), .idat0({ihssi_tx_data_in_buf[38], + ihssi_tx_data_in_buf[36], ihssi_tx_data_in_buf[34], + ihssi_tx_data_in_buf[32], ihssi_tx_data_in_buf[30], + ihssi_tx_data_in_buf[28], ihssi_tx_data_in_buf[26], + ihssi_tx_data_in_buf[24], ihssi_tx_data_in_buf[22], + ihssi_tx_data_in_buf[20], ihssi_tx_data_in_buf[18], + ihssi_tx_data_in_buf[16], ihssi_tx_data_in_buf[14], + ihssi_tx_data_in_buf[12], ihssi_tx_data_in_buf[10], + ihssi_tx_data_in_buf[8], ihssi_tx_data_in_buf[6], + ihssi_tx_data_in_buf[4], ihssi_tx_data_in_buf[2], + ihssi_tx_data_in_buf[0]}), .idat0_clkn(vccl_aibnd), + .idat0_clkp(vssl_aibnd), .idat1({ihssi_tx_data_in_buf[39], + ihssi_tx_data_in_buf[37], ihssi_tx_data_in_buf[35], + ihssi_tx_data_in_buf[33], ihssi_tx_data_in_buf[31], + ihssi_tx_data_in_buf[29], ihssi_tx_data_in_buf[27], + ihssi_tx_data_in_buf[25], ihssi_tx_data_in_buf[23], + ihssi_tx_data_in_buf[21], ihssi_tx_data_in_buf[19], + ihssi_tx_data_in_buf[17], ihssi_tx_data_in_buf[15], + ihssi_tx_data_in_buf[13], ihssi_tx_data_in_buf[11], + ihssi_tx_data_in_buf[9], ihssi_tx_data_in_buf[7], + ihssi_tx_data_in_buf[5], ihssi_tx_data_in_buf[3], + ihssi_tx_data_in_buf[1]}), .idat1_clkn(vssl_aibnd), + .idat1_clkp(vccl_aibnd), + .idataselb(ihssirx_out_dataselb_buf[3:0]), + .itxen(ihssirx_out_en_buf[3:0])); +aibnd_interface x15 ( .ihssirx_out_ddren_out(ihssirx_out_ddren_buf), + .ihssirx_out_ddren(ihssirx_out_ddren), + .iasyncdata_out(iasyncdata_out[2:0]), + .odat_async(oshared_direct_async[7:3]), + .iasyncdata(oshared_direct_async[2:0]), + .odat_async_in(odat_async_in[4:0]), + .ihssi_adapter_rx_pld_rst_n_out(ihssi_adapter_rx_pld_rst_n_buf), + .ihssi_pcs_rx_pld_rst_n_out(ihssi_pcs_rx_pld_rst_n_buf), + .ihssi_pld_pma_rxpma_rstb_out(ihssi_pld_pma_rxpma_rstb_buf), + .ihssi_pld_sclk_out(ihssi_pld_sclk_buf), + .ihssi_adapter_rx_pld_rst_n(ihssi_adapter_rx_pld_rst_n), + .ihssi_pcs_rx_pld_rst_n(ihssi_pcs_rx_pld_rst_n), + .ihssi_pld_pma_rxpma_rstb(ihssi_pld_pma_rxpma_rstb), + .ihssi_pld_sclk(ihssi_pld_sclk), + .indrv_r12_out(indrv_r12_buf[1:0]), + .indrv_r34_out(indrv_r34_buf[1:0]), + .indrv_r56_out(indrv_r56_buf[1:0]), + .indrv_r78_out(indrv_r78_buf[1:0]), + .ipdrv_r12_out(ipdrv_r12_buf[1:0]), + .ipdrv_r34_out(ipdrv_r34_buf[1:0]), + .ipdrv_r56_out(ipdrv_r56_buf[1:0]), + .ipdrv_r78_out(ipdrv_r78_buf[1:0]), .indrv_r12(indrv_r12[1:0]), + .indrv_r34(indrv_r34[1:0]), .indrv_r56(indrv_r56[1:0]), + .indrv_r78(indrv_r78[1:0]), .ipdrv_r12(ipdrv_r12[1:0]), + .ipdrv_r34(ipdrv_r34[1:0]), .ipdrv_r56(ipdrv_r56[1:0]), + .ipdrv_r78(ipdrv_r78[1:0]), .irstb_out(irstb_buf), .irstb(irstb), + .iavm2in_en0_out(iavm2in_en0_buf[2:0]), + .iavm2out_dataselb_out(iavm2out_dataselb_buf), + .iavm2out_en_out(iavm2out_en_buf), + .ihssi_avmm2_data_out_out(ihssi_avmm2_data_out_buf[1:0]), + .ired_rshift_en_rx_avmm2_out(ired_rshift_en_rx_avmm2_buf), + .ired_rshift_en_tx_avmm2_out(ired_rshift_en_tx_avmm2_buf[1:0]), + .ohssi_avmm2_data_in(ohssi_avmm2_data_in), + .iavm2in_en0(iavm2in_en0[2:0]), + .iavm2out_dataselb(iavm2out_dataselb), .iavm2out_en(iavm2out_en), + .ihssi_avmm2_data_out(ihssi_avmm2_data_out[1:0]), + .ired_rshift_en_rx_avmm2(ired_rshift_en_rx_avmm2), + .ired_rshift_en_tx_avmm2(ired_rshift_en_tx_avmm2[1:0]), + .ohssi_avmm2_data_in_in(ohssi_avmm2_data_in_in), + .iavm1_sr_clk_out_out(iavm1_sr_clk_out_buf), + .iavm1in_en0_out(iavm1in_en0_buf[2:0]), + .iavm1in_en1_out(iavm1in_en1_buf[2:0]), + .iavm1in_en2_out(iavm1in_en2_buf[2:0]), + .iavm1out_dataselb_out(iavm1out_dataselb_buf[2:0]), + .iavm1out_en_out(iavm1out_en_buf[2:0]), + .ihssi_avmm1_data_out_out(ihssi_avmm1_data_out_buf[1:0]), + .ihssi_fsr_data_out_out(ihssi_fsr_data_out_buf), + .ihssi_fsr_load_out_out(ihssi_fsr_load_out_buf), + .ihssi_ssr_data_out_out(ihssi_ssr_data_out_buf), + .ihssi_ssr_load_out_out(ihssi_ssr_load_out_buf), + .ired_avm1_shift_en_out(ired_avm1_shift_en_buf[14:0]), + .ohssi_avmm1_data_in(ohssi_avmm1_data_in), + .ohssi_fsr_data_in(ohssi_fsr_data_in), + .ohssi_fsr_load_in(ohssi_fsr_load_in), + .ohssi_sr_clk_in(ohssi_sr_clk_in), + .ohssi_sr_clk_n_in(ohssi_sr_clk_n_in), + .ohssi_ssr_data_in(ohssi_ssr_data_in), + .ohssi_ssr_load_in(ohssi_ssr_load_in), + .iavm1_sr_clk_out(iavm1_sr_clk_out), + .iavm1in_en0(iavm1in_en0[2:0]), .iavm1in_en1(iavm1in_en1[2:0]), + .iavm1in_en2(iavm1in_en2[2:0]), + .iavm1out_dataselb(iavm1out_dataselb[2:0]), + .iavm1out_en(iavm1out_en[2:0]), + .ihssi_avmm1_data_out(ihssi_avmm1_data_out[1:0]), + .ihssi_fsr_data_out(ihssi_fsr_data_out), + .ihssi_fsr_load_out(ihssi_fsr_load_out), + .ihssi_ssr_data_out(ihssi_ssr_data_out), + .ihssi_ssr_load_out(ihssi_ssr_load_out), + .ired_avm1_shift_en(ired_avm1_shift_en[14:0]), + .ohssi_avmm1_data_in_in(ohssi_avmm1_data_in_in), + .ohssi_fsr_data_in_in(ohssi_fsr_data_in_in), + .ohssi_fsr_load_in_in(ohssi_fsr_load_in_in), + .ohssi_sr_clk_in_in(ohssi_sr_clk_in_in), + .ohssi_sr_clk_n_in_in(ohssi_sr_clk_n_in_in), + .ohssi_ssr_data_in_in(ohssi_ssr_data_in_in), + .ohssi_ssr_load_in_in(ohssi_ssr_load_in_in), + .iatpg_scan_clk_in0_out(iatpg_scan_clk_in0_buf), + .iatpg_scan_in0_out(iatpg_scan_in0_buf), + .ihssi_pld_pma_coreclkin_out(ihssi_pld_pma_coreclkin_buf), + .ihssi_rb_dll_test_clk_pll_en_n_out(ihssi_rb_dll_test_clk_pll_en_n_buf), + .ihssi_tx_dll_lock_req_out(ihssi_tx_dll_lock_req_buf), + .ihssitx_in_en0_out(ihssitx_in_en0_buf[2:0]), + .ihssitx_in_en1_out(ihssitx_in_en1_buf[2:0]), + .ihssitx_in_en2_out(ihssitx_in_en2_buf[2:0]), + .ihssitx_in_en3_out(ihssitx_in_en3_buf[2:0]), + .ihssitx_out_dataselb_out(ihssitx_out_dataselb_buf[2:0]), + .ihssitx_out_en_out(ihssitx_out_en_buf[2:0]), + .ihssitxdll_rb_clkdiv_str_out(ihssitxdll_rb_clkdiv_str_buf[2:0]), + .ihssitxdll_rb_half_code_str_out(ihssitxdll_rb_half_code_str_buf), + .ihssitxdll_rb_selflock_str_out(ihssitxdll_rb_selflock_str_buf), + .ihssitxdll_str_align_dly_pst_out(ihssitxdll_str_align_dly_pst_buf[9:0]), + .ihssitxdll_str_align_dyconfig_ctl_static_out(ihssitxdll_str_align_dyconfig_ctl_static_buf[9:0]), + .ihssitxdll_str_align_dyconfig_ctlsel_out(ihssitxdll_str_align_dyconfig_ctlsel_buf), + .ihssitxdll_str_align_entest_out(ihssitxdll_str_align_entest_buf), + .ihssitxdll_str_align_stconfig_core_dn_prgmnvrt_out(ihssitxdll_str_align_stconfig_core_dn_prgmnvrt_buf), + .ihssitxdll_str_align_stconfig_core_up_prgmnvrt_out(ihssitxdll_str_align_stconfig_core_up_prgmnvrt_buf), + .ihssitxdll_str_align_stconfig_core_updnen_out(ihssitxdll_str_align_stconfig_core_updnen_buf), + .ihssitxdll_str_align_stconfig_dftmuxsel_out(ihssitxdll_str_align_stconfig_dftmuxsel_buf[19:0]), + .ihssitxdll_str_align_stconfig_dll_en_out(ihssitxdll_str_align_stconfig_dll_en_buf), + .ihssitxdll_str_align_stconfig_dll_rst_en_out(ihssitxdll_str_align_stconfig_dll_rst_en_buf), + .ihssitxdll_str_align_stconfig_hps_ctrl_en_out(ihssitxdll_str_align_stconfig_hps_ctrl_en_buf), + .ihssitxdll_str_align_stconfig_ndllrst_prgmnvrt_out(ihssitxdll_str_align_stconfig_ndllrst_prgmnvrt_buf), + .ihssitxdll_str_align_stconfig_new_dll_out(ihssitxdll_str_align_stconfig_new_dll_buf[2:0]), + .ihssitxdll_str_align_stconfig_spare_out(ihssitxdll_str_align_stconfig_spare_buf), + .ired_rx_shift_en_out(ired_rx_shift_en_buf[36:0]), + .oatpg_scan_out0(oatpg_scan_out0), + .ohssi_pld_8g_rxelecidle(ohssi_pld_8g_rxelecidle), + .ohssi_pld_pcs_rx_clk_out(ohssi_pld_pcs_rx_clk_out), + .ohssi_pld_pma_clkdiv_rx_user(ohssi_pld_pma_clkdiv_rx_user), + .ohssi_pld_pma_hclk(ohssi_pld_pma_hclk), + .ohssi_pld_pma_internal_clk1(ohssi_pld_pma_internal_clk1), + .ohssi_pld_pma_internal_clk2(ohssi_pld_pma_internal_clk2), + .ohssi_pld_pma_rxpll_lock(ohssi_pld_pma_rxpll_lock), + .ohssi_pld_rx_hssi_fifo_latency_pulse(ohssi_pld_rx_hssi_fifo_latency_pulse), + .ohssi_rx_data_out(ohssi_rx_data_out[39:0]), + .ohssi_rx_transfer_clk(ohssi_rx_transfer_clk), + .ohssi_tx_dll_lock(ohssi_tx_dll_lock), + .iatpg_scan_clk_in0(iatpg_scan_clk_in0), + .iatpg_scan_in0(iatpg_scan_in0), + .ihssi_pld_pma_coreclkin(ihssi_pld_pma_coreclkin), + .ihssi_rb_dll_test_clk_pll_en_n(ihssi_rb_dll_test_clk_pll_en_n), + .ihssi_tx_dll_lock_req(ihssi_tx_dll_lock_req), + .ihssitx_in_en0(ihssitx_in_en0[2:0]), + .ihssitx_in_en1(ihssitx_in_en1[2:0]), + .ihssitx_in_en2(ihssitx_in_en2[2:0]), + .ihssitx_in_en3(ihssitx_in_en3[2:0]), + .ihssitx_out_dataselb(ihssitx_out_dataselb[2:0]), + .ihssitx_out_en(ihssitx_out_en[2:0]), + .ihssitxdll_rb_clkdiv_str(ihssitxdll_rb_clkdiv_str[2:0]), + .ihssitxdll_rb_half_code_str(ihssitxdll_rb_half_code_str), + .ihssitxdll_rb_selflock_str(ihssitxdll_rb_selflock_str), + .ihssitxdll_str_align_dly_pst(ihssitxdll_str_align_dly_pst[9:0]), + .ihssitxdll_str_align_dyconfig_ctl_static(ihssitxdll_str_align_dyconfig_ctl_static[9:0]), + .ihssitxdll_str_align_dyconfig_ctlsel(ihssitxdll_str_align_dyconfig_ctlsel), + .ihssitxdll_str_align_entest(ihssitxdll_str_align_entest), + .ihssitxdll_str_align_stconfig_core_dn_prgmnvrt(ihssitxdll_str_align_stconfig_core_dn_prgmnvrt), + .ihssitxdll_str_align_stconfig_core_up_prgmnvrt(ihssitxdll_str_align_stconfig_core_up_prgmnvrt), + .ihssitxdll_str_align_stconfig_core_updnen(ihssitxdll_str_align_stconfig_core_updnen), + .ihssitxdll_str_align_stconfig_dftmuxsel(ihssitxdll_str_align_stconfig_dftmuxsel[19:0]), + .ihssitxdll_str_align_stconfig_dll_en(ihssitxdll_str_align_stconfig_dll_en), + .ihssitxdll_str_align_stconfig_dll_rst_en(ihssitxdll_str_align_stconfig_dll_rst_en), + .ihssitxdll_str_align_stconfig_hps_ctrl_en(ihssitxdll_str_align_stconfig_hps_ctrl_en), + .ihssitxdll_str_align_stconfig_ndllrst_prgmnvrt(ihssitxdll_str_align_stconfig_ndllrst_prgmnvrt), + .ihssitxdll_str_align_stconfig_new_dll(ihssitxdll_str_align_stconfig_new_dll[2:0]), + .ihssitxdll_str_align_stconfig_spare(ihssitxdll_str_align_stconfig_spare), + .ired_rx_shift_en(ired_rx_shift_en[36:0]), + .oatpg_scan_out0_in(oatpg_scan_out0_in), + .ohssi_pld_8g_rxelecidle_in(ohssi_pld_8g_rxelecidle_in), + .ohssi_pld_pcs_rx_clk_out_in(ohssi_pld_pcs_rx_clk_out_in), + .ohssi_pld_pma_clkdiv_rx_user_in(ohssi_pld_pma_clkdiv_rx_user_in), + .ohssi_pld_pma_hclk_in(ohssi_pld_pma_hclk_in), + .ohssi_pld_pma_internal_clk1_in(ohssi_pld_pma_internal_clk1_in), + .ohssi_pld_pma_internal_clk2_in(ohssi_pld_pma_internal_clk2_in), + .ohssi_pld_pma_rxpll_lock_in(ohssi_pld_pma_rxpll_lock_in), + .ohssi_pld_rx_hssi_fifo_latency_pulse_in(ohssi_pld_rx_hssi_fifo_latency_pulse_in), + .ohssi_rx_data_out_in(ohssi_rx_data_out_in[39:0]), + .ohssi_rx_transfer_clk_in(ohssi_rx_transfer_clk_in), + .ohssi_tx_dll_lock_in(ohssi_tx_dll_lock_in), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .iatpg_pipeline_global_en_out(iatpg_pipeline_global_en_buf), + .iatpg_scan_clk_in1_out(iatpg_scan_clk_in1_buf), + .iatpg_scan_in1_out(iatpg_scan_in1_buf), + .iatpg_scan_mode_n_out(iatpg_scan_mode_n_buf), + .iatpg_scan_rst_n_out(iatpg_scan_rst_n_buf), + .iatpg_scan_shift_n_out(iatpg_scan_shift_n_buf), + .ihssi_adapter_tx_pld_rst_n_out(ihssi_adapter_tx_pld_rst_n_buf), + .ihssi_dcc_dft_nrst_coding_out(ihssi_dcc_dft_nrst_coding_buf), + .ihssi_dcc_dft_nrst_out(ihssi_dcc_dft_nrst_buf), + .ihssi_dcc_dft_up_out(ihssi_dcc_dft_up_buf), + .ihssi_dcc_dll_core2dll_str_out(ihssi_dcc_dll_core2dll_str_buf[2:0]), + .ihssi_dcc_dll_csr_reg_out(ihssi_dcc_dll_csr_reg_buf[51:0]), + .ihssi_dcc_dll_entest_out(ihssi_dcc_dll_entest_buf), + .ihssi_dcc_req_out(ihssi_dcc_req_buf), + .ihssi_pcs_tx_pld_rst_n_out(ihssi_pcs_tx_pld_rst_n_buf), + .ihssi_pld_pma_txdetectrx_out(ihssi_pld_pma_txdetectrx_buf), + .ihssi_pld_pma_txpma_rstb_out(ihssi_pld_pma_txpma_rstb_buf), + .ihssi_rb_clkdiv_out(ihssi_rb_clkdiv_buf[2:0]), + .ihssi_rb_dcc_byp_out(ihssi_rb_dcc_byp_buf), + .ihssi_rb_dcc_dft_out(ihssi_rb_dcc_dft_buf), + .ihssi_rb_dcc_dft_sel_out(ihssi_rb_dcc_dft_sel_buf), + .ihssi_rb_dcc_dll_dft_sel_out(ihssi_rb_dcc_dll_dft_sel_buf), + .ihssi_rb_dcc_en_out(ihssi_rb_dcc_en_buf), + .ihssi_rb_dcc_manual_dn_out(ihssi_rb_dcc_manual_dn_buf[4:0]), + .ihssi_rb_dcc_manual_mode_out(ihssi_rb_dcc_manual_mode_buf), + .ihssi_rb_dcc_manual_up_out(ihssi_rb_dcc_manual_up_buf[4:0]), + .ihssi_rb_dcc_test_clk_pll_en_n_out(ihssi_rb_dcc_test_clk_pll_en_n_buf), + .ihssi_rb_half_code_out(ihssi_rb_half_code_buf), + .ihssi_rb_selflock_out(ihssi_rb_selflock_buf), + .ihssi_tx_data_in_out(ihssi_tx_data_in_buf[39:0]), + .ihssi_tx_transfer_clk_out(ihssi_tx_transfer_clk_buf), + .ihssirx_async_en_out(ihssirx_async_en_buf[2:0]), + .ihssirx_clk_en_out(ihssirx_clk_en_buf[2:0]), + .ihssirx_out_dataselb_out(ihssirx_out_dataselb_buf[3:0]), + .ihssirx_out_en_out(ihssirx_out_en_buf[3:0]), + .oatpg_scan_out1(oatpg_scan_out1), + .ohssi_pld_pcs_tx_clk_out(ohssi_pld_pcs_tx_clk_out), + .ohssi_pld_pma_clkdiv_tx_user(ohssi_pld_pma_clkdiv_tx_user), + .ohssi_pld_pma_pfdmode_lock(ohssi_pld_pma_pfdmode_lock), + .ohssi_pld_tx_hssi_fifo_latency_pulse(ohssi_pld_tx_hssi_fifo_latency_pulse), + .ohssi_pma_aib_tx_clk(ohssi_pma_aib_tx_clk), + .ohssitx_dcc_done(ohssitx_dcc_done), + .ohssitx_odcc_dll2core(ohssitx_odcc_dll2core[12:0]), + .iatpg_pipeline_global_en(iatpg_pipeline_global_en_inv), + .iatpg_scan_clk_in1(iatpg_scan_clk_in1), + .iatpg_scan_in1(iatpg_scan_in1), + .iatpg_scan_mode_n(iatpg_scan_mode_n), + .iatpg_scan_rst_n(iatpg_scan_rst_n), + .iatpg_scan_shift_n(iatpg_scan_shift_n), + .ihssi_adapter_tx_pld_rst_n(ihssi_adapter_tx_pld_rst_n), + .ihssi_dcc_dft_nrst(ihssi_dcc_dft_nrst), + .ihssi_dcc_dft_nrst_coding(ihssi_dcc_dft_nrst_coding), + .ihssi_dcc_dft_up(ihssi_dcc_dft_up), + .ihssi_dcc_dll_core2dll_str(ihssi_dcc_dll_core2dll_str[2:0]), + .ihssi_dcc_dll_csr_reg(ihssi_dcc_dll_csr_reg[51:0]), + .ihssi_dcc_dll_entest(ihssi_dcc_dll_entest), + .ihssi_dcc_req(ihssi_dcc_req), + .ihssi_pcs_tx_pld_rst_n(ihssi_pcs_tx_pld_rst_n), + .ihssi_pld_pma_txdetectrx(ihssi_pld_pma_txdetectrx), + .ihssi_pld_pma_txpma_rstb(ihssi_pld_pma_txpma_rstb), + .ihssi_rb_clkdiv(ihssi_rb_clkdiv[2:0]), + .ihssi_rb_dcc_byp(ihssi_rb_dcc_byp), + .ihssi_rb_dcc_dft(ihssi_rb_dcc_dft), + .ihssi_rb_dcc_dft_sel(ihssi_rb_dcc_dft_sel), + .ihssi_rb_dcc_dll_dft_sel(ihssi_rb_dcc_dll_dft_sel), + .ihssi_rb_dcc_en(ihssi_rb_dcc_en), + .ihssi_rb_dcc_manual_dn(ihssi_rb_dcc_manual_dn[4:0]), + .ihssi_rb_dcc_manual_mode(ihssi_rb_dcc_manual_mode), + .ihssi_rb_dcc_manual_up(ihssi_rb_dcc_manual_up[4:0]), + .ihssi_rb_dcc_test_clk_pll_en_n(ihssi_rb_dcc_test_clk_pll_en_n), + .ihssi_rb_half_code(ihssi_rb_half_code), + .ihssi_rb_selflock(ihssi_rb_selflock), + .ihssi_tx_data_in(ihssi_tx_data_in_dly[39:0]), + .ihssi_tx_transfer_clk(ihssi_tx_transfer_clk), + .ihssirx_async_en(ihssirx_async_en[2:0]), + .ihssirx_clk_en(ihssirx_clk_en[2:0]), + .ihssirx_out_dataselb(ihssirx_out_dataselb[3:0]), + .ihssirx_out_en(ihssirx_out_en[3:0]), + .oatpg_scan_out1_in(vssl_aibnd), + .ohssi_pld_pcs_tx_clk_out_in(ohssi_pld_pcs_tx_clk_out_in), + .ohssi_pld_pma_clkdiv_tx_user_in(ohssi_pld_pma_clkdiv_tx_user_in), + .ohssi_pld_pma_pfdmode_lock_in(ohssi_pld_pma_pfdmode_lock_in), + .ohssi_pld_tx_hssi_fifo_latency_pulse_in(ohssi_pld_tx_hssi_fifo_latency_pulse_in), + .ohssi_pma_aib_tx_clk_in(ohssi_pma_aib_tx_clk_in), + .ohssitx_dcc_done_in(ohssitx_dcc_done_in), + .ohssitx_odcc_dll2core_in(ohssitx_odcc_dll2core_in[12:0])); + +aibnd_dly_mimic x17 ( .csr_reg6(ihssi_dcc_dll_csr_reg[6]), + .idll_core2dll_1(ihssi_dcc_dll_core2dll_str[1]), .vss_aibnd(vssl_aibnd), + .vcc_aibnd(vccl_aibnd), + .ihssi_tx_data_out_dly(ihssi_tx_data_in_dly[39:0]), + .ihssi_tx_data_out(ihssi_tx_data_in[39:0]), + .rb_dcc_byp(ihssi_rb_dcc_byp), + .rb_dcc_byp_dprio(ihssi_rb_dcc_byp_dprio)); + + +assign clkdr_xr1r = jtag_clkdr_mid; +assign clkdr_xr2r = clkdr_xr1r; +assign clkdr_xr3l = clkdr_xr2l; +assign clkdr_xr6r = clkdr_xr5r; +assign clkdr_xr7r = clkdr_xr6r; +assign clkdr_xr6l = clkdr_xr5l; +assign clkdr_xr7l = clkdr_xr6l; +assign clkdr_xr8r = clkdr_xr7r; +assign clkdr_xr5l = clkdr_xr4l; +assign clkdr_xr4l = clkdr_xr3l; +assign clkdr_xr8l = clkdr_xr7l; +assign clkdr_xr5r = clkdr_xr4r; +assign clkdr_xr4r = clkdr_xr3r; +assign clkdr_xr2l = clkdr_xr1l; +assign clkdr_xr3r = clkdr_xr2r; +assign clkdr_xr1l = jtag_clkdr_mid; +assign ojtag_last_bs_out_chain = ijtag_last_bs_in_chain; +assign jtag_clksel_out = jtag_clksel; +assign jtag_mode_out = jtag_mode_in; +assign jtag_rstb_en_out = jtag_rstb_en; +assign jtag_rstb_out = jtag_rstb; +assign jtag_weakpdn_out = jtag_weakpdn; +assign jtag_intest_out = jtag_intest; +assign jtag_weakpu_out = jtag_weakpu; +assign jtag_tx_scanen_out = jtag_tx_scanen_in; + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_top_wrp.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_top_wrp.v new file mode 100644 index 0000000..ce484da --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_top_wrp.v @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_top_wrp, View - schematic +// LAST TIME SAVED: Apr 8 09:44:04 2015 +// NETLIST TIME: May 12 19:29:56 2015 +`timescale 1ps / 1ps + +module aibnd_top_wrp ( aib65, aib66, aib76, aib79, aib77, aib81, aib91, + aib89, aib90, aib88, aib63, aib64, aib61, aib49, aib56, aib48, + aib55, aib50, aib51, aib57, aib59, aib54, aib52, aib53, aib60, + aib47, aib44, aib67, aib45, aib46, aib58, aib62, aib87, aib86, + aib19, aib41, aib40, aib85, aib84, aib82, aib83, aib95, aib93, + aib94, aib92, aib39, aib43, aib42, aib74, + aib_fabric_adapter_rx_pld_rst_n, aib_fabric_adapter_tx_pld_rst_n, + aib_fabric_avmm1_data_in, aib_fabric_avmm1_data_out, + aib_fabric_avmm2_data_in, aib_fabric_avmm2_data_out, + aib_fabric_fsr_data_in, aib_fabric_fsr_data_out, + aib_fabric_fsr_load_in, aib_fabric_fsr_load_out, + aib_fabric_pcs_rx_pld_rst_n, aib_fabric_pcs_tx_pld_rst_n, + aib_fabric_pld_8g_rxelecidle, aib_fabric_pld_pcs_rx_clk_out, + aib_fabric_pld_pcs_tx_clk_out, aib_fabric_pld_pma_clkdiv_rx_user, + aib_fabric_pld_pma_clkdiv_tx_user, aib_fabric_pld_pma_coreclkin, + aib_fabric_pld_pma_hclk, aib_fabric_pld_pma_internal_clk1, + aib_fabric_pld_pma_internal_clk2, aib_fabric_pld_pma_pfdmode_lock, + aib_fabric_pld_pma_rxpll_lock, aib_fabric_pld_pma_rxpma_rstb, + aib_fabric_pld_pma_txdetectrx, aib_fabric_pld_pma_txpma_rstb, + aib_fabric_pld_rx_hssi_fifo_latency_pulse, aib_fabric_pld_sclk, + aib_fabric_pld_tx_hssi_fifo_latency_pulse, + aib_fabric_pma_aib_tx_clk, aib_fabric_rx_data_in, + aib_fabric_rx_transfer_clk, aib_fabric_tx_sr_clk_out, + aib_fabric_rx_sr_clk_in, aib_fabric_tx_sr_clk_in, + aib_fabric_ssr_data_in, aib_fabric_ssr_load_out, + aib_fabric_tx_data_out, aib_fabric_tx_transfer_clk, + aib_fabric_fpll_shared_direct_async_in, + aib_fabric_fpll_shared_direct_async_out, + aib_fabric_tx_dcd_cal_req, aib_fabric_rx_dll_lock_req, + aib_fabric_rx_dll_lock, aib_fabric_tx_dcd_cal_done, + aib_fabric_csr_rdy_dly_in, r_aib_csr_ctrl_0, r_aib_csr_ctrl_1, + r_aib_csr_ctrl_2, r_aib_csr_ctrl_3, r_aib_csr_ctrl_4, + r_aib_csr_ctrl_5, r_aib_csr_ctrl_6, r_aib_csr_ctrl_7, + r_aib_csr_ctrl_8, r_aib_csr_ctrl_9, r_aib_csr_ctrl_10, + r_aib_csr_ctrl_11, r_aib_csr_ctrl_12, r_aib_csr_ctrl_13, + r_aib_csr_ctrl_14, r_aib_csr_ctrl_15, r_aib_csr_ctrl_16, + r_aib_csr_ctrl_17, r_aib_csr_ctrl_18, r_aib_csr_ctrl_19, + r_aib_csr_ctrl_20, r_aib_csr_ctrl_21, r_aib_csr_ctrl_22, + r_aib_csr_ctrl_23, r_aib_csr_ctrl_24, r_aib_csr_ctrl_25, + r_aib_csr_ctrl_26, r_aib_csr_ctrl_27, r_aib_csr_ctrl_28, + r_aib_csr_ctrl_29, r_aib_csr_ctrl_30, r_aib_csr_ctrl_31, + r_aib_csr_ctrl_32, r_aib_csr_ctrl_33, r_aib_csr_ctrl_34, + r_aib_csr_ctrl_35, r_aib_csr_ctrl_36, r_aib_csr_ctrl_37, + r_aib_csr_ctrl_38, r_aib_csr_ctrl_39, r_aib_csr_ctrl_40, + r_aib_csr_ctrl_41, r_aib_csr_ctrl_42, r_aib_csr_ctrl_43, + r_aib_csr_ctrl_44, r_aib_csr_ctrl_45, r_aib_csr_ctrl_46, + r_aib_csr_ctrl_47, r_aib_csr_ctrl_48, r_aib_csr_ctrl_49, + r_aib_csr_ctrl_50, r_aib_csr_ctrl_51, r_aib_csr_ctrl_52, + r_aib_csr_ctrl_53, r_aib_csr_ctrl_54, r_aib_csr_ctrl_55, + r_aib_csr_ctrl_56, r_aib_csr_ctrl_57, r_aib_dprio_ctrl_0, + r_aib_dprio_ctrl_1, r_aib_dprio_ctrl_2, r_aib_dprio_ctrl_3, + r_aib_dprio_ctrl_4, ired_directin_data_in_chain1, + ired_directin_data_in_chain2, ired_irxen_in_chain1, + ired_irxen_in_chain2, ored_directin_data_out0_chain1, + ored_directin_data_out0_chain2, ored_rxen_out_chain1, + ored_rxen_out_chain2, // vccl_aibnd, vssl_aibnd, + aib_fabric_ssr_data_out, aib_fabric_ssr_load_in, oaibdftdll2core, + ojtag_clkdr_out_chain, ojtag_last_bs_out_chain, + ojtag_rx_scan_out_chain, ijtag_clkdr_in_chain, + ijtag_last_bs_in_chain, ijtag_tx_scan_in_chain, iaibdftcore2dll, + jtag_mode_in, jtag_rstb_en, jtag_rstb, jtag_tx_scanen_in, + jtag_weakpdn, jtag_weakpu, jtag_intest, jtag_clksel, + jtag_mode_out, jtag_rstb_en_out, jtag_rstb_out, + jtag_tx_scanen_out, jtag_weakpdn_out, jtag_weakpu_out, + jtag_intest_out, jtag_clksel_out, iatpg_scan_rst_n, + iatpg_pipeline_global_en, iatpg_scan_mode_n, iatpg_scan_shift_n, + iatpg_scan_clk_in0, iatpg_scan_clk_in1, iatpg_scan_in0, + iatpg_scan_in1, oatpg_scan_out0, oatpg_scan_out1, aib73, aib72, + aib75, aib70, aib71, aib69, aib68, aib18, aib17, aib16, aib15, + aib14, aib13, aib12, aib11, aib10, aib9, aib8, aib7, aib6, aib5, + aib4, aib3, aib2, aib1, aib0, aib78, aib80, aib38, aib37, aib36, + aib35, aib34, aib33, aib32, aib31, aib30, aib29, aib28, aib27, + aib26, aib25, aib24, aib23, aib22, aib21, aib20, + ired_shift_en_in_chain2, ired_shift_en_in_chain1, + ored_shift_en_out_chain1, ored_shift_en_out_chain2 ); + +output aib_fabric_avmm1_data_in, aib_fabric_avmm2_data_in, + aib_fabric_fsr_data_in, aib_fabric_fsr_load_in, + aib_fabric_pld_8g_rxelecidle, aib_fabric_pld_pcs_rx_clk_out, + aib_fabric_pld_pcs_tx_clk_out, aib_fabric_pld_pma_clkdiv_rx_user, + aib_fabric_pld_pma_clkdiv_tx_user, aib_fabric_pld_pma_hclk, + aib_fabric_pld_pma_internal_clk1, + aib_fabric_pld_pma_internal_clk2, aib_fabric_pld_pma_pfdmode_lock, + aib_fabric_pld_pma_rxpll_lock, + aib_fabric_pld_rx_hssi_fifo_latency_pulse, + aib_fabric_pld_tx_hssi_fifo_latency_pulse, + aib_fabric_pma_aib_tx_clk, aib_fabric_rx_dll_lock, + aib_fabric_rx_sr_clk_in, aib_fabric_rx_transfer_clk, + aib_fabric_ssr_data_in, aib_fabric_ssr_load_in, + aib_fabric_tx_dcd_cal_done, aib_fabric_tx_sr_clk_in, + jtag_clksel_out, jtag_intest_out, jtag_mode_out, jtag_rstb_en_out, + jtag_rstb_out, jtag_tx_scanen_out, jtag_weakpdn_out, + jtag_weakpu_out, oatpg_scan_out0, oatpg_scan_out1, + ojtag_clkdr_out_chain, ojtag_last_bs_out_chain, + ojtag_rx_scan_out_chain, ored_directin_data_out0_chain1, + ored_directin_data_out0_chain2, ored_shift_en_out_chain1, + ored_shift_en_out_chain2; + +inout aib0, aib1, aib2, aib3, aib4, aib5, aib6, aib7, aib8, aib9, + aib10, aib11, aib12, aib13, aib14, aib15, aib16, aib17, aib18, + aib19, aib20, aib21, aib22, aib23, aib24, aib25, aib26, aib27, + aib28, aib29, aib30, aib31, aib32, aib33, aib34, aib35, aib36, + aib37, aib38, aib39, aib40, aib41, aib42, aib43, aib44, aib45, + aib46, aib47, aib48, aib49, aib50, aib51, aib52, aib53, aib54, + aib55, aib56, aib57, aib58, aib59, aib60, aib61, aib62, aib63, + aib64, aib65, aib66, aib67, aib68, aib69, aib70, aib71, aib72, + aib73, aib74, aib75, aib76, aib77, aib78, aib79, aib80, aib81, + aib82, aib83, aib84, aib85, aib86, aib87, aib88, aib89, aib90, + aib91, aib92, aib93, aib94, aib95; + +input aib_fabric_adapter_rx_pld_rst_n, + aib_fabric_adapter_tx_pld_rst_n, aib_fabric_csr_rdy_dly_in, + aib_fabric_fsr_data_out, aib_fabric_fsr_load_out, + aib_fabric_pcs_rx_pld_rst_n, aib_fabric_pcs_tx_pld_rst_n, + aib_fabric_pld_pma_coreclkin, aib_fabric_pld_pma_rxpma_rstb, + aib_fabric_pld_pma_txdetectrx, aib_fabric_pld_pma_txpma_rstb, + aib_fabric_pld_sclk, aib_fabric_rx_dll_lock_req, + aib_fabric_ssr_data_out, aib_fabric_ssr_load_out, + aib_fabric_tx_dcd_cal_req, aib_fabric_tx_sr_clk_out, + aib_fabric_tx_transfer_clk, iatpg_pipeline_global_en, + iatpg_scan_clk_in0, iatpg_scan_clk_in1, iatpg_scan_in0, + iatpg_scan_in1, iatpg_scan_mode_n, iatpg_scan_rst_n, + iatpg_scan_shift_n, ijtag_clkdr_in_chain, ijtag_last_bs_in_chain, + ijtag_tx_scan_in_chain, ired_directin_data_in_chain1, + ired_directin_data_in_chain2, ired_shift_en_in_chain1, + ired_shift_en_in_chain2, jtag_clksel, jtag_intest, jtag_mode_in, + jtag_rstb, jtag_rstb_en, jtag_tx_scanen_in, jtag_weakpdn, + jtag_weakpu; + //vccl_aibnd, vssl_aibnd; + +assign vccl_aibnd = 1'b1; +assign vssl_aibnd = 1'b0; + +output [2:0] ored_rxen_out_chain1; +output [2:0] ored_rxen_out_chain2; +output [12:0] oaibdftdll2core; +output [39:0] aib_fabric_rx_data_in; +output [4:0] aib_fabric_fpll_shared_direct_async_in; + +input [7:0] r_aib_csr_ctrl_57; +input [7:0] r_aib_csr_ctrl_51; +input [7:0] r_aib_csr_ctrl_40; +input [7:0] r_aib_csr_ctrl_46; +input [2:0] ired_irxen_in_chain2; +input [7:0] r_aib_csr_ctrl_36; +input [7:0] r_aib_csr_ctrl_42; +input [7:0] r_aib_csr_ctrl_48; +input [7:0] r_aib_csr_ctrl_49; +input [7:0] r_aib_csr_ctrl_44; +input [7:0] r_aib_csr_ctrl_39; +input [7:0] r_aib_csr_ctrl_43; +input [7:0] r_aib_csr_ctrl_38; +input [7:0] r_aib_csr_ctrl_55; +input [7:0] r_aib_csr_ctrl_41; +input [1:0] aib_fabric_avmm2_data_out; +input [7:0] r_aib_csr_ctrl_56; +input [7:0] r_aib_dprio_ctrl_4; +input [7:0] r_aib_csr_ctrl_52; +input [7:0] r_aib_csr_ctrl_54; +input [7:0] r_aib_csr_ctrl_47; +input [2:0] ired_irxen_in_chain1; +input [7:0] r_aib_csr_ctrl_45; +input [39:0] aib_fabric_tx_data_out; +input [7:0] r_aib_csr_ctrl_50; +input [7:0] r_aib_csr_ctrl_53; +input [1:0] aib_fabric_avmm1_data_out; +input [2:0] iaibdftcore2dll; +input [2:0] aib_fabric_fpll_shared_direct_async_out; +input [7:0] r_aib_csr_ctrl_16; +input [7:0] r_aib_dprio_ctrl_0; +input [7:0] r_aib_dprio_ctrl_1; +input [7:0] r_aib_csr_ctrl_33; +input [7:0] r_aib_csr_ctrl_35; +input [7:0] r_aib_csr_ctrl_34; +input [7:0] r_aib_csr_ctrl_26; +input [7:0] r_aib_csr_ctrl_27; +input [7:0] r_aib_dprio_ctrl_2; +input [7:0] r_aib_dprio_ctrl_3; +input [7:0] r_aib_csr_ctrl_30; +input [7:0] r_aib_csr_ctrl_25; +input [7:0] r_aib_csr_ctrl_37; +input [7:0] r_aib_csr_ctrl_28; +input [7:0] r_aib_csr_ctrl_29; +input [7:0] r_aib_csr_ctrl_31; +input [7:0] r_aib_csr_ctrl_23; +input [7:0] r_aib_csr_ctrl_24; +input [7:0] r_aib_csr_ctrl_18; +input [7:0] r_aib_csr_ctrl_15; +input [7:0] r_aib_csr_ctrl_14; +input [7:0] r_aib_csr_ctrl_13; +input [7:0] r_aib_csr_ctrl_12; +input [7:0] r_aib_csr_ctrl_32; +input [7:0] r_aib_csr_ctrl_20; +input [7:0] r_aib_csr_ctrl_21; +input [7:0] r_aib_csr_ctrl_19; +input [7:0] r_aib_csr_ctrl_17; +input [7:0] r_aib_csr_ctrl_22; +input [7:0] r_aib_csr_ctrl_10; +input [7:0] r_aib_csr_ctrl_9; +input [7:0] r_aib_csr_ctrl_1; +input [7:0] r_aib_csr_ctrl_6; +input [7:0] r_aib_csr_ctrl_7; +input [7:0] r_aib_csr_ctrl_8; +input [7:0] r_aib_csr_ctrl_5; +input [7:0] r_aib_csr_ctrl_0; +input [7:0] r_aib_csr_ctrl_3; +input [7:0] r_aib_csr_ctrl_11; +input [7:0] r_aib_csr_ctrl_4; +input [7:0] r_aib_csr_ctrl_2; + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_top_wrp"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +aibnd_top xaibnd_top ( .ihssirx_out_ddren(r_aib_csr_ctrl_24[6]), + .ijtag_tx_scan_in_chain(ijtag_tx_scan_in_chain), + .ojtag_rx_scan_out_chain(ojtag_rx_scan_out_chain), + .iatpg_scan_shift_n(iatpg_scan_shift_n), + .ired_shift_en_in_chain2(ired_shift_en_in_chain2), + .ired_shift_en_in_chain1(ired_shift_en_in_chain1), + .ored_shift_en_out_chain1(ored_shift_en_out_chain1), + .ihssitxdll_rb_clkdiv_str({r_aib_csr_ctrl_22[4], + r_aib_csr_ctrl_18[7:6]}), + .ored_shift_en_out_chain2(ored_shift_en_out_chain2), + .ihssi_rb_clkdiv({r_aib_csr_ctrl_22[3], r_aib_csr_ctrl_25[7:6]}), + .iatpg_scan_in1(iatpg_scan_in1), .iatpg_scan_in0(iatpg_scan_in0), + .iatpg_scan_clk_in1(iatpg_scan_clk_in1), + .oatpg_scan_out0(oatpg_scan_out0), + .oatpg_scan_out1(oatpg_scan_out1), + .iatpg_scan_clk_in0(iatpg_scan_clk_in0), + .jtag_tx_scanen_out(jtag_tx_scanen_out), + .jtag_weakpdn_out(jtag_weakpdn_out), + .jtag_weakpu_out(jtag_weakpu_out), .jtag_rstb_en(jtag_rstb_en), + .jtag_intest_out(jtag_intest_out), .jtag_mode_out(jtag_mode_out), + .jtag_rstb_en_out(jtag_rstb_en_out), + .jtag_rstb_out(jtag_rstb_out), .jtag_clksel_out(jtag_clksel_out), + .jtag_intest(jtag_intest), .jtag_clksel(jtag_clksel), + .ihssi_rb_dcc_manual_dn(r_aib_csr_ctrl_33[4:0]), + .ihssi_rb_dcc_manual_up(r_aib_csr_ctrl_32[4:0]), + .ihssi_rb_dcc_test_clk_pll_en_n(r_aib_csr_ctrl_28[2]), + .ihssi_rb_dll_test_clk_pll_en_n(r_aib_csr_ctrl_21[7]), + .ihssi_rb_dcc_dll_dft_sel(r_aib_csr_ctrl_28[3]), + .iatpg_scan_rst_n(iatpg_scan_rst_n), + .ohssi_sr_clk_n_in(aib_fabric_tx_sr_clk_in), + .aib_shared_direct_async({aib75, aib70, aib71, aib69, aib68, + aib74, aib73, aib72}), + .oshared_direct_async({aib_fabric_fpll_shared_direct_async_in[4:0], + aib_fabric_fpll_shared_direct_async_out[2:0]}), + .aib_hssi_adapter_rx_pld_rst_n(aib65), + .aib_hssi_adapter_tx_pld_rst_n(aib61), + .aib_hssi_avmm1_data_out({aib79, aib78}), + .aib_hssi_avmm2_data_out({aib81, aib80}), + .aib_hssi_fsr_data_out(aib89), .aib_hssi_fsr_load_out(aib88), + .aib_hssi_pcs_rx_pld_rst_n(aib63), + .aib_hssi_pcs_tx_pld_rst_n(aib64), + .aib_hssi_pld_pma_coreclkin(aib57), + .aib_hssi_pld_pma_coreclkin_n(aib59), + .aib_hssi_pld_pma_rxpma_rstb(aib44), + .aib_hssi_pld_pma_txdetectrx(aib67), + .aib_hssi_pld_pma_txpma_rstb(aib45), .aib_hssi_pld_sclk(aib58), + .aib_hssi_rx_transfer_clk(aib41), + .aib_hssi_rx_transfer_clk_n(aib40), .aib_hssi_sr_clk_n_out(aib82), + .aib_hssi_sr_clk_out(aib83), .aib_hssi_ssr_data_out(aib93), + .aib_hssi_ssr_load_out(aib92), .aib_hssi_tx_data_in({aib39, aib38, + aib37, aib36, aib35, aib34, aib33, aib32, aib31, aib30, aib29, + aib28, aib27, aib26, aib25, aib24, aib23, aib22, aib21, aib20}), + .aib_hssi_tx_transfer_clk(aib43), + .aib_hssi_tx_transfer_clk_n(aib42), + .ohssi_avmm1_data_in(aib_fabric_avmm1_data_in), + .ohssi_avmm2_data_in(aib_fabric_avmm2_data_in), + .ohssi_fsr_data_in(aib_fabric_fsr_data_in), + .ohssi_fsr_load_in(aib_fabric_fsr_load_in), + .ohssi_pld_8g_rxelecidle(aib_fabric_pld_8g_rxelecidle), + .ohssi_pld_pcs_rx_clk_out(aib_fabric_pld_pcs_rx_clk_out), + .ohssi_pld_pcs_tx_clk_out(aib_fabric_pld_pcs_tx_clk_out), + .ohssi_pld_pma_clkdiv_rx_user(aib_fabric_pld_pma_clkdiv_rx_user), + .ohssi_pld_pma_clkdiv_tx_user(aib_fabric_pld_pma_clkdiv_tx_user), + .ohssi_pld_pma_hclk(aib_fabric_pld_pma_hclk), + .ohssi_pld_pma_internal_clk1(aib_fabric_pld_pma_internal_clk1), + .ohssi_pld_pma_internal_clk2(aib_fabric_pld_pma_internal_clk2), + .ohssi_pld_pma_pfdmode_lock(aib_fabric_pld_pma_pfdmode_lock), + .ohssi_pld_pma_rxpll_lock(aib_fabric_pld_pma_rxpll_lock), + .ohssi_pld_rx_hssi_fifo_latency_pulse(aib_fabric_pld_rx_hssi_fifo_latency_pulse), + .ohssi_pld_tx_hssi_fifo_latency_pulse(aib_fabric_pld_tx_hssi_fifo_latency_pulse), + .ohssi_pma_aib_tx_clk(aib_fabric_pma_aib_tx_clk), + .ohssi_rx_data_out(aib_fabric_rx_data_in[39:0]), + .ohssi_rx_transfer_clk(aib_fabric_rx_transfer_clk), + .ohssi_sr_clk_in(aib_fabric_rx_sr_clk_in), + .ohssi_ssr_data_in(aib_fabric_ssr_data_in), + .ohssi_ssr_load_in(aib_fabric_ssr_load_in), + .ohssi_tx_dll_lock(aib_fabric_rx_dll_lock), + .ohssitx_dcc_done(aib_fabric_tx_dcd_cal_done), + .ohssitx_odcc_dll2core(oaibdftdll2core[12:0]), + .ojtag_clkdr_out_chain(ojtag_clkdr_out_chain), + .ojtag_last_bs_out_chain(ojtag_last_bs_out_chain), + .ored_directin_data_out0_chain1(ored_directin_data_out0_chain1), + .ored_directin_data_out0_chain2(ored_directin_data_out0_chain2), + .ored_rxen_out_chain1(ored_rxen_out_chain1[2:0]), + .ored_rxen_out_chain2(ored_rxen_out_chain2[2:0]), + .aib_hssi_avmm1_data_in(aib76), .aib_hssi_avmm2_data_in(aib77), + .aib_hssi_fsr_data_in(aib91), .aib_hssi_fsr_load_in(aib90), + .aib_hssi_pld_8g_rxelecidle(aib66), + .aib_hssi_pld_pcs_rx_clk_out(aib53), + .aib_hssi_pld_pcs_rx_clk_out_n(aib54), + .aib_hssi_pld_pcs_tx_clk_out(aib48), + .aib_hssi_pld_pcs_tx_clk_out_n(aib55), + .aib_hssi_pld_pma_clkdiv_rx_user(aib49), + .aib_hssi_pld_pma_clkdiv_tx_user(aib56), + .aib_hssi_pld_pma_hclk(aib50), + .aib_hssi_pld_pma_internal_clk1(aib52), + .aib_hssi_pld_pma_internal_clk2(aib51), + .aib_hssi_pld_pma_pfdmode_lock(aib46), + .aib_hssi_pld_pma_rxpll_lock(aib47), + .aib_hssi_pld_rx_hssi_fifo_latency_pulse(aib60), + .aib_hssi_pld_tx_hssi_fifo_latency_pulse(aib62), + .aib_hssi_pma_aib_tx_clk(aib87), + .aib_hssi_pma_aib_tx_clk_n(aib86), .aib_hssi_rx_data_out({aib19, + aib18, aib17, aib16, aib15, aib14, aib13, aib12, aib11, aib10, + aib9, aib8, aib7, aib6, aib5, aib4, aib3, aib2, aib1, aib0}), + .aib_hssi_sr_clk_in(aib85), .aib_hssi_sr_clk_n_in(aib84), + .aib_hssi_ssr_data_in(aib95), .aib_hssi_ssr_load_in(aib94), + .iatpg_pipeline_global_en(iatpg_pipeline_global_en), + .iatpg_scan_mode_n(iatpg_scan_mode_n), + .iavm1_sr_clk_out(aib_fabric_tx_sr_clk_out), + .iavm1in_en0(r_aib_csr_ctrl_34[2:0]), + .iavm1in_en1(r_aib_csr_ctrl_34[5:3]), + .iavm1in_en2({r_aib_csr_ctrl_34[7:6], r_aib_csr_ctrl_35[0]}), + .iavm1out_dataselb(r_aib_csr_ctrl_35[6:4]), + .iavm1out_en(r_aib_csr_ctrl_35[3:1]), + .iavm2in_en0(r_aib_csr_ctrl_37[2:0]), + .iavm2out_dataselb(r_aib_csr_ctrl_37[4]), + .iavm2out_en(r_aib_csr_ctrl_37[3]), + .ihssi_adapter_rx_pld_rst_n(aib_fabric_adapter_rx_pld_rst_n), + .ihssi_adapter_tx_pld_rst_n(aib_fabric_adapter_tx_pld_rst_n), + .ihssi_avmm1_data_out(aib_fabric_avmm1_data_out[1:0]), + .ihssi_avmm2_data_out(aib_fabric_avmm2_data_out[1:0]), + .ihssi_dcc_dft_nrst(vssl_aibnd), + .ihssi_dcc_dft_nrst_coding(vssl_aibnd), + .ihssi_dcc_dft_up(vssl_aibnd), + .ihssi_dcc_dll_core2dll_str(iaibdftcore2dll[2:0]), + .ihssi_dcc_dll_csr_reg({r_aib_csr_ctrl_31[3:0], + r_aib_csr_ctrl_30[7:0], r_aib_csr_ctrl_29[7:0], + r_aib_csr_ctrl_28[7:4], r_aib_dprio_ctrl_3[2:0], + r_aib_dprio_ctrl_2[7:0], r_aib_csr_ctrl_28[0], + r_aib_csr_ctrl_27[7:0], r_aib_csr_ctrl_26[7:0]}), + .ihssi_dcc_dll_entest(r_aib_csr_ctrl_31[4]), + .ihssi_dcc_req(aib_fabric_tx_dcd_cal_req), + .ihssi_fsr_data_out(aib_fabric_fsr_data_out), + .ihssi_fsr_load_out(aib_fabric_fsr_load_out), + .ihssi_pcs_rx_pld_rst_n(aib_fabric_pcs_rx_pld_rst_n), + .ihssi_pcs_tx_pld_rst_n(aib_fabric_pcs_tx_pld_rst_n), + .ihssi_pld_pma_coreclkin(aib_fabric_pld_pma_coreclkin), + .ihssi_pld_pma_rxpma_rstb(aib_fabric_pld_pma_rxpma_rstb), + .ihssi_pld_pma_txdetectrx(aib_fabric_pld_pma_txdetectrx), + .ihssi_pld_pma_txpma_rstb(aib_fabric_pld_pma_txpma_rstb), + .ihssi_pld_sclk(aib_fabric_pld_sclk), + .ihssi_rb_dcc_byp(r_aib_csr_ctrl_25[5]), + .ihssi_rb_dcc_byp_dprio(r_aib_dprio_ctrl_3[3]), + .ihssi_rb_dcc_dft(r_aib_csr_ctrl_25[4]), + .ihssi_rb_dcc_dft_sel(r_aib_csr_ctrl_25[3]), + .ihssi_rb_dcc_en(r_aib_csr_ctrl_25[2]), + .ihssi_rb_dcc_en_dprio(r_aib_dprio_ctrl_3[4]), + .ihssi_rb_dcc_manual_mode(r_aib_csr_ctrl_25[1]), + .ihssi_rb_dcc_manual_mode_dprio(r_aib_dprio_ctrl_3[5]), + .ihssi_rb_half_code(r_aib_csr_ctrl_25[0]), + .ihssi_rb_selflock(r_aib_csr_ctrl_24[7]), + .ihssi_ssr_data_out(aib_fabric_ssr_data_out), + .ihssi_ssr_load_out(aib_fabric_ssr_load_out), + .ihssi_tx_data_in(aib_fabric_tx_data_out[39:0]), + .ihssi_tx_dll_lock_req(aib_fabric_rx_dll_lock_req), + .ihssi_tx_transfer_clk(aib_fabric_tx_transfer_clk), + .ihssirx_async_en(r_aib_csr_ctrl_24[5:3]), + .ihssirx_clk_en(r_aib_csr_ctrl_24[2:0]), + .ihssirx_out_dataselb(r_aib_csr_ctrl_23[7:4]), + .ihssirx_out_en(r_aib_csr_ctrl_23[3:0]), + .ihssitx_in_en0(r_aib_csr_ctrl_12[2:0]), + .ihssitx_in_en1(r_aib_csr_ctrl_12[5:3]), + .ihssitx_in_en2({r_aib_csr_ctrl_12[7:6], r_aib_csr_ctrl_13[0]}), + .ihssitx_in_en3(r_aib_csr_ctrl_13[3:1]), + .ihssitx_out_dataselb(r_aib_csr_ctrl_13[7:5]), + .ihssitx_out_en(r_aib_csr_ctrl_22[2:0]), + .ihssitxdll_rb_half_code_str(r_aib_csr_ctrl_21[5]), + .ihssitxdll_rb_selflock_str(r_aib_csr_ctrl_21[4]), + .ihssitxdll_str_align_dly_pst({r_aib_csr_ctrl_18[1:0], + r_aib_csr_ctrl_17[7:0]}), + .ihssitxdll_str_align_dyconfig_ctl_static({r_aib_dprio_ctrl_1[1:0], + r_aib_dprio_ctrl_0[7:0]}), + .ihssitxdll_str_align_dyconfig_ctlsel(r_aib_dprio_ctrl_1[2]), + .ihssitxdll_str_align_entest(r_aib_csr_ctrl_21[6]), + .ihssitxdll_str_align_stconfig_core_dn_prgmnvrt(r_aib_csr_ctrl_16[4]), + .ihssitxdll_str_align_stconfig_core_up_prgmnvrt(r_aib_csr_ctrl_16[3]), + .ihssitxdll_str_align_stconfig_core_updnen(r_aib_csr_ctrl_16[5]), + .ihssitxdll_str_align_stconfig_dftmuxsel({r_aib_csr_ctrl_21[3:0], + r_aib_csr_ctrl_20[7:0], r_aib_csr_ctrl_19[7:0]}), + .ihssitxdll_str_align_stconfig_dll_en(r_aib_csr_ctrl_16[1]), + .ihssitxdll_str_align_stconfig_dll_rst_en(r_aib_csr_ctrl_16[0]), + .ihssitxdll_str_align_stconfig_hps_ctrl_en(r_aib_csr_ctrl_16[6]), + .ihssitxdll_str_align_stconfig_ndllrst_prgmnvrt(r_aib_csr_ctrl_16[2]), + .ihssitxdll_str_align_stconfig_new_dll(r_aib_csr_ctrl_18[5:3]), + .ihssitxdll_str_align_stconfig_spare(r_aib_csr_ctrl_18[2]), + .ijtag_clkdr_in_chain(ijtag_clkdr_in_chain), + .ijtag_last_bs_in_chain(ijtag_last_bs_in_chain), + .indrv_r12(r_aib_csr_ctrl_14[1:0]), + .indrv_r34(r_aib_csr_ctrl_14[3:2]), + .indrv_r56(r_aib_csr_ctrl_14[5:4]), + .indrv_r78(r_aib_csr_ctrl_14[7:6]), + .ipdrv_r12(r_aib_csr_ctrl_15[1:0]), + .ipdrv_r34(r_aib_csr_ctrl_15[3:2]), + .ipdrv_r56(r_aib_csr_ctrl_15[5:4]), + .ipdrv_r78(r_aib_csr_ctrl_15[7:6]), + .ired_avm1_shift_en({r_aib_csr_ctrl_5[1], r_aib_csr_ctrl_4[7], + r_aib_csr_ctrl_4[5], r_aib_csr_ctrl_4[1], r_aib_csr_ctrl_4[0], + r_aib_csr_ctrl_4[4], r_aib_csr_ctrl_4[6], r_aib_csr_ctrl_5[0], + r_aib_csr_ctrl_0[7], r_aib_csr_ctrl_1[1], r_aib_csr_ctrl_1[3], + r_aib_csr_ctrl_1[4], r_aib_csr_ctrl_1[2], r_aib_csr_ctrl_1[0], + r_aib_csr_ctrl_0[6]}), + .ired_directin_data_in_chain1(ired_directin_data_in_chain1), + .ired_directin_data_in_chain2(ired_directin_data_in_chain2), + .ired_irxen_in_chain1(ired_irxen_in_chain1[2:0]), + .ired_irxen_in_chain2(ired_irxen_in_chain2[2:0]), + .ired_rshift_en_dirclkn({r_aib_csr_ctrl_2[1], + r_aib_csr_ctrl_4[3]}), + .ired_rshift_en_dirclkp({r_aib_csr_ctrl_2[0], + r_aib_csr_ctrl_4[2]}), .ired_rshift_en_drx({r_aib_csr_ctrl_2[7], + r_aib_csr_ctrl_11[6], r_aib_csr_ctrl_2[2]}), + .ired_rshift_en_dtx({r_aib_csr_ctrl_3[4], r_aib_csr_ctrl_0[0], + r_aib_csr_ctrl_5[7], r_aib_csr_ctrl_8[7]}), + .ired_rshift_en_poutp({r_aib_csr_ctrl_8[5:0], + r_aib_csr_ctrl_7[7:4], r_aib_csr_ctrl_7[1:0], + r_aib_csr_ctrl_6[7:0]}), + .ired_rshift_en_rx(r_aib_csr_ctrl_0[5:2]), + .ired_rshift_en_rx_avmm2(r_aib_csr_ctrl_1[5]), + .ired_rshift_en_tx({r_aib_csr_ctrl_5[3], r_aib_csr_ctrl_5[2], + r_aib_csr_ctrl_5[5], r_aib_csr_ctrl_5[4]}), + .ired_rshift_en_tx_avmm2(r_aib_csr_ctrl_3[7:6]), + .ired_rshift_en_txferclkout(r_aib_csr_ctrl_7[2]), + .ired_rshift_en_txferclkoutn(r_aib_csr_ctrl_7[3]), + .ired_rx_shift_en({r_aib_csr_ctrl_11[7], r_aib_csr_ctrl_2[3], + r_aib_csr_ctrl_11[5:0], r_aib_csr_ctrl_10[7:0], + r_aib_csr_ctrl_9[7:0], r_aib_csr_ctrl_8[6], r_aib_csr_ctrl_1[7:6], + r_aib_csr_ctrl_3[5], r_aib_csr_ctrl_2[5:4], r_aib_csr_ctrl_3[1], + r_aib_csr_ctrl_3[3:2], r_aib_csr_ctrl_0[1], r_aib_csr_ctrl_3[0], + r_aib_csr_ctrl_2[6], r_aib_csr_ctrl_5[6]}), + .irstb(aib_fabric_csr_rdy_dly_in), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scanen_in(jtag_tx_scanen_in), + .jtag_weakpdn(jtag_weakpdn), .jtag_weakpu(jtag_weakpu), + .vccl_aibnd(vccl_aibnd), .vssl_aibnd(vssl_aibnd)); + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_triinv_dig_str.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_triinv_dig_str.v new file mode 100644 index 0000000..4bbcf57 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_triinv_dig_str.v @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_triinv_dig_str, View - schematic +// LAST TIME SAVED: May 19 10:54:10 2015 +// NETLIST TIME: May 19 12:48:22 2015 +//`timescale 1ns / 1ns + +module aibnd_triinv_dig_str ( dat_out, dat_in, en, enb); + +output dat_out; + +input dat_in, en, enb; + +assign vccl_aibnd = 1'b1; +assign vssl_aibnd = 1'b0; + +//specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_triinv_dig_str"; +// specparam CDS_VIEWNAME = "schematic"; +//endspecify + +assign dat_out = ((en == 1'b1) & (enb == 1'b0))? ~dat_in : 1'bz; + +endmodule diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_txanlg.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_txanlg.v new file mode 100644 index 0000000..d12f152 --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_txanlg.v @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Verilog HDL and netlist files of +// "aibnd_lib aibnd_txanlg schematic" + + +// alias module. For internal use only. +//hdlFilesDir/cds_alias.v + +// Library - aibnd_lib, Cell - aibnd_txanlg, View - schematic +// LAST TIME SAVED: Sep 10 18:08:54 2014 +// NETLIST TIME: Sep 11 16:10:47 2014 +//`timescale 1ps / 1ps + +module aibnd_txanlg ( txpadout, vccl_aibnd, vssl_aibnd, din, ndrv_enb, pdrv_en, + weak_pulldownen, weak_pullupenb ); + +inout txpadout; + +input din, weak_pulldownen, weak_pullupenb; +input vccl_aibnd, vssl_aibnd; +input [15:0] ndrv_enb; +input [15:0] pdrv_en; + +// Buses in the design + +wire [15:0] ngin; + +wire [15:0] pgin; + + +wire txpadout; + +//specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_txanlg"; +// specparam CDS_VIEWNAME = "schematic"; +//endspecify + +//need to gate txpadout with vccl and vssl in future +// wek_pulldownen Vs. (pdrv_en and ndrv_enb) are mutually exclusive in txdig. No X check. +// weak_pulldownen = 1 and weak_pullupenb =1 is weak pulldown. +// weak_pulldownen = 0 and weak_pullupenb =0 is weak pull up. +//Other condition is high Z. +assign (weak0, weak1) txpadout = ((weak_pulldownen & weak_pullupenb) == 1'b1) ? 1'b0: (((weak_pulldownen | weak_pullupenb) == 1'b0)? 1'b1: 1'bz); +assign txpadout = (|pdrv_en & din)? 1'b1: 1'bz; +assign txpadout = (~&ndrv_enb & ~din)? 1'b0: 1'bz; +endmodule + + +// End HDL models + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_txdat_mimic.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_txdat_mimic.v new file mode 100644 index 0000000..16a76ab --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_txdat_mimic.v @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module aibnd_txdat_mimic ( + input wire vccl_aibnd, + input wire vssl_aibnd, + input wire idata_in, + output wire idata_out +); + +assign idata_out = idata_in; + +endmodule diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_txdatapath_tx.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_txdatapath_tx.v new file mode 100644 index 0000000..136c8fd --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_txdatapath_tx.v @@ -0,0 +1,2334 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_txdatapath_tx, View - schematic +// LAST TIME SAVED: Jul 7 15:46:47 2015 +// NETLIST TIME: Jul 8 13:09:52 2015 +// `timescale 1ns / 1ns + +module aibnd_txdatapath_tx ( async_dat_outpdir1_1, dcc_done, + dft_rx_clk, iasyncdata_oshared2, idat0_outpdir6, idat0_poutp18, + idat1_poutp18, idataselb_oshared2, idataselb_outpdir1_1, + idataselb_outpdir6, idataselb_poutp18, iddren_poutp18, + ilaunch_clk_poutp18, irxen_chain2, irxen_inpclk3, irxen_inpdir3, + irxen_inpshared0, irxen_inpshared4, irxen_ptxclkin, + itxen_oshared2, itxen_outpdir1_1, itxen_outpdir6, itxen_poutp18, + jtag_clkdr_inpclk0n, jtag_clkdr_inpshared0, jtag_clkdr_inpshared4, + jtag_clkdr_oshared2, jtag_clkdr_out_chain2, + jtag_clkdr_out_inpclk3, jtag_clkdr_out_inpdir3, + jtag_clkdr_out_outpdir1_1, jtag_clkdr_out_outpdir6, + jtag_clkdr_out_poutp18, jtag_clkdr_ptxclkin, jtag_clkdr_ptxclkinn, + jtag_rx_scan_inpclk0n, jtag_rx_scan_inpshared0, + jtag_rx_scan_inpshared4, jtag_rx_scan_oshared2, + jtag_rx_scan_out_inpclk3, jtag_rx_scan_out_inpdir3, + jtag_rx_scan_out_outpdir1_1, jtag_rx_scan_out_outpdir6, + jtag_rx_scan_out_poutp18, jtag_rx_scan_ptxclkin, + jtag_rx_scan_ptxclkinn, jtag_scan_out_chain2, oaibdftcore2dll, + oaibdftdll2core, oclk_inpclk3, oclkb_inpclk3, oclkn_inpclk3, + oclkn_outpdir4_1, odat0_inpdir0, odat1_inpdir0, odat_async, + odat_async_oshared1, odat_async_pout0, odirectin_data, + odirectin_data_out0_chain2, out_rx_fast_clk, scan_out, + shift_en_inpclk0n, shift_en_inpclk3, shift_en_inpdir3, + shift_en_inpshared0, shift_en_inpshared4, shift_en_oshared2, + shift_en_out_chain2, shift_en_outpdir1_1, shift_en_outpdir6, + shift_en_poutp18, shift_en_ptxclkin, shift_en_ptxclkinn, + iopad_async_in, iopad_async_out, iopad_clkn, iopad_clkp, + iopad_dat, iopad_direct_input, iopad_directinclkn, + iopad_directinclkp, iopad_directout, async_dat_outpclk1_1, + async_dat_outpdir0_1, avmm_sync_rstb, clkdr_xr1l, clkdr_xr1r, + clkdr_xr2l, clkdr_xr2r, clkdr_xr3l, clkdr_xr3r, clkdr_xr4l, + clkdr_xr4r, clkdr_xr5l, clkdr_xr5r, clkdr_xr6l, clkdr_xr6r, + clkdr_xr7l, clkdr_xr7r, clkdr_xr8l, clkdr_xr8r, csr_reg, + dcc_dft_nrst, dcc_dft_nrst_coding, dcc_dft_up, dcc_req, + dll_csr_reg6, iaibdftcore2dll, iasyncdata, iclkin_dist_pinp0, + idat0, idat0_clkn, idat0_clkp, idat0_in0_dout_clkp, idat0_voutp00, + idat0_voutp01, idat1, idat1_clkn, idat1_clkp, idat1_in0_dout_clkp, + idat1_voutp00, idat1_voutp01, idata0_ssrdout, idata0_ssrldout, + idata1_ssrdout, idata1_ssrldout, idataselb, + idataselb_in0_dout_clkp, idataselb_outpclk1_1, + idataselb_outpdir0_1, idataselb_ssrdout, idataselb_ssrldout, + idataselb_voutp00, idataselb_voutp01, iddren, idirectout_data, + idll_dll2core, idll_entest, ilaunch_clk_in0_dout_clkp, + ilaunch_clk_ssrdout, ilaunch_clk_ssrldout, ilaunch_clk_voutp00, + ilaunch_clk_voutp01, indrv_r12, indrv_r34, indrv_r56, ipdrv_r12, + ipdrv_r34, ipdrv_r56, irxen_in_chain2, irxen_inpclk6, + irxen_inpdir2, irxen_pinp0, irxen_r0, irxen_r1, irxen_r2, + istrbclk_pinp0, itxen, itxen_in0_dout_clkp, itxen_outpclk1_1, + itxen_outpdir0_1, itxen_ssrdout, itxen_ssrldout, itxen_voutp00, + itxen_voutp01, jtag_clkdr_in_chain2, jtag_clkdr_in_ssrdout, + jtag_clkdr_in_ssrldout, jtag_clkdr_inpclk1n, jtag_clkdr_inpclk6, + jtag_clkdr_out_diin_clkp, jtag_clkdr_out_directin2, + jtag_clkdr_outpclk1_1, jtag_clkdr_outpdir0_1, jtag_clkdr_pinp0, + jtag_clkdr_voutp00, jtag_clkdr_voutp01, jtag_clksel, jtag_intest, + jtag_mode_in, jtag_rstb, jtag_rstb_en, jtag_rx_scan_in_ssrdout, + jtag_rx_scan_in_ssrldout, jtag_rx_scan_inpclk1n, + jtag_rx_scan_inpclk6, jtag_rx_scan_out_diin_clkp, + jtag_rx_scan_out_directin2, jtag_rx_scan_outpclk1_1, + jtag_rx_scan_outpdir0_1, jtag_rx_scan_voutp00, + jtag_rx_scan_voutp01, jtag_scan_in_chain2, jtag_scan_pinp0, + jtag_tx_scanen_in, jtag_weakpdn, jtag_weakpu, oclk_inpdir2, + oclk_srclkout, oclkb_inpdir2, oclkb_srclkout, oclkn_inpdir4, + odat_async_chain2, odat_async_fsrdin, odat_async_inpclk1, + odat_async_inpclk4, output_buffer_clk, output_rstb, + pipeline_global_en, poutp_dig_rstb, rb_clkdiv, rb_dcc_byp, + rb_dcc_byp_dprio, // Mod : Added new port + rb_dcc_dft, rb_dcc_dft_sel, rb_dcc_dll_dft_sel, rb_dcc_en, + rb_dcc_en_dprio, //Mod : Added new port + rb_dcc_manual_dn, rb_dcc_manual_mode, + rb_dcc_manual_mode_dprio, // Mod : Added new port + rb_dcc_manual_up, + rb_dcc_test_clk_pll_en_n, rb_half_code, rb_selflock, + rshift_en_dirclkn, rshift_en_dirclkp, rshift_en_drx, + rshift_en_dtx, rshift_en_poutp, rshift_en_rx, rshift_en_tx, + rshift_en_txferclkout, rshift_en_txferclkoutn, scan_clk_in, + scan_in, scan_mode_n, scan_rst_n, scan_shift_n, + shift_en_in_chain2, shift_en_inpclk1n, shift_en_inpclk6, + shift_en_inpdir2, shift_en_outpclk0, shift_en_outpclk1_1, + shift_en_outpdir0_1, shift_en_pinp0, shift_en_ssrdout, + shift_en_ssrldout, shift_en_voutp00, shift_en_voutp01, vccl_aibnd, + vssl_aibnd ); + +output async_dat_outpdir1_1, dcc_done, dft_rx_clk, + iasyncdata_oshared2, idat0_outpdir6, idat0_poutp18, idat1_poutp18, + idataselb_oshared2, idataselb_outpdir1_1, idataselb_outpdir6, + idataselb_poutp18, iddren_poutp18, ilaunch_clk_poutp18, + itxen_oshared2, itxen_outpdir1_1, itxen_outpdir6, itxen_poutp18, + jtag_clkdr_inpclk0n, jtag_clkdr_inpshared0, jtag_clkdr_inpshared4, + jtag_clkdr_oshared2, jtag_clkdr_out_chain2, + jtag_clkdr_out_inpclk3, jtag_clkdr_out_inpdir3, + jtag_clkdr_out_outpdir1_1, jtag_clkdr_out_outpdir6, + jtag_clkdr_out_poutp18, jtag_clkdr_ptxclkin, jtag_clkdr_ptxclkinn, + jtag_rx_scan_inpclk0n, jtag_rx_scan_inpshared0, + jtag_rx_scan_inpshared4, jtag_rx_scan_oshared2, + jtag_rx_scan_out_inpclk3, jtag_rx_scan_out_inpdir3, + jtag_rx_scan_out_outpdir1_1, jtag_rx_scan_out_outpdir6, + jtag_rx_scan_out_poutp18, jtag_rx_scan_ptxclkin, + jtag_rx_scan_ptxclkinn, jtag_scan_out_chain2, oclk_inpclk3, + oclkb_inpclk3, oclkn_inpclk3, oclkn_outpdir4_1, odat0_inpdir0, + odat1_inpdir0, odat_async_oshared1, odat_async_pout0, + odirectin_data_out0_chain2, scan_out, shift_en_inpclk0n, + shift_en_inpclk3, shift_en_inpdir3, shift_en_inpshared0, + shift_en_inpshared4, shift_en_oshared2, shift_en_out_chain2, + shift_en_outpdir1_1, shift_en_outpdir6, shift_en_poutp18, + shift_en_ptxclkin, shift_en_ptxclkinn; + +inout iopad_clkn, iopad_clkp; + +input async_dat_outpclk1_1, async_dat_outpdir0_1, avmm_sync_rstb, + clkdr_xr1l, clkdr_xr1r, clkdr_xr2l, clkdr_xr2r, clkdr_xr3l, + clkdr_xr3r, clkdr_xr4l, clkdr_xr4r, clkdr_xr5l, clkdr_xr5r, + clkdr_xr6l, clkdr_xr6r, clkdr_xr7l, clkdr_xr7r, clkdr_xr8l, + clkdr_xr8r, dcc_dft_nrst, dcc_dft_nrst_coding, dcc_dft_up, + dcc_req, dll_csr_reg6, iclkin_dist_pinp0, idat0_clkn, idat0_clkp, + idat0_in0_dout_clkp, idat0_voutp00, idat0_voutp01, idat1_clkn, + idat1_clkp, idat1_in0_dout_clkp, idat1_voutp00, idat1_voutp01, + idata0_ssrdout, idata0_ssrldout, idata1_ssrdout, idata1_ssrldout, + idataselb_in0_dout_clkp, idataselb_outpclk1_1, + idataselb_outpdir0_1, idataselb_ssrdout, idataselb_ssrldout, + idataselb_voutp00, idataselb_voutp01, iddren, idll_entest, + ilaunch_clk_in0_dout_clkp, ilaunch_clk_ssrdout, + ilaunch_clk_ssrldout, ilaunch_clk_voutp00, ilaunch_clk_voutp01, + istrbclk_pinp0, itxen_in0_dout_clkp, itxen_outpclk1_1, + itxen_outpdir0_1, itxen_ssrdout, itxen_ssrldout, itxen_voutp00, + itxen_voutp01, jtag_clkdr_in_chain2, jtag_clkdr_in_ssrdout, + jtag_clkdr_in_ssrldout, jtag_clkdr_inpclk1n, jtag_clkdr_inpclk6, + jtag_clkdr_out_diin_clkp, jtag_clkdr_out_directin2, + jtag_clkdr_outpclk1_1, jtag_clkdr_outpdir0_1, jtag_clkdr_pinp0, + jtag_clkdr_voutp00, jtag_clkdr_voutp01, jtag_clksel, jtag_intest, + jtag_mode_in, jtag_rstb, jtag_rstb_en, jtag_rx_scan_in_ssrdout, + jtag_rx_scan_in_ssrldout, jtag_rx_scan_inpclk1n, + jtag_rx_scan_inpclk6, jtag_rx_scan_out_diin_clkp, + jtag_rx_scan_out_directin2, jtag_rx_scan_outpclk1_1, + jtag_rx_scan_outpdir0_1, jtag_rx_scan_voutp00, + jtag_rx_scan_voutp01, jtag_scan_in_chain2, jtag_scan_pinp0, + jtag_tx_scanen_in, jtag_weakpdn, jtag_weakpu, oclk_inpdir2, + oclk_srclkout, oclkb_inpdir2, oclkb_srclkout, oclkn_inpdir4, + odat_async_chain2, odat_async_fsrdin, odat_async_inpclk1, + odat_async_inpclk4, output_buffer_clk, output_rstb, + pipeline_global_en, poutp_dig_rstb, rb_dcc_byp, + rb_dcc_byp_dprio, // Mod : Added new port + rb_dcc_dft, + rb_dcc_dft_sel, rb_dcc_dll_dft_sel, rb_dcc_en, + rb_dcc_en_dprio, // Mod : Added new port + rb_dcc_manual_mode, + rb_dcc_manual_mode_dprio, // Mod : Added new port + rb_dcc_test_clk_pll_en_n, rb_half_code, rb_selflock, + rshift_en_txferclkout, rshift_en_txferclkoutn, scan_clk_in, + scan_in, scan_mode_n, scan_rst_n, scan_shift_n, + shift_en_in_chain2, shift_en_inpclk1n, shift_en_inpclk6, + shift_en_inpdir2, shift_en_outpclk0, shift_en_outpclk1_1, + shift_en_outpdir0_1, shift_en_pinp0, shift_en_ssrdout, + shift_en_ssrldout, shift_en_voutp00, shift_en_voutp01, vccl_aibnd, + vssl_aibnd; + +output [2:0] irxen_chain2; +output [2:0] irxen_inpclk3; +output [12:0] oaibdftdll2core; +output [2:0] irxen_inpdir3; +output [2:0] irxen_inpshared0; +output [2:0] irxen_ptxclkin; +output [2:0] oaibdftcore2dll; +output [2:0] odirectin_data; +output [2:0] irxen_inpshared4; +output [4:0] odat_async; +output [1:0] out_rx_fast_clk; + +inout [2:0] iopad_direct_input; +inout [1:0] iopad_directinclkp; +inout [1:0] iopad_directinclkn; +inout [2:0] iopad_async_out; +inout [4:0] iopad_async_in; +inout [3:0] iopad_directout; +inout [19:0] iopad_dat; + +input [1:0] indrv_r34; +input [1:0] ipdrv_r34; +input [2:0] irxen_inpdir2; +input [12:0] idll_dll2core; +input [1:0] ipdrv_r12; +input [2:0] irxen_r0; +input [1:0] indrv_r12; +input [1:0] ipdrv_r56; +input [1:0] indrv_r56; +input [2:0] irxen_pinp0; +input [2:0] irxen_in_chain2; +input [1:0] rshift_en_dirclkn; +input [2:0] irxen_inpclk6; +input [2:0] iaibdftcore2dll; +input [1:0] rshift_en_dirclkp; +input [51:0] csr_reg; +input [2:0] irxen_r1; +input [2:0] rshift_en_drx; +input [4:0] rb_dcc_manual_up; +input [4:0] rb_dcc_manual_dn; +input [2:0] iasyncdata; +input [2:0] irxen_r2; +input [3:0] rshift_en_rx; +input [2:0] rb_clkdiv; +input [3:0] rshift_en_tx; +input [3:0] rshift_en_dtx; +input [3:0] idirectout_data; +input [19:0] rshift_en_poutp; +input [3:0] idataselb; +input [3:0] itxen; +input [19:0] idat1; +input [19:0] idat0; + +wire output_buffer_clk, outbuf_clk_buf, rb_dcc_dll_dft_sel, dcc_scan_out, scan_out, clk_mimic0, clk_mimic0_buf, clk_mimic1, clk_mimic1_buf, gated_clk_mimic1, dft_rx_clk, dll_csr_reg6, nc_clk_repb, clk_rep, nc_clk_mimic, clk_mimic; // Conversion Sript Generated + +wire out_rx_fast_clk0_buf; +wire nc_out_rx_fast_clk0_io; + +// Buses in the design + +wire [1:1] ncdtx_oclkb_aib; + +wire [0:0] drx_oclk_aib; + +wire [0:12] mux_dft_dll2core; + +wire [0:12] buf_dcc2core; + +wire [2:0] oaibdftcore2dcc; + +wire [4:4] ncrx_oclk; + +wire [0:0] ncdrx_odat0_aib; + +wire [0:1] ncout_rx_fast_clkn; + +wire [0:1] ncout_rx_fast_clknb; + +wire [0:1] nc_rxodat0_clkn; + +wire [0:1] nc_rxodat1_clkn; + +wire [0:1] nc_rxodat_async_clkn; + +wire [0:1] nc_rxpd_data_clkn; + +wire [0:1] out_rx_fast_clkb; + +wire [0:1] nc_rxodat0_clkp; + +wire [0:1] nc_rxodat1_clkp; + +wire [0:1] nc_rxodat_async_clkp; + +wire [0:1] nc_rxpd_data_clkp; + +wire [1:1] ncdrx_oclk_aib; + +wire [1:1] ncdrx_oclkb_aib; + +wire [0:2] ncdrx_oclk; + +wire [0:2] ncdrx_oclkb; + +wire [0:2] ncdrx_odat0; + +wire [0:2] ncdrx_odat1; + +wire [0:2] ncdrx_pd_data; + +wire [2:2] ncdrx_odat1_aib; + +wire [0:2] nctx_odat_async; + +wire [0:12] buf_dll2core; + +wire [0:0] drx_oclkb_aib; + +wire [4:4] ncrx_oclk_aib; + +wire [4:4] ncrx_oclkb_aib; + +wire [0:2] ncdrx_odat_async_aib; + +wire [0:2] nctx_oclkn; + +wire [0:2] nctx_oclk; + +wire [0:2] nctx_oclkb; + +wire [0:2] nctx_odat0; + +wire [0:2] nctx_odat1; + +wire [0:2] nctx_pd_data; + +wire [0:2] nctx_oclk_aib; + +wire [0:2] nctx_oclkb_aib; + +wire [0:2] nctx_odat0_aib; + +wire [0:2] nctx_odat1_aib; + +wire [0:2] nctx_pd_data_aib; + +wire [0:11] tx_launch_clk_l; + +wire [0:4] ncrx_odat0_aib; + +wire [0:4] ncrx_odat1_aib; + +wire [0:4] ncrx_pd_data_aib; + +wire [0:4] ncrx_oclkb; + +wire [0:4] ncrx_odat0; + +wire [0:4] ncrx_odat1; + +wire [0:4] ncrx_pd_data; + +wire [3:3] ncdtx_oclk_aib; + +wire [0:3] ncrx_odat_async_aib; + +wire [2:3] ncdtx_oclkn; + +wire [0:2] ncdrx_pd_data_aib; + +wire [0:11] tx_launch_clk_r; + +wire [0:3] ncdtx_oclk; + +wire [0:3] ncdtx_oclkb; + +wire [0:3] ncdtx_odat0; + +wire [0:3] ncdtx_odat1; + +wire [0:3] ncdtx_odat_async; + +wire [0:3] ncdtx_pd_data; + +wire [0:3] ncdtx_odat0_aib; + +wire [0:3] ncdtx_odat1_aib; + +wire [0:1] ncdtx_odat_async_aib; + +wire [0:3] ncdtx_pd_data_aib; + +wire [12:0] odcc_dll2core; + +wire [0:19] nc_oclkn_pout; + +wire [0:19] nc_oclkb_aib_pout; + +wire [0:19] nc_odat1_aib_pout; + +wire [0:19] nc_pd_data_aib_pout; + +wire [0:19] nc_oclk; + +wire [0:19] nc_oclkb; + +wire [0:19] nc_odat1; + +wire [0:19] nc_odat0_aib_pout; + +wire [1:19] nc_odat_async_aib_pout; + +wire [0:19] nc_odat_async; + +wire [0:19] nc_odat0; + +wire [0:19] nc_oclk_aib_pout; + +wire [0:19] nc_pd_data; + + +// specify +// specparam CDS_LIBNAME = "aibnd_lib"; +// specparam CDS_CELLNAME = "aibnd_txdatapath_tx"; +// specparam CDS_VIEWNAME = "schematic"; +// endspecify + +aibnd_clktree xclktree ( //.vcc_aibnd(vccl_aibnd), + //.vss_aibnd(vssl_aibnd), + .lstrbclk_r_11(tx_launch_clk_r[11]), + .lstrbclk_r_10(tx_launch_clk_r[10]), + .lstrbclk_l_11(tx_launch_clk_l[11]), .lstrbclk_mimic2(clk_mimic), + .lstrbclk_mimic1(clk_mimic1), .lstrbclk_mimic0(clk_mimic0), + .lstrbclk_l_10(tx_launch_clk_l[10]), + .lstrbclk_r_9(tx_launch_clk_r[9]), + .lstrbclk_r_8(tx_launch_clk_r[8]), + .lstrbclk_r_7(tx_launch_clk_r[7]), + .lstrbclk_r_6(tx_launch_clk_r[6]), + .lstrbclk_r_5(tx_launch_clk_r[5]), + .lstrbclk_r_4(tx_launch_clk_r[4]), + .lstrbclk_r_3(tx_launch_clk_r[3]), + .lstrbclk_r_2(tx_launch_clk_r[2]), + .lstrbclk_r_1(tx_launch_clk_r[1]), + .lstrbclk_r_0(tx_launch_clk_r[0]), + .lstrbclk_l_0(tx_launch_clk_l[0]), + .lstrbclk_l_1(tx_launch_clk_l[1]), + .lstrbclk_l_2(tx_launch_clk_l[2]), + .lstrbclk_l_3(tx_launch_clk_l[3]), + .lstrbclk_l_4(tx_launch_clk_l[4]), + .lstrbclk_l_5(tx_launch_clk_l[5]), + .lstrbclk_l_6(tx_launch_clk_l[6]), + .lstrbclk_l_7(tx_launch_clk_l[7]), + .lstrbclk_l_8(tx_launch_clk_l[8]), + .lstrbclk_l_9(tx_launch_clk_l[9]), .lstrbclk_rep(clk_rep), + .clkin(clktree_in)); +aibnd_buffx1_top xasyncrx3 ( .idata1_in1_jtag_out(nc_idat1_async_in3), + .async_dat_in1_jtag_out(nc_async_dat_async_in3), + .idata0_in1_jtag_out(nc_idat0_async_in3), + .jtag_clkdr_outn(jtag_clkdr_outn_inpshared3), + .prev_io_shift_en(shift_en_ssrldout), .anlg_rstb(output_rstb), + .pd_data_aib(ncrx_pd_data_aib[3]), .oclk_out(odat_async[3]), + .oclkb_out(ncrx_oclkb[3]), .odat0_out(ncrx_odat0[3]), + .odat1_out(ncrx_odat1[3]), .odat_async_out(ncrx_async_data_out3), + .pd_data_out(ncrx_pd_data[3]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(vssl_aibnd), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(idata0_ssrldout), .idata1_in0(vssl_aibnd), + .idata1_in1(idata1_ssrldout), .idataselb_in0(vssl_aibnd), + .idataselb_in1(idataselb_ssrldout), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(ilaunch_clk_ssrldout), + .ilpbk_dat_in0(vssl_aibnd), .ilpbk_dat_in1(vssl_aibnd), + .ilpbk_en_in0(vssl_aibnd), .ilpbk_en_in1(vssl_aibnd), + .indrv_in0({vssl_aibnd, vssl_aibnd}), .indrv_in1(indrv_r34[1:0]), + .ipdrv_in0({vssl_aibnd, vssl_aibnd}), .ipdrv_in1(ipdrv_r34[1:0]), + .irxen_in0({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(vssl_aibnd), .itxen_in1(itxen_ssrldout), + .oclk_in1(vssl_aibnd), .odat_async_aib(ncrx_odat_async_aib[3]), + .oclkb_in1(vssl_aibnd), .jtag_clksel(jtag_clksel), + .odat0_in1(vssl_aibnd), .vssl_aibnd(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_tx[3]), .pd_data_in1(vssl_aibnd), + .dig_rstb(avmm_sync_rstb), .jtag_clkdr_out(jtag_clkdr_async_in3), + .jtag_intest(jtag_intest), .odat1_aib(ncrx_odat1_aib[3]), + .jtag_rx_scan_out(jtag_rx_scan_async_in3), + .odat0_aib(ncrx_odat0_aib[3]), .oclk_aib(ncrx_oclk_aib3), + .last_bs_out(nc_last_bs_out_diro3), .vccl_aibnd(vccl_aibnd), + .oclkb_aib(ncrx_oclkb_aib3), .jtag_clkdr_in(clkdr_xr4r), + .jtag_rstb_en(jtag_rstb_en), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_in_ssrldout), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_async_in[3]), .oclkn(oclkn_inpshared3), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xasyncrx1 ( .idata1_in1_jtag_out(nc_idat1_async_in1), + .async_dat_in1_jtag_out(nc_async_dat_async_in1), + .idata0_in1_jtag_out(nc_idat0_async_in1), + .jtag_clkdr_outn(jtag_clkdr_outn_inpshared1), + .prev_io_shift_en(rshift_en_tx[3]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(output_rstb), .pd_data_aib(ncrx_pd_data_aib[1]), + .oclk_out(odat_async[1]), .oclkb_out(ncrx_oclkb[1]), + .odat0_out(ncrx_odat0[1]), .odat1_out(ncrx_odat1[1]), + .odat_async_out(ncrx_async_data_out1), + .pd_data_out(ncrx_pd_data[1]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(vssl_aibnd), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vssl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(ncrx_odat_async_aib[1]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_tx[1]), .pd_data_in1(vssl_aibnd), + .dig_rstb(output_rstb), .jtag_clkdr_out(jtag_clkdr_async_in1), + .odat1_aib(ncrx_odat1_aib[1]), + .jtag_rx_scan_out(jtag_rx_scan_async_in1), + .odat0_aib(ncrx_odat0_aib[1]), .oclk_aib(ncrx_oclk_aib1), + .last_bs_out(nc_last_bs_out_diro1), .oclkb_aib(ncrx_oclkb_aib1), + .jtag_clkdr_in(clkdr_xr4r), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_async_in3), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_async_in[1]), .oclkn(oclkn_inpshared1), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top x455 ( .idata1_in1_jtag_out(idat1_poutp9), + .async_dat_in1_jtag_out(nc_async_dat_poutp9), + .idata0_in1_jtag_out(idat0_poutp9), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp9), + .prev_io_shift_en(rshift_en_poutp[7]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_pout[9]), .oclk_out(nc_oclk[9]), + .oclkb_out(nc_oclkb[9]), .odat0_out(nc_odat0[9]), + .odat1_out(nc_odat1[9]), .odat_async_out(nc_odat_async[9]), + .pd_data_out(nc_pd_data[9]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp9), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[9]), + .idata0_in1(idat0_poutp7), .idata1_in0(idat1[9]), + .idata1_in1(idat1_poutp7), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[0]), .iddren_in0(iddren), + .iddren_in1(iddren), .ilaunch_clk_in0(tx_launch_clk_r[4]), + .ilaunch_clk_in1(tx_launch_clk_r[4]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp9), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[9]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[9]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_poutp9), + .odat1_aib(nc_odat1_aib_pout[9]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp9), + .odat0_aib(nc_odat0_aib_pout[9]), .oclk_aib(nc_oclk_aib_pout[9]), + .last_bs_out(nc_last_bs_out_poutp9), + .oclkb_aib(nc_oclkb_aib_pout[9]), .jtag_clkdr_in(clkdr_xr6r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_poutp7), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[9]), .oclkn(nc_oclkn_pout[9]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top x454 ( .idata1_in1_jtag_out(idata1_in1_clkn), + .async_dat_in1_jtag_out(nc_async_dat_clkn), + .idata0_in1_jtag_out(idata0_in1_clkn), + .jtag_clkdr_outn(jtag_clkdr_outn_clkn), + .prev_io_shift_en(rshift_en_poutp[9]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_txferclkoutn), + .oclk_out(nc_oclk_clkn), .oclkb_out(nc_oclkb_clkn), + .odat0_out(nc_odat0_clkn), .odat1_out(nc_odat1_clkn), + .odat_async_out(nc_odat_async_clkn), + .pd_data_out(nc_pd_data_clkn), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_clkn), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0_clkn), + .idata0_in1(idat0_poutp9), .idata1_in0(idat1_clkn), + .idata1_in1(idat1_poutp9), .idataselb_in0(idataselb[1]), + .idataselb_in1(idataselb[0]), .iddren_in0(vccl_aibnd), + .iddren_in1(iddren), .ilaunch_clk_in0(tx_launch_clk_r[8]), + .ilaunch_clk_in1(tx_launch_clk_r[8]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_clkn), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[1]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_txferclkoutn), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_txferclkoutn), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_clkn), + .odat1_aib(nc_odat1_aib_txferclkoutn), + .jtag_rx_scan_out(jtag_rx_scan_out_clkn), + .odat0_aib(nc_odat0_aib_txferclkoutn), + .oclk_aib(nc_oclk_aib_txferclkoutn), + .last_bs_out(nc_last_bs_out_txferclkoutn), + .oclkb_aib(nc_oclkb_aib_txferclkoutn), .jtag_clkdr_in(clkdr_xr6r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_poutp9), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_clkn), .oclkn(nc_oclkn_txferclkoutn), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top x446 ( .idata1_in1_jtag_out(idat1_poutp5), + .async_dat_in1_jtag_out(nc_async_dat_poutp5), + .idata0_in1_jtag_out(idat0_poutp5), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp5), + .prev_io_shift_en(rshift_en_poutp[3]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_pout[5]), .oclk_out(nc_oclk[5]), + .oclkb_out(nc_oclkb[5]), .odat0_out(nc_odat0[5]), + .odat1_out(nc_odat1[5]), .odat_async_out(nc_odat_async[5]), + .pd_data_out(nc_pd_data[5]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp5), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[5]), + .idata0_in1(idat0_poutp3), .idata1_in0(idat1[5]), + .idata1_in1(idat1_poutp3), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[0]), .iddren_in0(iddren), + .iddren_in1(iddren), .ilaunch_clk_in0(tx_launch_clk_r[2]), + .ilaunch_clk_in1(tx_launch_clk_r[2]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp5), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[5]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[5]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_poutp5), + .odat1_aib(nc_odat1_aib_pout[5]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp5), + .odat0_aib(nc_odat0_aib_pout[5]), .oclk_aib(nc_oclk_aib_pout[5]), + .last_bs_out(nc_last_bs_out_poutp5), + .oclkb_aib(nc_oclkb_aib_pout[5]), .jtag_clkdr_in(clkdr_xr6r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_poutp3), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[5]), .oclkn(nc_oclkn_pout[5]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top x438 ( .idata1_in1_jtag_out(idat1_poutp3), + .async_dat_in1_jtag_out(nc_async_dat_poutp3), + .idata0_in1_jtag_out(idat0_poutp3), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp3), + .prev_io_shift_en(rshift_en_poutp[1]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_pout[3]), .oclk_out(nc_oclk[3]), + .oclkb_out(nc_oclkb[3]), .odat0_out(nc_odat0[3]), + .odat1_out(nc_odat1[3]), .odat_async_out(nc_odat_async[3]), + .pd_data_out(nc_pd_data[3]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp3), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[3]), + .idata0_in1(idat0_poutp1), .idata1_in0(idat1[3]), + .idata1_in1(idat1_poutp1), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[0]), .iddren_in0(iddren), + .iddren_in1(iddren), .ilaunch_clk_in0(tx_launch_clk_r[6]), + .ilaunch_clk_in1(tx_launch_clk_r[6]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp3), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[3]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[3]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_poutp3), + .odat1_aib(nc_odat1_aib_pout[3]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp3), + .odat0_aib(nc_odat0_aib_pout[3]), .oclk_aib(nc_oclk_aib_pout[3]), + .last_bs_out(nc_last_bs_out_poutp3), + .oclkb_aib(nc_oclkb_aib_pout[3]), .jtag_clkdr_in(clkdr_xr6r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_poutp1), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[3]), .oclkn(nc_oclkn_pout[3]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top x430 ( .idata1_in1_jtag_out(idat1_poutp1), + .async_dat_in1_jtag_out(nc_async_dat_poutp1), + .idata0_in1_jtag_out(idat0_poutp1), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp1), + .prev_io_shift_en(rshift_en_dtx[1]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(output_rstb), .pd_data_aib(nc_pd_data_aib_pout[1]), + .oclk_out(nc_oclk[1]), .oclkb_out(nc_oclkb[1]), + .odat0_out(nc_odat0[1]), .odat1_out(nc_odat1[1]), + .odat_async_out(nc_odat_async[1]), .pd_data_out(nc_pd_data[1]), + .async_dat_in0(vssl_aibnd), .async_dat_in1(async_dat_outpdir4_1), + .iclkin_dist_in0(jtag_clkdr_outn_poutp1), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[1]), + .idata0_in1(vssl_aibnd), .idata1_in0(idat1[1]), + .idata1_in1(vssl_aibnd), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[3]), .iddren_in0(iddren), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(tx_launch_clk_r[10]), + .ilaunch_clk_in1(tx_launch_clk_r[10]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp1), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[3]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[1]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[1]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_poutp1), + .odat1_aib(nc_odat1_aib_pout[1]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp1), + .odat0_aib(nc_odat0_aib_pout[1]), .oclk_aib(nc_oclk_aib_pout[1]), + .last_bs_out(nc_last_bs_out_poutp1), + .oclkb_aib(nc_oclkb_aib_pout[1]), .jtag_clkdr_in(clkdr_xr6r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_outpdir4_1), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[1]), .oclkn(nc_oclkn_pout[1]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top x429 ( .idata1_in1_jtag_out(idat1_poutp7), + .async_dat_in1_jtag_out(nc_async_dat_poutp7), + .idata0_in1_jtag_out(idat0_poutp7), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp7), + .prev_io_shift_en(rshift_en_poutp[5]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_pout[7]), .oclk_out(nc_oclk[7]), + .oclkb_out(nc_oclkb[7]), .odat0_out(nc_odat0[7]), + .odat1_out(nc_odat1[7]), .odat_async_out(nc_odat_async[7]), + .pd_data_out(nc_pd_data[7]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp7), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[7]), + .idata0_in1(idat0_poutp5), .idata1_in0(idat1[7]), + .idata1_in1(idat1_poutp5), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[0]), .iddren_in0(iddren), + .iddren_in1(iddren), .ilaunch_clk_in0(tx_launch_clk_r[0]), + .ilaunch_clk_in1(tx_launch_clk_r[0]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp7), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[7]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[7]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_poutp7), + .odat1_aib(nc_odat1_aib_pout[7]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp7), + .odat0_aib(nc_odat0_aib_pout[7]), .oclk_aib(nc_oclk_aib_pout[7]), + .last_bs_out(nc_last_bs_out_poutp7), + .oclkb_aib(nc_oclkb_aib_pout[7]), .jtag_clkdr_in(clkdr_xr6r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_poutp5), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[7]), .oclkn(nc_oclkn_pout[7]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpoutp2 ( .idata1_in1_jtag_out(idat1_poutp2), + .async_dat_in1_jtag_out(nc_async_dat_poutp2), + .idata0_in1_jtag_out(idat0_poutp2), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp2), + .prev_io_shift_en(rshift_en_poutp[0]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_pout[2]), .oclk_out(nc_oclk[2]), + .oclkb_out(nc_oclkb[2]), .odat0_out(nc_odat0[2]), + .odat1_out(nc_odat1[2]), .odat_async_out(nc_odat_async[2]), + .pd_data_out(nc_pd_data[2]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp2), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[2]), + .idata0_in1(idat0_poutp0), .idata1_in0(idat1[2]), + .idata1_in1(idat1_poutp0), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[0]), .iddren_in0(iddren), + .iddren_in1(iddren), .ilaunch_clk_in0(tx_launch_clk_r[7]), + .ilaunch_clk_in1(tx_launch_clk_r[7]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp2), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[2]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[2]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_poutp2), + .odat1_aib(nc_odat1_aib_pout[2]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp2), + .odat0_aib(nc_odat0_aib_pout[2]), .oclk_aib(nc_oclk_aib_pout[2]), + .last_bs_out(nc_last_bs_out_poutp2), + .oclkb_aib(nc_oclkb_aib_pout[2]), .jtag_clkdr_in(clkdr_xr5r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_poutp0), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[2]), .oclkn(nc_oclkn_pout[2]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpoutp0 ( .idata1_in1_jtag_out(idat1_poutp0), + .async_dat_in1_jtag_out(nc_async_dat_poutp0), + .idata0_in1_jtag_out(idat0_poutp0), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp0), + .prev_io_shift_en(shift_en_inpdir2), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(output_rstb), .pd_data_aib(nc_pd_data_aib_pout[0]), + .oclk_out(nc_oclk[0]), .oclkb_out(nc_oclkb[0]), + .odat0_out(nc_odat0[0]), .odat1_out(nc_odat1[0]), + .odat_async_out(nc_odat_async[0]), .pd_data_out(nc_pd_data[0]), + .async_dat_in0(vssl_aibnd), .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp0), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[0]), + .idata0_in1(vssl_aibnd), .idata1_in0(idat1[0]), + .idata1_in1(vssl_aibnd), .idataselb_in0(idataselb[0]), + .idataselb_in1(vssl_aibnd), .iddren_in0(iddren), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(tx_launch_clk_r[11]), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1({vssl_aibnd, vssl_aibnd}), .irxen_in0({vssl_aibnd, + vccl_aibnd, vssl_aibnd}), .irxen_in1(irxen_inpdir2[2:0]), + .istrbclk_in0(jtag_clkdr_outn_poutp0), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(odat_async_pout0), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[0]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_poutp0), + .odat1_aib(nc_odat1_aib_pout[0]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp0), + .odat0_aib(nc_odat0_aib_pout[0]), .oclk_aib(nc_oclk_aib_pout[0]), + .last_bs_out(nc_last_bs_out_poutp0), + .oclkb_aib(nc_oclkb_aib_pout[0]), .jtag_clkdr_in(clkdr_xr5r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_directin2), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[0]), .oclkn(nc_oclkn_pout[0]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpoutp4 ( .idata1_in1_jtag_out(idat1_poutp4), + .async_dat_in1_jtag_out(nc_async_dat_poutp4), + .idata0_in1_jtag_out(idat0_poutp4), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp4), + .prev_io_shift_en(rshift_en_poutp[2]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_pout[4]), .oclk_out(nc_oclk[4]), + .oclkb_out(nc_oclkb[4]), .odat0_out(nc_odat0[4]), + .odat1_out(nc_odat1[4]), .odat_async_out(nc_odat_async[4]), + .pd_data_out(nc_pd_data[4]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp4), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[4]), + .idata0_in1(idat0_poutp2), .idata1_in0(idat1[4]), + .idata1_in1(idat1_poutp2), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[0]), .iddren_in0(iddren), + .iddren_in1(iddren), .ilaunch_clk_in0(tx_launch_clk_r[3]), + .ilaunch_clk_in1(tx_launch_clk_r[3]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp4), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[4]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[4]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_poutp4), + .odat1_aib(nc_odat1_aib_pout[4]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp4), + .odat0_aib(nc_odat0_aib_pout[4]), .oclk_aib(nc_oclk_aib_pout[4]), + .last_bs_out(nc_last_bs_out_poutp4), + .oclkb_aib(nc_oclkb_aib_pout[4]), .jtag_clkdr_in(clkdr_xr5r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_poutp2), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[4]), .oclkn(nc_oclkn_pout[4]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpoutp11 ( .idata1_in1_jtag_out(idat1_poutp11), + .async_dat_in1_jtag_out(nc_async_dat_poutp11), + .idata0_in1_jtag_out(idat0_poutp11), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp11), + .prev_io_shift_en(rshift_en_txferclkoutn), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_pout[11]), .oclk_out(nc_oclk[11]), + .oclkb_out(nc_oclkb[11]), .odat0_out(nc_odat0[11]), + .odat1_out(nc_odat1[11]), .odat_async_out(nc_odat_async[11]), + .pd_data_out(nc_pd_data[11]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp11), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[11]), + .idata0_in1(idata0_in1_clkn), .idata1_in0(idat1[11]), + .idata1_in1(idata1_in1_clkn), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[1]), .iddren_in0(iddren), + .iddren_in1(vccl_aibnd), .ilaunch_clk_in0(tx_launch_clk_l[10]), + .ilaunch_clk_in1(tx_launch_clk_l[10]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp11), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[1]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[11]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[11]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), + .jtag_clkdr_out(jtag_clkdr_out_poutp11), + .odat1_aib(nc_odat1_aib_pout[11]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp11), + .odat0_aib(nc_odat0_aib_pout[11]), + .oclk_aib(nc_oclk_aib_pout[11]), + .last_bs_out(nc_last_bs_out_poutp11), + .oclkb_aib(nc_oclkb_aib_pout[11]), .jtag_clkdr_in(clkdr_xr6l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_clkn), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[11]), .oclkn(nc_oclkn_pout[11]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xasyncrx0 ( .idata1_in1_jtag_out(nc_idat1_inpshared0), + .async_dat_in1_jtag_out(nc_async_dat_inpshared0), + .idata0_in1_jtag_out(nc_idat0_inpshared0), + .jtag_clkdr_outn(jtag_clkdr_outn_inpshared0), + .prev_io_shift_en(rshift_en_tx[2]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(output_rstb), .pd_data_aib(ncrx_pd_data_aib[0]), + .oclk_out(odat_async[0]), .oclkb_out(ncrx_oclkb[0]), + .odat0_out(ncrx_odat0[0]), .odat1_out(ncrx_odat1[0]), + .odat_async_out(ncrx_async_data_out0), + .pd_data_out(ncrx_pd_data[0]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(vssl_aibnd), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vssl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r0[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(oclk_inpdir2), .odat_async_aib(ncrx_odat_async_aib[0]), + .oclkb_in1(oclkb_inpdir2), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_tx[0]), .pd_data_in1(vssl_aibnd), + .dig_rstb(output_rstb), .jtag_clkdr_out(jtag_clkdr_inpshared0), + .odat1_aib(ncrx_odat1_aib[0]), + .jtag_rx_scan_out(jtag_rx_scan_inpshared0), + .odat0_aib(ncrx_odat0_aib[0]), .oclk_aib(oclk_inpshared0), + .last_bs_out(nc_last_bs_out_diro0), .oclkb_aib(oclkb_inpshared0), + .jtag_clkdr_in(clkdr_xr3r), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_async_in2), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_async_in[0]), .oclkn(ncrx_oclkn0), + .iclkn(oclkn_inpshared1), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdirect_in2 ( .idata1_in1_jtag_out(nc_idat1_inpclk3), + .async_dat_in1_jtag_out(nc_async_dat_inpclk3), + .idata0_in1_jtag_out(nc_idat0_inpclk3), + .jtag_clkdr_outn(jtag_clkdr_outn_inpclk3), + .prev_io_shift_en(shift_en_inpclk1n), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(output_rstb), .pd_data_aib(ncdrx_pd_data_aib[2]), + .oclk_out(ncdrx_oclk[2]), .oclkb_out(ncdrx_oclkb[2]), + .odat0_out(ncdrx_odat0[2]), .odat1_out(ncdrx_odat1[2]), + .odat_async_out(odirectin_data[2]), + .pd_data_out(ncdrx_pd_data[2]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(vssl_aibnd), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vssl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r1[2:0]), .irxen_in1({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .istrbclk_in0(vssl_aibnd), + .istrbclk_in1(vssl_aibnd), .itxen_in0(vssl_aibnd), + .itxen_in1(vssl_aibnd), .oclk_in1(vssl_aibnd), + .odat_async_aib(ncdrx_odat_async_aib[2]), .oclkb_in1(vssl_aibnd), + .odat0_in1(vssl_aibnd), .odat1_in1(vssl_aibnd), + .odat_async_in1(odat_async_inpclk4), .shift_en(rshift_en_drx[2]), + .pd_data_in1(vssl_aibnd), .dig_rstb(output_rstb), + .jtag_clkdr_out(jtag_clkdr_out_inpclk3), + .odat1_aib(ncdrx_odat1_aib[2]), + .jtag_rx_scan_out(jtag_rx_scan_out_inpclk3), + .odat0_aib(ncdrx_odat0_aib2), .oclk_aib(oclk_inpclk3), + .last_bs_out(nc_last_bs_out_inpclk3), .oclkb_aib(oclkb_inpclk3), + .jtag_clkdr_in(clkdr_xr2l), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_inpclk1n), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_direct_input[2]), .oclkn(oclkn_inpclk3), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdirect_out3 ( + .idata1_in1_jtag_out(nc_idat1_outpdir1_1), + .async_dat_in1_jtag_out(async_dat_outpdir1_1), + .idata0_in1_jtag_out(nc_idat0_outpdir1_1), + .jtag_clkdr_outn(jtag_clkdr_outn_outpdir1_1), + .prev_io_shift_en(shift_en_outpclk0), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(output_rstb), .pd_data_aib(ncdtx_pd_data_aib[3]), + .oclk_out(ncdtx_oclk[3]), .oclkb_out(ncdtx_oclkb[3]), + .odat0_out(ncdtx_odat0[3]), .odat1_out(ncdtx_odat1[3]), + .odat_async_out(ncdtx_odat_async[3]), + .pd_data_out(ncdtx_pd_data[3]), + .async_dat_in0(idirectout_data[3]), .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(vssl_aibnd), .iclkin_dist_in1(vssl_aibnd), + .idata0_in0(vssl_aibnd), .idata0_in1(idat0_in0_dout_clkp), + .idata1_in0(vssl_aibnd), .idata1_in1(idat1_in0_dout_clkp), + .idataselb_in0(idataselb[3]), + .idataselb_in1(idataselb_in0_dout_clkp), .iddren_in0(vssl_aibnd), + .iddren_in1(vccl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(ilaunch_clk_in0_dout_clkp), + .ilpbk_dat_in0(vssl_aibnd), .ilpbk_dat_in1(vssl_aibnd), + .ilpbk_en_in0(vssl_aibnd), .ilpbk_en_in1(vssl_aibnd), + .indrv_in0(indrv_r34[1:0]), .indrv_in1(indrv_r34[1:0]), + .ipdrv_in0(ipdrv_r34[1:0]), .ipdrv_in1(ipdrv_r34[1:0]), + .irxen_in0({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[3]), .itxen_in1(itxen_in0_dout_clkp), + .oclk_in1(vssl_aibnd), .odat_async_aib(ncdtx_odat_async_aib3), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_dtx[3]), .pd_data_in1(vssl_aibnd), + .dig_rstb(output_rstb), + .jtag_clkdr_out(jtag_clkdr_out_outpdir1_1), + .odat1_aib(ncdtx_odat1_aib[3]), + .jtag_rx_scan_out(jtag_rx_scan_out_outpdir1_1), + .odat0_aib(ncdtx_odat0_aib[3]), .oclk_aib(ncdtx_oclk_aib[3]), + .last_bs_out(nc_last_bs_out_outpdir1_1), + .oclkb_aib(ncdtx_oclkb_aib3), .jtag_clkdr_in(clkdr_xr3l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_diin_clkp), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_directout[3]), .oclkn(ncdtx_oclkn[3]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpoutp6 ( .idata1_in1_jtag_out(idat1_poutp6), + .async_dat_in1_jtag_out(nc_async_dat_poutp6), + .idata0_in1_jtag_out(idat0_poutp6), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp6), + .prev_io_shift_en(rshift_en_poutp[4]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_pout[6]), .oclk_out(nc_oclk[6]), + .oclkb_out(nc_oclkb[6]), .odat0_out(nc_odat0[6]), + .odat1_out(nc_odat1[6]), .odat_async_out(nc_odat_async[6]), + .pd_data_out(nc_pd_data[6]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp6), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[6]), + .idata0_in1(idat0_poutp4), .idata1_in0(idat1[6]), + .idata1_in1(idat1_poutp4), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[0]), .iddren_in0(iddren), + .iddren_in1(iddren), .ilaunch_clk_in0(tx_launch_clk_r[1]), + .ilaunch_clk_in1(tx_launch_clk_r[1]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp6), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[6]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[6]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_poutp6), + .odat1_aib(nc_odat1_aib_pout[6]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp6), + .odat0_aib(nc_odat0_aib_pout[6]), .oclk_aib(nc_oclk_aib_pout[6]), + .last_bs_out(nc_last_bs_out_poutp6), + .oclkb_aib(nc_oclkb_aib_pout[6]), .jtag_clkdr_in(clkdr_xr5r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_poutp4), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[6]), .oclkn(nc_oclkn_pout[6]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpoutp8 ( .idata1_in1_jtag_out(idat1_poutp8), + .async_dat_in1_jtag_out(nc_async_dat_poutp8), + .idata0_in1_jtag_out(idat0_poutp8), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp8), + .prev_io_shift_en(rshift_en_poutp[6]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_pout[8]), .oclk_out(nc_oclk[8]), + .oclkb_out(nc_oclkb[8]), .odat0_out(nc_odat0[8]), + .odat1_out(nc_odat1[8]), .odat_async_out(nc_odat_async[8]), + .pd_data_out(nc_pd_data[8]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp8), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[8]), + .idata0_in1(idat0_poutp6), .idata1_in0(idat1[8]), + .idata1_in1(idat1_poutp6), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[0]), .iddren_in0(iddren), + .iddren_in1(iddren), .ilaunch_clk_in0(tx_launch_clk_r[5]), + .ilaunch_clk_in1(tx_launch_clk_r[5]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp8), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[8]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[8]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_poutp8), + .odat1_aib(nc_odat1_aib_pout[8]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp8), + .odat0_aib(nc_odat0_aib_pout[8]), .oclk_aib(nc_oclk_aib_pout[8]), + .last_bs_out(nc_last_bs_out_poutp8), + .oclkb_aib(nc_oclkb_aib_pout[8]), .jtag_clkdr_in(clkdr_xr5r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_poutp6), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[8]), .oclkn(nc_oclkn_pout[8]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top x187 ( .idata1_in1_jtag_out(idata1_in1_clkp), + .async_dat_in1_jtag_out(nc_async_dat_clkp), + .idata0_in1_jtag_out(idata0_in1_clkp), + .jtag_clkdr_outn(jtag_clkdr_outn_clkp), + .prev_io_shift_en(rshift_en_poutp[8]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_txferclkout), .oclk_out(nc_oclk_clkp), + .oclkb_out(nc_oclkb_clkp), .odat0_out(nc_odat0_clkp), + .odat1_out(nc_odat1_clkp), .odat_async_out(nc_odat_async_clkp), + .pd_data_out(nc_pd_data_clkp), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_clkp), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0_clkp), + .idata0_in1(idat0_poutp8), .idata1_in0(idat1_clkp), + .idata1_in1(idat1_poutp8), .idataselb_in0(idataselb[1]), + .idataselb_in1(idataselb[0]), .iddren_in0(vccl_aibnd), + .iddren_in1(iddren), .ilaunch_clk_in0(tx_launch_clk_r[9]), + .ilaunch_clk_in1(tx_launch_clk_r[9]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_clkp), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[1]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_txferclkout), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_txferclkout), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), .jtag_clkdr_out(jtag_clkdr_out_clkp), + .odat1_aib(nc_odat1_aib_txferclkout), + .jtag_rx_scan_out(jtag_rx_scan_out_clkp), + .odat0_aib(nc_odat0_aib_txferclkout), + .oclk_aib(nc_oclk_aib_txferclkout), + .last_bs_out(nc_last_bs_out_txferclkout), + .oclkb_aib(nc_oclkb_aib_txferclkout), .jtag_clkdr_in(clkdr_xr5r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_poutp8), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_clkp), .oclkn(nc_oclkn_txferclkout), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpoutp10 ( .idata1_in1_jtag_out(idat1_poutp10), + .async_dat_in1_jtag_out(nc_async_dat_poutp10), + .idata0_in1_jtag_out(idat0_poutp10), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp10), + .prev_io_shift_en(rshift_en_txferclkout), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_pout[10]), .oclk_out(nc_oclk[10]), + .oclkb_out(nc_oclkb[10]), .odat0_out(nc_odat0[10]), + .odat1_out(nc_odat1[10]), .odat_async_out(nc_odat_async[10]), + .pd_data_out(nc_pd_data[10]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp10), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[10]), + .idata0_in1(idata0_in1_clkp), .idata1_in0(idat1[10]), + .idata1_in1(idata1_in1_clkp), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[1]), .iddren_in0(iddren), + .iddren_in1(vccl_aibnd), .ilaunch_clk_in0(tx_launch_clk_l[11]), + .ilaunch_clk_in1(tx_launch_clk_l[11]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp10), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[1]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[10]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[10]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), + .jtag_clkdr_out(jtag_clkdr_out_poutp10), + .odat1_aib(nc_odat1_aib_pout[10]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp10), + .odat0_aib(nc_odat0_aib_pout[10]), + .oclk_aib(nc_oclk_aib_pout[10]), + .last_bs_out(nc_last_bs_out_poutp10), + .oclkb_aib(nc_oclkb_aib_pout[10]), .jtag_clkdr_in(clkdr_xr5l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_clkp), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[10]), .oclkn(nc_oclkn_pout[10]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpoutp12 ( .idata1_in1_jtag_out(idat1_poutp12), + .async_dat_in1_jtag_out(nc_async_dat_poutp12), + .idata0_in1_jtag_out(idat0_poutp12), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp12), + .prev_io_shift_en(rshift_en_poutp[10]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_pout[12]), .oclk_out(nc_oclk[12]), + .oclkb_out(nc_oclkb[12]), .odat0_out(nc_odat0[12]), + .odat1_out(nc_odat1[12]), .odat_async_out(nc_odat_async[12]), + .pd_data_out(nc_pd_data[12]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp12), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[12]), + .idata0_in1(idat0_poutp10), .idata1_in0(idat1[12]), + .idata1_in1(idat1_poutp10), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[0]), .iddren_in0(iddren), + .iddren_in1(iddren), .ilaunch_clk_in0(tx_launch_clk_l[7]), + .ilaunch_clk_in1(tx_launch_clk_l[7]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp12), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[12]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[12]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), + .jtag_clkdr_out(jtag_clkdr_out_poutp12), + .odat1_aib(nc_odat1_aib_pout[12]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp12), + .odat0_aib(nc_odat0_aib_pout[12]), + .oclk_aib(nc_oclk_aib_pout[12]), + .last_bs_out(nc_last_bs_out_poutp12), + .oclkb_aib(nc_oclkb_aib_pout[12]), .jtag_clkdr_in(clkdr_xr5l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_poutp10), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[12]), .oclkn(nc_oclkn_pout[12]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpoutp13 ( .idata1_in1_jtag_out(idat1_poutp13), + .async_dat_in1_jtag_out(nc_async_dat_poutp13), + .idata0_in1_jtag_out(idat0_poutp13), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp13), + .prev_io_shift_en(rshift_en_poutp[11]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_pout[13]), .oclk_out(nc_oclk[13]), + .oclkb_out(nc_oclkb[13]), .odat0_out(nc_odat0[13]), + .odat1_out(nc_odat1[13]), .odat_async_out(nc_odat_async[13]), + .pd_data_out(nc_pd_data[13]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp13), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[13]), + .idata0_in1(idat0_poutp11), .idata1_in0(idat1[13]), + .idata1_in1(idat1_poutp11), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[0]), .iddren_in0(iddren), + .iddren_in1(iddren), .ilaunch_clk_in0(tx_launch_clk_l[6]), + .ilaunch_clk_in1(tx_launch_clk_l[6]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp13), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[13]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[13]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), + .jtag_clkdr_out(jtag_clkdr_out_poutp13), + .odat1_aib(nc_odat1_aib_pout[13]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp13), + .odat0_aib(nc_odat0_aib_pout[13]), + .oclk_aib(nc_oclk_aib_pout[13]), + .last_bs_out(nc_last_bs_out_poutp13), + .oclkb_aib(nc_oclkb_aib_pout[13]), .jtag_clkdr_in(clkdr_xr6l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_poutp11), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[13]), .oclkn(nc_oclkn_pout[13]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpoutp14 ( .idata1_in1_jtag_out(idat1_poutp14), + .async_dat_in1_jtag_out(nc_async_dat_poutp14), + .idata0_in1_jtag_out(idat0_poutp14), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp14), + .prev_io_shift_en(rshift_en_poutp[12]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_pout[14]), .oclk_out(nc_oclk[14]), + .oclkb_out(nc_oclkb[14]), .odat0_out(nc_odat0[14]), + .odat1_out(nc_odat1[14]), .odat_async_out(nc_odat_async[14]), + .pd_data_out(nc_pd_data[14]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp14), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[14]), + .idata0_in1(idat0_poutp12), .idata1_in0(idat1[14]), + .idata1_in1(idat1_poutp12), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[0]), .iddren_in0(iddren), + .iddren_in1(iddren), .ilaunch_clk_in0(tx_launch_clk_l[3]), + .ilaunch_clk_in1(tx_launch_clk_l[3]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp14), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[14]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[14]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), + .jtag_clkdr_out(jtag_clkdr_out_poutp14), + .odat1_aib(nc_odat1_aib_pout[14]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp14), + .odat0_aib(nc_odat0_aib_pout[14]), + .oclk_aib(nc_oclk_aib_pout[14]), + .last_bs_out(nc_last_bs_out_poutp14), + .oclkb_aib(nc_oclkb_aib_pout[14]), .jtag_clkdr_in(clkdr_xr5l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_poutp12), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[14]), .oclkn(nc_oclkn_pout[14]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpoutp15 ( .idata1_in1_jtag_out(idat1_poutp15), + .async_dat_in1_jtag_out(nc_async_dat_poutp15), + .idata0_in1_jtag_out(idat0_poutp15), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp15), + .prev_io_shift_en(rshift_en_poutp[13]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_pout[15]), .oclk_out(nc_oclk[15]), + .oclkb_out(nc_oclkb[15]), .odat0_out(nc_odat0[15]), + .odat1_out(nc_odat1[15]), .odat_async_out(nc_odat_async[15]), + .pd_data_out(nc_pd_data[15]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp15), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[15]), + .idata0_in1(idat0_poutp13), .idata1_in0(idat1[15]), + .idata1_in1(idat1_poutp13), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[0]), .iddren_in0(iddren), + .iddren_in1(iddren), .ilaunch_clk_in0(tx_launch_clk_l[2]), + .ilaunch_clk_in1(tx_launch_clk_l[2]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp15), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[15]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[15]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), + .jtag_clkdr_out(jtag_clkdr_out_poutp15), + .odat1_aib(nc_odat1_aib_pout[15]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp15), + .odat0_aib(nc_odat0_aib_pout[15]), + .oclk_aib(nc_oclk_aib_pout[15]), + .last_bs_out(nc_last_bs_out_poutp15), + .oclkb_aib(nc_oclkb_aib_pout[15]), .jtag_clkdr_in(clkdr_xr6l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_poutp13), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[15]), .oclkn(nc_oclkn_pout[15]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdirect_in0 ( .idata1_in1_jtag_out(nc_idat1_inpdir3), + .async_dat_in1_jtag_out(nc_async_dat_inpdir3), + .idata0_in1_jtag_out(nc_idat0_inpdir3), + .jtag_clkdr_outn(jtag_clkdr_outn_inpdir3), + .prev_io_shift_en(rshift_en_dirclkp[1]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(ncdrx_pd_data_aib[0]), .oclk_out(ncdrx_oclk[0]), + .oclkb_out(ncdrx_oclkb[0]), .odat0_out(ncdrx_odat0[0]), + .odat1_out(ncdrx_odat1[0]), .odat_async_out(odirectin_data[0]), + .pd_data_out(ncdrx_pd_data[0]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(vssl_aibnd), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vssl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r1[2:0]), .irxen_in1(irxen_r0[2:0]), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(ncdrx_odat_async_aib[0]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(odat_async_inpclk1), + .shift_en(rshift_en_drx[0]), .pd_data_in1(vssl_aibnd), + .dig_rstb(output_rstb), .jtag_clkdr_out(jtag_clkdr_out_inpdir3), + .odat1_aib(ncdrx_odat1_aib0), + .jtag_rx_scan_out(jtag_rx_scan_out_inpdir3), + .odat0_aib(ncdrx_odat0_aib[0]), .oclk_aib(drx_oclk_aib[0]), + .last_bs_out(nc_last_bs_out_inpdir3), + .oclkb_aib(drx_oclkb_aib[0]), .jtag_clkdr_in(clkdr_xr1l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_dirclkp1), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_direct_input[0]), .oclkn(ncdrx_oclkn0), + .iclkn(oclkn_inpdir4), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xasynctx1 ( .idata1_in1_jtag_out(nc_idat1_async_out1), + .async_dat_in1_jtag_out(async_dat_async_out1), + .idata0_in1_jtag_out(nc_idat0_async_out1), + .jtag_clkdr_outn(jtag_clkdr_outn_async_out1), + .prev_io_shift_en(shift_en_inpclk6), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(output_rstb), .pd_data_aib(nctx_pd_data_aib[1]), + .oclk_out(nctx_oclk[1]), .oclkb_out(nctx_oclkb[1]), + .odat0_out(nctx_odat0[1]), .odat1_out(nctx_odat1[1]), + .odat_async_out(nctx_odat_async[1]), + .pd_data_out(nctx_pd_data[1]), .async_dat_in0(iasyncdata[1]), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(vssl_aibnd), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(idataselb[2]), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r12[1:0]), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0(ipdrv_r12[1:0]), + .ipdrv_in1({vssl_aibnd, vssl_aibnd}), .irxen_in0({vssl_aibnd, + vccl_aibnd, vssl_aibnd}), .irxen_in1(irxen_inpclk6[2:0]), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[2]), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(odat_async_oshared1), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(odat_async_aib2), + .shift_en(rshift_en_rx[1]), .pd_data_in1(vssl_aibnd), + .dig_rstb(output_rstb), .jtag_clkdr_out(jtag_clkdr_async_out1), + .odat1_aib(nctx_odat1_aib[1]), + .jtag_rx_scan_out(jtag_rx_scan_async_out1), + .odat0_aib(nctx_odat0_aib[1]), .oclk_aib(nctx_oclk_aib[1]), + .last_bs_out(nc_last_bs_out_oshared1), + .oclkb_aib(nctx_oclkb_aib[1]), .jtag_clkdr_in(clkdr_xr2r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_inpclk6), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_async_out[1]), .oclkn(nctx_oclkn[1]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xasynctx2 ( .idata1_in1_jtag_out(nc_idat1_async_out2), + .async_dat_in1_jtag_out(iasyncdata_oshared2), + .idata0_in1_jtag_out(nc_idat0_async_out2), + .jtag_clkdr_outn(jtag_clkdr_outn_async_out2), + .prev_io_shift_en(rshift_en_rx[1]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(output_rstb), .pd_data_aib(nctx_pd_data_aib[2]), + .oclk_out(nctx_oclk[2]), .oclkb_out(nctx_oclkb[2]), + .odat0_out(nctx_odat0[2]), .odat1_out(nctx_odat1[2]), + .odat_async_out(nctx_odat_async[2]), + .pd_data_out(nctx_pd_data[2]), .async_dat_in0(iasyncdata[2]), + .async_dat_in1(async_dat_async_out1), + .iclkin_dist_in0(vssl_aibnd), .iclkin_dist_in1(vssl_aibnd), + .idata0_in0(vssl_aibnd), .idata0_in1(vssl_aibnd), + .idata1_in0(vssl_aibnd), .idata1_in1(vssl_aibnd), + .idataselb_in0(idataselb[2]), .idataselb_in1(idataselb[2]), + .iddren_in0(vssl_aibnd), .iddren_in1(vssl_aibnd), + .ilaunch_clk_in0(vssl_aibnd), .ilaunch_clk_in1(vssl_aibnd), + .ilpbk_dat_in0(vssl_aibnd), .ilpbk_dat_in1(vssl_aibnd), + .ilpbk_en_in0(vssl_aibnd), .ilpbk_en_in1(vssl_aibnd), + .indrv_in0(indrv_r12[1:0]), .indrv_in1(indrv_r12[1:0]), + .ipdrv_in0(ipdrv_r12[1:0]), .ipdrv_in1(ipdrv_r12[1:0]), + .irxen_in0({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[2]), .itxen_in1(itxen[2]), .oclk_in1(vssl_aibnd), + .odat_async_aib(odat_async_aib2), .oclkb_in1(vssl_aibnd), + .odat0_in1(vssl_aibnd), .odat1_in1(vssl_aibnd), + .odat_async_in1(vssl_aibnd), .shift_en(rshift_en_rx[3]), + .pd_data_in1(vssl_aibnd), .dig_rstb(output_rstb), + .jtag_clkdr_out(jtag_clkdr_oshared2), + .odat1_aib(nctx_odat1_aib[2]), + .jtag_rx_scan_out(jtag_rx_scan_oshared2), + .odat0_aib(nctx_odat0_aib[2]), .oclk_aib(nctx_oclk_aib[2]), + .last_bs_out(nc_last_bs_out_oshared2), + .oclkb_aib(nctx_oclkb_aib[2]), .jtag_clkdr_in(clkdr_xr2r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_async_out1), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_async_out[2]), .oclkn(nctx_oclkn[2]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xasyncrx4 ( .idata1_in1_jtag_out(nc_idat1_inpshared4), + .async_dat_in1_jtag_out(nc_async_dat_inpshared4), + .idata0_in1_jtag_out(nc_idat0_inpshared4), + .jtag_clkdr_outn(jtag_clkdr_outn_inpshared4), + .prev_io_shift_en(rshift_en_rx[0]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(output_rstb), .pd_data_aib(ncrx_pd_data_aib[4]), + .oclk_out(ncrx_oclk[4]), .oclkb_out(ncrx_oclkb[4]), + .odat0_out(ncrx_odat0[4]), .odat1_out(ncrx_odat1[4]), + .odat_async_out(odat_async[4]), .pd_data_out(ncrx_pd_data[4]), + .async_dat_in0(vssl_aibnd), .async_dat_in1(async_dat_async_out0), + .iclkin_dist_in0(vssl_aibnd), .iclkin_dist_in1(vssl_aibnd), + .idata0_in0(vssl_aibnd), .idata0_in1(vssl_aibnd), + .idata1_in0(vssl_aibnd), .idata1_in1(vssl_aibnd), + .idataselb_in0(vssl_aibnd), .idataselb_in1(idataselb[2]), + .iddren_in0(vssl_aibnd), .iddren_in1(vssl_aibnd), + .ilaunch_clk_in0(vssl_aibnd), .ilaunch_clk_in1(vssl_aibnd), + .ilpbk_dat_in0(vssl_aibnd), .ilpbk_dat_in1(vssl_aibnd), + .ilpbk_en_in0(vssl_aibnd), .ilpbk_en_in1(vssl_aibnd), + .indrv_in0({vssl_aibnd, vssl_aibnd}), .indrv_in1(indrv_r12[1:0]), + .ipdrv_in0({vssl_aibnd, vssl_aibnd}), .ipdrv_in1(ipdrv_r12[1:0]), + .irxen_in0(irxen_r2[2:0]), .irxen_in1({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .istrbclk_in0(vssl_aibnd), + .istrbclk_in1(vssl_aibnd), .itxen_in0(vssl_aibnd), + .itxen_in1(itxen[2]), .oclk_in1(vssl_aibnd), + .odat_async_aib(odat_async_aib4), .oclkb_in1(vssl_aibnd), + .odat0_in1(vssl_aibnd), .odat1_in1(vssl_aibnd), + .odat_async_in1(odat_async_fsrdin), .shift_en(rshift_en_rx[2]), + .pd_data_in1(vssl_aibnd), .dig_rstb(output_rstb), + .jtag_clkdr_out(jtag_clkdr_inpshared4), + .odat1_aib(ncrx_odat1_aib[4]), + .jtag_rx_scan_out(jtag_rx_scan_inpshared4), + .odat0_aib(ncrx_odat0_aib[4]), .oclk_aib(ncrx_oclk_aib[4]), + .last_bs_out(nc_last_bs_out_inpshared4), + .oclkb_aib(ncrx_oclkb_aib[4]), .jtag_clkdr_in(clkdr_xr1r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_async_out0), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_async_in[4]), .oclkn(ncrx_oclkn4), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top x740 ( .idata1_in1_jtag_out(nc_idat1_ptxclkinn), + .async_dat_in1_jtag_out(nc_async_dat_ptxclkinn), + .idata0_in1_jtag_out(nc_idat0_ptxclkinn), + .jtag_clkdr_outn(jtag_clkdr_outn_ptxclkinn), + .prev_io_shift_en(shift_en_voutp01), .anlg_rstb(output_rstb), + .pd_data_aib(ncrx_pd_data_aib_clkn0), + .oclk_out(ncout_rx_fast_clkn[0]), + .oclkb_out(ncout_rx_fast_clknb[0]), + .odat0_out(nc_rxodat0_clkn[0]), .odat1_out(nc_rxodat1_clkn[0]), + .odat_async_out(nc_rxodat_async_clkn[0]), + .pd_data_out(nc_rxpd_data_clkn[0]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(vssl_aibnd), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(idat0_voutp01), .idata1_in0(vssl_aibnd), + .idata1_in1(idat1_voutp01), .idataselb_in0(vssl_aibnd), + .idataselb_in1(idataselb_voutp01), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(ilaunch_clk_voutp01), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1(indrv_r34[1:0]), .ipdrv_in0({vssl_aibnd, vssl_aibnd}), + .ipdrv_in1(ipdrv_r34[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(vssl_aibnd), .itxen_in1(itxen_voutp01), + .oclk_in1(vssl_aibnd), .odat_async_aib(ncrx_odat_async_aib_clkn0), + .oclkb_in1(vssl_aibnd), .jtag_clksel(jtag_clksel), + .odat0_in1(vssl_aibnd), .vssl_aibnd(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_dirclkn[0]), .pd_data_in1(vssl_aibnd), + .dig_rstb(avmm_sync_rstb), .jtag_clkdr_out(jtag_clkdr_ptxclkinn), + .jtag_intest(jtag_intest), .odat1_aib(ncrx_odat1_aib_clkn0), + .jtag_rx_scan_out(jtag_rx_scan_ptxclkinn), + .odat0_aib(ncrx_odat0_aib_clkn0), + .oclk_aib(nc_out_rx_fast_clkn_aib0), + .last_bs_out(nc_last_bs_out_ptxclkinn), .vccl_aibnd(vccl_aibnd), + .oclkb_aib(nc_out_rx_fast_clknb_aib0), .jtag_clkdr_in(clkdr_xr4l), + .jtag_rstb_en(jtag_rstb_en), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_voutp01), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_directinclkn[0]), .oclkn(oclkn_clkn0), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdirect_out1 ( + .idata1_in1_jtag_out(nc_idat1_outpdir4_1), + .async_dat_in1_jtag_out(async_dat_outpdir4_1), + .idata0_in1_jtag_out(nc_idat0_outpdir4_1), + .jtag_clkdr_outn(jtag_clkdr_outn_outpdir4_1), + .prev_io_shift_en(rshift_en_tx[1]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(output_rstb), .pd_data_aib(ncdtx_pd_data_aib[1]), + .oclk_out(ncdtx_oclk[1]), .oclkb_out(ncdtx_oclkb[1]), + .odat0_out(ncdtx_odat0[1]), .odat1_out(ncdtx_odat1[1]), + .odat_async_out(ncdtx_odat_async[1]), + .pd_data_out(ncdtx_pd_data[1]), + .async_dat_in0(idirectout_data[1]), .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(vssl_aibnd), .iclkin_dist_in1(vssl_aibnd), + .idata0_in0(vssl_aibnd), .idata0_in1(vssl_aibnd), + .idata1_in0(vssl_aibnd), .idata1_in1(vssl_aibnd), + .idataselb_in0(idataselb[3]), .idataselb_in1(vssl_aibnd), + .iddren_in0(vssl_aibnd), .iddren_in1(vssl_aibnd), + .ilaunch_clk_in0(vssl_aibnd), .ilaunch_clk_in1(vssl_aibnd), + .ilpbk_dat_in0(vssl_aibnd), .ilpbk_dat_in1(vssl_aibnd), + .ilpbk_en_in0(vssl_aibnd), .ilpbk_en_in1(vssl_aibnd), + .indrv_in0(indrv_r34[1:0]), .indrv_in1({vssl_aibnd, vssl_aibnd}), + .ipdrv_in0(ipdrv_r34[1:0]), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[3]), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(ncdtx_odat_async_aib[1]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_dtx[1]), .pd_data_in1(vssl_aibnd), + .dig_rstb(output_rstb), + .jtag_clkdr_out(jtag_clkdr_out_outpdir4_1), + .odat1_aib(ncdtx_odat1_aib[1]), + .jtag_rx_scan_out(jtag_rx_scan_out_outpdir4_1), + .odat0_aib(ncdtx_odat0_aib[1]), .oclk_aib(ncdtx_oclk_aib1), + .last_bs_out(nc_last_bs_out_outpdir4_1), + .oclkb_aib(ncdtx_oclkb_aib[1]), .jtag_clkdr_in(clkdr_xr4r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_async_in1), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_directout[1]), .oclkn(dtx_oclkn1), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpoutp18 ( .idata1_in1_jtag_out(idat1_poutp18), + .async_dat_in1_jtag_out(nc_async_dat_poutp18), + .idata0_in1_jtag_out(idat0_poutp18), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp18), + .prev_io_shift_en(rshift_en_poutp[16]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_pout[18]), .oclk_out(nc_oclk[18]), + .oclkb_out(nc_oclkb[18]), .odat0_out(nc_odat0[18]), + .odat1_out(nc_odat1[18]), .odat_async_out(nc_odat_async[18]), + .pd_data_out(nc_pd_data[18]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp18), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[18]), + .idata0_in1(idat0_poutp16), .idata1_in0(idat1[18]), + .idata1_in1(idat1_poutp16), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[0]), .iddren_in0(iddren), + .iddren_in1(iddren), .ilaunch_clk_in0(tx_launch_clk_l[5]), + .ilaunch_clk_in1(tx_launch_clk_l[5]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp18), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[18]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[18]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), + .jtag_clkdr_out(jtag_clkdr_out_poutp18), + .odat1_aib(nc_odat1_aib_pout[18]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp18), + .odat0_aib(nc_odat0_aib_pout[18]), + .oclk_aib(nc_oclk_aib_pout[18]), + .last_bs_out(nc_last_bs_out_poutp18), + .oclkb_aib(nc_oclkb_aib_pout[18]), .jtag_clkdr_in(clkdr_xr5l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_poutp16), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[18]), .oclkn(nc_oclkn_pout[18]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdiin_clkn ( .idata1_in1_jtag_out(nc_idat1_inpclk0n), + .async_dat_in1_jtag_out(nc_async_dat_inpclk0n), + .idata0_in1_jtag_out(nc_idat0_inpclk0n), + .jtag_clkdr_outn(jtag_clkdr_outn_inpclk0n), + .prev_io_shift_en(shift_en_outpdir0_1), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(ncrx_pd_data_aib_clkn1), + .oclk_out(ncout_rx_fast_clkn[1]), + .oclkb_out(ncout_rx_fast_clknb[1]), + .odat0_out(nc_rxodat0_clkn[1]), .odat1_out(nc_rxodat1_clkn[1]), + .odat_async_out(nc_rxodat_async_clkn[1]), + .pd_data_out(nc_rxpd_data_clkn[1]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(async_dat_outpdir0_1), + .iclkin_dist_in0(vssl_aibnd), .iclkin_dist_in1(vssl_aibnd), + .idata0_in0(vssl_aibnd), .idata0_in1(vssl_aibnd), + .idata1_in0(vssl_aibnd), .idata1_in1(vssl_aibnd), + .idataselb_in0(vssl_aibnd), .idataselb_in1(idataselb_outpdir0_1), + .iddren_in0(vssl_aibnd), .iddren_in1(vssl_aibnd), + .ilaunch_clk_in0(vssl_aibnd), .ilaunch_clk_in1(vssl_aibnd), + .ilpbk_dat_in0(vssl_aibnd), .ilpbk_dat_in1(vssl_aibnd), + .ilpbk_en_in0(vssl_aibnd), .ilpbk_en_in1(vssl_aibnd), + .indrv_in0({vssl_aibnd, vssl_aibnd}), .indrv_in1(indrv_r12[1:0]), + .ipdrv_in0({vssl_aibnd, vssl_aibnd}), .ipdrv_in1(ipdrv_r12[1:0]), + .irxen_in0({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(vssl_aibnd), .itxen_in1(itxen_outpdir0_1), + .oclk_in1(vssl_aibnd), .odat_async_aib(ncrx_odat_async_aib_clkn1), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_dirclkn[1]), .pd_data_in1(vssl_aibnd), + .dig_rstb(output_rstb), .jtag_clkdr_out(jtag_clkdr_inpclk0n), + .odat1_aib(ncrx_odat1_aib_clkn1), + .jtag_rx_scan_out(jtag_rx_scan_inpclk0n), + .odat0_aib(ncrx_odat0_aib_clkn1), + .oclk_aib(nc_out_rx_fast_clkn_aib1), + .last_bs_out(nc_last_bs_out_inpclk0n), + .oclkb_aib(nc_out_rx_fast_clknb_aib1), .jtag_clkdr_in(clkdr_xr2l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_outpdir0_1), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_directinclkn[1]), .oclkn(oclkn_clkn1), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpoutp16 ( .idata1_in1_jtag_out(idat1_poutp16), + .async_dat_in1_jtag_out(nc_async_dat_poutp16), + .idata0_in1_jtag_out(idat0_poutp16), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp16), + .prev_io_shift_en(rshift_en_poutp[14]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_pout[16]), .oclk_out(nc_oclk[16]), + .oclkb_out(nc_oclkb[16]), .odat0_out(nc_odat0[16]), + .odat1_out(nc_odat1[16]), .odat_async_out(nc_odat_async[16]), + .pd_data_out(nc_pd_data[16]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp16), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[16]), + .idata0_in1(idat0_poutp14), .idata1_in0(idat1[16]), + .idata1_in1(idat1_poutp14), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[0]), .iddren_in0(iddren), + .iddren_in1(iddren), .ilaunch_clk_in0(tx_launch_clk_l[1]), + .ilaunch_clk_in1(tx_launch_clk_l[1]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp16), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[16]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[16]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), + .jtag_clkdr_out(jtag_clkdr_out_poutp16), + .odat1_aib(nc_odat1_aib_pout[16]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp16), + .odat0_aib(nc_odat0_aib_pout[16]), + .oclk_aib(nc_oclk_aib_pout[16]), + .last_bs_out(nc_last_bs_out_poutp16), + .oclkb_aib(nc_oclkb_aib_pout[16]), .jtag_clkdr_in(clkdr_xr5l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_poutp14), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[16]), .oclkn(nc_oclkn_pout[16]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpoutp19 ( .idata1_in1_jtag_out(idat1_poutp19), + .async_dat_in1_jtag_out(nc_async_dat_poutp19), + .idata0_in1_jtag_out(idat0_poutp19), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp19), + .prev_io_shift_en(rshift_en_poutp[17]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .dig_rstb(poutp_dig_rstb), .pd_data_aib(nc_pd_data_aib_pout[19]), + .oclk_out(nc_oclk[19]), .oclkb_out(nc_oclkb[19]), + .odat0_out(nc_odat0[19]), .odat1_out(nc_odat1[19]), + .odat_async_out(nc_odat_async[19]), .pd_data_out(nc_pd_data[19]), + .async_dat_in0(vssl_aibnd), .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp19), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[19]), + .idata0_in1(idat0_poutp17), .idata1_in0(idat1[19]), + .idata1_in1(idat1_poutp17), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[0]), .iddren_in0(iddren), + .iddren_in1(iddren), .ilaunch_clk_in0(tx_launch_clk_l[4]), + .ilaunch_clk_in1(tx_launch_clk_l[4]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp19), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[19]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[19]), .pd_data_in1(vssl_aibnd), + .jtag_clkdr_out(jtag_clkdr_out_poutp19), + .odat1_aib(nc_odat1_aib_pout[19]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp19), + .odat0_aib(nc_odat0_aib_pout[19]), + .oclk_aib(nc_oclk_aib_pout[19]), + .last_bs_out(nc_last_bs_out_poutp19), + .oclkb_aib(nc_oclkb_aib_pout[19]), .jtag_clkdr_in(clkdr_xr6l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_poutp17), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[19]), .oclkn(nc_oclkn_pout[19]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xasyncrx2 ( .idata1_in1_jtag_out(nc_idat1_async_in2), + .async_dat_in1_jtag_out(nc_async_dat_async_in2), + .idata0_in1_jtag_out(nc_idat0_async_in2), + .jtag_clkdr_outn(jtag_clkdr_outn_inpshared2), + .prev_io_shift_en(shift_en_ssrdout), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(output_rstb), .pd_data_aib(ncrx_pd_data_aib[2]), + .oclk_out(odat_async[2]), .oclkb_out(ncrx_oclkb[2]), + .odat0_out(ncrx_odat0[2]), .odat1_out(ncrx_odat1[2]), + .odat_async_out(ncrx_async_data_out2), + .pd_data_out(ncrx_pd_data[2]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(vssl_aibnd), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(idata0_ssrdout), .idata1_in0(vssl_aibnd), + .idata1_in1(idata1_ssrdout), .idataselb_in0(vssl_aibnd), + .idataselb_in1(idataselb_ssrdout), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(ilaunch_clk_ssrdout), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1(indrv_r34[1:0]), .ipdrv_in0({vssl_aibnd, vssl_aibnd}), + .ipdrv_in1(ipdrv_r34[1:0]), .irxen_in0(irxen_r0[2:0]), + .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(vssl_aibnd), .itxen_in1(itxen_ssrdout), + .oclk_in1(oclk_inpshared0), + .odat_async_aib(ncrx_odat_async_aib[2]), + .oclkb_in1(oclkb_inpshared0), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_tx[2]), .pd_data_in1(vssl_aibnd), + .dig_rstb(avmm_sync_rstb), .jtag_clkdr_out(jtag_clkdr_async_in2), + .odat1_aib(ncrx_odat1_aib[2]), + .jtag_rx_scan_out(jtag_rx_scan_async_in2), + .odat0_aib(ncrx_odat0_aib[2]), .oclk_aib(ncrx_oclk_aib2), + .last_bs_out(nc_last_bs_out_diro2), .oclkb_aib(ncrx_oclkb_aib2), + .jtag_clkdr_in(clkdr_xr3r), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_in_ssrdout), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_async_in[2]), .oclkn(ncrx_oclkn2), + .iclkn(oclkn_inpshared3), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdirect_out2 ( + .idata1_in1_jtag_out(nc_idat1_outpdir3_1), + .async_dat_in1_jtag_out(async_dat_outpdir3_1), + .idata0_in1_jtag_out(nc_idat0_outpdir3_1), + .jtag_clkdr_outn(jtag_clkdr_outn_outpdir3_1), + .prev_io_shift_en(shift_en_in_chain2), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(ncdtx_pd_data_aib[2]), .oclk_out(ncdtx_oclk[2]), + .oclkb_out(ncdtx_oclkb[2]), .odat0_out(ncdtx_odat0[2]), + .odat1_out(ncdtx_odat1[2]), .odat_async_out(ncdtx_odat_async[2]), + .pd_data_out(ncdtx_pd_data[2]), + .async_dat_in0(idirectout_data[2]), .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(vssl_aibnd), .iclkin_dist_in1(vssl_aibnd), + .idata0_in0(vssl_aibnd), .idata0_in1(vssl_aibnd), + .idata1_in0(vssl_aibnd), .idata1_in1(vssl_aibnd), + .idataselb_in0(idataselb[3]), .idataselb_in1(vssl_aibnd), + .iddren_in0(vssl_aibnd), .iddren_in1(vssl_aibnd), + .ilaunch_clk_in0(vssl_aibnd), .ilaunch_clk_in1(vssl_aibnd), + .ilpbk_dat_in0(vssl_aibnd), .ilpbk_dat_in1(vssl_aibnd), + .ilpbk_en_in0(vssl_aibnd), .ilpbk_en_in1(vssl_aibnd), + .indrv_in0(indrv_r12[1:0]), .indrv_in1({vssl_aibnd, vssl_aibnd}), + .ipdrv_in0(ipdrv_r12[1:0]), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .irxen_in1(irxen_in_chain2[2:0]), .istrbclk_in0(vssl_aibnd), + .istrbclk_in1(vssl_aibnd), .itxen_in0(itxen[3]), + .itxen_in1(vssl_aibnd), .oclk_in1(vssl_aibnd), + .odat_async_aib(odirectin_data_out0_chain2), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_dtx[2]), .pd_data_in1(vssl_aibnd), + .dig_rstb(output_rstb), + .jtag_clkdr_out(jtag_clkdr_out_outpdir3_1), + .odat1_aib(ncdtx_odat1_aib[2]), + .jtag_rx_scan_out(jtag_rx_scan_out_outpdir3_1), + .odat0_aib(ncdtx_odat0_aib[2]), .oclk_aib(oclk_outdir3_1), + .last_bs_out(nc_last_bs_out_outpdir3_1), + .oclkb_aib(oclkb_outdir3_1), .jtag_clkdr_in(clkdr_xr1r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_scan_in_chain2), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_directout[2]), .oclkn(ncdtx_oclkn[2]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xpoutp17 ( .idata1_in1_jtag_out(idat1_poutp17), + .async_dat_in1_jtag_out(nc_async_dat_poutp17), + .idata0_in1_jtag_out(idat0_poutp17), + .jtag_clkdr_outn(jtag_clkdr_outn_poutp17), + .prev_io_shift_en(rshift_en_poutp[15]), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(nc_pd_data_aib_pout[17]), .oclk_out(nc_oclk[17]), + .oclkb_out(nc_oclkb[17]), .odat0_out(nc_odat0[17]), + .odat1_out(nc_odat1[17]), .odat_async_out(nc_odat_async[17]), + .pd_data_out(nc_pd_data[17]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(jtag_clkdr_outn_poutp17), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(idat0[17]), + .idata0_in1(idat0_poutp15), .idata1_in0(idat1[17]), + .idata1_in1(idat1_poutp15), .idataselb_in0(idataselb[0]), + .idataselb_in1(idataselb[0]), .iddren_in0(iddren), + .iddren_in1(iddren), .ilaunch_clk_in0(tx_launch_clk_l[0]), + .ilaunch_clk_in1(tx_launch_clk_l[0]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(jtag_clkdr_outn_poutp17), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[0]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(nc_odat_async_aib_pout[17]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_poutp[17]), .pd_data_in1(vssl_aibnd), + .dig_rstb(poutp_dig_rstb), + .jtag_clkdr_out(jtag_clkdr_out_poutp17), + .odat1_aib(nc_odat1_aib_pout[17]), + .jtag_rx_scan_out(jtag_rx_scan_out_poutp17), + .odat0_aib(nc_odat0_aib_pout[17]), + .oclk_aib(nc_oclk_aib_pout[17]), + .last_bs_out(nc_last_bs_out_poutp17), + .oclkb_aib(nc_oclkb_aib_pout[17]), .jtag_clkdr_in(clkdr_xr6l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_poutp15), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_dat[17]), .oclkn(nc_oclkn_pout[17]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xasynctx0 ( .idata1_in1_jtag_out(nc_idat1_async_out0), + .async_dat_in1_jtag_out(async_dat_async_out0), + .idata0_in1_jtag_out(nc_idat0_async_out0), + .jtag_clkdr_outn(jtag_clkdr_outn_async_out0), + .prev_io_shift_en(rshift_en_dtx[2]), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(output_rstb), .pd_data_aib(nctx_pd_data_aib[0]), + .oclk_out(nctx_oclk[0]), .oclkb_out(nctx_oclkb[0]), + .odat0_out(nctx_odat0[0]), .odat1_out(nctx_odat1[0]), + .odat_async_out(nctx_odat_async[0]), + .pd_data_out(nctx_pd_data[0]), .async_dat_in0(iasyncdata[0]), + .async_dat_in1(async_dat_outpdir3_1), + .iclkin_dist_in0(vssl_aibnd), .iclkin_dist_in1(vssl_aibnd), + .idata0_in0(vssl_aibnd), .idata0_in1(vssl_aibnd), + .idata1_in0(vssl_aibnd), .idata1_in1(vssl_aibnd), + .idataselb_in0(idataselb[2]), .idataselb_in1(idataselb[3]), + .iddren_in0(vssl_aibnd), .iddren_in1(vssl_aibnd), + .ilaunch_clk_in0(vssl_aibnd), .ilaunch_clk_in1(vssl_aibnd), + .ilpbk_dat_in0(vssl_aibnd), .ilpbk_dat_in1(vssl_aibnd), + .ilpbk_en_in0(vssl_aibnd), .ilpbk_en_in1(vssl_aibnd), + .indrv_in0(indrv_r12[1:0]), .indrv_in1(indrv_r12[1:0]), + .ipdrv_in0(ipdrv_r12[1:0]), .ipdrv_in1(ipdrv_r12[1:0]), + .irxen_in0({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[2]), .itxen_in1(itxen[3]), .oclk_in1(vssl_aibnd), + .odat_async_aib(odat_async_oshared0), .oclkb_in1(vssl_aibnd), + .odat0_in1(vssl_aibnd), .odat1_in1(vssl_aibnd), + .odat_async_in1(odat_async_aib4), .shift_en(rshift_en_rx[0]), + .pd_data_in1(vssl_aibnd), .dig_rstb(output_rstb), + .jtag_clkdr_out(jtag_clkdr_async_out0), + .odat1_aib(nctx_odat1_aib[0]), + .jtag_rx_scan_out(jtag_rx_scan_async_out0), + .odat0_aib(nctx_odat0_aib[0]), .oclk_aib(nctx_oclk_aib[0]), + .last_bs_out(nc_last_bs_out_oshared0), + .oclkb_aib(nctx_oclkb_aib[0]), .jtag_clkdr_in(clkdr_xr1r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_out_outpdir3_1), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_async_out[0]), .oclkn(nctx_oclkn[0]), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdirect_out0 ( + .idata1_in1_jtag_out(nc_idat1_outpdir6), + .async_dat_in1_jtag_out(idat0_outpdir6), + .idata0_in1_jtag_out(nc_idat0_outpdir6), + .jtag_clkdr_outn(jtag_clkdr_outn_outpdir6), + .prev_io_shift_en(rshift_en_poutp[19]), .anlg_rstb(output_rstb), + .pd_data_aib(ncdtx_pd_data_aib[0]), .oclk_out(ncdtx_oclk[0]), + .oclkb_out(ncdtx_oclkb[0]), .odat0_out(ncdtx_odat0[0]), + .odat1_out(ncdtx_odat1[0]), .odat_async_out(ncdtx_odat_async[0]), + .pd_data_out(ncdtx_pd_data[0]), + .async_dat_in0(idirectout_data[0]), .async_dat_in1(vssl_aibnd), + .iclkin_dist_in0(vssl_aibnd), .iclkin_dist_in1(vssl_aibnd), + .idata0_in0(vssl_aibnd), .idata0_in1(idat0_poutp19), + .idata1_in0(vssl_aibnd), .idata1_in1(idat1_poutp19), + .idataselb_in0(idataselb[3]), .idataselb_in1(idataselb[0]), + .iddren_in0(vssl_aibnd), .iddren_in1(iddren), + .ilaunch_clk_in0(tx_launch_clk_l[8]), + .ilaunch_clk_in1(tx_launch_clk_l[8]), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0(indrv_r56[1:0]), + .indrv_in1(indrv_r56[1:0]), .ipdrv_in0(ipdrv_r56[1:0]), + .ipdrv_in1(ipdrv_r56[1:0]), .irxen_in0({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(itxen[3]), .itxen_in1(itxen[0]), .oclk_in1(vssl_aibnd), + .odat_async_aib(ncdtx_odat_async_aib[0]), .oclkb_in1(vssl_aibnd), + .jtag_clksel(jtag_clksel), .odat0_in1(vssl_aibnd), + .vssl_aibnd(vssl_aibnd), .odat1_in1(vssl_aibnd), + .odat_async_in1(vssl_aibnd), .shift_en(rshift_en_dtx[0]), + .pd_data_in1(vssl_aibnd), .dig_rstb(poutp_dig_rstb), + .jtag_clkdr_out(jtag_clkdr_out_outpdir6), + .jtag_intest(jtag_intest), .odat1_aib(ncdtx_odat1_aib[0]), + .jtag_rx_scan_out(jtag_rx_scan_out_outpdir6), + .odat0_aib(ncdtx_odat0_aib[0]), .oclk_aib(ncdtx_oclk_aib0), + .last_bs_out(nc_last_bs_out_outpdir6), .vccl_aibnd(vccl_aibnd), + .oclkb_aib(ncdtx_oclkb_aib0), .jtag_clkdr_in(clkdr_xr6l), + .jtag_rstb_en(jtag_rstb_en), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_out_poutp19), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_directout[0]), .oclkn(ncdtx_oclkn0), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdiin_clkp ( .idata1_in1_jtag_out(nc_idat1_dirclkp1), + .async_dat_in1_jtag_out(nc_async_dat_dirclkp1), + .idata0_in1_jtag_out(nc_idat0_dirclkp1), + .jtag_clkdr_outn(jtag_clkdr_outn_inpclk0), + .prev_io_shift_en(shift_en_outpclk1_1), + .jtag_rstb_en(jtag_rstb_en), .jtag_clksel(jtag_clksel), + .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd), + .jtag_intest(jtag_intest), .anlg_rstb(output_rstb), + .pd_data_aib(ncrx_pd_data_aib_clkp1), + .oclk_out(out_rx_fast_clk[1]), .oclkb_out(out_rx_fast_clkb[1]), + .odat0_out(nc_rxodat0_clkp[1]), .odat1_out(nc_rxodat1_clkp[1]), + .odat_async_out(nc_rxodat_async_clkp[1]), + .pd_data_out(nc_rxpd_data_clkp[1]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(async_dat_outpclk1_1), + .iclkin_dist_in0(vssl_aibnd), .iclkin_dist_in1(vssl_aibnd), + .idata0_in0(vssl_aibnd), .idata0_in1(vssl_aibnd), + .idata1_in0(vssl_aibnd), .idata1_in1(vssl_aibnd), + .idataselb_in0(vssl_aibnd), .idataselb_in1(idataselb_outpclk1_1), + .iddren_in0(vssl_aibnd), .iddren_in1(vssl_aibnd), + .ilaunch_clk_in0(vssl_aibnd), .ilaunch_clk_in1(vssl_aibnd), + .ilpbk_dat_in0(vssl_aibnd), .ilpbk_dat_in1(vssl_aibnd), + .ilpbk_en_in0(vssl_aibnd), .ilpbk_en_in1(vssl_aibnd), + .indrv_in0({vssl_aibnd, vssl_aibnd}), .indrv_in1(indrv_r12[1:0]), + .ipdrv_in0({vssl_aibnd, vssl_aibnd}), .ipdrv_in1(ipdrv_r12[1:0]), + .irxen_in0(irxen_r0[2:0]), .irxen_in1({vssl_aibnd, vccl_aibnd, + vssl_aibnd}), .istrbclk_in0(vssl_aibnd), + .istrbclk_in1(vssl_aibnd), .itxen_in0(vssl_aibnd), + .itxen_in1(itxen_outpclk1_1), .oclk_in1(drx_oclk_aib[0]), + .odat_async_aib(ncrx_odat_async_aib_clkp1), + .oclkb_in1(drx_oclkb_aib[0]), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_dirclkp[1]), .pd_data_in1(vssl_aibnd), + .dig_rstb(output_rstb), .jtag_clkdr_out(jtag_clkdr_out_dirclkp1), + .odat1_aib(nc_odat1_aib1), + .jtag_rx_scan_out(jtag_rx_scan_out_dirclkp1), + .odat0_aib(nc_odat0_aib1), .oclk_aib(nc_out_rx_fast_clk_aib1), + .last_bs_out(nc_last_bs_out_inpclk0), + .oclkb_aib(nc_out_rx_fast_clkb_aib1), .jtag_clkdr_in(clkdr_xr1l), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_rx_scan_outpclk1_1), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_directinclkp[1]), .oclkn(nc_rxoclk_clkp1), + .iclkn(oclkn_clkn1), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top xdirect_in1 ( .idata1_in1_jtag_out(nc_idat1_inpdir0), + .async_dat_in1_jtag_out(nc_async_dat_inpdir0), + .idata0_in1_jtag_out(nc_idat0_inpdir0), + .jtag_clkdr_outn(jtag_clkdr_outn_inpdir0), + .prev_io_shift_en(shift_en_pinp0), .jtag_rstb_en(jtag_rstb_en), + .jtag_clksel(jtag_clksel), .vssl_aibnd(vssl_aibnd), + .vccl_aibnd(vccl_aibnd), .jtag_intest(jtag_intest), + .anlg_rstb(output_rstb), .pd_data_aib(ncdrx_pd_data_aib[1]), + .oclk_out(ncdrx_oclk[1]), .oclkb_out(ncdrx_oclkb[1]), + .odat0_out(ncdrx_odat0[1]), .odat1_out(ncdrx_odat1[1]), + .odat_async_out(odirectin_data[1]), + .pd_data_out(ncdrx_pd_data[1]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(iclkin_dist_pinp0), + .iclkin_dist_in1(iclkin_dist_pinp0), .idata0_in0(vssl_aibnd), + .idata0_in1(vssl_aibnd), .idata1_in0(vssl_aibnd), + .idata1_in1(vssl_aibnd), .idataselb_in0(vssl_aibnd), + .idataselb_in1(vssl_aibnd), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(vssl_aibnd), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1({vssl_aibnd, vssl_aibnd}), .ipdrv_in0({vssl_aibnd, + vssl_aibnd}), .ipdrv_in1({vssl_aibnd, vssl_aibnd}), + .irxen_in0(irxen_r1[2:0]), .irxen_in1(irxen_pinp0[2:0]), + .istrbclk_in0(istrbclk_pinp0), .istrbclk_in1(istrbclk_pinp0), + .itxen_in0(vssl_aibnd), .itxen_in1(vssl_aibnd), + .oclk_in1(vssl_aibnd), .odat_async_aib(ncdrx_odat_async_aib[1]), + .oclkb_in1(vssl_aibnd), .odat0_in1(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(odat_async_chain2), + .shift_en(rshift_en_drx[1]), .pd_data_in1(vssl_aibnd), + .dig_rstb(output_rstb), .jtag_clkdr_out(jtag_clkdr_out_chain2), + .odat1_aib(odat1_inpdir0), + .jtag_rx_scan_out(jtag_scan_out_chain2), + .odat0_aib(odat0_inpdir0), .oclk_aib(ncdrx_oclk_aib[1]), + .last_bs_out(nc_last_bs_out_inpdir0), + .oclkb_aib(ncdrx_oclkb_aib[1]), .jtag_clkdr_in(clkdr_xr7r), + .jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb), + .jtag_tx_scan_in(jtag_scan_pinp0), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_direct_input[1]), .oclkn(ncdrx_oclkn1), + .iclkn(vssl_aibnd), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +aibnd_buffx1_top x750 ( .idata1_in1_jtag_out(nc_idat1_ptxclkin), + .async_dat_in1_jtag_out(nc_async_dat_ptxclkin), + .idata0_in1_jtag_out(nc_idat0_ptxclkin), + .jtag_clkdr_outn(jtag_clkdr_outn_ptxclkin), + .prev_io_shift_en(shift_en_voutp00), .anlg_rstb(output_rstb), + .pd_data_aib(ncrx_pd_data_aib_clkp0), + .oclk_out(nc_out_rx_fast_clk0_io), .oclkb_out(out_rx_fast_clkb[0]), + .odat0_out(nc_rxodat0_clkp[0]), .odat1_out(nc_rxodat1_clkp[0]), + .odat_async_out(nc_rxodat_async_clkp[0]), + .pd_data_out(nc_rxpd_data_clkp[0]), .async_dat_in0(vssl_aibnd), + .async_dat_in1(vssl_aibnd), .iclkin_dist_in0(vssl_aibnd), + .iclkin_dist_in1(vssl_aibnd), .idata0_in0(vssl_aibnd), + .idata0_in1(idat0_voutp00), .idata1_in0(vssl_aibnd), + .idata1_in1(idat1_voutp00), .idataselb_in0(vssl_aibnd), + .idataselb_in1(idataselb_voutp00), .iddren_in0(vssl_aibnd), + .iddren_in1(vssl_aibnd), .ilaunch_clk_in0(vssl_aibnd), + .ilaunch_clk_in1(ilaunch_clk_voutp00), .ilpbk_dat_in0(vssl_aibnd), + .ilpbk_dat_in1(vssl_aibnd), .ilpbk_en_in0(vssl_aibnd), + .ilpbk_en_in1(vssl_aibnd), .indrv_in0({vssl_aibnd, vssl_aibnd}), + .indrv_in1(indrv_r34[1:0]), .ipdrv_in0({vssl_aibnd, vssl_aibnd}), + .ipdrv_in1(ipdrv_r34[1:0]), .irxen_in0(irxen_r0[2:0]), + .irxen_in1({vssl_aibnd, vccl_aibnd, vssl_aibnd}), + .istrbclk_in0(vssl_aibnd), .istrbclk_in1(vssl_aibnd), + .itxen_in0(vssl_aibnd), .itxen_in1(itxen_voutp00), + .oclk_in1(out_rx_fast_clk0_buf), + .odat_async_aib(ncrx_odat_async_aib_clkp0), + .oclkb_in1(oclkb_srclkout), .jtag_clksel(jtag_clksel), + .odat0_in1(vssl_aibnd), .vssl_aibnd(vssl_aibnd), + .odat1_in1(vssl_aibnd), .odat_async_in1(vssl_aibnd), + .shift_en(rshift_en_dirclkp[0]), .pd_data_in1(vssl_aibnd), + .dig_rstb(avmm_sync_rstb), .jtag_clkdr_out(jtag_clkdr_ptxclkin), + .jtag_intest(jtag_intest), .odat1_aib(odat1_ptxclkin), + .jtag_rx_scan_out(jtag_rx_scan_ptxclkin), + .odat0_aib(odat0_ptxclkin), .oclk_aib(oclk_aib_ptxclkin), + .last_bs_out(nc_last_bs_out_ptxclkin), .vccl_aibnd(vccl_aibnd), + .oclkb_aib(oclkb_aib_ptxclkin), .jtag_clkdr_in(clkdr_xr3l), + .jtag_rstb_en(jtag_rstb_en), .jtag_mode_in(jtag_mode_in), + .jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_rx_scan_voutp00), + .jtag_tx_scanen_in(jtag_tx_scanen_in), .last_bs_in(vssl_aibnd), + .iopad(iopad_directinclkp[0]), .oclkn(nc_rxoclk_clkp0), + .iclkn(oclkn_clkn0), .test_weakpu(jtag_weakpu), + .test_weakpd(jtag_weakpdn)); +assign outbuf_clk_buf = output_buffer_clk; + +wire rb_dcc_byp_inv; +assign rb_dcc_byp_inv = ~rb_dcc_byp_dprio; + +wire rb_dcc_en_dprio_buf , rb_dcc_manual_mode_dprio_buf; +assign rb_dcc_en_dprio_buf = rb_dcc_en_dprio; +assign rb_dcc_manual_mode_dprio_buf = rb_dcc_manual_mode_dprio ; //modified by Ana to pass linting(undriven),suspected typo[Nov4,2015] + +aibnd_dcc_top x711 ( .vcc_aibnd(vccl_aibnd), + .rb_cont_cal(rb_dcc_manual_mode_dprio_buf), .scan_shift_n(scan_shift_n), + .vss_aibnd(vssl_aibnd), .rb_clkdiv(rb_clkdiv[2:0]), + .rb_dcc_manual_up(rb_dcc_manual_up[4:0]), .scan_rst_n(scan_rst_n), + .clktree_out(clk_mimic0_buf), + .rb_dcc_manual_dn(rb_dcc_manual_dn[4:0]), + .dcc_dft_nrst_coding(dcc_dft_nrst_coding), + .dcc_dft_nrst(dcc_dft_nrst), .dcc_dft_up(dcc_dft_up), + .rb_dcc_dft(rb_dcc_dft), .rb_dcc_dft_sel(rb_dcc_dft_sel), + .scan_out(dcc_scan_out), .scan_mode_n(scan_mode_n), + .scan_in(scan_in), .pipeline_global_en(pipeline_global_en), + .scan_clk_in(scan_clk_in), .rb_dcc_byp(rb_dcc_byp_inv), + .vcc_io(vccl_aibnd), .clk_dcc(clktree_in), .dcc_done(dcc_done), + .odll_dll2core(odcc_dll2core[12:0]), .clk_dcd(outbuf_clk_buf), + .csr_reg(csr_reg[51:0]), .dcc_req(dcc_req), + .idll_core2dll(oaibdftcore2dcc[2:0]), .idll_entest(idll_entest), + .nfrzdrv(output_rstb), .rb_dcc_en(rb_dcc_en_dprio_buf), + .rb_half_code(rb_half_code), .rb_selflock(rb_selflock), + .test_clk_pll_en_n(rb_dcc_test_clk_pll_en_n)); +aibnd_aliasd aliasv8 ( .MINUS(ilaunch_clk_poutp18), .PLUS(tx_launch_clk_l[9])); +aibnd_aliasd aliasd21 ( .MINUS(shift_en_ptxclkinn), .PLUS(rshift_en_dirclkn[0])); +aibnd_aliasd aliasd20 ( .MINUS(oclkn_outpdir4_1), .PLUS(dtx_oclkn1)); +aibnd_aliasd aliasd12 ( .MINUS(shift_en_inpshared4), .PLUS(rshift_en_rx[2])); +aibnd_aliasd aliasd13 ( .MINUS(shift_en_oshared2), .PLUS(rshift_en_rx[3])); +aibnd_aliasd aliasd18 ( .MINUS(shift_en_outpdir6), .PLUS(rshift_en_dtx[0])); +aibnd_aliasd aliasv25[2:0] ( .MINUS(irxen_chain2[2:0]), .PLUS(irxen_r1[2:0])); +aibnd_aliasd aliasv24[2:0] ( .MINUS(irxen_inpdir3[2:0]), .PLUS(irxen_r1[2:0])); +aibnd_aliasd aliasv23[2:0] ( .MINUS(irxen_ptxclkin[2:0]), .PLUS(irxen_r0[2:0])); +aibnd_aliasd aliasd19 ( .MINUS(shift_en_poutp18), .PLUS(rshift_en_poutp[18])); +aibnd_aliasd aliasd17 ( .MINUS(shift_en_ptxclkin), .PLUS(rshift_en_dirclkp[0])); +aibnd_aliasd aliasd16 ( .MINUS(shift_en_outpdir1_1), .PLUS(rshift_en_dtx[3])); +aibnd_aliasd aliasd6 ( .MINUS(idataselb_oshared2), .PLUS(idataselb[2])); +aibnd_aliasd aliasd9 ( .MINUS(itxen_oshared2), .PLUS(itxen[2])); +aibnd_aliasd aliasd10[2:0] ( .MINUS(irxen_inpshared0[2:0]), .PLUS(irxen_r0[2:0])); +aibnd_aliasd aliasd3[2:0] ( .MINUS(irxen_inpshared4[2:0]), .PLUS(irxen_r2[2:0])); +aibnd_aliasd aliasv19[2:0] ( .MINUS(irxen_inpclk3[2:0]), .PLUS(irxen_r1[2:0])); +aibnd_aliasd aliasv15 ( .MINUS(idataselb_outpdir1_1), .PLUS(idataselb[3])); +aibnd_aliasd aliasd11 ( .MINUS(shift_en_inpshared0), .PLUS(rshift_en_tx[0])); +aibnd_aliasd aliasd15 ( .MINUS(shift_en_inpclk0n), .PLUS(rshift_en_dirclkn[1])); +aibnd_aliasd aliasv12 ( .MINUS(itxen_outpdir1_1), .PLUS(itxen[3])); +aibnd_aliasd aliasv7 ( .MINUS(itxen_outpdir6), .PLUS(itxen[3])); +aibnd_aliasd aliasv9 ( .MINUS(idataselb_poutp18), .PLUS(idataselb[0])); +aibnd_aliasd aliasv17 ( .MINUS(iddren_poutp18), .PLUS(iddren)); +aibnd_aliasd aliasd23 ( .MINUS(shift_en_inpclk3), .PLUS(rshift_en_drx[2])); +aibnd_aliasd aliasd22 ( .MINUS(shift_en_out_chain2), .PLUS(rshift_en_drx[1])); +aibnd_aliasd aliasv16 ( .MINUS(idataselb_outpdir6), .PLUS(idataselb[3])); +aibnd_aliasd aliasv1 ( .MINUS(itxen_poutp18), .PLUS(itxen[0])); +aibnd_aliasd aliasd14 ( .MINUS(shift_en_inpdir3), .PLUS(rshift_en_drx[0])); + +aibnd_clkmux2 xtx_rx_clkmx ( + .oclk_out(out_rx_fast_clk[0]), + .mux_sel(rshift_en_dirclkp[0]), .oclk_in0(oclk_aib_ptxclkin), + .oclk_in1(oclk_srclkout)); + +assign out_rx_fast_clk0_buf = out_rx_fast_clk[0] ; + +assign oaibdftdll2core[10] = mux_dft_dll2core[10]; +assign oaibdftdll2core[11] = mux_dft_dll2core[11]; +assign oaibdftdll2core[9] = mux_dft_dll2core[9]; +assign buf_dcc2core[1] = odcc_dll2core[1]; +assign oaibdftdll2core[12] = mux_dft_dll2core[12]; +assign oaibdftcore2dll[2] = oaibdftcore2dcc[2]; +assign oaibdftcore2dcc[1] = iaibdftcore2dll[1]; +assign buf_dcc2core[2] = odcc_dll2core[2]; +assign oaibdftcore2dll[1] = oaibdftcore2dcc[1]; +assign buf_dcc2core[11] = odcc_dll2core[11]; +assign buf_dll2core[8] = idll_dll2core[8]; +assign buf_dll2core[7] = idll_dll2core[7]; +assign buf_dll2core[5] = idll_dll2core[5]; +assign oaibdftdll2core[8] = mux_dft_dll2core[8]; +assign buf_dcc2core[6] = odcc_dll2core[6]; +assign oaibdftdll2core[7] = mux_dft_dll2core[7]; +assign buf_dcc2core[8] = odcc_dll2core[8]; +assign buf_dll2core[6] = idll_dll2core[6]; +assign oaibdftdll2core[5] = mux_dft_dll2core[5]; +assign buf_dcc2core[7] = odcc_dll2core[7]; +assign oaibdftdll2core[6] = mux_dft_dll2core[6]; +assign buf_dcc2core[5] = odcc_dll2core[5]; +assign buf_dll2core[4] = idll_dll2core[4]; +assign buf_dcc2core[12] = odcc_dll2core[12]; +assign buf_dll2core[10] = idll_dll2core[10]; +assign buf_dll2core[9] = idll_dll2core[9]; +assign buf_dll2core[11] = idll_dll2core[11]; +assign oaibdftdll2core[4] = mux_dft_dll2core[4]; +assign buf_dcc2core[4] = odcc_dll2core[4]; +assign buf_dcc2core[3] = odcc_dll2core[3]; +assign oaibdftdll2core[0] = mux_dft_dll2core[0]; +assign buf_dcc2core[0] = odcc_dll2core[0]; +assign oaibdftcore2dcc[2] = iaibdftcore2dll[2]; +assign buf_dll2core[1] = idll_dll2core[1]; +assign oaibdftdll2core[1] = mux_dft_dll2core[1]; +assign oaibdftcore2dll[0] = oaibdftcore2dcc[0]; +assign buf_dll2core[0] = idll_dll2core[0]; +assign oaibdftcore2dcc[0] = iaibdftcore2dll[0]; +assign buf_dcc2core[9] = odcc_dll2core[9]; +assign buf_dll2core[12] = idll_dll2core[12]; +assign oaibdftdll2core[2] = mux_dft_dll2core[2]; +assign buf_dll2core[2] = idll_dll2core[2]; +assign buf_dll2core[3] = idll_dll2core[3]; +assign oaibdftdll2core[3] = mux_dft_dll2core[3]; +assign buf_dcc2core[10] = odcc_dll2core[10]; +assign mux_dft_dll2core[2] = rb_dcc_dll_dft_sel ? buf_dcc2core[2] : buf_dll2core[2]; +assign mux_dft_dll2core[10] = rb_dcc_dll_dft_sel ? buf_dcc2core[10] : buf_dll2core[10]; +assign mux_dft_dll2core[6] = rb_dcc_dll_dft_sel ? buf_dcc2core[6] : buf_dll2core[6]; +assign mux_dft_dll2core[8] = rb_dcc_dll_dft_sel ? buf_dcc2core[8] : buf_dll2core[8]; +assign mux_dft_dll2core[7] = rb_dcc_dll_dft_sel ? buf_dcc2core[7] : buf_dll2core[7]; +assign mux_dft_dll2core[5] = rb_dcc_dll_dft_sel ? buf_dcc2core[5] : buf_dll2core[5]; +assign mux_dft_dll2core[4] = rb_dcc_dll_dft_sel ? buf_dcc2core[4] : buf_dll2core[4]; +assign mux_dft_dll2core[3] = rb_dcc_dll_dft_sel ? buf_dcc2core[3] : buf_dll2core[3]; +assign mux_dft_dll2core[0] = rb_dcc_dll_dft_sel ? buf_dcc2core[0] : buf_dll2core[0]; +assign mux_dft_dll2core[1] = rb_dcc_dll_dft_sel ? buf_dcc2core[1] : buf_dll2core[1]; +assign mux_dft_dll2core[9] = rb_dcc_dll_dft_sel ? buf_dcc2core[9] : buf_dll2core[9]; +assign mux_dft_dll2core[12] = rb_dcc_dll_dft_sel ? buf_dcc2core[12] : buf_dll2core[12]; +assign mux_dft_dll2core[11] = rb_dcc_dll_dft_sel ? buf_dcc2core[11] : buf_dll2core[11]; +assign scan_out = dcc_scan_out; +//assign clk_mimic0_buf = clk_mimic0; +assign clk_mimic0_buf = 1'b0; +assign clk_mimic1_buf = clk_mimic1; +assign dft_rx_clk = gated_clk_mimic1; +assign gated_clk_mimic1 = clk_mimic1_buf & dll_csr_reg6; +assign nc_clk_repb = !clk_rep; +//assign nc_clk_mimic = !clk_mimic; +assign nc_clk_mimic = 1'b1; + + +endmodule + diff --git a/maib_rtl/aibnd_lib/rtl/block_function/aibnd_txdig.v b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_txdig.v new file mode 100644 index 0000000..f5ab27e --- /dev/null +++ b/maib_rtl/aibnd_lib/rtl/block_function/aibnd_txdig.v @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Library - aibnd_lib, Cell - aibnd_txdig, View - schematic +// LAST TIME SAVED: Dec 12 16:40:31 2014 +// NETLIST TIME: Dec 17 10:24:02 2014 + +module aibnd_txdig ( ndrv_sel0b, ndrv_sel1b, ndrv_sel2b, ndrv_sel3b, + pdrv_sel0, pdrv_sel1, pdrv_sel2, pdrv_sel3, tx_dat_out, + weak_pulld_en, weak_pullu_enb, async_data, clkdr, idat0, idat1, + idataselb, iddrctrl, ilaunch_clk, ilpbk_dat, ilpbk_en, indrv, + ipadrstb, ipdrv, irstb, itx_en, rx_enb, test_weakpd, test_weakpu, + testmode_en, vccl_aibnd, vssl_aibnd ); + +output ndrv_sel0b, ndrv_sel1b, ndrv_sel2b, ndrv_sel3b, pdrv_sel0, + pdrv_sel1, pdrv_sel2, pdrv_sel3, tx_dat_out, weak_pulld_en, + weak_pullu_enb; + +input async_data, clkdr, idat0, idat1, idataselb, iddrctrl, + ilaunch_clk, ilpbk_dat, ilpbk_en, ipadrstb, irstb, itx_en, rx_enb, + test_weakpd, test_weakpu, testmode_en, vccl_aibnd, vssl_aibnd; + +input [1:0] indrv; +input [1:0] ipdrv; + +wire mux_clk, testmode_en, clkdr, ilaunch_clk, ff1_latch_input, iddrctrl, ff1_dout, ff0_dout, mux_out, clk, ff1_latch_dout, lpb_or_clk, ilpbk_en_buf, ilpbk_dat, async_data_buf, mux_din, idataselb, tx_dat_out, clkb, idat1, din1, idat0, din0, itx_enb, itx_en_buf, weak_pullu_enb, ipadrstb_buf, test_weakpu_buf, weak_pulld_en, weak_pulld_enb, itx_en, ipadrstb, test_weakpd_buf, txenb_rxenb, ilpbk_en, async_data, irstb_buf, irstb, rx_enb, test_weakpu, test_weakpd; // Conversion Sript Generated + +// Buses in the design + +wire [1:0] indrv_buf; + +wire [1:0] ipdrv_buf; + + +//Bypass by KSCHIA ww21. +//assign mux_clk = testmode_en ? clkdr : ilaunch_clk; +assign ff1_latch_input = iddrctrl ? ff1_dout : ff0_dout; +assign mux_out = clk ? ff1_latch_dout : ff0_dout; + +//Bypass by KSCHIA ww21. +//assign lpb_or_clk = ilpbk_en_buf ? ilpbk_dat : async_data_buf; +//assign mux_din = idataselb ? mux_out : lpb_or_clk; +//assign mux_din = idataselb ? mux_out : async_data_buf; +//assign tx_dat_out = mux_din; +assign tx_dat_out = idataselb ? mux_out : async_data_buf; +aibnd_latch lyn0 ( .clk(clkb), .rb(irstb_buf) /*`ifndef INTCNOPWR , .vcc(vccl_aibnd) , .vss(vssl_aibnd) `endif*/ , .d(ff1_latch_input), .o(ff1_latch_dout)); +assign clkb = !clk; +aibnd_2to4dec xpredriver_decoder ( .vccl_aibnd(vccl_aibnd), + .vssl_aibnd(vssl_aibnd), .nsel_out3b(ndrv_sel3b), + .nsel_out2b(ndrv_sel2b), .nsel_out1b(ndrv_sel1b), + .nsel_out0b(ndrv_sel0b), .psel_out0(pdrv_sel0), + .psel_in(ipdrv_buf[1:0]), .psel_out1(pdrv_sel1), + .psel_out2(pdrv_sel2), .psel_out3(pdrv_sel3), + .nsel_in(indrv_buf[1:0]), .enable(itx_en_buf)); +assign indrv_buf[1:0] = indrv[1:0]; +assign ipdrv_buf[1:0] = ipdrv[1:0]; +//assign clk = mux_clk; +assign clk = ilaunch_clk; +assign din1 = idat1; +assign din0 = idat0; +assign itx_en_buf = !itx_enb; +aibnd_ff_r fyn1 ( .o(ff0_dout), .d(din0), .clk(clk) /*`ifndef INTCNOPWR , .vss(vssl_aibnd) , .vcc(vccl_aibnd) `endif*/ , .rb(irstb_buf)); +aibnd_ff_r fyn0 ( .o(ff1_dout), .d(din1), .clk(clk) /*`ifndef INTCNOPWR , .vss(vssl_aibnd) , .vcc(vccl_aibnd) `endif*/ , .rb(irstb_buf)); +assign weak_pullu_enb = !(ipadrstb_buf & test_weakpu_buf); +assign weak_pulld_en = !(ipadrstb_buf & weak_pulld_enb); +wire test_weakpdb_por; +wire txen_an_weakpdb; +assign test_weakpdb_por = !test_weakpd ; +assign txen_an_weakpdb = itx_en & test_weakpdb_por ; + +assign itx_enb = !(txen_an_weakpdb & ipadrstb); +assign weak_pulld_enb = !(test_weakpd_buf | txenb_rxenb); +assign ilpbk_en_buf = ilpbk_en; +assign async_data_buf = async_data; +assign irstb_buf = irstb; +assign txenb_rxenb = rx_enb & itx_enb; +assign ipadrstb_buf = ipadrstb; +assign test_weakpu_buf = test_weakpu; +assign test_weakpd_buf = test_weakpd; + +endmodule + diff --git a/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_bsr_red_wrap.v b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_bsr_red_wrap.v new file mode 100644 index 0000000..0374989 --- /dev/null +++ b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_bsr_red_wrap.v @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Verilog HDL and netlist files of +// "aibndpnr_lib aibndpnr_bsr_red_wrap schematic" + + +// Library - aibndpnr_lib(// Library - aibndpnr_lib), Cell - aibndpnr_bsr_red_wrap, View - schematic +// LAST TIME SAVED: Oct 24 09:56:41 2014 +// NETLIST TIME: Oct 29 15:26:36 2014 + +module aibndpnr_bsr_red_wrap ( anlg_rstb_aib, async_data_out, + dig_rstb_aib, idata0_out, idata1_out, + idataselb_out, iddren_out, + indrv_out, ipdrv_out, irxen_out, + itxen_out, jtag_clkdr_out, jtag_rx_scan_out, + odat0_out, odat1_out, + odat_async_out, anlg_rstb_adap, //removed VCCL & VSS port + async_dat_in0, async_dat_in1, dig_rstb_adap, + idata0_in0, idata0_in1, idata1_in0, idata1_in1, + idataselb_in0, idataselb_in1, iddren_in0, iddren_in1, + indrv_in0, indrv_in1, ipdrv_in0, + ipdrv_in1, irxen_in0, irxen_in1, + itxen_in0, itxen_in1, jtag_clkdr_in, + jtag_mode_in, jtag_rstb_en, jtag_rstb, + jtag_tx_scan_in, jtag_tx_scanen_in, + oclk_in, oclkb_in, + odat0_in0, odat0_in1, odat1_in0, odat1_in1, + odat_async_in0, odat_async_in1, + shift_en, jtag_intest, jtag_clkdr_outn, idata0_red, idata1_red, async_dat_red ); + +output anlg_rstb_aib, async_data_out, dig_rstb_aib, + idata0_out, idata1_out, idataselb_out, iddren_out, + itxen_out, + jtag_clkdr_out, jtag_clkdr_outn, jtag_rx_scan_out, + odat0_out, odat1_out, odat_async_out; + +//input vccl, vssl; + +input anlg_rstb_adap, async_dat_in0, async_dat_in1, dig_rstb_adap, + idata0_in0, idata0_in1, + idata1_in0, idata1_in1, idataselb_in0, idataselb_in1, iddren_in0, + iddren_in1, + itxen_in0, itxen_in1, jtag_clkdr_in, + jtag_mode_in, jtag_rstb_en, jtag_rstb, + jtag_tx_scan_in, + jtag_tx_scanen_in, + oclk_in, oclkb_in, + odat0_in0, odat0_in1, + odat1_in0, odat1_in1, odat_async_in0, + odat_async_in1, shift_en; + +output [2:0] irxen_out; +output [1:0] ipdrv_out; +output [1:0] indrv_out; +output idata0_red; +output idata1_red; +output async_dat_red; + +input [1:0] indrv_in1; +input [2:0] irxen_in0; +input [1:0] ipdrv_in1; +input [2:0] irxen_in1; +input [1:0] ipdrv_in0; +input [1:0] indrv_in0; +input jtag_intest; + +wire [2:0] irxen_red; +wire odat0_red; +wire odat1_red; +wire odat_async_red; +wire itxen_red; + +aibndpnr_redundancy xredundancy ( +//input of input mux +.idata0_in1(idata0_in1), +.idata0_in0(idata0_red), +.idata1_in1(idata1_in1), +.idata1_in0(idata1_red), +.idataselb_in1(idataselb_in1), +.idataselb_in0(idataselb_in0), +.iddren_in1(iddren_in1), +.iddren_in0(iddren_in0), +.irxen_in1(irxen_in1), +.irxen_in0(irxen_red), +.itxen_in1(itxen_in1), +.itxen_in0(itxen_red), +.indrv_in1(indrv_in1), +.indrv_in0(indrv_in0), +.ipdrv_in1(ipdrv_in1), +.ipdrv_in0(ipdrv_in0), +.async_dat_in1(async_dat_in1), +.async_dat_in0(async_dat_red), +//Output of input mux +.idata0_out(idata0_out), +.idata1_out(idata1_out), +.idataselb_out(idataselb_out), +.iddren_out(iddren_out), +.irxen_out(irxen_out), +.itxen_out(itxen_out), +.indrv_out(indrv_out), +.ipdrv_out(ipdrv_out), +.async_dat_out(async_data_out), + +//input of output mux +.odat0_in1(odat0_in1), +.odat0_in0(odat0_in0), +.odat1_in1(odat1_in1), +.odat1_in0(odat1_in0), +.odat_async_in1(odat_async_in1), +.odat_async_in0(odat_async_in0), + +//Output of output mux +.odat0_out(odat0_red), +.odat1_out(odat1_red), +.odat_async_out(odat_async_red), + +//Mux selection signal +.shift_en(shift_en) + ); //removed VCCL & VSS port + + +aibndpnr_jtag_bscan xjtag( +.odat0_aib(odat0_red), //sync data0 RX from AIB +.odat1_aib(odat1_red), //sync data1 RX from AIB +.odat_asyn_aib(odat_async_red), //async data RX from AIB +.oclkp_aib(oclk_in), //diff clk RX from AIB +.oclkn_aib(oclkb_in), //diff clk RX from AIB +.itxen_adap(itxen_in0), //OE TX from HSSI Adapter +.idat0_adap(idata0_in0), //SDR dat0 TX from HSSI Adapter +.idat1_adap(idata1_in0), //SDR dat1 TX from HSSI Adapter +.async_data_adap(async_dat_in0), //async data TX from HSSI Adapter +.jtag_tx_scanen_in(jtag_tx_scanen_in), //JTAG shift DR, active high +//.jtag_rx_scanen_in(jtag_rx_scanen_in), //JTAG shift DR, active high +.jtag_clkdr_in(jtag_clkdr_in), //JTAG boundary scan clock +.jtag_tx_scan_in(jtag_tx_scan_in), //JTAG TX data scan in +//.jtag_rx_scan_in(jtag_rx_scan_in), //JTAG TX data scan in +.jtag_mode_in(jtag_mode_in), //JTAG mode select +//.idataselb_adap(idataselb_in0), //idat_selb functional tie-off +//.iddren_adap(iddren_in0), //iddr_en functional tie-off + + +//.jtag_loopbacken_in(jtag_loopbacken_in), //HIJACK_DFT TW: need to remove from top level schematic +.anlg_rstb_adap(anlg_rstb_adap), //IRSTB from Adaptor +.dig_rstb_adap(dig_rstb_adap), //IRSTB from Adaptor +.jtag_rstb_en(jtag_rstb_en), //reset_en from TAP +.jtag_rstb(jtag_rstb), //reset signal from TAP +.jtag_intest(jtag_intest), +.irxen_adap(irxen_in0), + +.jtag_clkdr_out(jtag_clkdr_out), //CLKDR to remaining BSR +//.jtag_tx_scan_out(jtag_tx_scan_out), //JTAG TX scan chain output +.jtag_rx_scan_out(jtag_rx_scan_out), //JTAG TX scan chain output +.odat0_adap(odat0_out), //sync data0 RX to HSSI Adapter +.odat1_adap(odat1_out), //sync data1 RX to HSSI Adapter +.odat_asyn_adap(odat_async_out), //async data RX to HSSI Adapter +.itxen_aib(itxen_red), //OE TX to AIB +.idat0_aib(idata0_red), //SDR dat0 TX to AIB +.idat1_aib(idata1_red), //SDR dat1 TX to AIB +.async_data_aib(async_dat_red), //async data TX to AIB +.anlg_rstb_aib(anlg_rstb_aib), //irstb to AIB +.dig_rstb_aib(dig_rstb_aib), //irstb to AIB +.irxen_aib(irxen_red), +.jtag_clkdr_outn(jtag_clkdr_outn) +//.idataselb_aib(idataselb_red), //idat_selb to AIB +//.iddren_aib(iddren_red), //iddr_en to AIB + +); + + +endmodule + + +// End HDL models + diff --git a/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_define.v b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_define.v new file mode 100644 index 0000000..25f0fef --- /dev/null +++ b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_define.v @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +`define ALTR_HPS_INTEL_MACROS_OFF +`define ALTR_HPS_MEMORY_OFF diff --git a/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkgate_cgc00.v b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkgate_cgc00.v new file mode 100644 index 0000000..d822184 --- /dev/null +++ b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkgate_cgc00.v @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module aibndpnr_dll_atech_clkgate_cgc00 +( + input wire clk, + input wire en, + output wire clkout +); + +reg o; + +always @ (en, clk) + begin + if (~clk) + begin + o <=en; + end + end + +assign clkout = clk & o; + + + +endmodule diff --git a/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkgate_cgc01.v b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkgate_cgc01.v new file mode 100644 index 0000000..d58d2b2 --- /dev/null +++ b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkgate_cgc01.v @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module aibndpnr_dll_atech_clkgate_cgc01 +( + input wire clk, + input wire en, + input wire te, + output wire clkout +); + +wire d; +reg o; + +assign d = en | te; + +always @ (d, clk) + begin + if (~clk) + begin + o <=d; + end + end + +assign clkout = clk & o; + + + +endmodule diff --git a/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkmux.v b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkmux.v new file mode 100644 index 0000000..e3f193c --- /dev/null +++ b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkmux.v @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module aibndpnr_dll_atech_clkmux + +// IMPORTANT NOTICE: This clock mux behavioral model +// must be mapped to either a transmission gate mux +// or a pass gate mux in the standard cell library. +// Failure to comply will result in glitch hazards. + +( + input wire clk1, + input wire clk2, + input wire s, // Select + output wire clkout +); + +assign clkout = s ? clk1 : clk2; // 2:1 clock mux + +endmodule diff --git a/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_core.v b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_core.v new file mode 100644 index 0000000..1a44a96 --- /dev/null +++ b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_core.v @@ -0,0 +1,556 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +// +// Revision: $Revision: #6 $ +// Date: $DateTime: 2015/12/02 22:11:55 $ +//------------------------------------------------------------------------ +// Description: dll core logic +// 1. added in new csr bits : rb_clkdiv[1:0],rb_selflock,rb_half_code,rb_dly_pst +// 2. changed dll_lock port to lock (to cater for self-timed lock signal +// 3. instanciated aibndpnr_self_lock_assertion and aibndpnr_half_cycle_code_gen +// 4. added output port pvt_ref_half_gry[9:0] +// 5. added synchronizers for t_up and t_down +// 6. separated coarse and fine delay codes in gray-code generation +// 7. move synchronizers to aibndpnr_dll_pnr level +// 8. bring out [6:0] gate_shf +// 9. added synchronizers for core_up and core_dn +// 10. added prelock to partition >1 step jump and <=1 step jump +// 11. increase bus width of rb_clkdiv to 3 bit +// 12. removed up[4:1] and down[4:1] from tcalc_up and tcalc_down calculations +// 13. added scan_mode_n for self_lock_assertion scan chain +// 14. removed pvt_ref_half_gray_pst by directly reset pvt_ref_half_gry bits to 0 +// 15. updated core_up and core_dn cdclib instance parameters +//------------------------------------------------------------------------ +// To be changed : +//------------------------------------------------------------------------ + +module aibndpnr_dll_core +#( +//----------------------------------------------------------------------------------------------------------------------- +// Configuration parameters +//----------------------------------------------------------------------------------------------------------------------- +//----------------------------------------------------------------------------------------------------------------------- +// Local calculated parameters +//----------------------------------------------------------------------------------------------------------------------- +parameter FF_DELAY = 200 +) +( + input wire clk, + input wire reset_n, + input wire rb_ctlsel, // static setting selection + input wire [9:0] rb_ctl_static, // dll static setting from csr + input wire rb_core_updnen, // core updown control enable + input wire [9:0] rb_dly_pst, // counter preset value + output wire up_core, // updown signal to core + output wire dn_core, // updown signal to core + input wire core_up, // up signal from core + input wire core_dn, // down signal from core + input wire t_up, // output of phase detector + input wire t_down, // output of phase detector + input wire [2:0] rb_clkdiv, //select division factor for clock + input wire rb_selflock, //select between lock signal from self-timed logics or FSM lock monitor + input wire rb_half_code, //select between original or half-cycle codes + input wire scan_mode_n, + output wire launch, // Decode from gate_shf, Used as the input to the delay line + output wire measure, // Decode from gate_shf, Used as the clock for the phase detector + output wire [6:0] f_gray, // gray code for nand delay chain + output wire [2:0] i_gray, // gray code for phase interpolator + output wire lock, // "1" when lock found. Output lock to core + output wire [9:0] pvt_ref_binary, // output binary pvt value for delay chain + output reg [9:0] internal_pvt_binary, // registered binary pvt value for dll internal delay chain + output reg search_overflow, + output reg [3:0] gate_state, // State Machine used to implement the fast binary search + output reg [6:0] gate_shf, // Used with gate_cnt to process the UP/DOWN sampling + output reg [9:0] pvt_ref_gry, // output gray code for dll delay setting + output reg [9:0] pvt_ref_half_gry // divided-by-4 output gray code for dll delay setting +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +//----------------------------------------------------------------------------------------------------------------------- +// reg and wire +//----------------------------------------------------------------------------------------------------------------------- + +wire core_up_sync; +wire core_dn_sync; +wire [9:0] int_pvt_value; // binary pvt value for delay chain +reg [12:0] pvt_value; // binary pvt value for delay chain +wire [9:0] pvt_ref_gray; // output gray pvt value for delay chain nand +wire [9:0] pvt_ref_half_gray; // divided-by-2 output gray pvt value for delay chain nand +wire [9:0] pvt_ref_half_binary;//divided-by-2 output binary pvt value for delay chain nand +reg [3:0] gate_cnt; // Counter used to time the UP/DOWN sampling +//reg [6:0] gate_shf; // Used with gate_cnt to process the UP/DOWN sampling +wire core_capture; // Decode from gate_shf, Used to time when to capture core_up and core_dn +wire up_down_capture; // Decode from gate_shf, Used to time when to use the t_up,t_down outputs of the phase detector +wire tog_state; // Decode from gate_shf, Used to time when to change the value of the state machine +wire pgm_write; // Decode from gate_shf, Used to time when to change the value of the delay chain, ??? +wire load_en; // Decode from gate_shf, Used to time when to change the value of the delay chain, ??? +wire filter_load; // Decode from gate_shf, Used to time when to update the UP/DOWN counter, {pvt_value[12:0],o_filter[7:0]} +wire [4:0] state_adder; // The offset from the internal_value used for the fast binary search +wire [13:0] search_value; // The internal_value + offset used to set the delay of the delay line +wire phase_clk; +reg [4:0] up, down; +reg core_up_reg; +reg core_dn_reg; +wire t_up_in; +wire t_down_in; +wire new_t_up; +wire new_t_down; +wire any_up; +wire any_down; +wire large_up; +wire large_down; +reg mem_up, mem_down; +reg [5:0] accel_up; +reg [5:0] accel_down; +reg [3:0] lock_cnt; +wire dll_lock_det; +wire [15:0] tcalc_up; +wire [15:0] tcalc_down; +reg [12:0] internal_value; // The internal UP/DOWN value, the unfiltered version of pvt_value[12:0] +reg [1:0] i_filter; // The tiny filter 2-bits used with internal_value[12:0] +reg [7:0] o_filter; // The larger filter 8-bits use with pvt_value[12:0] +wire dll_lock; // lock signal from FSM (lock monitor) +wire [9:0] pvt_ref_bin; // pre-divided-by-2 delay setting +wire [9:0] pvt_ref_half_binary_pst; //divided-by-2 preset binary setting +wire [9:0] pvt_ref_half_gray_pst; // divided-by-2 preset gray setting +wire prelock; +//----------------------------------------------------------------------------------------------------------------------- +// Divide the clock by 16 +// ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ +// gate_cnt |__1_|__2_|__3_|__4_|__5_|__6_|__7_|__8_|__9_|_10_|_11_| +// _________ _________ +// gate_shf[0] ______/ \_____________________________________________________________________/ \_______ +// _________ _________ +// gate_shf[1] ___________/ \_____________________________________________________________________/ \__ +// _________ _______ +// gate_shf[2] ________________/ \_____________________________________________________________________/ +// _________ __ +// gate_shf[3] _____________________/ \_____________________________________________________________________/ +// _________ +// gate_shf[4] __________________________/ \___________________________________________________________________ +// _________ +// gate_shf[5] _______________________________/ \______________________________________________________________ +// _________ +// gate_shf[6] ____________________________________/ \_________________________________________________________ +// _________ _________ +// launch ______/ \_____________________________________________________________________/ \_______ +// _________ _________ +// measure ___________/ \_____________________________________________________________________/ \__ +// ____ __ +// core_capture _____________________/ \__________________________________________________________________________/ +// ____ +// up_down_capture _______________________/ \________________________________________________________________________ +// ____ +// up--down _______________________________/ \___________________________________________________________________ +// __________________________________ ___________________________________________________________________ +// internal_value ______________15223_______________X__________________15224____________________________________________ +// ____ +// tog_state _______________________________/ \___________________________________________________________________ +// ____________________________________ ___________________________________________________________________ +// gate_state _________________State 1____________X________________State 2____________________________________________ +// ____ +// pgm_write ____________________________________/ \______________________________________________________________ +// ____ +// load_en _________________________________________/ \_________________________________________________________ +// ____ +// filter_load _________________________________________/ \_________________________________________________________ +// +//----------------------------------------------------------------------------------------------------------------------- + +always @(posedge clk or negedge reset_n) + if (~reset_n) gate_cnt[3:0] <= #FF_DELAY 4'b0000; + else gate_cnt[3:0] <= #FF_DELAY gate_cnt[3:0] + 1'b1; + +always @(posedge clk or negedge reset_n) + if (~reset_n) gate_shf[6:0] <= 7'b000_0000; + else gate_shf[6:0] <= {gate_shf[5:0],(gate_cnt[3:1] == 3'b000)}; + +assign launch = gate_shf[0]; +assign measure = gate_shf[1]; +assign core_capture = (gate_shf[3:2] == 2'b11); +assign up_down_capture = (gate_shf[5:4] == 2'b01); +assign tog_state = (gate_shf[5:4] == 2'b11); +assign pgm_write = (gate_shf[5:4] == 2'b10); +assign load_en = (gate_shf[6:5] == 2'b10); +assign filter_load = (gate_shf[6:5] == 2'b10); + +//core_up and core_dn synchronization +//cdclib_bitsync2 #(.CLK_FREQ_MHZ(1000)) ucoreup ( .rst_n(reset_n), .clk(clk), .data_in(core_up), .data_out(core_up_sync) ); +//cdclib_bitsync2 #(.CLK_FREQ_MHZ(1000)) ucoredn ( .rst_n(reset_n), .clk(clk), .data_in(core_dn), .data_out(core_dn_sync) ); +cdclib_bitsync2 #( + .DWIDTH(1), + .RESET_VAL(0), + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE(1), + .VID(1) +) ucoreup ( .rst_n(reset_n), .clk(clk), .data_in(core_up), .data_out(core_up_sync) ); + +cdclib_bitsync2 #( + .DWIDTH(1), + .RESET_VAL(0), + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE(1), + .VID(1) +) ucoredn ( .rst_n(reset_n), .clk(clk), .data_in(core_dn), .data_out(core_dn_sync) ); + + + +always @(posedge clk or negedge reset_n) + if (~reset_n) core_up_reg <= #FF_DELAY 1'b0; + else if (core_capture) core_up_reg <= #FF_DELAY core_up_sync; + else core_up_reg <= #FF_DELAY core_up_reg; + +always @(posedge clk or negedge reset_n) + if (~reset_n) core_dn_reg <= #FF_DELAY 1'b0; + else if (core_capture) core_dn_reg <= #FF_DELAY core_dn_sync; + else core_dn_reg <= #FF_DELAY core_dn_reg; + +assign up_core = t_up; +assign dn_core = t_down; +assign t_up_in = rb_core_updnen? core_up_reg: t_up; +assign t_down_in = rb_core_updnen? core_dn_reg: t_down; +assign new_t_up = ~t_down_in & t_up_in; +assign new_t_down = ~t_up_in & t_down_in; + + +//sync core_up and core_dn and combine with t_up and t_down using rb_core_updnen +//end will update + +//----------------------------------------------------------------------------------------------------------------------- +// 16 state machine used for a binary search +//----------------------------------------------------------------------------------------------------------------------- + +parameter UP_STATE_0 = 4'b0_000; +parameter UP_STATE_1 = 4'b0_100; +parameter UP_STATE_2 = 4'b0_101; +parameter UP_STATE_3 = 4'b0_110; +parameter UP_STATE_4 = 4'b0_111; +parameter DN_STATE_0 = 4'b1_000; +parameter DN_STATE_1 = 4'b1_100; +parameter DN_STATE_2 = 4'b1_101; +parameter DN_STATE_3 = 4'b1_110; +parameter DN_STATE_4 = 4'b1_111; + +reg [4:0] gate_counter; + +always @(posedge clk or negedge reset_n) + if (~reset_n) gate_counter[4:0] <= #FF_DELAY 5'h0; + else if (~tog_state) gate_counter[4:0] <= #FF_DELAY gate_counter[4:0]; + else casez ({gate_state[3],mem_down,mem_up}) + 3'b000 : gate_counter[4:0] <= #FF_DELAY gate_counter[4:0]; + 3'b001 : gate_counter[4:0] <= #FF_DELAY gate_counter[4:0] + 1'b1; + 3'b010 : gate_counter[4:0] <= #FF_DELAY 5'h00; + 3'b011 : gate_counter[4:0] <= #FF_DELAY gate_counter[4:0]; + 3'b100 : gate_counter[4:0] <= #FF_DELAY gate_counter[4:0]; + 3'b101 : gate_counter[4:0] <= #FF_DELAY 5'h00; + 3'b110 : gate_counter[4:0] <= #FF_DELAY gate_counter[4:0] + 1'b1; + 3'b111 : gate_counter[4:0] <= #FF_DELAY gate_counter[4:0]; + endcase + +always @(posedge clk or negedge reset_n) + if (~reset_n) gate_state <= #FF_DELAY UP_STATE_0; + else if (~tog_state) gate_state <= #FF_DELAY gate_state; + else if (rb_core_updnen) gate_state <= #FF_DELAY mem_up ? UP_STATE_1 : + mem_down ? DN_STATE_1 : + gate_state[3] ? DN_STATE_0 : + UP_STATE_0 ; + else if ( (internal_value[12:5] == 8'h00) & gate_state[3] ) gate_state <= #FF_DELAY UP_STATE_0; + else if ( (internal_value[12:5] == 8'hFF) & ~gate_state[3] ) gate_state <= #FF_DELAY DN_STATE_0; + else if (~prelock) case (gate_state) + UP_STATE_0 : gate_state <= #FF_DELAY (mem_up & (gate_counter[4:0] == 5'h1F)) ? UP_STATE_1 : + (mem_up & ~mem_down) ? UP_STATE_0 : + DN_STATE_0 ; + UP_STATE_1 : gate_state <= #FF_DELAY (mem_up & (gate_counter[3:0] == 4'hF)) ? UP_STATE_2 : + (mem_up & ~mem_down) ? UP_STATE_1 : + UP_STATE_0 ; + UP_STATE_2 : gate_state <= #FF_DELAY (mem_up & (gate_counter[2:0] == 3'h7)) ? UP_STATE_3 : + (mem_up & ~mem_down) ? UP_STATE_2 : + UP_STATE_1 ; + UP_STATE_3 : gate_state <= #FF_DELAY (mem_up & (gate_counter[1:0] == 2'h3)) ? UP_STATE_4 : + (mem_up & ~mem_down) ? UP_STATE_3 : + UP_STATE_2 ; + UP_STATE_4 : gate_state <= #FF_DELAY (mem_up & ~mem_down) ? UP_STATE_4 : + UP_STATE_3 ; + DN_STATE_0 : gate_state <= #FF_DELAY (mem_down & (gate_counter[4:0] == 5'h1F)) ? DN_STATE_1 : + (mem_down & ~mem_up) ? DN_STATE_0 : + UP_STATE_0 ; + DN_STATE_1 : gate_state <= #FF_DELAY (mem_down & (gate_counter[3:0] == 4'hF)) ? DN_STATE_2 : + (mem_down & ~mem_up) ? DN_STATE_1 : + DN_STATE_0 ; + DN_STATE_2 : gate_state <= #FF_DELAY (mem_down & (gate_counter[2:0] == 3'h7)) ? DN_STATE_3 : + (mem_down & ~mem_up) ? DN_STATE_2 : + DN_STATE_1 ; + DN_STATE_3 : gate_state <= #FF_DELAY (mem_down & (gate_counter[1:0] == 2'h3)) ? DN_STATE_4 : + (mem_down & ~mem_up) ? DN_STATE_3 : + DN_STATE_2 ; + DN_STATE_4 : gate_state <= #FF_DELAY (mem_down & ~mem_up) ? DN_STATE_4 : + DN_STATE_3 ; + default : gate_state <= #FF_DELAY UP_STATE_0; + endcase + else case (gate_state) + UP_STATE_0 : gate_state <= #FF_DELAY (mem_up & (gate_counter[4:0] == 5'h1F)) ? UP_STATE_0 : + (mem_up & ~mem_down) ? UP_STATE_0 : + DN_STATE_0 ; + UP_STATE_1 : gate_state <= #FF_DELAY (mem_up & (gate_counter[3:0] == 4'hF)) ? UP_STATE_0 : + (mem_up & ~mem_down) ? UP_STATE_0 : + UP_STATE_0 ; + UP_STATE_2 : gate_state <= #FF_DELAY (mem_up & (gate_counter[2:0] == 3'h7)) ? UP_STATE_3 : + (mem_up & ~mem_down) ? UP_STATE_2 : + UP_STATE_1 ; + UP_STATE_3 : gate_state <= #FF_DELAY (mem_up & (gate_counter[1:0] == 2'h3)) ? UP_STATE_4 : + (mem_up & ~mem_down) ? UP_STATE_3 : + UP_STATE_2 ; + UP_STATE_4 : gate_state <= #FF_DELAY (mem_up & ~mem_down) ? UP_STATE_4 : + UP_STATE_3 ; + DN_STATE_0 : gate_state <= #FF_DELAY (mem_down & (gate_counter[4:0] == 5'h1F)) ? DN_STATE_0 : + (mem_down & ~mem_up) ? DN_STATE_0 : + UP_STATE_0 ; + DN_STATE_1 : gate_state <= #FF_DELAY (mem_down & (gate_counter[3:0] == 4'hF)) ? DN_STATE_0 : + (mem_down & ~mem_up) ? DN_STATE_0 : + DN_STATE_0 ; + DN_STATE_2 : gate_state <= #FF_DELAY (mem_down & (gate_counter[2:0] == 3'h7)) ? DN_STATE_3 : + (mem_down & ~mem_up) ? DN_STATE_2 : + DN_STATE_1 ; + DN_STATE_3 : gate_state <= #FF_DELAY (mem_down & (gate_counter[1:0] == 2'h3)) ? DN_STATE_4 : + (mem_down & ~mem_up) ? DN_STATE_3 : + DN_STATE_2 ; + DN_STATE_4 : gate_state <= #FF_DELAY (mem_down & ~mem_up) ? DN_STATE_4 : + DN_STATE_3 ; + default : gate_state <= #FF_DELAY UP_STATE_0; + endcase + +//----------------------------------------------------------------------------------------------------------------------- +// coarse_delay : Delay the clk by (128 * COARSE_DELAY) + INTRINSIC_DELAY +// stg_b : Fine Delay - Multiply, Round, Truncate, Out Pipe (Integer overflow will never happen, clip not needed) +//----------------------------------------------------------------------------------------------------------------------- + +assign state_adder[4] = gate_state[3] & gate_state[2] ; +assign state_adder[3] = (gate_state[3:0] == UP_STATE_4) | (gate_state[3:0] == DN_STATE_1) | (gate_state[3:0] == DN_STATE_2) | (gate_state[3:0] == DN_STATE_3) | (gate_state[3:0] == DN_STATE_4); +assign state_adder[2] = (gate_state[3:0] == UP_STATE_3) | (gate_state[3:0] == DN_STATE_1) | (gate_state[3:0] == DN_STATE_2) | (gate_state[3:0] == DN_STATE_3); +assign state_adder[1] = (gate_state[3:0] == UP_STATE_2) | (gate_state[3:0] == DN_STATE_1) | (gate_state[3:0] == DN_STATE_2); +assign state_adder[0] = (gate_state[3:0] == UP_STATE_1) | (gate_state[3:0] == DN_STATE_1); + +//assign search_value[13:0] = internal_value[12:0] + {{6{state_adder[4]}},state_adder[3:0],4'b0000} ; // Check for max,min - borrow or carry out ????? +assign search_value[13:0] = prelock ? {1'b0,internal_value[12:0]} : (internal_value[12:0] + {{6{state_adder[4]}},state_adder[3:0],4'b0000}); + +assign int_pvt_value[9:0] = search_value[13] ? internal_value[12:3] : search_value[12:3]; + +always @(posedge clk or negedge reset_n) + if (~reset_n) internal_pvt_binary[9:0] <= #FF_DELAY rb_dly_pst[9:0]; + else if (rb_ctlsel) internal_pvt_binary[9:0] <= #FF_DELAY rb_ctl_static[9:0]; + else if (pgm_write) internal_pvt_binary[9:0] <= #FF_DELAY int_pvt_value[9:0]; + else internal_pvt_binary[9:0] <= #FF_DELAY internal_pvt_binary[9:0]; + +assign f_gray[6:0] = { internal_pvt_binary[9], + internal_pvt_binary[9] ^ internal_pvt_binary[8], + internal_pvt_binary[8] ^ internal_pvt_binary[7], + internal_pvt_binary[7] ^ internal_pvt_binary[6], + internal_pvt_binary[6] ^ internal_pvt_binary[5], + internal_pvt_binary[5] ^ internal_pvt_binary[4], + internal_pvt_binary[4] ^ internal_pvt_binary[3] }; + +assign i_gray[2:0] = { internal_pvt_binary[2], + internal_pvt_binary[2] ^ internal_pvt_binary[1], + internal_pvt_binary[1] ^ internal_pvt_binary[0] }; + +always @(posedge clk or negedge reset_n) + if (~reset_n) search_overflow <= #FF_DELAY 1'b0; + else if (pgm_write) search_overflow <= #FF_DELAY search_value[13]; + else search_overflow <= #FF_DELAY search_overflow; + +always @(posedge clk or negedge reset_n) + if (~reset_n) {up[4:0],down[4:0]} <= #FF_DELAY 10'b00000_00000; + else if (~up_down_capture) {up[4:0],down[4:0]} <= #FF_DELAY 10'b00000_00000; + else if (search_overflow) {up[4:0],down[4:0]} <= #FF_DELAY 10'b10000_00000; + else if (rb_core_updnen) {up[4:0],down[4:0]} <= #FF_DELAY {3'b000,new_t_up,4'b0000,new_t_down,1'b0}; + else if (~prelock) case (gate_state) + UP_STATE_0 : {up[4:0],down[4:0]} <= #FF_DELAY {4'b0000,new_t_up,4'b0000,new_t_down}; + UP_STATE_1 : {up[4:0],down[4:0]} <= #FF_DELAY {3'b000,new_t_up,6'b00_0000}; + UP_STATE_2 : {up[4:0],down[4:0]} <= #FF_DELAY {2'b00,new_t_up,7'b000_0000}; + UP_STATE_3 : {up[4:0],down[4:0]} <= #FF_DELAY {1'b0,new_t_up,8'b0000_0000}; + UP_STATE_4 : {up[4:0],down[4:0]} <= #FF_DELAY {new_t_up,9'b00000_0000}; + DN_STATE_0 : {up[4:0],down[4:0]} <= #FF_DELAY {4'b0000,new_t_up,4'b0000,new_t_down}; + DN_STATE_1 : {up[4:0],down[4:0]} <= #FF_DELAY {8'b0000_0000,new_t_down,1'b0}; + DN_STATE_2 : {up[4:0],down[4:0]} <= #FF_DELAY {7'b000_0000,new_t_down,2'b00}; + DN_STATE_3 : {up[4:0],down[4:0]} <= #FF_DELAY {6'b00_0000,new_t_down,3'b000}; + DN_STATE_4 : {up[4:0],down[4:0]} <= #FF_DELAY {5'b0_0000,new_t_down,4'b0000}; + default : {up[4:0],down[4:0]} <= #FF_DELAY 10'b00000_00000; + endcase + else case (gate_state) + UP_STATE_0 : {up[4:0],down[4:0]} <= #FF_DELAY {4'b0000,new_t_up,4'b0000,new_t_down}; + UP_STATE_1 : {up[4:0],down[4:0]} <= #FF_DELAY {4'b0000,new_t_up,4'b0000,new_t_down}; + UP_STATE_2 : {up[4:0],down[4:0]} <= #FF_DELAY {4'b0000,new_t_up,4'b0000,new_t_down}; + UP_STATE_3 : {up[4:0],down[4:0]} <= #FF_DELAY {4'b0000,new_t_up,4'b0000,new_t_down}; + UP_STATE_4 : {up[4:0],down[4:0]} <= #FF_DELAY {4'b0000,new_t_up,4'b0000,new_t_down}; + DN_STATE_0 : {up[4:0],down[4:0]} <= #FF_DELAY {4'b0000,new_t_up,4'b0000,new_t_down}; + DN_STATE_1 : {up[4:0],down[4:0]} <= #FF_DELAY {4'b0000,new_t_up,4'b0000,new_t_down}; + DN_STATE_2 : {up[4:0],down[4:0]} <= #FF_DELAY {4'b0000,new_t_up,4'b0000,new_t_down}; + DN_STATE_3 : {up[4:0],down[4:0]} <= #FF_DELAY {4'b0000,new_t_up,4'b0000,new_t_down}; + DN_STATE_4 : {up[4:0],down[4:0]} <= #FF_DELAY {4'b0000,new_t_up,4'b0000,new_t_down}; + default : {up[4:0],down[4:0]} <= #FF_DELAY 10'b00000_00000; + endcase + +assign any_up = |up[4:0]; +assign any_down = |down[4:0]; +assign large_up = |up[4:1]; +assign large_down = |down[4:1]; + +always @(posedge clk or negedge reset_n) + if (~reset_n) {mem_up,mem_down} <= #FF_DELAY 2'b00; + else if (search_overflow) {mem_up,mem_down} <= #FF_DELAY 2'b00; + else if (up_down_capture) {mem_up,mem_down} <= #FF_DELAY {new_t_up,new_t_down}; + else {mem_up,mem_down} <= #FF_DELAY {mem_up,mem_down}; + +//----------------------------------------------------------------------------------------------------------------------- +// UP/DOWN Acceleration +//----------------------------------------------------------------------------------------------------------------------- + +always @(posedge clk or negedge reset_n) + if (~reset_n) accel_up[5:0] <= #FF_DELAY 6'h00; + else if (down[0]) accel_up[5:0] <= #FF_DELAY 6'h00; + else if (rb_core_updnen) accel_up[5:0] <= #FF_DELAY 6'h00; + else if (up[0] & (accel_up[5:3] != 3'b111)) accel_up[5:0] <= #FF_DELAY accel_up[5:0] + 1'b1; + else accel_up[5:0] <= #FF_DELAY accel_up[5:0]; + +always @(posedge clk or negedge reset_n) + if (~reset_n) accel_down[5:0] <= #FF_DELAY 6'h00; + else if (up[0]) accel_down[5:0] <= #FF_DELAY 6'h00; + else if (rb_core_updnen) accel_down[5:0] <= #FF_DELAY 6'h00; + else if (down[0] & (accel_down[5:3] != 3'b111)) accel_down[5:0] <= #FF_DELAY accel_down[5:0] + 1'b1; + else accel_down[5:0] <= #FF_DELAY accel_down[5:0]; + +//----------------------------------------------------------------------------------------------------------------------- +// Lock detect +//----------------------------------------------------------------------------------------------------------------------- + +wire [12:0] difference_value; + +assign difference_value[12:0] = internal_value[12:0] - pvt_value[12:0]; + +assign dll_lock_det = filter_load & (difference_value[12:2] == 11'h000); + +always @(posedge clk or negedge reset_n) + if (~reset_n) lock_cnt[3:0] <= #FF_DELAY 4'h0; + else if (gate_state[2]) lock_cnt[3:0] <= #FF_DELAY 4'h0; + else if (search_overflow) lock_cnt[3:0] <= #FF_DELAY 4'h0; + else if (lock_cnt[3]) lock_cnt[3:0] <= #FF_DELAY 4'h8; + else lock_cnt[3:0] <= #FF_DELAY lock_cnt[3:0] + dll_lock_det; + +assign dll_lock = lock_cnt[3]; + +//----------------------------------------------------------------------------------------------------------------------- +// internal_value : UP/DOWN Counter +//----------------------------------------------------------------------------------------------------------------------- + +/* +assign tcalc_up[15:0] = {internal_value[12:0],i_filter[1:0]} + {up[4:1],5'b00000,up[0]} + ({6{up[0]}} & accel_up[5:0]); +assign tcalc_down[15:0] = {internal_value[12:0],i_filter[1:0]} - {down[4:1],5'b00000,down[0]} - ({6{down[0]}} & accel_down[5:0]); +*/ + +/* +assign tcalc_up[15:0] = {internal_value[12:0],i_filter[1:0]} + {up[4:1],5'b00000,up[0]}; +assign tcalc_down[15:0] = {internal_value[12:0],i_filter[1:0]} - {down[4:1],5'b00000,down[0]}; +*/ + +//assign int_pvt_value[9:0] = search_value[13] ? internal_value[12:3] : search_value[12:3]; + +assign tcalc_up[15:0] = prelock ? ({internal_value[12:0],i_filter[1:0]} + up[0]) : ({internal_value[12:0],i_filter[1:0]} + {up[4:1],5'b00000,up[0]} + ({6{up[0]}} & accel_up[5:0])); +assign tcalc_down[15:0] = prelock ? ({internal_value[12:0],i_filter[1:0]} - down[0]): ({internal_value[12:0],i_filter[1:0]} - {down[4:1],5'b00000,down[0]} - ({6{down[0]}} & accel_down[5:0])); + +always @(posedge clk or negedge reset_n) + if (~reset_n) {internal_value[12:0],i_filter[1:0]} <= #FF_DELAY {rb_dly_pst,5'h00}; + else if (any_up) {internal_value[12:0],i_filter[1:0]} <= #FF_DELAY tcalc_up[15] ? 15'h7FFF : tcalc_up[14:0]; + else if (any_down) {internal_value[12:0],i_filter[1:0]} <= #FF_DELAY tcalc_down[15] ? 15'h0000 : tcalc_down[14:0]; + else {internal_value[12:0],i_filter[1:0]} <= #FF_DELAY {internal_value[12:0],i_filter[1:0]}; + +//----------------------------------------------------------------------------------------------------------------------- +// pvt_value : Output filter + hysteresis +//----------------------------------------------------------------------------------------------------------------------- + +always @(posedge clk or negedge reset_n) + if (~reset_n) {pvt_value[12:0],o_filter[7:0]} <= #FF_DELAY {rb_dly_pst,11'h000}; + else if (rb_ctlsel) {pvt_value[12:0],o_filter[7:0]} <= #FF_DELAY {rb_ctl_static[9:0],11'h000}; + else if (large_up) {pvt_value[12:0],o_filter[7:0]} <= #FF_DELAY tcalc_up[15] ? 21'h1FFF80 : {tcalc_up[14:2],8'b1000_0000}; + else if (large_down) {pvt_value[12:0],o_filter[7:0]} <= #FF_DELAY tcalc_down[15] ? 21'h000000 : {tcalc_down[14:2],8'b1000_0000}; + else if (~filter_load) {pvt_value[12:0],o_filter[7:0]} <= #FF_DELAY {pvt_value[12:0],o_filter[7:0]}; + else if ((internal_value[12:0] == pvt_value[12:0]) & ~o_filter[7]) {pvt_value[12:0],o_filter[7:0]} <= #FF_DELAY {pvt_value[12:0],o_filter[7:0]} + {~dll_lock,3'h4}; + else if ((internal_value[12:0] == pvt_value[12:0]) & o_filter[7]) {pvt_value[12:0],o_filter[7:0]} <= #FF_DELAY {pvt_value[12:0],o_filter[7:0]} - {~dll_lock,3'h4}; + else if (dll_lock) {pvt_value[12:0],o_filter[7:0]} <= #FF_DELAY {pvt_value[12:0],o_filter[7:0]} + internal_value[12:0] - pvt_value[12:0]; + else {pvt_value[12:0],o_filter[7:0]} <= #FF_DELAY {pvt_value[12:0],o_filter[7:0]} + {internal_value[12:0],6'h0} - {pvt_value[12:0],6'h0}; + +// self-timed based lock assertion +aibndpnr_self_lock_assertion xaibndpnr_self_lock_assertion ( +.clk ( clk ), +.reset_n ( reset_n ), +.rb_clkdiv ( rb_clkdiv[2:0]), +.rb_selflock ( rb_selflock ), +.scan_mode_n ( scan_mode_n ), +.fsm_lock ( dll_lock ), +.prelock ( prelock ), +.lock ( lock ) +); + +//send out dll setting + +assign pvt_ref_binary[9:0] = pvt_value[12:3]; + +assign pvt_ref_gray[9:0] = { pvt_ref_binary[9], + pvt_ref_binary[9] ^ pvt_ref_binary[8], + pvt_ref_binary[8] ^ pvt_ref_binary[7], + pvt_ref_binary[7] ^ pvt_ref_binary[6], + pvt_ref_binary[6] ^ pvt_ref_binary[5], + pvt_ref_binary[5] ^ pvt_ref_binary[4], + pvt_ref_binary[4] ^ pvt_ref_binary[3], + pvt_ref_binary[2], + pvt_ref_binary[2] ^ pvt_ref_binary[1], + pvt_ref_binary[1] ^ pvt_ref_binary[0] }; + +wire [9:0] pvt_ref_gray_pst; +assign pvt_ref_gray_pst[9:0] = {rb_dly_pst[9], + rb_dly_pst[9] ^ rb_dly_pst[8], + rb_dly_pst[8] ^ rb_dly_pst[7], + rb_dly_pst[7] ^ rb_dly_pst[6], + rb_dly_pst[6] ^ rb_dly_pst[5], + rb_dly_pst[5] ^ rb_dly_pst[4], + rb_dly_pst[4] ^ rb_dly_pst[3], + rb_dly_pst[2], + rb_dly_pst[2] ^ rb_dly_pst[1], + rb_dly_pst[1] ^ rb_dly_pst[0] }; + + +always @(posedge clk or negedge reset_n) + if (~reset_n) pvt_ref_gry[9:0] <= pvt_ref_gray_pst[9:0]; + else pvt_ref_gry[9:0] <= pvt_ref_gray[9:0]; + +//half-cycle code generation (bypass or divide by 2) + +aibndpnr_half_cycle_code_gen xaibndpnr_half_cycle_code_gen ( +.clk ( clk ), +.reset_n ( reset_n ), +.pvt_ref_binary ( internal_pvt_binary[9:0]), +.rb_half_code ( rb_half_code ), +.pvt_ref_half_binary ( pvt_ref_half_binary[9:0]) +); + +assign pvt_ref_half_gray[9:0] = { pvt_ref_half_binary[9], + pvt_ref_half_binary[9] ^ pvt_ref_half_binary[8], + pvt_ref_half_binary[8] ^ pvt_ref_half_binary[7], + pvt_ref_half_binary[7] ^ pvt_ref_half_binary[6], + pvt_ref_half_binary[6] ^ pvt_ref_half_binary[5], + pvt_ref_half_binary[5] ^ pvt_ref_half_binary[4], + pvt_ref_half_binary[4] ^ pvt_ref_half_binary[3], + pvt_ref_half_binary[2], + pvt_ref_half_binary[2] ^ pvt_ref_half_binary[1], + pvt_ref_half_binary[1] ^ pvt_ref_half_binary[0] }; + +always @(posedge clk or negedge reset_n) + if (~reset_n) pvt_ref_half_gry[9:0] <= 10'b00_0000_0000; + else pvt_ref_half_gry[9:0] <= pvt_ref_half_gray[9:0]; + +endmodule // aibndpnr_dll_core + diff --git a/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_ctrl.v b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_ctrl.v new file mode 100644 index 0000000..1f9b734 --- /dev/null +++ b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_ctrl.v @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #3 $ +// Date: $DateTime: 2015/04/02 02:14:27 $ +//------------------------------------------------------------------------ +// Description: dll reset control +// +//------------------------------------------------------------------------ + +module aibndpnr_dll_ctrl ( + input wire clk, //reference clock from pll + input wire reinit, //initialization enable + input wire entest, //test enable + input wire ndllrst_in, //reset from core + input wire rb_dll_en, //dll enable + input wire rb_dll_rst_en, //dll reset enable + input wire atpg_en_n, //atpg + input wire test_clr_n, //test clear + output wire dll_reset_n //output for dll reset +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +wire eni; +wire dll_rst; + +//////////////////////////////////////////////////////////////////// +// // +// reset and preset // +// // +//////////////////////////////////////////////////////////////////// + +assign dll_rst = (rb_dll_rst_en) ? ~ndllrst_in : 1'b0; //core reset at "1" if core_reset enabled +assign eni = ~entest & rb_dll_en & (~reinit) & (~dll_rst); //dll enable and non-test +cdclib_rst_n_sync unrst ( .rst_n(eni), .rst_n_bypass(test_clr_n), .clk(clk), .scan_mode_n(atpg_en_n), .rst_n_sync(dll_reset_n) ); + +endmodule // aibndpnr_dll_ctrl + diff --git a/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_pnr.v b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_pnr.v new file mode 100644 index 0000000..5f62d88 --- /dev/null +++ b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_pnr.v @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #6 $ +// Date: $DateTime: 2015/08/05 02:22:16 $ +//------------------------------------------------------------------------ +// Description: AIB DLL PnR +//1. Copied over from io_dll_pnr and modified : +// a. added input port csr_reg[51:0] --> AIB will receive csr/dprio from PCS adapter. +// i. csrclk, csren, early_csren, csrdatain, csr_scan_shift_n, csrdataout, cas_csrdin, cas_csrdout ports removed +// ii. instanciated csr registers removed +// iii. csr related parameters commented out +// b. added in input ports rb_clkdiv[1:0],rb_selflock,rb_half_code,dll_lock +// c. added output port pvt_ref_half_gry +// d. removed ports : +/* scan_shift_n, + dft_pipeline_global_en_n, + bhniotri, //core control signal + early_bhniotri, //hps control signal + enrnsl, //core control signal + early_enrnsl, //hps control signal + frzreg, //core control signal + early_frzreg, //hps control signal + nfrzdrv, //core control signal + early_nfrzdrv, //hps control signal + niotri, //core control signal + early_niotri, //hps control signal + plniotri, //core control signal + early_plniotri, //hps control signal + usermode, //core control signal + early_usermode, //hps control signal + wkpullup, //core control signal + local_bhniotri, //local control signal + local_enrnsl, //local control signal + local_frzreg, //local control signal + local_nfrzdrv, //local control signal + local_niotri, //local control signal + local_plniotri, //local control signal + local_usermode, //local control signal + local_wkpullup, //local control signal + hps_to_core_ctrl_en, //rbpa_hps_ctrl_en sent to core + test_si_dll, //negative scan chain in + test_so_dll, //positive scan chain output + test_dqs_o1, // DFT test o from io_dqs_lgc_pnr scan chain1 + test_dqs_o2, // DFT test o from io_dqs_lgc_pnr scan chain2 +*/ +// e. added scan ports +/* pipeline_global_en, + scan_mode_n, + scan_shift, + scan_rst_n, + scan_clk_in, + scan_in, + scan_out +*/ +// f. replaced inherited test* ports with scan* ports +/* (i) test_clk ==> scan_clk_in + (ii) atpg_en_n ==> scan_mode_n + (iii) test_clr_n ==> scan_rst_n +*/ +// g. added synchronizers for t_up and t_down +// h. bring out gate_shf +// i. updated ctrl reset (follow io_dll_ctrl) after adding synchronizer +// j. increase bus width of rb_clkdiv from 2 to 3-bit +// k. replaced aibndpnr_sync with cdclib_bitsync3 +// l. changed scan_shift to scan_shift_n +// m. connected scan_mode_n to dll_core +// n. use cascaded-2FF SYNC as replacement for 3-stage SYNC +// o. updated up & down cdclib sync parameters +//------------------------------------------------------------------------ +// Uncertainity : +//1. Need to remove all the hps and dqs related ports? +//------------------------------------------------------------------------ + +module aibndpnr_dll_pnr +#( +//----------------------------------------------------------------------------------------------------------------------- +// Local calculated parameters +//----------------------------------------------------------------------------------------------------------------------- +parameter FF_DELAY = 200 +) +( + input wire [2:0] core_dll, // input from core to dll + input wire clk_pll, // dll clock from pll + input [51:0] csr_reg, // combinations of csr and dprio bits from pcs adapter *added for aib + input wire reinit, // initialization enable + input wire entest, // test enable + input wire t_up, // output of phase detector + input wire t_down, // output of phase detector + output wire launch, // Decode from gate_shf, Used as the input to the delay line + output wire measure, // Decode from gate_shf, Used as the clock for the phase detector + output wire [6:0] f_gray, // gray code for nand delay chain + output wire [2:0] i_gray, // gray code for phase interpolator + output wire [12:0] dll_core, // output from dll to core + output wire [9:0] pvt_ref_gry, // delay setting from dll + output wire [9:0] pvt_ref_half_gry, // divided-by-4 delay setting from dll + output wire dll_phdet_reset_n, // + output wire dll_lock, + output wire [6:0] gate_shf, // for synchronizing purpose + input wire test_clk_pll_en_n, // ATPG : + input wire [2:0] rb_clkdiv, + input wire rb_selflock, + input wire rb_half_code, + input wire pipeline_global_en, + input wire scan_mode_n, + input wire scan_shift_n, + input wire scan_rst_n, + input wire scan_clk_in, + input wire scan_in, + output wire scan_out +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +//---------------------------------------------------------------------------------------------------------------------------------------------------------------- +//--- wire & reg ------------------------------------------------------------------------------------------------------------------------------------------------- +//---------------------------------------------------------------------------------------------------------------------------------------------------------------- + + wire clk_pll_gated; + wire clk_pll_gated_tmux; + wire clk_pll_tmux; + wire reset_n_tmux; +// reg clk_pll_obs; +// reg reset_n_obs; + + wire rb_dll_rst_en; + wire rb_dll_en; + wire rb_ndllrst_prgmnvrt; + wire rb_core_up_prgmnvrt; + wire rb_core_dn_prgmnvrt; + wire rb_core_updnen; + wire rb_spare; + wire [9:0] rb_dly_pst; + wire rb_ctlsel; + wire [9:0] rb_ctl_static; + wire [19:0] rb_dftmuxsel; + wire [3:0] rb_new_dll; + wire core_up_in; + wire core_dn_in; + wire [9:0] pvt_ref_binary; + wire [9:0] internal_pvt_binary; // binary pvt value for dll internal delay chain + wire search_overflow; + wire [3:0] gate_state; + reg [9:0] dll_dftout; + wire up_core; + wire dn_core; + wire core_up; + wire core_dn; + wire ndllrst; + wire ndllrst_in; + wire dll_reset_n; + wire test_clk_en; + wire test_clk_gated; + wire scan_shift; +//======================================================================================================================================================================== +// test_clk muxes +//======================================================================================================================================================================== + +assign test_clk_en = ~test_clk_pll_en_n; +assign scan_shift = ~scan_shift_n; + +aibndpnr_dll_atech_clkgate_cgc00 gated_clk_pll_inst +( + .clk (clk_pll), + .en (1'b1), + .clkout (clk_pll_gated) +); + +aibndpnr_dll_atech_clkgate_cgc01 gated_test_clk_inst +( + .clk (scan_clk_in), + .en (test_clk_en), + .te (scan_shift), + .clkout (test_clk_gated) +); + +aibndpnr_dll_atech_clkmux muxed_pll_gated_inst +( + .clk1 (clk_pll_gated), + .clk2 (test_clk_gated), + .s (scan_mode_n), + .clkout (clk_pll_gated_tmux) +); + +aibndpnr_dll_atech_clkmux muxed_pll_inst +( + .clk1 (clk_pll), + .clk2 (test_clk_gated), + .s (scan_mode_n), + .clkout (clk_pll_tmux) +); + +assign dll_phdet_reset_n = scan_mode_n ? reset_n_tmux : 1'b0 ; + +//always @(posedge scan_clk_in) clk_pll_obs <= #FF_DELAY clk_pll; +//always @(posedge scan_clk_in) reset_n_obs <= #FF_DELAY reset_n_tmux; + +//======================================================================================================================================================================== +//end csr for phase alignment +//======================================================================================================================================================================== + + assign rb_dll_rst_en = csr_reg[0]; //core reset enable + assign rb_dll_en = csr_reg[1]; //dll enable + assign rb_ndllrst_prgmnvrt = csr_reg[2]; //core reset signal programmable inv + assign rb_core_up_prgmnvrt = csr_reg[3]; //core_up signal programmable inv + assign rb_core_dn_prgmnvrt = csr_reg[4]; //core_dn signal programmable inv + assign rb_core_updnen = csr_reg[5]; //core updown control enable + assign rb_spare = csr_reg[6]; //Not used + assign rb_dly_pst[9:0] = csr_reg[16:7]; //delay preset setting + assign rb_ctlsel = csr_reg[17]; //dll setting selection + assign rb_ctl_static[9:0] = csr_reg[27:18]; //dll static setting + assign rb_dftmuxsel[19:0] = csr_reg[47:28]; //dft mux selection + assign rb_new_dll[3:0] = csr_reg[51:48]; // Not used + + assign core_up = core_dll[0]; + assign core_dn = core_dll[1]; + assign ndllrst = core_dll[2]; + +always @(*) + case (rb_dftmuxsel[19:18]) + 2'b00 : dll_dftout[9] = pvt_ref_half_gry[9]; + 2'b01 : dll_dftout[9] = pvt_ref_binary[9]; + 2'b10 : dll_dftout[9] = internal_pvt_binary[9]; + 2'b11 : dll_dftout[9] = 1'b0; + default : dll_dftout[9] = 1'b0; + endcase + +always @(*) + case (rb_dftmuxsel[17:16]) + 2'b00 : dll_dftout[8] = pvt_ref_half_gry[8]; + 2'b01 : dll_dftout[8] = pvt_ref_binary[8]; + 2'b10 : dll_dftout[8] = internal_pvt_binary[8]; + 2'b11 : dll_dftout[8] = 1'b0; + default : dll_dftout[8] = 1'b0; + endcase + +always @(*) + case (rb_dftmuxsel[15:14]) + 2'b00 : dll_dftout[7] = pvt_ref_half_gry[7]; + 2'b01 : dll_dftout[7] = pvt_ref_binary[7]; + 2'b10 : dll_dftout[7] = internal_pvt_binary[7]; + 2'b11 : dll_dftout[7] = 1'b0; + default : dll_dftout[7] = 1'b0; + endcase + +always @(*) + case (rb_dftmuxsel[13:12]) + 2'b00 : dll_dftout[6] = pvt_ref_half_gry[6]; + 2'b01 : dll_dftout[6] = pvt_ref_binary[6]; + 2'b10 : dll_dftout[6] = internal_pvt_binary[6]; + 2'b11 : dll_dftout[6] = 1'b0; + default : dll_dftout[6] = 1'b0; + endcase + +always @(*) + case (rb_dftmuxsel[11:10]) + 2'b00 : dll_dftout[5] = pvt_ref_half_gry[5]; + 2'b01 : dll_dftout[5] = pvt_ref_binary[5]; + 2'b10 : dll_dftout[5] = internal_pvt_binary[5]; + 2'b11 : dll_dftout[5] = gate_state[3]; + default : dll_dftout[5] = 1'b0; + endcase + +always @(*) + case (rb_dftmuxsel[9:8]) + 2'b00 : dll_dftout[4] = pvt_ref_half_gry[4]; + 2'b01 : dll_dftout[4] = pvt_ref_binary[4]; + 2'b10 : dll_dftout[4] = internal_pvt_binary[4]; + 2'b11 : dll_dftout[4] = gate_state[2]; + default : dll_dftout[4] = 1'b0; + endcase + +always @(*) + case (rb_dftmuxsel[7:6]) + 2'b00 : dll_dftout[3] = pvt_ref_half_gry[3]; + 2'b01 : dll_dftout[3] = pvt_ref_binary[3]; + 2'b10 : dll_dftout[3] = internal_pvt_binary[3]; + 2'b11 : dll_dftout[3] = gate_state[1]; + default : dll_dftout[3] = 1'b0; + endcase + +always @(*) + case (rb_dftmuxsel[5:4]) + 2'b00 : dll_dftout[2] = pvt_ref_half_gry[2]; + 2'b01 : dll_dftout[2] = pvt_ref_binary[2]; + 2'b10 : dll_dftout[2] = internal_pvt_binary[2]; + 2'b11 : dll_dftout[2] = gate_state[0]; + default : dll_dftout[2] = 1'b0; + endcase + +always @(*) + case (rb_dftmuxsel[3:2]) + 2'b00 : dll_dftout[1] = pvt_ref_half_gry[1]; + 2'b01 : dll_dftout[1] = pvt_ref_binary[1]; + 2'b10 : dll_dftout[1] = internal_pvt_binary[1]; + 2'b11 : dll_dftout[1] = search_overflow; + default : dll_dftout[1] = 1'b0; + endcase + +always @(*) + case (rb_dftmuxsel[1:0]) + 2'b00 : dll_dftout[0] = pvt_ref_half_gry[0]; + 2'b01 : dll_dftout[0] = pvt_ref_binary[0]; + 2'b10 : dll_dftout[0] = internal_pvt_binary[0]; + 2'b11 : dll_dftout[0] = reset_n_tmux; + default : dll_dftout[0] = 1'b0; + endcase + + assign dll_core[12] = dn_core; + assign dll_core[11] = up_core; + assign dll_core[10] = scan_mode_n ? dll_lock : clk_pll_gated; //dft request + assign dll_core[9:0] = dll_dftout; + + assign ndllrst_in = (rb_ndllrst_prgmnvrt) ? ~ndllrst : ndllrst; //core reset + assign core_up_in = (rb_core_up_prgmnvrt) ? ~core_up : core_up; //core up signal + assign core_dn_in = (rb_core_dn_prgmnvrt) ? ~core_dn : core_dn; //core dn signal + +aibndpnr_dll_ctrl xdll_ctrl ( + .clk(clk_pll_tmux), + .reinit(reinit), + .entest(entest), + .ndllrst_in(ndllrst_in), + .rb_dll_en(rb_dll_en), + .rb_dll_rst_en(rb_dll_rst_en), + .atpg_en_n(scan_mode_n), + .test_clr_n(scan_rst_n), + .dll_reset_n(reset_n_tmux) +); + +//t_up and t_down synchronization + +wire t_up_sync,t_down_sync; + +//cdclib_bitsync4 #(.CLK_FREQ_MHZ(1000)) xsync_tup ( .rst_n(reset_n_tmux), .clk(clk_pll_gated_tmux), .data_in(t_up), .data_out(t_up_sync) ); +//cdclib_bitsync4 #(.CLK_FREQ_MHZ(1000)) xsync_tdown ( .rst_n(reset_n_tmux), .clk(clk_pll_gated_tmux), .data_in(t_down), .data_out(t_down_sync) ); + +cdclib_bitsync4 #( + .DWIDTH(1), + .RESET_VAL(0), + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE(1), + .VID(1) +) xsync_tup ( .rst_n(reset_n_tmux), .clk(clk_pll_gated_tmux), .data_in(t_up), .data_out(t_up_sync) ); + +cdclib_bitsync4 #( + .DWIDTH(1), + .RESET_VAL(0), + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE(1), + .VID(1) +) xsync_tdown ( .rst_n(reset_n_tmux), .clk(clk_pll_gated_tmux), .data_in(t_down), .data_out(t_down_sync) ); + +aibndpnr_dll_core xdll_core ( +.clk ( clk_pll_gated_tmux ), +.reset_n ( reset_n_tmux ), +.rb_ctlsel ( rb_ctlsel ), +.rb_ctl_static ( rb_ctl_static[9:0] ), +.rb_core_updnen ( rb_core_updnen ), +.rb_clkdiv ( rb_clkdiv[2:0] ), +.rb_selflock ( rb_selflock ), +.rb_half_code ( rb_half_code ), +.rb_dly_pst ( rb_dly_pst[9:0] ), +.core_up ( core_up_in ), +.core_dn ( core_dn_in ), +.t_up ( t_up_sync ), +.t_down ( t_down_sync ), +.launch ( launch ), +.measure ( measure ), +.f_gray ( f_gray[6:0] ), +.i_gray ( i_gray[2:0] ), +.up_core ( up_core ), +.dn_core ( dn_core ), +.scan_mode_n ( scan_mode_n ), +.lock ( dll_lock ), +.pvt_ref_binary ( pvt_ref_binary[9:0] ), +.internal_pvt_binary ( internal_pvt_binary[9:0] ), +.search_overflow ( search_overflow ), +.gate_state ( gate_state[3:0] ), +.gate_shf ( gate_shf[6:0] ), +.pvt_ref_gry ( pvt_ref_gry[9:0] ), +.pvt_ref_half_gry ( pvt_ref_half_gry[9:0] ) +); + +endmodule // aibndpnr_dll_pnr diff --git a/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_half_cycle_code_gen.v b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_half_cycle_code_gen.v new file mode 100644 index 0000000..786a98b --- /dev/null +++ b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_half_cycle_code_gen.v @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #3 $ +// Date: $DateTime: 2015/06/17 03:55:49 $ +//------------------------------------------------------------------------ +// Description: half cycle delay code generation logics +//------------------------------------------------------------------------ + +//------------------------------------------------------------------------ +// To be considered : +// 1. any potential glitch between code switching? +//------------------------------------------------------------------------ +module aibndpnr_half_cycle_code_gen +#( +parameter FF_DELAY = 200 +) +( + input wire clk, //reference clock from pll + input wire reset_n, //output for dll reset + input wire [9:0] pvt_ref_binary, //output binary pvt value for delay chain + input wire rb_half_code, //select between original or half cycle codes + output reg [9:0] pvt_ref_half_binary //half cycle code (binary) for delay chain +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +wire [6:0] coarse_bin; +wire [2:0] fint_bin, fint_bin_inc; +wire [2:0] fine_bin; +wire [7:0] coarse_divided_bin; +wire [3:0] fine_divided_bin, coarse_frac_bin; + + assign coarse_divided_bin[7:0] = {1'b0,pvt_ref_binary[9:3]}; + assign fine_divided_bin[3:0] = {1'b0,pvt_ref_binary[2:0]}; + assign coarse_frac_bin[3:0] = {coarse_divided_bin[0],3'b000}; + assign fint_bin[2:0] = coarse_frac_bin[3:1] + fine_divided_bin[3:1]; + assign fint_bin_inc[2:0] = ((fine_divided_bin[0] >= 1'd1) && (fint_bin < 3'd7)) ? fint_bin[2:0] + 3'b001 : fint_bin[2:0]; + + assign coarse_bin = coarse_divided_bin[7:1]; + assign fine_bin = fint_bin_inc; + + always @(posedge clk or negedge reset_n) + begin + if(~reset_n) begin + pvt_ref_half_binary <= #FF_DELAY 10'b00_0000_0000; + end + else case (rb_half_code) + 1'b0 : pvt_ref_half_binary <= #FF_DELAY pvt_ref_binary; + 1'b1 : pvt_ref_half_binary <= #FF_DELAY {coarse_bin,fine_bin}; + default : pvt_ref_half_binary <= #FF_DELAY {coarse_bin,fine_bin}; + endcase + end + +endmodule // aibndpnr_half_cycle_code_gen diff --git a/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_jtag_bscan.v b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_jtag_bscan.v new file mode 100644 index 0000000..037cfa5 --- /dev/null +++ b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_jtag_bscan.v @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + + +module aibndpnr_jtag_bscan ( + input odat0_aib, //sync data0 RX from AIB + input odat1_aib, //sync data1 RX from AIB + input odat_asyn_aib, //async data RX from AIB + input oclkp_aib, //diff clk RX from AIB + input oclkn_aib, //diff clk RX from AIB + input itxen_adap, //OE TX from HSSI Adapter + input idat0_adap, //SDR dat0 TX from HSSI Adapter + input idat1_adap, //SDR dat1 TX from HSSI Adapter + input async_data_adap, //async data TX from HSSI Adapter + input jtag_tx_scanen_in, //JTAG shift DR, active high +// input jtag_rx_scanen_in, //JTAG shift DR, active high + input jtag_clkdr_in, //JTAG boundary scan clock + input jtag_tx_scan_in, //JTAG TX data scan in +// input jtag_rx_scan_in, //JTAG TX data scan in + input jtag_mode_in, //JTAG mode select +// input last_bs_in, //scan-out loopback feedthru back to SSM + input anlg_rstb_adap, //IRSTB from Adaptor + input dig_rstb_adap, //IRSTB from Adaptor + input jtag_rstb_en, //reset_en from TAP + input jtag_rstb, //reset signal from TAP + input jtag_intest, //intest from TAP + input [2:0] irxen_adap, //RXEN from adapter +// input idataselb_adap, //idataselb tie-off for functional +// input iddren_adap, //iddren tie-off for functional + + output jtag_clkdr_out, //CLKDR to remaining BSR +// output jtag_tx_scan_out, //JTAG TX scan chain output + output jtag_rx_scan_out, //JTAG TX scan chain output + output odat0_adap, //sync data0 RX to HSSI Adapter + output odat1_adap, //sync data1 RX to HSSI Adapter +// output oclkp_adap, //diff OCLKP RX to HSSI Adapter +// output oclkn_adap, //diff OCLKN RX to HSSI Adapter + output odat_asyn_adap, //async data RX to HSSI Adapter + output itxen_aib, //OE TX to AIB + output idat0_aib, //SDR dat0 TX to AIB + output idat1_aib, //SDR dat1 TX to AIB + output async_data_aib, //async data TX to AIB + output anlg_rstb_aib, //irstb to AIB + output dig_rstb_aib, //irstb to AIB + output [2:0] irxen_aib, //RXEN to AIB + output jtag_clkdr_outn //inverted clkdr for sync DDR TX +// output idataselb_aib, //idataselb +// output iddren_aib, //iddren +// output last_bs_out //scan-out loopback feedthru back to SSM +// output weakpu, //Weak Pull-up control for leakage test to AIB +// output weakpdn //Weak Pull-down control for leakage test to AIB +// output jtag_bsdout //Replaced with separate TX and RX Scan out + +); + +reg [6:0] tx_reg; +reg [4:0] rx_reg; +reg rx_nreg; +wire [6:0] tx_shift; +wire [6:0] tx_intst; +wire [4:0] rx_shift; + +assign jtag_rx_scan_out = rx_nreg; +assign idat0_aib = (jtag_mode_in)? tx_reg[6] : idat0_adap; +assign idat1_aib = (jtag_mode_in)? tx_reg[5] : idat1_adap; + +//Change this to CKMUX +//assign async_data_aib = (jtag_mode_in)? tx_reg[4] : async_data_adap; + +altr_hps_ckmux21 async_data_aib_ckmux ( + .clk_0(async_data_adap), + .clk_1(tx_reg[4]), + .clk_sel(jtag_mode_in), + .clk_o(async_data_aib) + ); + +assign itxen_aib = (jtag_mode_in)? tx_reg[3] : itxen_adap; +assign irxen_aib[2] = (jtag_mode_in)? tx_reg[2] : irxen_adap[2]; +assign irxen_aib[1] = (jtag_mode_in)? tx_reg[1] : irxen_adap[1]; +assign irxen_aib[0] = (jtag_mode_in)? tx_reg[0] : irxen_adap[0]; + +assign odat0_adap = (jtag_intest)? rx_reg[4] : odat0_aib; +assign odat1_adap = (jtag_intest)? rx_reg[3] : odat1_aib; + +//Change this to CKMUX +//assign odat_asyn_adap = (jtag_intest)? rx_reg[0] : odat_asyn_aib; + +altr_hps_ckmux21 odat_asyn_adap_ckmux ( + .clk_0(odat_asyn_aib), + .clk_1(rx_reg[0]), + .clk_sel(jtag_intest), + .clk_o(odat_asyn_adap) + ); + +assign anlg_rstb_aib = (jtag_rstb_en)? jtag_rstb : anlg_rstb_adap; +assign dig_rstb_aib = (jtag_rstb_en)? jtag_rstb : dig_rstb_adap; + +assign jtag_clkdr_out = jtag_clkdr_in; +//Change to ckinv +//assign jtag_clkdr_outn = ~jtag_clkdr_in; + +altr_hps_ckinv jtag_clkdr_ckinv ( + .clk(jtag_clkdr_in), + .clk_inv(jtag_clkdr_outn) + ); + +//assign tx_shift = (jtag_tx_scanen_in) ? tx_intst : tx_reg[6:0]; +// Change async_data_adap mux to CKMUX +//assign tx_shift = (jtag_tx_scanen_in) ? {jtag_tx_scan_in,tx_reg[6:1]} : tx_intst; +assign tx_shift[6:5] = (jtag_tx_scanen_in) ? {jtag_tx_scan_in,tx_reg[6]} : tx_intst[6:5]; +assign tx_shift[3:0] = (jtag_tx_scanen_in) ? {tx_reg[4:1]} : tx_intst[3:0]; + +altr_hps_ckmux21 tx_shift_4_ckmux ( + .clk_0(tx_intst[4]), + .clk_1(tx_reg[5]), + .clk_sel(jtag_tx_scanen_in), + .clk_o(tx_shift[4]) + ); + +//assign tx_intst = (jtag_intest) ? {idat0_adap,idat1_adap,async_data_adap,itxen_adap,irxen_adap[2],irxen_adap[1],irxen_adap[0]} : {jtag_tx_scan_in,tx_reg[6:1]}; +// Change async_data_adap mux to CKMUX +//assign tx_intst = (jtag_intest) ? {idat0_adap,idat1_adap,async_data_adap,itxen_adap,irxen_adap[2],irxen_adap[1],irxen_adap[0]} : tx_reg[6:0]; +assign tx_intst[6:5] = (jtag_intest) ? {idat0_adap,idat1_adap} : tx_reg[6:5]; +assign tx_intst[3:0] = (jtag_intest) ? {itxen_adap,irxen_adap[2],irxen_adap[1],irxen_adap[0]} : tx_reg[3:0]; + +altr_hps_ckmux21 tx_intst_4_ckmux ( + .clk_0(tx_reg[4]), + .clk_1(async_data_adap), + .clk_sel(jtag_intest), + .clk_o(tx_intst[4]) + ); + + + +always @( posedge jtag_clkdr_in ) +begin + tx_reg <= tx_shift; +end + +//assign rx_shift = (jtag_tx_scanen_in) ? {tx_reg[0],rx_reg[4:1]} : {odat0_aib,odat1_aib,oclkn_aib,oclkp_aib,odat_asyn_aib}; +//Change oclkn_aib, oclkp_aib and odat_asyn_adap to ckmux +//assign rx_shift = (jtag_tx_scanen_in) ? {tx_reg[0],rx_reg[4:1]} : {odat0_adap,odat1_adap,oclkn_aib,oclkp_aib,odat_asyn_adap}; +assign rx_shift[4:3] = (jtag_tx_scanen_in) ? {tx_reg[0],rx_reg[4]} : {odat0_adap,odat1_adap}; + +altr_hps_ckmux21 rx_shift_2_ckmux ( + .clk_0(oclkn_aib), + .clk_1(rx_reg[3]), + .clk_sel(jtag_tx_scanen_in), + .clk_o(rx_shift[2]) + ); + +altr_hps_ckmux21 rx_shift_1_ckmux ( + .clk_0(oclkp_aib), + .clk_1(rx_reg[2]), + .clk_sel(jtag_tx_scanen_in), + .clk_o(rx_shift[1]) + ); + +altr_hps_ckmux21 rx_shift_0_ckmux ( + .clk_0(odat_asyn_adap), + .clk_1(rx_reg[1]), + .clk_sel(jtag_tx_scanen_in), + .clk_o(rx_shift[0]) + ); + + +always @( posedge jtag_clkdr_in ) +begin + rx_reg <= rx_shift; +end + +always @ ( negedge jtag_clkdr_in ) +begin + rx_nreg <= rx_reg[0]; +end + +endmodule diff --git a/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_redundancy.v b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_redundancy.v new file mode 100644 index 0000000..a595ac0 --- /dev/null +++ b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_redundancy.v @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module aibndpnr_redundancy ( //input of input mux +idata0_in1, idata0_in0, idata1_in1, idata1_in0, +idataselb_in1, idataselb_in0, iddren_in1, iddren_in0, +irxen_in1, irxen_in0, itxen_in1, itxen_in0, indrv_in1, indrv_in0, ipdrv_in1, ipdrv_in0, async_dat_in1, async_dat_in0, +//Output of input mux +idata0_out, idata1_out, idataselb_out, iddren_out, +irxen_out, itxen_out, indrv_out, ipdrv_out, async_dat_out, + +//input of output mux +odat0_in1, odat0_in0, odat1_in1, odat1_in0, odat_async_in1, odat_async_in0, + +//Output of output mux +odat0_out, odat1_out, odat_async_out, + +//Mux selection signal +shift_en //Removed VCCL & VSS port + +); + +//Power Supply +//input vccl, vssl; + +//Mux selection signal +input shift_en; + +//input of input mux +input idata0_in1, idata0_in0; +input idata1_in1, idata1_in0; +input idataselb_in1, idataselb_in0; +input iddren_in1, iddren_in0; +input [2:0] irxen_in1, irxen_in0; +input itxen_in1, itxen_in0; +input [1:0] indrv_in1, indrv_in0; +input [1:0] ipdrv_in1, ipdrv_in0; +input async_dat_in1, async_dat_in0; + +//output of input mux +output idata0_out; +output idata1_out; +output idataselb_out; +output iddren_out; +output [2:0] irxen_out; +output itxen_out; +output [1:0] indrv_out; +output [1:0] ipdrv_out; +output async_dat_out; + + +//input of output mux +input odat0_in1, odat0_in0; +input odat1_in1, odat1_in0; +input odat_async_in1, odat_async_in0; + +//output of output mux +output odat0_out; +output odat1_out; +output odat_async_out; + +// Buses in the design + + +//input mux +assign idata0_out = shift_en? idata0_in1 : idata0_in0; +assign idata1_out = shift_en? idata1_in1 : idata1_in0; +assign idataselb_out = shift_en? idataselb_in1 : idataselb_in0 ; +assign iddren_out = shift_en? iddren_in1 : iddren_in0; +assign irxen_out[2] = shift_en? irxen_in1[2] : irxen_in0[2]; +assign irxen_out[1] = shift_en? irxen_in1[1] : irxen_in0[1]; +assign irxen_out[0] = shift_en? irxen_in1[0] : irxen_in0[0]; +assign itxen_out = shift_en? itxen_in1 : itxen_in0; +assign indrv_out[1] = shift_en? indrv_in1[1] : indrv_in0[1]; +assign indrv_out[0] = shift_en? indrv_in1[0] : indrv_in0[0]; +assign ipdrv_out[1] = shift_en? ipdrv_in1[1] : ipdrv_in0[1]; +assign ipdrv_out[0] = shift_en? ipdrv_in1[0] : ipdrv_in0[0]; + +//Change to CKMUX +//assign async_dat_out = shift_en? async_dat_in1 : async_dat_in0; + +altr_hps_ckmux21 async_dat_out_ckmux ( + .clk_0(async_dat_in0), + .clk_1(async_dat_in1), + .clk_sel(shift_en), + .clk_o(async_dat_out) + ); + + +//output mux +assign odat0_out = shift_en? odat0_in1 : odat0_in0; +assign odat1_out = shift_en? odat1_in1 : odat1_in0; + +//Change to CKMUX +//assign odat_async_out = shift_en? odat_async_in1 : odat_async_in0; + +altr_hps_ckmux21 odat_async_out_ckmux ( + .clk_0(odat_async_in0), + .clk_1(odat_async_in1), + .clk_sel(shift_en), + .clk_o(odat_async_out) + ); + +endmodule + diff --git a/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_self_lock_assertion.v b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_self_lock_assertion.v new file mode 100644 index 0000000..460a83e --- /dev/null +++ b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_self_lock_assertion.v @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #8 $ +// Date: $DateTime: 2015/12/02 22:11:55 $ +//------------------------------------------------------------------------ +// Description: self-timed lock assertion logics +//------------------------------------------------------------------------ + +module aibndpnr_self_lock_assertion +#( +parameter FF_DELAY = 200 +) +( + input wire clk, //reference clock from pll + input wire reset_n, //output for dll reset + input wire [2:0] rb_clkdiv, //select division factor for clock + input wire rb_selflock, //select between lock signal from self-timed logics or FSM lock monitor + input wire fsm_lock, //lock signal from FSM lock monitor + input wire scan_mode_n, + output wire prelock, //prelock signal for fast binary search + output wire lock //lock signal to core +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +wire clkdiv_2, clkdiv_4, clkdiv_8, clkdiv_16, clkdiv_32, clkdiv_64; +wire clkdiv_128, clkdiv_256, clkdiv_512, clkdiv_1024; +reg [7:0] cntr256; +reg pre_lock; +reg self_lock; +wire divclk; +reg [9:0] count1024; + + always @(posedge clk or negedge reset_n) + begin + if(~reset_n) begin + count1024 <= #FF_DELAY 10'b0; + end + else + count1024 <= #FF_DELAY (count1024 == 10'b11111_11111)? 0 : count1024+1; + end + + assign clkdiv_2 = count1024[0]; + assign clkdiv_4 = count1024[1]; + assign clkdiv_8 = count1024[2]; + assign clkdiv_16 = count1024[3]; + assign clkdiv_32 = count1024[4]; + assign clkdiv_64 = count1024[5]; + assign clkdiv_128 = count1024[6]; + assign clkdiv_256 = count1024[7]; + assign clkdiv_512 = count1024[8]; + assign clkdiv_1024 = count1024[9]; +/* + always @(posedge clk or negedge reset_n) + if (~reset_n) divclk <= #FF_DELAY 1'b0; + else case (rb_clkdiv) + 3'b000 : divclk <= #FF_DELAY clkdiv_8; //div8 when rb_clkdiv=000 + 3'b001 : divclk <= #FF_DELAY clkdiv_16; //div16 when rb_clkdiv=001 + 3'b010 : divclk <= #FF_DELAY clkdiv_32; //div32 when rb_clkdiv=010 + 3'b011 : divclk <= #FF_DELAY clkdiv_64; //div64 when rb_clkdiv=011 + 3'b100 : divclk <= #FF_DELAY clkdiv_128; //div128 when rb_clkdiv=100 + 3'b101 : divclk <= #FF_DELAY clkdiv_256; //div256 when rb_clkdiv=101 + 3'b110 : divclk <= #FF_DELAY clkdiv_512; //div512 when rb_clkdiv=110 + 3'b111 : divclk <= #FF_DELAY clkdiv_1024; //div1024 when rb_clkdiv=111 + default : divclk <= #FF_DELAY clkdiv_8; + endcase +*/ + +wire clk8_16,clk32_64,clk128_256,clk512_1024,clk8_16_32_64,clk128_256_512_1024; + +aibndpnr_dll_atech_clkmux clkmux_clk8_16 +( + .clk1 (clkdiv_16), + .clk2 (clkdiv_8), + .s (rb_clkdiv[0]), + .clkout (clk8_16) +); + +aibndpnr_dll_atech_clkmux clkmux_clk32_64 +( + .clk1 (clkdiv_64), + .clk2 (clkdiv_32), + .s (rb_clkdiv[0]), + .clkout (clk32_64) +); + +aibndpnr_dll_atech_clkmux clkmux_clk128_256 +( + .clk1 (clkdiv_256), + .clk2 (clkdiv_128), + .s (rb_clkdiv[0]), + .clkout (clk128_256) +); + +aibndpnr_dll_atech_clkmux clkmux_clk512_1024 +( + .clk1 (clkdiv_1024), + .clk2 (clkdiv_512), + .s (rb_clkdiv[0]), + .clkout (clk512_1024) +); + +aibndpnr_dll_atech_clkmux clkmux_clk8_16_32_64 +( + .clk1 (clk32_64), + .clk2 (clk8_16), + .s (rb_clkdiv[1]), + .clkout (clk8_16_32_64) +); + +aibndpnr_dll_atech_clkmux clkmux_clk128_256_512_1024 +( + .clk1 (clk512_1024), + .clk2 (clk128_256), + .s (rb_clkdiv[1]), + .clkout (clk128_256_512_1024) +); + +aibndpnr_dll_atech_clkmux clkmux_divclk +( + .clk1 (clk128_256_512_1024), + .clk2 (clk8_16_32_64), + .s (rb_clkdiv[2]), + .clkout (divclk) +); + + always @(posedge divclk or negedge reset_n) begin + if (~reset_n) begin + cntr256 <= #FF_DELAY 8'b0000_0000; + pre_lock <= #FF_DELAY 1'b0; + self_lock <= #FF_DELAY 1'b0; + end + else if ((cntr256 >= 8'd0) & (cntr256 < 8'd150)) begin + cntr256 <= #FF_DELAY cntr256 + 8'b0000_0001; + end + else if ((cntr256 >= 8'd150) & (cntr256 < 8'd255)) begin + pre_lock <= #FF_DELAY 1'b1; + cntr256 <= #FF_DELAY cntr256 + 8'b0000_0001; + end + else begin + self_lock <= #FF_DELAY 1'b1; + end + end + +wire lock_presync; + assign lock_presync = rb_selflock ? self_lock : fsm_lock; + +//lock synchronization +//cdclib_bitsync2 #(.CLK_FREQ_MHZ(1000)) prelock_sync ( .rst_n(reset_n), .clk(clk), .data_in(pre_lock), .data_out(prelock) ); +//cdclib_bitsync2 #(.CLK_FREQ_MHZ(1000)) lock_sync ( .rst_n(reset_n), .clk(clk), .data_in(lock_presync), .data_out(lock) ); +cdclib_bitsync2 #( + .DWIDTH(1), + .RESET_VAL(0), + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE(1), + .VID(1) +) prelock_sync ( .rst_n(reset_n), .clk(clk), .data_in(pre_lock), .data_out(prelock) ); + +cdclib_bitsync2 #( + .DWIDTH(1), + .RESET_VAL(0), + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE(1), + .VID(1) +) lock_sync ( .rst_n(reset_n), .clk(clk), .data_in(lock_presync), .data_out(lock) ); + +endmodule // aibndpnr_self_lock_assertion diff --git a/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_sync.v b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_sync.v new file mode 100644 index 0000000..418210a --- /dev/null +++ b/maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_sync.v @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module aibndpnr_sync +#( +//----------------------------------------------------------------------------------------------------------------------- +// Local calculated parameters +//----------------------------------------------------------------------------------------------------------------------- +parameter FF_DELAY = 200 +) + +( q, so, clk, d, rb, ssb, si ); + +output reg q, so; + +input clk, d, rb, ssb, si; + +`ifdef DLL_SYNOPSYS + +d04hgy23nd0c0 xsync0 ( .d(d), .clk(clk), .o(q0), + .rb(rb), .si(si), .so(so0), .ssb(ssb)); +d04hgy23nd0c0 xsync1 ( .d(q0), .clk(clk), .o(q), + .rb(rb), .si(so0), .so(so), .ssb(ssb)); + +`else + +reg t_reg0; +reg t_reg1; + +always @(posedge clk or negedge rb) + if (~rb) begin + t_reg0 <= #FF_DELAY 1'b0; + t_reg1 <= #FF_DELAY 1'b0; + q <= #FF_DELAY 1'b0; + end + else begin + t_reg0 <= #FF_DELAY d; + t_reg1 <= #FF_DELAY t_reg0; + q <= #FF_DELAY t_reg1; + end + +`endif + +endmodule + + diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_async_fifo.v b/maib_rtl/cdclib/rtl/block_function/cdclib_async_fifo.v new file mode 100644 index 0000000..a55bab9 --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_async_fifo.v @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_async_fifo.v.rca $ +// Revision: $Revision: #3 $ +// Date: $Date: 2015/03/20 $ +//----------------------------------------------------------------------------- +// Description : Async. FIFO module +//----------------------------------------------------------------------------- +module cdclib_async_fifo + #( + parameter DWIDTH = 8, // FIFO Input data width + parameter AWIDTH = 4, // FIFO Depth (address width) + parameter WR_CLK_FREQ_MHZ = 250, // Clock frequency (in MHz) + parameter RD_CLK_FREQ_MHZ = 250, // Clock frequency (in MHz) + parameter VID = 1 // 1: VID, 0: preVID + ) + ( + input wire wr_rst_n, // Write Domain Active low Reset + input wire wr_clk, // Write Domain Clock + input wire wr_en, // Write Data Enable + input wire [DWIDTH-1:0] wr_data, // Write Data In + input wire rd_rst_n, // Read Domain Active low Reset + input wire rd_clk, // Read Domain Clock + input wire rd_en, // Read Data Enable + input wire [AWIDTH-1:0] r_pempty, // FIFO partially empty threshold + input wire [AWIDTH-1:0] r_pfull, // FIFO partially full threshold + input wire [AWIDTH-1:0] r_empty, // FIFO empty threshold + input wire [AWIDTH-1:0] r_full, // FIFO full threshold + + output wire [DWIDTH-1:0] rd_data, // Read Data Out + output wire [AWIDTH-1:0] rd_numdata, // Number of Data available in Read clock + output wire [AWIDTH-1:0] wr_numdata, // Number of Data available in Write clock + + output reg wr_empty, // FIFO Empty + output reg wr_pempty, // FIFO Partial Empty + output reg wr_full, // FIFO Full + output reg wr_pfull, // FIFO Parial Full + output reg rd_empty, // FIFO Empty + output reg rd_pempty, // FIFO Partial Empty + output reg rd_full, // FIFO Full + output reg rd_pfull // FIFO Partial Full + ); + + //******************************************************************** + // Define variables + //******************************************************************** + integer m; + // Regs + reg [DWIDTH-1:0] fifo_mem [((1<>1) ^ wr_addr_bin_nxt); + cdclib_bintogray + #( + .WIDTH (AWIDTH+1) + ) wr_addr_nxt_bintogray + ( + .data_in (wr_addr_bin_nxt), + .data_out (wr_addr_gry_nxt) + ); + + //******************************************************************** + // WRITE CLOCK DOMAIN: Synchronize Read Address to Write Clock + //******************************************************************** + cdclib_bitsync2 + #( + .DWIDTH (AWIDTH+1), // Sync Data input + .RESET_VAL (0), // Reset value + .CLK_FREQ_MHZ(WR_CLK_FREQ_MHZ), + .TOGGLE_TYPE (1), + .VID (VID) + ) + wr_bitsync2 + ( + .clk (wr_clk), + .rst_n (wr_rst_n), + .data_in (rd_addr_gry), + .data_out (rd_addr_gry_sync) + ); +// assign rd_addr_bin_sync = greytobin(rd_addr_gry_sync); + cdclib_graytobin + #( + .WIDTH (AWIDTH+1) + ) rd_addr_graytobin + ( + .data_in (rd_addr_gry_sync), + .data_out (rd_addr_bin_sync) + ); + + assign wr_numdata = (wr_addr_bin_nxt - rd_addr_bin_sync); + + //******************************************************************** + // WRITE CLOCK DOMAIN: Generate Fifo Number of Data Present + // using Write Address and Synchronized Read Address + //******************************************************************** + always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + wr_full <= 1'b0; + wr_pfull <= 1'b0; + wr_empty <= 1'b1; + wr_pempty<= 1'b1; + end + else begin + + // Generate FIFO Empty + wr_empty <= (wr_numdata == r_empty) ? 1'b1 : 1'b0; + // Generate FIFO Almost Empty + wr_pempty <= (wr_numdata <= r_pempty) ? 1'b1 : 1'b0; + // Generate FIFO Full + wr_full <= (wr_numdata >= r_full) ? 1'b1 : 1'b0; + // Generate FIFO Almost Full + wr_pfull <= (wr_numdata >= r_pfull) ? 1'b1 : 1'b0; + + end + end + + //******************************************************************** + // READ CLOCK DOMAIN: Generate READ Address & READ Address GREY + //******************************************************************** + // Memory read-address pointer + assign rd_addr_mem = rd_addr_bin[AWIDTH-1:0]; + + always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + rd_addr_bin <= {(AWIDTH+1){1'b0}}; + rd_addr_gry <= {(AWIDTH+1){1'b0}}; + end + else begin + rd_addr_bin <= rd_addr_bin_nxt; + rd_addr_gry <= rd_addr_gry_nxt; + end + end + // Binary Next Read Address + assign rd_addr_bin_nxt = rd_addr_bin + (rd_en & ~rd_empty); + + // Grey Next Read Address + cdclib_bintogray + #( + .WIDTH (AWIDTH+1) + ) rd_addr_nxt_bintogray + ( + .data_in (rd_addr_bin_nxt), + .data_out (rd_addr_gry_nxt) + ); + + + //******************************************************************** + // READ CLOCK DOMAIN: Synchronize Write Address to Read Clock + //******************************************************************** + cdclib_bitsync2 + #( + .DWIDTH (AWIDTH+1), // Sync Data input + .RESET_VAL (0), // Reset value + .CLK_FREQ_MHZ(RD_CLK_FREQ_MHZ), + .TOGGLE_TYPE (1), + .VID (VID) + ) + rd_bitsync2 + ( + .clk (rd_clk), + .rst_n (rd_rst_n), + .data_in (wr_addr_gry), + .data_out (wr_addr_gry_sync) + ); + cdclib_graytobin + #( + .WIDTH (AWIDTH+1) + ) wr_addr_graytobin + ( + .data_in (wr_addr_gry_sync), + .data_out (wr_addr_bin_sync) + ); + assign rd_numdata = (wr_addr_bin_sync - rd_addr_bin_nxt); + + //******************************************************************** + // READ CLOCK DOMAIN: Generate Fifo Number of Data Present + // using Read Address and Synchronized Write Address + //******************************************************************** + always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + rd_empty <= 1'b1; + rd_pempty <= 1'b1; + rd_full <= 1'b0; + rd_pfull <= 1'b0; + end + else begin + // Generate FIFO Empty + rd_empty <= (rd_numdata == r_empty) ? 1'b1 : 1'b0; + // Generate FIFO Almost Empty + rd_pempty <= (rd_numdata <= r_pempty) ? 1'b1 : 1'b0; + // Generate FIFO Full + rd_full <= (rd_numdata >= r_full) ? 1'b1 : 1'b0; + // Generate FIFO Almost Full + rd_pfull <= (rd_numdata >= r_pfull) ? 1'b1 : 1'b0; + + end + end + +endmodule // cdclib_async_fifo + + diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_bintogray.v b/maib_rtl/cdclib/rtl/block_function/cdclib_bintogray.v new file mode 100644 index 0000000..0f59ff4 --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_bintogray.v @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #1 $ +// Date: $DateTime: 2014/08/24 20:43:27 $ +//------------------------------------------------------------------------ + +module cdclib_bintogray + #( + parameter WIDTH = 2 // Data width + ) + ( + // Inputs + input wire [WIDTH-1:0] data_in, // data in + // Outputs + output wire [WIDTH-1:0] data_out // data out + ); + + +assign data_out = (data_in>>1) ^ data_in; + +endmodule diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_bintogray_inc2.v b/maib_rtl/cdclib/rtl/block_function/cdclib_bintogray_inc2.v new file mode 100644 index 0000000..768db39 --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_bintogray_inc2.v @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #1 $ +// Date: $DateTime: 2014/08/24 20:43:27 $ +//------------------------------------------------------------------------ +//----------------------------------------------------------------------------- +// Description : Binary to Gray conversion when binary count is expected to increment by 2 +//----------------------------------------------------------------------------- + +module cdclib_bintogray_inc2 + #( + parameter WIDTH = 2 // Data width + ) + ( + // Inputs + input wire [WIDTH-1:0] data_in, // data in + // Outputs + output wire [WIDTH-1:0] data_out // data out + ); + + +assign data_out = {(data_in[WIDTH-1:1]>>1) ^ data_in[WIDTH-1:1], 1'b0}; + + +endmodule diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_bintogray_inc8.v b/maib_rtl/cdclib/rtl/block_function/cdclib_bintogray_inc8.v new file mode 100644 index 0000000..81def7b --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_bintogray_inc8.v @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #1 $ +// Date: $DateTime: 2014/08/24 20:43:27 $ +//------------------------------------------------------------------------ +//----------------------------------------------------------------------------- +// Description : Binary to Gray conversion when binary count is expected to increment by 8 +//----------------------------------------------------------------------------- + +module cdclib_bintogray_inc8 + #( + parameter WIDTH = 6 // Data width + ) + ( + // Inputs + input wire [WIDTH-1:0] data_in, // data in + // Outputs + output wire [WIDTH-1:0] data_out // data out + ); + + +assign data_out = {(data_in[WIDTH-1:3]>>1) ^ data_in[WIDTH-1:3], 3'b0}; + + +endmodule diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_bitsync.v b/maib_rtl/cdclib/rtl/block_function/cdclib_bitsync.v new file mode 100644 index 0000000..eaf0c2d --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_bitsync.v @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_bitsync.v.rca $ +// Revision: $Revision: #2 $ +// Date: $Date: 2015/01/23 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ +module cdclib_bitsync + #( + parameter DWIDTH = 1, // Sync Data input + parameter SYNCSTAGE = 2, // Sync stages + parameter RESET_VAL = 0, // Reset value + parameter CLK_FREQ_MHZ = 250 // Clock frequency (in MHz) + ) + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire [DWIDTH-1:0] data_in, // data in + output wire [DWIDTH-1:0] data_out // data out + ); + + // Define wires/regs + reg [(DWIDTH*SYNCSTAGE)-1:0] sync_regs; + //wire reset_value; + + localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0; // To eliminate truncating warning + + // Sync Always block + always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + sync_regs[(DWIDTH*SYNCSTAGE)-1:DWIDTH] <= {(DWIDTH*(SYNCSTAGE-1)){reset_value}}; + end + else begin + sync_regs[(DWIDTH*SYNCSTAGE)-1:DWIDTH] <= sync_regs[((DWIDTH*(SYNCSTAGE-1))-1):0]; + end + end + + // NF: both FF stages have reset + always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + sync_regs[DWIDTH-1:0] <= {(DWIDTH){reset_value}}; + end + else begin + sync_regs[DWIDTH-1:0] <= data_in; + end + end + + assign data_out = sync_regs[((DWIDTH*SYNCSTAGE)-1):(DWIDTH*(SYNCSTAGE-1))]; + +endmodule // cdclib_bitsync + diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_bitsync2.v b/maib_rtl/cdclib/rtl/block_function/cdclib_bitsync2.v new file mode 100644 index 0000000..244c83b --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_bitsync2.v @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_bitsync2.v.rca $ +// Revision: $Revision: #3 $ +// Date: $Date: 2015/03/20 $ +//------------------------------------------------------------------------ +// Description: 2-stage synchronizer +// +//------------------------------------------------------------------------ +module cdclib_bitsync2 + #( + parameter DWIDTH = 1, // Sync Data input + parameter RESET_VAL = 0, // Reset value + parameter CLK_FREQ_MHZ = 250, // Clock frequency (in MHz) + parameter TOGGLE_TYPE = 1, // Toggle type: 1 --> 5 + parameter VID = 1 // 1: VID, 0: preVID + ) + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire [DWIDTH-1:0] data_in, // data in + output wire [DWIDTH-1:0] data_out // data out + ); + + +// TOGGLE_TYPE = 1: once every clock cycle +// TOGGLE_TYPE = 2: once every 10 clock cycles +// TOGGLE_TYPE = 3: once every min +// TOGGLE_TYPE = 4: once every hour +// TOGGLE_TYPE = 5: once every day +// TOGGLE_TYPE = 0: never (default) + + +generate + genvar i; +if (VID == 1) begin +// Reset synchronizer +if (RESET_VAL == 0) begin + if (CLK_FREQ_MHZ <= 175) begin + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_reset_type_w_gate bit_sync2_reset_type_w_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end + else if (CLK_FREQ_MHZ <= 350 ) begin + if (TOGGLE_TYPE == 1 || TOGGLE_TYPE == 2) + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_reset_type_l_gate bit_sync2_reset_type_l_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + else + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_reset_type_w_gate bit_sync2_reset_type_w_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end + else if (CLK_FREQ_MHZ <= 850) begin + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_reset_type_l_gate bit_sync2_reset_type_l_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end + else if (CLK_FREQ_MHZ <= 1200 ) begin + if (TOGGLE_TYPE == 1 || TOGGLE_TYPE == 2) + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_reset_type_n_gate bit_sync2_reset_type_n_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + else + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_reset_type_l_gate bit_sync2_reset_type_l_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end + else if (CLK_FREQ_MHZ <= 1500 ) begin + if (TOGGLE_TYPE == 1 || TOGGLE_TYPE == 2 || TOGGLE_TYPE == 3) + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_reset_type_n_gate bit_sync2_reset_type_n_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + else + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_reset_type_l_gate bit_sync2_reset_type_l_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end + else if (CLK_FREQ_MHZ <= 1700 ) begin + if (TOGGLE_TYPE == 1 || TOGGLE_TYPE == 2 || TOGGLE_TYPE == 3 || TOGGLE_TYPE == 4) + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_reset_type_n_gate bit_sync2_reset_type_n_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + else + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_reset_type_l_gate bit_sync2_reset_type_l_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end + else begin + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_reset_type_n_gate bit_sync2_reset_type_n_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end +end +// Preset synchronizer +else begin + if (CLK_FREQ_MHZ <= 175) begin + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_set_type_w_gate bit_sync2_set_type_w_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end + else if (CLK_FREQ_MHZ <= 350 ) begin + if (TOGGLE_TYPE == 1 || TOGGLE_TYPE == 2) + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_set_type_l_gate bit_sync2_set_type_l_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + else + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_set_type_w_gate bit_sync2_set_type_w_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end + else if (CLK_FREQ_MHZ <= 850) begin + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_set_type_l_gate bit_sync2_set_type_l_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end + else if (CLK_FREQ_MHZ <= 1200 ) begin + if (TOGGLE_TYPE == 1 || TOGGLE_TYPE == 2) + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_set_type_n_gate bit_sync2_set_type_n_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + else + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_set_type_l_gate bit_sync2_set_type_l_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end + else if (CLK_FREQ_MHZ <= 1500 ) begin + if (TOGGLE_TYPE == 1 || TOGGLE_TYPE == 2 || TOGGLE_TYPE == 3) + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_set_type_n_gate bit_sync2_set_type_n_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + else + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_set_type_l_gate bit_sync2_set_type_l_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end + else if (CLK_FREQ_MHZ <= 1700 ) begin + if (TOGGLE_TYPE == 1 || TOGGLE_TYPE == 2 || TOGGLE_TYPE == 3 || TOGGLE_TYPE == 4) + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_set_type_n_gate bit_sync2_set_type_n_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + else + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_set_type_l_gate bit_sync2_set_type_l_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end + else begin + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_set_type_n_gate bit_sync2_set_type_n_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end +end +end +else begin // Pre-VID +if (RESET_VAL == 0) begin // sync with reset + if (CLK_FREQ_MHZ <= 300) begin + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_reset_type_l_gate bit_sync2_reset_type_l_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end + else begin + if (TOGGLE_TYPE == 1 || TOGGLE_TYPE == 2) + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_reset_type_n_gate bit_sync2_reset_type_n_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + else + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_reset_type_l_gate bit_sync2_reset_type_l_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end +end +else begin // sync with pre-set + if (CLK_FREQ_MHZ <= 300) begin + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_set_type_l_gate bit_sync2_set_type_l_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end + else begin + if (TOGGLE_TYPE == 1 || TOGGLE_TYPE == 2) + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_set_type_n_gate bit_sync2_set_type_n_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + else + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync2_set_type_l_gate bit_sync2_set_type_l_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end +end + +end // pre-VID + +endgenerate + +endmodule // cdclib_bitsync2 + diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_bitsync4.v b/maib_rtl/cdclib/rtl/block_function/cdclib_bitsync4.v new file mode 100644 index 0000000..bd68dc0 --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_bitsync4.v @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_bitsync4.v.rca $ +// Revision: $Revision: #3 $ +// Date: $Date: 2015/03/20 $ +//------------------------------------------------------------------------ +// Description: 4-stage synchonizer +// +//------------------------------------------------------------------------ +module cdclib_bitsync4 + #( + parameter DWIDTH = 1, // Sync Data input + parameter RESET_VAL = 0, // Reset value + parameter CLK_FREQ_MHZ = 1000, // Clock frequency (in MHz) + parameter TOGGLE_TYPE = 1, // Toggle type: 1 --> 5 + parameter VID = 1 // 1: VID, 0: preVID + ) + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire [DWIDTH-1:0] data_in, // data in + output wire [DWIDTH-1:0] data_out // data out + ); + + +// TOGGLE_TYPE = 1: once every clock cycle +// TOGGLE_TYPE = 2: once every 10 clock cycles +// TOGGLE_TYPE = 3: once every min +// TOGGLE_TYPE = 4: once every hour +// TOGGLE_TYPE = 5: once every day +// TOGGLE_TYPE = 0: never (default) + + +generate + genvar i; +// Reset synchronizer +if (RESET_VAL == 0) begin + if (CLK_FREQ_MHZ <= 850) begin + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync4_reset_type_w_gate bit_sync4_reset_type_w_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end + else begin + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync4_reset_type_l_gate bit_sync4_reset_type_l_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end +end +// Preset synchronizer +else begin + if (CLK_FREQ_MHZ <= 850) begin + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync4_set_type_w_gate bit_sync4_set_type_w_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end + else begin + begin + for (i=0; i < DWIDTH; i=i+1) + begin: bit_sync_i + cdclib_sync4_set_type_l_gate bit_sync4_set_type_l_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end + end + end +end + +endgenerate + +endmodule // cdclib_bitsync4 + diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_graytobin.v b/maib_rtl/cdclib/rtl/block_function/cdclib_graytobin.v new file mode 100644 index 0000000..9bba78b --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_graytobin.v @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #1 $ +// Date: $DateTime: 2014/08/24 20:43:27 $ +//------------------------------------------------------------------------ + +module cdclib_graytobin + #( + parameter WIDTH = 2 // Data width + ) + ( + // Inputs + input wire [WIDTH-1:0] data_in, // data in + // Outputs + output wire [WIDTH-1:0] data_out // data out + ); + + + genvar i; + + generate + for (i = 0; i <= WIDTH-1; i = i+1) begin: GREY_TO_BIN + assign data_out[i] = ^(data_in >> i); + + end // block: GRAY_TO_BIN + endgenerate + +endmodule diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_graytobin_inc2.v b/maib_rtl/cdclib/rtl/block_function/cdclib_graytobin_inc2.v new file mode 100644 index 0000000..d3e3d86 --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_graytobin_inc2.v @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #1 $ +// Date: $DateTime: 2014/08/24 20:43:27 $ +//------------------------------------------------------------------------ +//----------------------------------------------------------------------------- +// Description : Gray to binary conversion when binary count is expected to increment by 2 +//----------------------------------------------------------------------------- + +module cdclib_graytobin_inc2 + #( + parameter WIDTH = 2 // Data width + ) + ( + // Inputs + input wire [WIDTH-1:0] data_in, // data in + // Outputs + output wire [WIDTH-1:0] data_out // data out + ); + + + genvar i; + + assign data_out[0] = 1'b0; + generate + for (i = 1; i <= WIDTH-1; i = i+1) begin: GREY_TO_BIN + assign data_out[i] = ^(data_in >> i); + + end // block: GRAY_TO_BIN + endgenerate + + +endmodule diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_graytobin_inc8.v b/maib_rtl/cdclib/rtl/block_function/cdclib_graytobin_inc8.v new file mode 100644 index 0000000..4d374e4 --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_graytobin_inc8.v @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #1 $ +// Date: $DateTime: 2014/08/24 20:43:27 $ +//------------------------------------------------------------------------ +//----------------------------------------------------------------------------- +// Description : Gray to binary conversion when binary count is expected to increment by 8 +//----------------------------------------------------------------------------- + +module cdclib_graytobin_inc8 + #( + parameter WIDTH = 6 // Data width + ) + ( + // Inputs + input wire [WIDTH-1:0] data_in, // data in + // Outputs + output wire [WIDTH-1:0] data_out // data out + ); + + + genvar i; + + assign data_out[2:0] = 3'b000; + generate + for (i = 3; i <= WIDTH-1; i = i+1) begin: GREY_TO_BIN + assign data_out[i] = ^(data_in >> i); + + end // block: GRAY_TO_BIN + endgenerate + + +endmodule diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_lvlsync.v b/maib_rtl/cdclib/rtl/block_function/cdclib_lvlsync.v new file mode 100644 index 0000000..8fff706 --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_lvlsync.v @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #3 $ +// Date: $Date: 2015/03/20 $ +//----------------------------------------------------------------------------- +// Description : Parameterizable Level Sync Module +// PULSE MODE OFF : Generate a signal when ever the input changes +// PULSE MODE ON : Generate a ONE clock pulse o/p for every multicycle wide pulse +// on input +//----------------------------------------------------------------------------- +module cdclib_lvlsync + #( + parameter EN_PULSE_MODE = 0, // Enable Pulse mode i.e O/P data pulses for change in I/P + parameter DWIDTH = 1, // Sync Data input + parameter SYNCSTAGE = 2, // Sync stages + parameter ACTIVE_LEVEL = 1, // 1: Active high; 0: Active low + parameter WR_CLK_FREQ_MHZ = 250, // Clock frequency (in MHz) + parameter RD_CLK_FREQ_MHZ = 250, // Clock frequency (in MHz) + parameter VID = 1 // 1: VID, 0: preVID + ) + ( + // Inputs + input wire wr_clk, // write clock + input wire rd_clk, // read clock + input wire wr_rst_n, // async reset for write clock domain + input wire rd_rst_n, // async reset for read clock domain + input wire [DWIDTH-1:0] data_in, // data in + // Outputs + output reg [DWIDTH-1:0] data_out // data out + ); + +//****************************************************************************** +// Define regs +//****************************************************************************** +reg [DWIDTH-1:0] data_in_d0; +reg [DWIDTH-1:0] req_wr_clk; +wire [DWIDTH-1:0] req_rd_clk; +wire [DWIDTH-1:0] ack_wr_clk; +wire [DWIDTH-1:0] ack_rd_clk; +reg [DWIDTH-1:0] req_rd_clk_d0; + +//****************************************************************************** +// Generate for multi bits +//****************************************************************************** +genvar i; +generate +for (i=0; i < DWIDTH; i=i+1) begin : LVLSYNC +//****************************************************************************** +// WRITE CLOCK DOMAIN: Generate req & Store data when synchroniztion is not +// already in progress +//****************************************************************************** + always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + if (ACTIVE_LEVEL == 1) + begin + data_in_d0[i] <= 1'b0; + end + else // ACTIVE_LEVEL==0 + begin + data_in_d0[i] <= 1'b1; + end + req_wr_clk[i] <= 1'b0; + end + else begin + // Store data when Write Req equals Write Ack + if (req_wr_clk[i] == ack_wr_clk[i]) begin + data_in_d0[i] <= data_in[i]; + end + + // Generate a Req when there is change in data + if (EN_PULSE_MODE == 0) begin + if ((req_wr_clk[i] == ack_wr_clk[i]) & (data_in_d0[i] != data_in[i])) begin + req_wr_clk[i] <= ~req_wr_clk[i]; + end + end + else begin + if (ACTIVE_LEVEL == 1) begin + if ((req_wr_clk[i] == ack_wr_clk[i]) & (data_in_d0[i] != data_in[i]) & data_in[i] == 1'b1) begin + req_wr_clk[i] <= ~req_wr_clk[i]; + end + end + else begin + if ((req_wr_clk[i] == ack_wr_clk[i]) & (data_in_d0[i] != data_in[i]) & data_in[i] == 1'b0) begin + req_wr_clk[i] <= ~req_wr_clk[i]; + end + end + end + end + end + + +if (SYNCSTAGE == 4) begin +//****************************************************************************** +// WRITE CLOCK DOMAIN: +//****************************************************************************** +cdclib_bitsync4 +#( +.DWIDTH (1), // Sync Data input +.RESET_VAL (0), // Reset value +.CLK_FREQ_MHZ(WR_CLK_FREQ_MHZ), +.TOGGLE_TYPE (2), +.VID (VID) +) +bitsync4_u_ack_wr_clk + ( + .clk (wr_clk), + .rst_n (wr_rst_n), + .data_in (ack_rd_clk[i]), + .data_out (ack_wr_clk[i]) + ); + +//****************************************************************************** +// READ CLOCK DOMAIN: +//****************************************************************************** +cdclib_bitsync4 +#( +.DWIDTH (1), // Sync Data input +.RESET_VAL (0), // Reset value +.CLK_FREQ_MHZ(RD_CLK_FREQ_MHZ), +.TOGGLE_TYPE (2), +.VID (VID) +) +bitsync4_u_req_rd_clk +( + .clk (rd_clk), + .rst_n (rd_rst_n), + .data_in (req_wr_clk[i]), + .data_out (req_rd_clk[i]) +); +end +else begin +//****************************************************************************** +// WRITE CLOCK DOMAIN: +//****************************************************************************** +cdclib_bitsync2 +#( +.DWIDTH (1), // Sync Data input +.RESET_VAL (0), // Reset value +.CLK_FREQ_MHZ(WR_CLK_FREQ_MHZ), +.TOGGLE_TYPE (2), +.VID (VID) +) +bitsync2_u_ack_wr_clk + ( + .clk (wr_clk), + .rst_n (wr_rst_n), + .data_in (ack_rd_clk[i]), + .data_out (ack_wr_clk[i]) + ); + +//****************************************************************************** +// READ CLOCK DOMAIN: +//****************************************************************************** +cdclib_bitsync2 +#( +.DWIDTH (1), // Sync Data input +.RESET_VAL (0), // Reset value +.CLK_FREQ_MHZ(RD_CLK_FREQ_MHZ), +.TOGGLE_TYPE (2), +.VID (VID) +) +bitsync2_u_req_rd_clk +( + .clk (rd_clk), + .rst_n (rd_rst_n), + .data_in (req_wr_clk[i]), + .data_out (req_rd_clk[i]) +); +end + + assign ack_rd_clk[i] = req_rd_clk_d0[i]; + +//****************************************************************************** +// READ CLOCK DOMAIN: +//****************************************************************************** + always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + if (ACTIVE_LEVEL == 1) + begin + data_out[i] <= 1'b0; + end + else + begin + data_out[i] <= 1'b1; + end + req_rd_clk_d0[i] <= 1'b0; + end + else begin + req_rd_clk_d0[i] <= req_rd_clk[i]; + if (EN_PULSE_MODE == 0) begin + if (req_rd_clk_d0[i] != req_rd_clk[i]) begin + data_out[i] <= ~data_out[i]; + end + end + else if (EN_PULSE_MODE == 1) begin + if (req_rd_clk_d0[i] != req_rd_clk[i]) begin + if (ACTIVE_LEVEL == 1) + begin + data_out[i] <= 1'b1; + end + else // ACTIVE_LEVEL==0 + begin + data_out[i] <= 1'b0; + end + end + else begin // EN_PULSE_MODE==0 + if (ACTIVE_LEVEL == 1) + begin + data_out[i] <= 1'b0; + end + else // ACTIVE_LEVEL==0 + begin + data_out[i] <= 1'b1; + end + end + end + end + end +end +endgenerate + +endmodule // cdclib_lvlsync + diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_lvlsync2.v b/maib_rtl/cdclib/rtl/block_function/cdclib_lvlsync2.v new file mode 100644 index 0000000..b3ccdbb --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_lvlsync2.v @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_lvlsync2.v.rca $ +// Revision: $Revision: #3 $ +// Date: $Date: 2015/03/20 $ +//----------------------------------------------------------------------------- +// Description : 2-stage level sync module +//----------------------------------------------------------------------------- +module cdclib_lvlsync2 + #( + parameter EN_PULSE_MODE = 0, // Enable Pulse mode i.e O/P data pulses for change in I/P + parameter DWIDTH = 1, // Sync Data input + parameter ACTIVE_LEVEL = 1, // 1: Active high; 0: Active low + parameter WR_CLK_FREQ_MHZ = 250, // Clock frequency (in MHz) + parameter RD_CLK_FREQ_MHZ = 250, // Clock frequency (in MHz) + parameter VID = 1 // 1: VID, 0: preVID + ) + ( + // Inputs + input wire wr_clk, // write clock + input wire rd_clk, // read clock + input wire wr_rst_n, // async reset for write clock domain + input wire rd_rst_n, // async reset for read clock domain + input wire [DWIDTH-1:0] data_in, // data in + // Outputs + output wire [DWIDTH-1:0] data_out // data out + ); + +// 2-stage synchronizer +localparam SYNCSTAGE = 2; + +// level-sync module +cdclib_lvlsync + #( + .EN_PULSE_MODE(EN_PULSE_MODE), // Enable Pulse mode i.e O/P data pulses for change in I/P + .DWIDTH(DWIDTH), // Sync Data input + .SYNCSTAGE(SYNCSTAGE), // Sync stages + .ACTIVE_LEVEL(ACTIVE_LEVEL), // Active level + .WR_CLK_FREQ_MHZ(WR_CLK_FREQ_MHZ), + .RD_CLK_FREQ_MHZ(RD_CLK_FREQ_MHZ), + .VID (VID) + ) cdclib_lvlsync2 + ( + // Inputs + .wr_clk(wr_clk), // write clock + .rd_clk(rd_clk), // read clock + .wr_rst_n(wr_rst_n), // async reset for write clock domain + .rd_rst_n(rd_rst_n), // async reset for read clock domain + .data_in(data_in), // data in + // Outputs + .data_out(data_out) // data out + ); + +endmodule //cdclib_lvlsync2 diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_lvlsync4.v b/maib_rtl/cdclib/rtl/block_function/cdclib_lvlsync4.v new file mode 100644 index 0000000..8bb7603 --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_lvlsync4.v @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_lvlsync4.v.rca $ +// Revision: $Revision: #3 $ +// Date: $Date: 2015/03/20 $ +//----------------------------------------------------------------------------- +// Description : 4-stage level sync module +//----------------------------------------------------------------------------- +module cdclib_lvlsync4 + #( + parameter EN_PULSE_MODE = 0, // Enable Pulse mode i.e O/P data pulses for change in I/P + parameter DWIDTH = 1, // Sync Data input + parameter ACTIVE_LEVEL = 1, // 1: Active high; 0: Active low + parameter WR_CLK_FREQ_MHZ = 1000, // Clock frequency (in MHz) + parameter RD_CLK_FREQ_MHZ = 1000, // Clock frequency (in MHz) + parameter VID = 1 // 1: VID, 0: preVID + ) + ( + // Inputs + input wire wr_clk, // write clock + input wire rd_clk, // read clock + input wire wr_rst_n, // async reset for write clock domain + input wire rd_rst_n, // async reset for read clock domain + input wire [DWIDTH-1:0] data_in, // data in + // Outputs + output wire [DWIDTH-1:0] data_out // data out + ); + +// 4-stage synchronizer +localparam SYNCSTAGE = 4; + +// level-sync module +cdclib_lvlsync + #( + .EN_PULSE_MODE(EN_PULSE_MODE), // Enable Pulse mode i.e O/P data pulses for change in I/P + .DWIDTH(DWIDTH), // Sync Data input + .SYNCSTAGE(SYNCSTAGE), // Sync stages + .ACTIVE_LEVEL(ACTIVE_LEVEL), // Active level + .WR_CLK_FREQ_MHZ(WR_CLK_FREQ_MHZ), + .RD_CLK_FREQ_MHZ(RD_CLK_FREQ_MHZ), + .VID (VID) + ) cdclib_lvlsync4 + ( + // Inputs + .wr_clk(wr_clk), // write clock + .rd_clk(rd_clk), // read clock + .wr_rst_n(wr_rst_n), // async reset for write clock domain + .rd_rst_n(rd_rst_n), // async reset for read clock domain + .data_in(data_in), // data in + // Outputs + .data_out(data_out) // data out + ); + +endmodule //cdclib_lvlsync3 diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_pulse_stretch.v b/maib_rtl/cdclib/rtl/block_function/cdclib_pulse_stretch.v new file mode 100644 index 0000000..6213bec --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_pulse_stretch.v @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// (C) 2009 Altera Corporation. All rights reserved. +// +//------------------------------------------------------------------------ +// File: $RCSfile: hd_pcs10g_pulse_stretch.v.rca $ +// Revision: $Revision: #1 $ +// Date: $Date: 2014/08/24 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ + +module cdclib_pulse_stretch + #( + parameter RESET_VAL = 0, // Reset value + parameter HIGH_PULSE = 1 // High or low pulse + ) + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire [1:0] r_num_stages, // number of stages required + input wire data_in, // data in + output reg data_out // stretched data out + ); + + wire reset_value; + assign reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0; // To eliminate truncating warning + + reg data_d1, data_d2, data_d3, data_d4; + reg data_out_comb; + + always @* begin + data_out_comb = data_in; + + case (r_num_stages) + 2'b00: data_out_comb = data_in; + 2'b01: data_out_comb = HIGH_PULSE ? data_d1 | data_in : data_d1 & data_in; + 2'b10: data_out_comb = HIGH_PULSE ? data_d2 | data_d1 | data_in : data_d2 & data_d1 & data_in ; + 2'b11: data_out_comb = HIGH_PULSE ? data_d3 | data_d2 | data_d1 | data_in : data_d3 & data_d2 & data_d1 & data_in; + default: data_out_comb = data_in; + endcase // case(r_num_stages) + end // always @ * + + always @(negedge rst_n or posedge clk) begin + if (~rst_n) begin + data_d1 <= reset_value; + data_d2 <= reset_value; + data_d3 <= reset_value; + data_d4 <= reset_value; + data_out <= reset_value; + end + else begin + data_d1 <= data_in; + data_d2 <= data_d1; + data_d3 <= data_d2; + data_d4 <= data_d3; + data_out <= data_out_comb; + end + end // always @ (negedge rst_n or posedge clk) + +endmodule // cdclib_pulse_stretch diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_rst_n_sync.v b/maib_rtl/cdclib/rtl/block_function/cdclib_rst_n_sync.v new file mode 100644 index 0000000..a148e32 --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_rst_n_sync.v @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_rst_n_sync.v.rca $ +// Revision: $Revision: #1 $ +// Date: $Date: 2014/08/24 $ +//------------------------------------------------------------------------ +// Description: Active low reset synchronizer with bypass in scan mode +// +//------------------------------------------------------------------------ +module cdclib_rst_n_sync + ( input wire rst_n, // Asynchronous reset + input wire rst_n_bypass, // PLD reset input in scan mode + input wire clk, // Clock to synchronize rst_n to + input wire scan_mode_n, // Scan mode control + output wire rst_n_sync // Synchronized rst_n deassertion output + ); + +wire rst_n_sync_int; + +// reset synchronizer core +cdclib_rst_n_sync_core cdclib_rst_n_sync_core + ( + .rst_n(rst_n), // Asynchronous reset + .clk(clk), // Clock to synchronize rst_n to + .tie_high(1'b1), // Tie high input + .rst_n_sync(rst_n_sync_int) // Synchronized rst_n deassertion output + ); + +// Reset synchronizer bypass +assign rst_n_sync = (scan_mode_n == 1'b0) ? rst_n_bypass : rst_n_sync_int; + +endmodule diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_rst_n_sync_core.v b/maib_rtl/cdclib/rtl/block_function/cdclib_rst_n_sync_core.v new file mode 100644 index 0000000..9f54488 --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_rst_n_sync_core.v @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_rst_n_sync.v.rca $ +// Revision: $Revision: #2 $ +// Date: $Date: 2015/03/23 $ +//------------------------------------------------------------------------ +// Description: Active low reset synchronizer core which is replaced by +// special cells in synthesis +//------------------------------------------------------------------------ +module cdclib_rst_n_sync_core + ( input wire rst_n, // Asynchronous reset + input wire clk, // Clock to synchronize rst_n to + input wire tie_high, // Tie high input + output wire rst_n_sync // Synchronized rst_n deassertion output + ); + +//reg rst_n_sync1; + +// Reset synchronizer +// Assertion is asynchronous +// De-assertion is synchronous to clk +//always @(negedge rst_n or posedge clk) +// begin +// if (rst_n == 1'b0) +// begin +// rst_n_sync1 <= 1'b0; +// rst_n_sync <= 1'b0; +// end +// else +// begin +// rst_n_sync1 <= tie_high; +// rst_n_sync <= rst_n_sync1; +// end +// end + +cdclib_sync2_reset_type_l_gate bit_sync2_reset_type_l_inst + ( + .clk (clk), + .rst_n (rst_n), + .data_in (tie_high), + .data_out (rst_n_sync) + ); + + +endmodule diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_sync2_reset_type_l_gate.v b/maib_rtl/cdclib/rtl/block_function/cdclib_sync2_reset_type_l_gate.v new file mode 100644 index 0000000..e86b47c --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_sync2_reset_type_l_gate.v @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_sync2_reset_type_l_gate.v.rca $ +// Revision: $Revision: #1 $ +// Date: $Date: 2015/03/20 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ +module cdclib_sync2_reset_type_l_gate + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire data_in, // data in + output wire data_out // data out + ); + + + reg data_in_sync; + reg data_in_sync2; + + always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + data_in_sync <= 1'b0; + data_in_sync2 <= 1'b0; + end + else begin + data_in_sync <= data_in; + data_in_sync2 <= data_in_sync; + end + end + + assign data_out = data_in_sync2; + +endmodule // cdclib_sync2_reset_type_l_gate + diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_sync2_reset_type_n_gate.v b/maib_rtl/cdclib/rtl/block_function/cdclib_sync2_reset_type_n_gate.v new file mode 100644 index 0000000..ced7c56 --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_sync2_reset_type_n_gate.v @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_sync2_reset_type_n_gate.v.rca $ +// Revision: $Revision: #1 $ +// Date: $Date: 2015/03/20 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ +module cdclib_sync2_reset_type_n_gate + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire data_in, // data in + output wire data_out // data out + ); + + + reg data_in_sync; + reg data_in_sync2; + + always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + data_in_sync <= 1'b0; + data_in_sync2 <= 1'b0; + end + else begin + data_in_sync <= data_in; + data_in_sync2 <= data_in_sync; + end + end + + assign data_out = data_in_sync2; + +endmodule // cdclib_sync2_reset_type_n_gate + diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_sync2_reset_type_w_gate.v b/maib_rtl/cdclib/rtl/block_function/cdclib_sync2_reset_type_w_gate.v new file mode 100644 index 0000000..5439656 --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_sync2_reset_type_w_gate.v @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_sync2_reset_type_w_gate.v.rca $ +// Revision: $Revision: #1 $ +// Date: $Date: 2015/03/20 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ +module cdclib_sync2_reset_type_w_gate + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire data_in, // data in + output wire data_out // data out + ); + + + reg data_in_sync; + reg data_in_sync2; + + always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + data_in_sync <= 1'b0; + data_in_sync2 <= 1'b0; + end + else begin + data_in_sync <= data_in; + data_in_sync2 <= data_in_sync; + end + end + + assign data_out = data_in_sync2; + +endmodule // cdclib_sync2_reset_type_w_gate + diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_sync2_set_type_l_gate.v b/maib_rtl/cdclib/rtl/block_function/cdclib_sync2_set_type_l_gate.v new file mode 100644 index 0000000..bb17945 --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_sync2_set_type_l_gate.v @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_sync2_set_type_l_gate.v.rca $ +// Revision: $Revision: #1 $ +// Date: $Date: 2015/03/20 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ +module cdclib_sync2_set_type_l_gate + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire data_in, // data in + output wire data_out // data out + ); + + + reg data_in_sync; + reg data_in_sync2; + + always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + data_in_sync <= 1'b1; + data_in_sync2 <= 1'b1; + end + else begin + data_in_sync <= data_in; + data_in_sync2 <= data_in_sync; + end + end + + assign data_out = data_in_sync2; + +endmodule // cdclib_sync2_set_type_l_gate + diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_sync2_set_type_n_gate.v b/maib_rtl/cdclib/rtl/block_function/cdclib_sync2_set_type_n_gate.v new file mode 100644 index 0000000..a8d19f8 --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_sync2_set_type_n_gate.v @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_sync2_set_type_n_gate.v.rca $ +// Revision: $Revision: #1 $ +// Date: $Date: 2015/03/20 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ +module cdclib_sync2_set_type_n_gate + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire data_in, // data in + output wire data_out // data out + ); + + + reg data_in_sync; + reg data_in_sync2; + + always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + data_in_sync <= 1'b1; + data_in_sync2 <= 1'b1; + end + else begin + data_in_sync <= data_in; + data_in_sync2 <= data_in_sync; + end + end + + assign data_out = data_in_sync2; + +endmodule // cdclib_sync2_set_type_n_gate + diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_sync2_set_type_w_gate.v b/maib_rtl/cdclib/rtl/block_function/cdclib_sync2_set_type_w_gate.v new file mode 100644 index 0000000..5949a9b --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_sync2_set_type_w_gate.v @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_sync2_set_type_w_gate.v.rca $ +// Revision: $Revision: #1 $ +// Date: $Date: 2015/03/20 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ +module cdclib_sync2_set_type_w_gate + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire data_in, // data in + output wire data_out // data out + ); + + + reg data_in_sync; + reg data_in_sync2; + + always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + data_in_sync <= 1'b1; + data_in_sync2 <= 1'b1; + end + else begin + data_in_sync <= data_in; + data_in_sync2 <= data_in_sync; + end + end + + assign data_out = data_in_sync2; + +endmodule // cdclib_sync2_set_type_w_gate + diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_sync4_reset_type_l_gate.v b/maib_rtl/cdclib/rtl/block_function/cdclib_sync4_reset_type_l_gate.v new file mode 100644 index 0000000..1a0976d --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_sync4_reset_type_l_gate.v @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_sync4_reset_type_l_gate.v.rca $ +// Revision: $Revision: #1 $ +// Date: $Date: 2015/03/20 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ +module cdclib_sync4_reset_type_l_gate + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire data_in, // data in + output wire data_out // data out + ); + + + reg data_in_sync; + reg data_in_sync2; + reg data_in_sync3; + reg data_in_sync4; + + always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + data_in_sync <= 1'b0; + data_in_sync2 <= 1'b0; + data_in_sync3 <= 1'b0; + data_in_sync4 <= 1'b0; + end + else begin + data_in_sync <= data_in; + data_in_sync2 <= data_in_sync; + data_in_sync3 <= data_in_sync2; + data_in_sync4 <= data_in_sync3; + end + end + + assign data_out = data_in_sync4; + +endmodule // cdclib_sync4_reset_type_l_gate + diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_sync4_reset_type_w_gate.v b/maib_rtl/cdclib/rtl/block_function/cdclib_sync4_reset_type_w_gate.v new file mode 100644 index 0000000..6ee24d8 --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_sync4_reset_type_w_gate.v @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_sync4_reset_type_w_gate.v.rca $ +// Revision: $Revision: #1 $ +// Date: $Date: 2015/03/20 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ +module cdclib_sync4_reset_type_w_gate + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire data_in, // data in + output wire data_out // data out + ); + + + reg data_in_sync; + reg data_in_sync2; + reg data_in_sync3; + reg data_in_sync4; + + always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + data_in_sync <= 1'b0; + data_in_sync2 <= 1'b0; + data_in_sync3 <= 1'b0; + data_in_sync4 <= 1'b0; + end + else begin + data_in_sync <= data_in; + data_in_sync2 <= data_in_sync; + data_in_sync3 <= data_in_sync2; + data_in_sync4 <= data_in_sync3; + end + end + + assign data_out = data_in_sync4; + +endmodule // cdclib_sync4_reset_type_w_gate + diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_sync4_set_type_l_gate.v b/maib_rtl/cdclib/rtl/block_function/cdclib_sync4_set_type_l_gate.v new file mode 100644 index 0000000..9a47e02 --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_sync4_set_type_l_gate.v @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_sync4_set_type_l_gate.v.rca $ +// Revision: $Revision: #1 $ +// Date: $Date: 2015/03/20 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ +module cdclib_sync4_set_type_l_gate + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire data_in, // data in + output wire data_out // data out + ); + + + reg data_in_sync; + reg data_in_sync2; + reg data_in_sync3; + reg data_in_sync4; + + always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + data_in_sync <= 1'b1; + data_in_sync2 <= 1'b1; + data_in_sync3 <= 1'b1; + data_in_sync4 <= 1'b1; + end + else begin + data_in_sync <= data_in; + data_in_sync2 <= data_in_sync; + data_in_sync3 <= data_in_sync2; + data_in_sync4 <= data_in_sync3; + end + end + + assign data_out = data_in_sync4; + +endmodule // cdclib_sync4_set_type_l_gate + diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_sync4_set_type_w_gate.v b/maib_rtl/cdclib/rtl/block_function/cdclib_sync4_set_type_w_gate.v new file mode 100644 index 0000000..ef08a3a --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_sync4_set_type_w_gate.v @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_sync4_set_type_w_gate.v.rca $ +// Revision: $Revision: #1 $ +// Date: $Date: 2015/03/20 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ +module cdclib_sync4_set_type_w_gate + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire data_in, // data in + output wire data_out // data out + ); + + + reg data_in_sync; + reg data_in_sync2; + reg data_in_sync3; + reg data_in_sync4; + + always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + data_in_sync <= 1'b1; + data_in_sync2 <= 1'b1; + data_in_sync3 <= 1'b1; + data_in_sync4 <= 1'b1; + end + else begin + data_in_sync <= data_in; + data_in_sync2 <= data_in_sync; + data_in_sync3 <= data_in_sync2; + data_in_sync4 <= data_in_sync3; + end + end + + assign data_out = data_in_sync4; + +endmodule // cdclib_sync4_set_type_w_gate + diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_vecsync.v b/maib_rtl/cdclib/rtl/block_function/cdclib_vecsync.v new file mode 100644 index 0000000..69b4b7f --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_vecsync.v @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_vecsync.v.rca $ +// Revision: $Revision: #3 $ +// Date: $Date: 2015/03/20 $ +//----------------------------------------------------------------------------- +// Description : Parameterizable Vector Sync Module, This can only be used +// for SLOW changing vector, i.e vector should be stable at least for the +// synchronization latency. +//----------------------------------------------------------------------------- +module cdclib_vecsync + #( + parameter DWIDTH = 2, // Sync Data input + parameter SYNCSTAGE = 2, // Sync stages + parameter WR_CLK_FREQ_MHZ = 250, // Clock frequency (in MHz) + parameter RD_CLK_FREQ_MHZ = 250, // Clock frequency (in MHz) + parameter VID = 1 // 1: VID, 0: preVID + ) + ( + // Inputs + input wire wr_clk, // write clock + input wire rd_clk, // read clock + input wire wr_rst_n, // async write reset + input wire rd_rst_n, // async read reset + input wire [DWIDTH-1:0] data_in, // data in + // Outputs + output reg [DWIDTH-1:0] data_out // data out + ); + +//****************************************************************************** +// Define regs +//****************************************************************************** +reg [DWIDTH-1:0] data_in_d0; +reg req_wr_clk; +wire req_rd_clk; +wire ack_wr_clk; +wire ack_rd_clk; +reg req_rd_clk_d0; + +//****************************************************************************** +// WRITE CLOCK DOMAIN: Generate req & Store data when synchroniztion is not +// already in progress +//****************************************************************************** +always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + data_in_d0 <= {DWIDTH{1'b0}}; + req_wr_clk <= 1'b0; + end + else begin + // Store data when Write Req equals Write Ack + if (req_wr_clk == ack_wr_clk) begin + data_in_d0 <= data_in; + end + + // Generate a Req when there is change in data + if ((req_wr_clk == ack_wr_clk) & (data_in_d0 != data_in)) begin + req_wr_clk <= ~req_wr_clk; + end + end +end + +generate + +if (SYNCSTAGE == 4) begin +//****************************************************************************** +// WRITE CLOCK DOMAIN: +//****************************************************************************** +cdclib_bitsync4 +#( +.DWIDTH (1), // Sync Data input +.RESET_VAL (0), // Reset value +.CLK_FREQ_MHZ(WR_CLK_FREQ_MHZ), +.TOGGLE_TYPE (2), +.VID (VID) +) +bitsync4_u_ack_wr_clk + ( + .clk (wr_clk), + .rst_n (wr_rst_n), + .data_in (ack_rd_clk), + .data_out (ack_wr_clk) + ); + +//****************************************************************************** +// READ CLOCK DOMAIN: +//****************************************************************************** +cdclib_bitsync4 +#( +.DWIDTH (1), // Sync Data input +.RESET_VAL (0), // Reset value +.CLK_FREQ_MHZ(RD_CLK_FREQ_MHZ), +.TOGGLE_TYPE (2), +.VID (VID) +) +bitsync4_u_req_rd_clk +( + .clk (rd_clk), + .rst_n (rd_rst_n), + .data_in (req_wr_clk), + .data_out (req_rd_clk) +); +end +else begin +//****************************************************************************** +// WRITE CLOCK DOMAIN: +//****************************************************************************** +cdclib_bitsync2 +#( +.DWIDTH (1), // Sync Data input +.RESET_VAL (0), // Reset value +.CLK_FREQ_MHZ(WR_CLK_FREQ_MHZ), +.TOGGLE_TYPE (2), +.VID (VID) +) +bitsync2_u_ack_wr_clk + ( + .clk (wr_clk), + .rst_n (wr_rst_n), + .data_in (ack_rd_clk), + .data_out (ack_wr_clk) + ); + +//****************************************************************************** +// READ CLOCK DOMAIN: +//****************************************************************************** +cdclib_bitsync2 +#( +.DWIDTH (1), // Sync Data input +.RESET_VAL (0), // Reset value +.CLK_FREQ_MHZ(RD_CLK_FREQ_MHZ), +.TOGGLE_TYPE (2), +.VID (VID) +) +bitsync2_u_req_rd_clk +( + .clk (rd_clk), + .rst_n (rd_rst_n), + .data_in (req_wr_clk), + .data_out (req_rd_clk) +); +end + +endgenerate + +assign ack_rd_clk = req_rd_clk_d0; + +//****************************************************************************** +// READ CLOCK DOMAIN: +//****************************************************************************** +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + data_out <= {DWIDTH{1'b0}}; + req_rd_clk_d0 <= 1'b0; + end + else begin + req_rd_clk_d0 <= req_rd_clk; + if (req_rd_clk_d0 != req_rd_clk) begin + data_out <= data_in_d0; + end + end +end + + +endmodule // cdclib_vecsync + diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_vecsync2.v b/maib_rtl/cdclib/rtl/block_function/cdclib_vecsync2.v new file mode 100644 index 0000000..c4b08cb --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_vecsync2.v @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_vecsync2.v.rca $ +// Revision: $Revision: #3 $ +// Date: $Date: 2015/03/20 $ +//----------------------------------------------------------------------------- +// Description : 2-stage vector synchronizer +//----------------------------------------------------------------------------- +module cdclib_vecsync2 + #( + parameter DWIDTH = 2, // Sync Data input + parameter WR_CLK_FREQ_MHZ = 250, // Clock frequency (in MHz) + parameter RD_CLK_FREQ_MHZ = 250, // Clock frequency (in MHz) + parameter VID = 1 // 1: VID, 0: preVID + ) + ( + // Inputs + input wire wr_clk, // write clock + input wire rd_clk, // read clock + input wire wr_rst_n, // async write reset + input wire rd_rst_n, // async read reset + input wire [DWIDTH-1:0] data_in, // data in + // Outputs + output wire [DWIDTH-1:0] data_out // data out + ); + +// 2-stage synchronizer +localparam SYNCSTAGE = 2; + +// Vecsync module +cdclib_vecsync + #( + .DWIDTH(DWIDTH), // Sync Data input + .SYNCSTAGE(SYNCSTAGE), // Sync stages + .WR_CLK_FREQ_MHZ(WR_CLK_FREQ_MHZ), + .RD_CLK_FREQ_MHZ(RD_CLK_FREQ_MHZ), + .VID (VID) + ) cdclib_vecsync2 + ( + // Inputs + .wr_clk(wr_clk), // write clock + .rd_clk(rd_clk), // read clock + .wr_rst_n(wr_rst_n), // async write reset + .rd_rst_n(rd_rst_n), // async read reset + .data_in(data_in), // data in + // Outputs + .data_out(data_out) // data out + ); + +endmodule // cdclib_vecsync2 + diff --git a/maib_rtl/cdclib/rtl/block_function/cdclib_vecsync4.v b/maib_rtl/cdclib/rtl/block_function/cdclib_vecsync4.v new file mode 100644 index 0000000..59b5607 --- /dev/null +++ b/maib_rtl/cdclib/rtl/block_function/cdclib_vecsync4.v @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2009 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// File: $RCSfile: cdclib_vecsync4.v.rca $ +// Revision: $Revision: #3 $ +// Date: $Date: 2015/03/20 $ +//----------------------------------------------------------------------------- +// Description : 4-stage vector synchronizer +//----------------------------------------------------------------------------- +module cdclib_vecsync4 + #( + parameter DWIDTH = 2, // Sync Data input + parameter WR_CLK_FREQ_MHZ = 1000, // Clock frequency (in MHz) + parameter RD_CLK_FREQ_MHZ = 1000, // Clock frequency (in MHz) + parameter VID = 1 // 1: VID, 0: preVID + ) + ( + // Inputs + input wire wr_clk, // write clock + input wire rd_clk, // read clock + input wire wr_rst_n, // async write reset + input wire rd_rst_n, // async read reset + input wire [DWIDTH-1:0] data_in, // data in + // Outputs + output wire [DWIDTH-1:0] data_out // data out + ); + +// 3-stage synchronizer +localparam SYNCSTAGE = 4; + +// Vecsync module +cdclib_vecsync + #( + .DWIDTH(DWIDTH), // Sync Data input + .SYNCSTAGE(SYNCSTAGE), // Sync stages + .WR_CLK_FREQ_MHZ(WR_CLK_FREQ_MHZ), + .RD_CLK_FREQ_MHZ(RD_CLK_FREQ_MHZ), + .VID (VID) + ) cdclib_vecsync4 + ( + // Inputs + .wr_clk(wr_clk), // write clock + .rd_clk(rd_clk), // read clock + .wr_rst_n(wr_rst_n), // async write reset + .rd_rst_n(rd_rst_n), // async read reset + .data_in(data_in), // data in + // Outputs + .data_out(data_out) // data out + ); + +endmodule // cdclib_vecsync4 + diff --git a/maib_rtl/cfg_shared/rtl/block_function/cfg_bead.v b/maib_rtl/cfg_shared/rtl/block_function/cfg_bead.v new file mode 100644 index 0000000..696f8ac --- /dev/null +++ b/maib_rtl/cfg_shared/rtl/block_function/cfg_bead.v @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module cfg_bead + ( + // Bead interface + input wire scan_clk_in, + input wire scan_data_in, + input wire capture_in, + input wire update_in, + input wire clr_n_in, + + // Bead interface + output wire scan_data_out, + + // BEAD_CFG_IF + output wire bead_val + ); + + wire bead_val_int; + wire scan_reg_in_int; + wire bead_in_int; + + assign bead_val_int = bead_val | clr_n_in; + assign scan_reg_in_int = (capture_in)? bead_val_int : scan_data_in; + assign bead_in_int = scan_data_out & clr_n_in; + + // Non resettablei & non scannable reg +// always @(posedge scan_clk_in) +// scan_data_out <= scan_reg_in_int; + cfg_cmn_non_scan_reg bead_ns_reg ( + .din (scan_reg_in_int), + .clk (scan_clk_in), + .dout (scan_data_out) + ); + + // Non resettable latch +// always @(*) +// if (update_in) +// bead_val <= bead_in_int; + cfg_cmn_latch bead_latch ( + .din (bead_in_int), + .clk (update_in), + .dout(bead_val) + ); + +endmodule // cfg_bead diff --git a/maib_rtl/cfg_shared/rtl/block_function/cfg_bead_bus.v b/maib_rtl/cfg_shared/rtl/block_function/cfg_bead_bus.v new file mode 100644 index 0000000..cc6d7de --- /dev/null +++ b/maib_rtl/cfg_shared/rtl/block_function/cfg_bead_bus.v @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module cfg_bead_bus + #( + parameter FW_BEAD_LENGTH = 8, + parameter RV_BEAD_LENGTH = 8, + parameter FW_NEG_REG = 1, + parameter RV_NEG_REG = 0, + parameter BBUS_CHAIN = 0, + parameter BBUS_BINDEX = 0, + parameter SECTOR_ROW = 0, + parameter SECTOR_COL = 0 + ) + ( + // Bead interface on forward path + input wire scan_clk_in_fw, + input wire scan_data_in_fw, + input wire capture_in_fw, + input wire update_in_fw, + input wire clr_n_in_fw, + + // Bead interface on reverse path + input wire scan_clk_in_rv, + input wire scan_data_in_rv, + input wire capture_in_rv, + input wire update_in_rv, + input wire clr_n_in_rv, + + // Bead interface on forward path + output wire scan_clk_out_fw, + output wire scan_data_out_fw, + output wire capture_out_fw, + output wire update_out_fw, + output wire clr_n_out_fw, + + // Bead interface on reverse path + output wire scan_clk_out_rv, + output wire scan_data_out_rv, + output wire capture_out_rv, + output wire update_out_rv, + output wire clr_n_out_rv, + + // BEAD_CFG_IF on forward path + output wire [FW_BEAD_LENGTH-1:0] bead_val_fw, + output wire [RV_BEAD_LENGTH:0] bead_val_rv + ); + + wire [FW_BEAD_LENGTH:0] scan_data_int_fw; + wire [RV_BEAD_LENGTH:0] scan_data_int_rv; + + reg scan_data_out_neg_fw; + reg scan_data_out_neg_rv; + + // Backdoor access + `ifdef TOP_SIM + `include "cfg_bead_backdoor_access.vh" + `endif + + generate + genvar h; + if (FW_BEAD_LENGTH >= 1) + begin: assign_fw + assign scan_clk_out_fw = scan_clk_in_fw; + assign capture_out_fw = capture_in_fw; + assign update_out_fw = update_in_fw; + assign clr_n_out_fw = clr_n_in_fw; + + assign scan_data_int_fw[0] = scan_data_in_fw; + end + + for (h=0; h= 1) + begin: assign_rv + assign scan_clk_out_rv = scan_clk_in_rv; + assign capture_out_rv = capture_in_rv; + assign update_out_rv = update_in_rv; + assign clr_n_out_rv = clr_n_in_rv; + + assign scan_data_int_rv[0] = scan_data_in_rv; + assign bead_val_rv[RV_BEAD_LENGTH] = 1'b0; + end + else + begin: tied_off_rv + assign scan_clk_out_rv = 1'b0; + assign capture_out_rv = 1'b0; + assign update_out_rv = 1'b0; + assign clr_n_out_rv = 1'b1; + + assign scan_data_int_rv[0] = 1'b0; + assign bead_val_rv[0] = 1'b0; + end + endgenerate + + generate + genvar i; + for (i=0; i 1) + begin: CHAIN_1 + if (NUM_ATPG_SCAN_CHAIN == 2) + for (j=NUM_REG_PER_CHAIN+1; j < NUM_CTRL_REGS; j=j+1) + begin: chain_connection_1 + assign chain_in[j] = chain_out[j-1]; + end + else // More than 2 + for (j=NUM_REG_PER_CHAIN+1; j < 2*NUM_REG_PER_CHAIN; j=j+1) + begin: chain_connection_1 + assign chain_in[j] = chain_out[j-1]; + end + + assign chain_in[NUM_REG_PER_CHAIN] = csr_chain_in[1]; + assign csr_chain_out[0] = chain_out[NUM_REG_PER_CHAIN-1]; + end + +// Chain 3 +if (NUM_ATPG_SCAN_CHAIN > 2) + begin: CHAIN_2 + if (NUM_ATPG_SCAN_CHAIN == 3) + for (j=2*NUM_REG_PER_CHAIN+1; j < NUM_CTRL_REGS; j=j+1) + begin: chain_connection_2 + assign chain_in[j] = chain_out[j-1]; + end + else // More than 3 + for (j=2*NUM_REG_PER_CHAIN+1; j < 3*NUM_REG_PER_CHAIN; j=j+1) + begin: chain_connection_2 + assign chain_in[j] = chain_out[j-1]; + end + + assign chain_in[2*NUM_REG_PER_CHAIN] = csr_chain_in[2]; + assign csr_chain_out[1] = chain_out[2*NUM_REG_PER_CHAIN-1]; + end + +// Chain 4 +if (NUM_ATPG_SCAN_CHAIN > 3) + begin: CHAIN_3 + if (NUM_ATPG_SCAN_CHAIN == 4) + for (j=3*NUM_REG_PER_CHAIN+1; j < NUM_CTRL_REGS; j=j+1) + begin: chain_connection_3 + assign chain_in[j] = chain_out[j-1]; + end + else // More than 4 + for (j=3*NUM_REG_PER_CHAIN+1; j < 4*NUM_REG_PER_CHAIN; j=j+1) + begin: chain_connection_3 + assign chain_in[j] = chain_out[j-1]; + end + + assign chain_in[3*NUM_REG_PER_CHAIN] = csr_chain_in[3]; + assign csr_chain_out[2] = chain_out[3*NUM_REG_PER_CHAIN-1]; + end + +endgenerate + +endmodule + diff --git a/maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_interface_top.v b/maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_interface_top.v new file mode 100644 index 0000000..2e7e310 --- /dev/null +++ b/maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_interface_top.v @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2012 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//************************************************************************** +// Description: +// +// There are 2 interfaces to access the DPRIO registers: Avalon-MM and CSR +//************************************************************************** +module cfg_dprio_ctrl_stat_interface_top +#( + parameter DATA_WIDTH = 16, // Data width + parameter ADDR_WIDTH = 10, // Address width + parameter NUM_CHNL = 18, // Number of DPRIO blocks interfacing with this interface + parameter CSR_OUT_NEG_FF_EN = 1 // Enable negative FF on csr_out + ) +( +// POR hard reset +input wire npor, // NPOR from CB +input wire plniotri, // PLNIOTRI from CB +input wire entest, // ENTEST from CB + +// Scan interface +input wire scan_mode_n, // active low scan mode enable +input wire scan_shift_n, // active low scan shift +input wire refclk_dig, // scan clock + +output wire scan_mode_n_chnl, // active low scan mode enable for top channel +output wire scan_shift_n_chnl, // active low scan mode enable for top channel + +// CSR interface +input wire csr_rst_n, // CSR reset +input wire csr_clk, // CSR clock +input wire csr_in, // Serial CSR input +input wire csr_en, // CSR enable + +output wire csr_out, // Serial CSR output + +// internal CSR interface to channels +input wire csr_out_chnl, // CSR output from top channel + +output wire csr_en_chnl, // CSR enable to channels +output wire csr_clk_chnl, // CSR clock to channels +output wire csr_in_chnl, // CSR input to top channel + +// CSR test mux interface +input wire csr_cbdin, // CSR configuration mode data input +input wire csr_tcsrin, // CSR test/scan mode data input +input wire csr_din, // Previous CSR bit data output +input wire csr_seg, // VSS for Seg0, VCC for seg[31:1] +input wire csr_entest, // enable test control input +input wire csr_enscan, // enable scan control input +input wire csr_tverify, // test verify control input +input wire csr_load_csr, // JTAG scan mode control input +input wire csr_pipe_in, // Input to the Pipeline register to suport 200MHz + +output wire csr_dout, // CSR input MUX Data output +output wire csr_pipe_out, // Pipelined register data output +output wire csr_test_mode, // CSR test mode for DPRIO module + +// Control inputs to select the interface +input wire interface_sel, // Interface selection inputs + // 1'b1: select CSR interface + // 1'b0: select AVMM interface + +// Avalon-MM interface +input wire avmm_rst_n, // Avalon-MM reset +input wire avmm_clk, // Avalon-MM clock +input wire avmm_write, // Avalon-MM write enable input +input wire avmm_read, // Avalon-MM read enable input +input wire [(DATA_WIDTH/8)-1:0] avmm_byte_en, // Avalon-MM Byte enable +input wire [ADDR_WIDTH-1:0] avmm_reg_addr, // Avalon-MM address input +input wire [DATA_WIDTH-1:0] avmm_writedata, // Avalon-MM write data input + +output wire [DATA_WIDTH-1:0] avmm_readdata, // Avalon-MM read data output + +// IO interface to/from channels +input wire [NUM_CHNL-1:0] block_select, // Signal to tell the central interface to select its readdata +input wire [DATA_WIDTH*NUM_CHNL-1:0] readdata_chnl, // Read data from channels + +output wire dprio_rst_n, // Active low reset to channel +output wire dprio_clk, // Clock to channel +output wire mdio_dis_chnl, // 1'b1=CRAM is from CSR + // 1'b0=CRAM is from DPRIO register +output reg [DATA_WIDTH-1:0] writedata_chnl, // Write data to channel +output reg [ADDR_WIDTH-1:0] reg_addr_chnl, // Address to channel +output reg write_chnl, // Write enable to channel +output reg read_chnl, // Read enable to channel +output reg [(DATA_WIDTH/8)-1:0] byte_en_chnl // Byte enable to channel +); + +wire [DATA_WIDTH-1:0] readdata_chnl_int; +wire [15:0] mdio_reg_addr; +wire [15:0] mdio_write_data; +wire mdio_wr; +wire mdio_rd; +reg [DATA_WIDTH-1:0] mdio_read_data; +reg [DATA_WIDTH-1:0] mdio_read_data_reg; +integer i; + +reg avmm_write_reg; +reg avmm_read_reg; +reg [(DATA_WIDTH/8)-1:0] avmm_byte_en_reg; +reg [ADDR_WIDTH-1:0] avmm_reg_addr_reg; +reg [DATA_WIDTH-1:0] avmm_writedata_reg; + +wire csr_out_int; +reg csr_out_reg; +wire csr_out_neg_bypass; + +wire hard_rst_n; +wire interface_sel_int; + +wire csr_clk_int; +wire dprio_clk_1_mo; + +// Internet interface selection +assign interface_sel_int = interface_sel | csr_test_mode | (~csr_en); + +// CSR test mode +assign csr_test_mode = csr_entest | csr_enscan | csr_tverify | csr_load_csr; + +// Hard Reset logic +assign hard_rst_n = plniotri & ~entest & npor; + +// Scan signal distribution +assign scan_mode_n_chnl = scan_mode_n; +assign scan_shift_n_chnl = scan_shift_n; + +// Singal to the channels +// mdio_dis output assignment +assign mdio_dis_chnl = interface_sel; + +// Clock selection +//assign dprio_clk = (scan_mode_n == 1'b0) ? refclk_dig : +// (interface_sel_int == 1'b1) ? csr_clk : avmm_clk; + cfg_cmn_clk_mux dprio_clk_1_mux ( + .clk1 (csr_clk), // Select this clock when sel == 1'b1 + .clk2 (avmm_clk), // Select this clock when sel == 1'b0 + .sel (interface_sel_int), + .clk_out (dprio_clk_1_mo) + ); + + cfg_cmn_clk_mux dprio_clk_2_mux ( + .clk1 (dprio_clk_1_mo), // Select this clock when sel == 1'b1 + .clk2 (refclk_dig), // Select this clock when sel == 1'b0 + .sel (scan_mode_n), + .clk_out (dprio_clk) + ); + +//assign csr_clk_int = (scan_mode_n == 1'b0) ? refclk_dig : csr_clk; + cfg_cmn_clk_mux csr_clk_mux ( + .clk1 (csr_clk), // Select this clock when sel == 1'b1 + .clk2 (refclk_dig), // Select this clock when sel == 1'b0 + .sel (scan_mode_n), + .clk_out (csr_clk_int) + ); + +// Reset selection +assign dprio_rst_n = (scan_mode_n == 1'b0) ? avmm_rst_n : hard_rst_n; + + +// Selection of signals to the channels +always @(*) + begin + case (interface_sel) + 1'b0: // Avalon-MM interface + begin + writedata_chnl = avmm_writedata_reg; + reg_addr_chnl = avmm_reg_addr_reg; + write_chnl = avmm_write_reg; + read_chnl = avmm_read_reg; + byte_en_chnl = avmm_byte_en_reg; + end + 1'b1: // CSR interface + begin + writedata_chnl = {DATA_WIDTH{1'b0}}; + reg_addr_chnl = {ADDR_WIDTH{1'b0}}; + write_chnl = 1'b0; + read_chnl = 1'b0; + byte_en_chnl = {(DATA_WIDTH/8){1'b0}}; + end + default: // CSR + begin + writedata_chnl = {DATA_WIDTH{1'b0}}; + reg_addr_chnl = {ADDR_WIDTH{1'b0}}; + write_chnl = 1'b0; + read_chnl = 1'b0; + byte_en_chnl = {(DATA_WIDTH/8){1'b0}}; + end + endcase + end + +// Selection of read data from channels +cfg_dprio_readdata_mux +#( + .DATA_WIDTH(DATA_WIDTH), // Data width + .NUM_INPUT(NUM_CHNL) // Number of n-bit input + ) cfg_dprio_readdata_mux +( + .clk(dprio_clk), + .rst_n(dprio_rst_n), + .read(1'b1), + .sel(block_select), // 1-hot selection input + .data_in(readdata_chnl), // data input + + .data_out(readdata_chnl_int) // data output +); + +// Registering Avalon-MM interface IOs +assign avmm_readdata = readdata_chnl_int; + +always @(negedge dprio_rst_n or posedge dprio_clk) + if (dprio_rst_n == 1'b0) + begin + avmm_write_reg <= 1'b0; + avmm_read_reg <= 1'b0; + avmm_byte_en_reg <= {(DATA_WIDTH/8){1'b0}}; + avmm_reg_addr_reg <= {ADDR_WIDTH{1'b0}}; + avmm_writedata_reg <= {DATA_WIDTH{1'b0}}; + end + else + begin + avmm_write_reg <= avmm_write; + avmm_read_reg <= avmm_read; + avmm_byte_en_reg <= avmm_byte_en; + avmm_reg_addr_reg <= avmm_reg_addr; + avmm_writedata_reg <= avmm_writedata; + end + +// CSR feedthough +assign csr_en_chnl = csr_en; +assign csr_clk_chnl = csr_clk_int; + +assign csr_in_chnl = csr_in; +assign csr_out_int = csr_out_chnl; + +// Negative FF for csr_out +always @ (negedge csr_rst_n or negedge csr_clk_int) + if (csr_rst_n == 1'b0) + begin + csr_out_reg <= 1'b0; + end + else + begin + csr_out_reg <= csr_out_int; + end + +// Bypassing negative FF in scan_shift +assign csr_out_neg_bypass = (scan_shift_n == 1'b1) ? csr_out_reg : csr_out_int; + +// csr_out assignment +assign csr_out = (CSR_OUT_NEG_FF_EN == 1) ? csr_out_neg_bypass : csr_out_int; + +// CSR test mux +cfg_dprio_csr_test_mux cfg_dprio_csr_test_mux +( + .rst_n(csr_rst_n), // Active low hard reset + .clk(csr_clk_int), // Clock + .cbdin(csr_cbdin), // CSR configuration mode data input + .tcsrin(csr_tcsrin), // CSR test/scan mode data input + .csrdin(csr_din), // Previous CSR bit data output + .csr_seg(csr_seg), // VSS for Seg0(), VCC for seg[31:1] + .entest(csr_entest), // enable test control input + .enscan(csr_enscan), // enable scan control input + .tverify(csr_tverify), // test verify control input + .load_csr(csr_load_csr), // JTAG scan mode control input + .pipe_in(csr_pipe_in), // Input to the Pipeline register to suport 200MHz + .csrdout(csr_dout), // CSR input MUX Data output + .pipe_out(csr_pipe_out) // Pipelined register data output +); + +endmodule diff --git a/maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_reg_chnl.v b/maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_reg_chnl.v new file mode 100644 index 0000000..9619a67 --- /dev/null +++ b/maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_reg_chnl.v @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2012 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//***************************************************************** +// Description: +// +//***************************************************************** +module cfg_dprio_ctrl_stat_reg_chnl +#( + parameter BINDEX = 0, // Base index + parameter SEGMENT = 0, // CSR segment + parameter DATA_WIDTH = 16, // Data width + parameter ADDR_WIDTH = 10, // Address width + parameter NUM_CTRL_REGS = 18, // Number of n-bit control registers + parameter NUM_STATUS_REGS = 1, // Number of n-bit status registers + parameter BYPASS_STAT_SYNC = 0, // Parameter to bypass the Synchronization SM in case of individual status bits + parameter NUM_ATPG_SCAN_CHAIN = 1, // Number of ATPG scan chains + parameter CLK_FREQ_MHZ = 250, // Clock freq in MHz + parameter SECTOR_ROW = 0, + parameter SECTOR_COL = 0, + parameter TOGGLE_TYPE = 1, + parameter VID = 1 + ) +( +// Avalon-MM interface +input wire rst_n, // reset +input wire clk, // clock +input wire write, // write enable input +input wire read, // read enable input +input wire [ADDR_WIDTH-1:0] reg_addr, // address input +input wire [ADDR_WIDTH-1:0] base_addr, // base address value from CSR +input wire [DATA_WIDTH-1:0] writedata, // write data input +input wire hold_csr, // Hold CSR value +input wire gated_cram, // Gating CRAM output +input wire dprio_sel, // 1'b1=choose csr_in + // 1'b0=choose dprio_in +input wire pma_csr_test_dis, // Disable PMA CSR test +input wire [(DATA_WIDTH/8)-1:0] byte_en, // Byte enable +input wire broadcast_en, // Broadcast enable (controlled by extra CSR bit) +input wire [DATA_WIDTH*NUM_STATUS_REGS-1:0] user_datain, // status from custom logic +input wire [NUM_STATUS_REGS-1:0] write_en_ack, // write data acknowlege from user logic +input wire [NUM_ATPG_SCAN_CHAIN-1:0] csr_chain_in, // ATPG scan input + +output wire [NUM_ATPG_SCAN_CHAIN-1:0] csr_chain_out, // ATPG scan output +output wire [NUM_STATUS_REGS-1:0] write_en, // write data enable to user logic +output wire [DATA_WIDTH-1:0] readdata, // Read data to route back to central Avalon-MM +output wire [DATA_WIDTH*NUM_CTRL_REGS-1:0] user_dataout, // CRAM connecting to custom logic +output reg block_select // Signal to tell the central interface to select its readdata +); + +wire [ADDR_WIDTH*NUM_CTRL_REGS-1:0] ctrl_target_addr; +wire [ADDR_WIDTH*NUM_STATUS_REGS-1:0] stat_target_addr; +wire [DATA_WIDTH*NUM_STATUS_REGS-1:0] user_readdata; + +reg read_reg; +reg [ADDR_WIDTH-1:0] reg_addr_reg; + +wire [NUM_CTRL_REGS+NUM_STATUS_REGS-1:0] readdata_sel; + +// Target address for control registers +generate + genvar i; + for (i=0; i < NUM_CTRL_REGS; i=i+1) + begin: ctrl_target_address + assign ctrl_target_addr[ADDR_WIDTH*(i+1)-1:ADDR_WIDTH*i] = base_addr + i; + end +endgenerate + +// Target address for status registers +generate + genvar j; + for (j=0; j < NUM_STATUS_REGS; j=j+1) + begin: status_target_address + assign stat_target_addr[ADDR_WIDTH*(j+1)-1:ADDR_WIDTH*j] = base_addr + NUM_CTRL_REGS + j; + end +endgenerate + +// registering address and read signal +always @ (negedge rst_n or posedge clk) +begin + if (rst_n == 1'b0) + begin + read_reg <= 1'b0; + reg_addr_reg <= {ADDR_WIDTH{1'b0}}; + end + else + begin + read_reg <= read; + reg_addr_reg <= reg_addr; + end +end + +// Control Registers +cfg_dprio_ctrl_reg_nregs + #( + .BINDEX(BINDEX), + .SEGMENT(SEGMENT), + .DATA_WIDTH(DATA_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .NUM_CTRL_REGS(NUM_CTRL_REGS), + .NUM_ATPG_SCAN_CHAIN(NUM_ATPG_SCAN_CHAIN), + .SECTOR_ROW(SECTOR_ROW), + .SECTOR_COL(SECTOR_COL) + ) ctrl_reg_nregs + (.clk (clk), + .write (write), + .reg_addr (reg_addr), + .target_addr (ctrl_target_addr), + .writedata (writedata), + .hold_csr (hold_csr), + .gated_cram (gated_cram), + .dprio_sel (dprio_sel), + .pma_csr_test_dis (pma_csr_test_dis), + .byte_en (byte_en), + .broadcast_en (broadcast_en), + .csr_chain_in (csr_chain_in), + .csr_chain_out(csr_chain_out), + .user_dataout (user_dataout) + ); + +// Status Registers +cfg_dprio_status_reg_nregs +#( + .DATA_WIDTH(DATA_WIDTH), // Data width + .ADDR_WIDTH(ADDR_WIDTH), // Address width + .NUM_STATUS_REGS(NUM_STATUS_REGS), // Number of n-bit status registers + .BYPASS_STAT_SYNC(BYPASS_STAT_SYNC), // Parameter to bypass the Synchronization SM in case of individual status bits + .CLK_FREQ_MHZ(CLK_FREQ_MHZ), + .TOGGLE_TYPE(TOGGLE_TYPE), + .VID(VID) + ) status_reg_nregs +(.rst_n (rst_n), // reset + .clk(clk), // clock + .read(read), // read enable input + .reg_addr(reg_addr), // address input + .target_addr(stat_target_addr), // hardwired address value + .user_datain(user_datain), // status from custom logic + .write_en_ack(write_en_ack), // write data acknowlege from user logic + .write_en(write_en), // write data enable to user logic + .user_readdata(user_readdata) // status register outputs +); + +// 1-hot muxing +generate + genvar k; + for (k=0; k < NUM_CTRL_REGS; k=k+1) + begin: ctrl_select + //assign readdata_sel[k] = (reg_addr_reg == ctrl_target_addr[ADDR_WIDTH*(k+1)-1:ADDR_WIDTH*k]) ? 1'b1 : 1'b0; + cfg_dprio_readdata_sel + #( + .ADDR_WIDTH(ADDR_WIDTH) // Address width + ) ctrl_select_i + ( + .reg_addr (reg_addr_reg), // address input + .target_addr (ctrl_target_addr[ADDR_WIDTH*(k+1)-1:ADDR_WIDTH*k]), // target address input + .readdata_sel (readdata_sel[k]) // read select output + ); + end +endgenerate + +generate + genvar m; + for (m=0; m < NUM_STATUS_REGS; m=m+1) + begin: status_select + //assign readdata_sel[NUM_CTRL_REGS+m] = (reg_addr_reg == stat_target_addr[ADDR_WIDTH*(m+1)-1:ADDR_WIDTH*m]) ? 1'b1 : 1'b0; + cfg_dprio_readdata_sel + #( + .ADDR_WIDTH(ADDR_WIDTH) // Address width + ) status_select_i + ( + .reg_addr (reg_addr_reg), // address input + .target_addr (stat_target_addr[ADDR_WIDTH*(m+1)-1:ADDR_WIDTH*m]), // target address input + .readdata_sel (readdata_sel[NUM_CTRL_REGS+m]) // read select output + ); + end +endgenerate + +cfg_dprio_readdata_mux +#( + .DATA_WIDTH(DATA_WIDTH), // Data width + .NUM_INPUT(NUM_CTRL_REGS+NUM_STATUS_REGS) // Number of n-bit input + ) cfg_dprio_readdata_mux +( + .clk(clk), + .rst_n(rst_n), + .read(read_reg), + .sel(readdata_sel), // 1-hot selection input + .data_in({user_readdata,user_dataout}), // data input + + .data_out(readdata) // data output +); + +// Block select logic to indicate if read address matches one of the CONTROL/STATUS address +always @ (negedge rst_n or posedge clk) + if (rst_n == 1'b0) + begin + block_select <= 1'b0; + end + else + begin + if (read_reg == 1'b1) + begin + block_select <= |readdata_sel; + end + else + begin + block_select <= 1'b0; + end + end + +endmodule diff --git a/maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_reg_top.v b/maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_reg_top.v new file mode 100644 index 0000000..acaa429 --- /dev/null +++ b/maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_reg_top.v @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2012 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//***************************************************************** +// Description: +// +//***************************************************************** +module cfg_dprio_ctrl_stat_reg_top +#( + parameter BINDEX = 0, // Base index + parameter SEGMENT = 0, // CSR segment + parameter DATA_WIDTH = 16, // Data width + parameter ADDR_WIDTH = 10, // Address width + parameter NUM_CTRL_REGS = 20, // Number of n-bit control registers + parameter NUM_EXTRA_CSR_REG = 1, // Number of extra 16-bit register for CSR + parameter NUM_STATUS_REGS = 5, // Number of n-bit status registers + parameter CSR_OUT_NEG_FF_EN = 0, // Enable negative FF on csr_out + parameter BYPASS_STAT_SYNC = 0, // Parameter to bypass the Synchronization SM in case of individual status bits + parameter USE_AVMM_INTF = 0, // Specify if AVMM Interface is used. Bypass clock selection if using AVMM Interface. + parameter FORCE_INTER_SEL_CVP_EN = 0, // 1: Enable logic to force interface_sel in CVP mode + parameter NUM_ATPG_SCAN_CHAIN = 1, // Number of ATPG scan chains + parameter NUM_CSR_ATPG_SCAN_CHAIN = 0, // Set this to 2 to enable 2 separate scan chain for CSR; + // ELSE, SET THIS TO 0 to connect the last csr chain from DPRIO to CSR. + // DEFAULT IS 0, REUSE NF DESIGN! + parameter DIS_CVP_CLK_FREQ_MHZ = 250, // Dis cvp clock freq in MHz + parameter STAT_REG_CLK_FREQ_MHZ = 250, // Status register clock freq in MHz + parameter SECTOR_ROW = 0, + parameter SECTOR_COL = 0, + parameter DIS_CVP_TOGGLE_TYPE = 1, + parameter DIS_CVP_VID = 1, + parameter STAT_REG_TOGGLE_TYPE = 1, + parameter STAT_REG_VID = 1 + ) +( +// Scan interface +input wire scan_mode_n, // active low scan mode enable +input wire scan_shift_n, // active low scan shift + +// CSR interface +input wire csr_clk, // CSR clock +input wire csr_in, // Serial CSR input +input wire csr_en, // CSR enable +//input wire [NUM_ATPG_SCAN_CHAIN-1:0] atpg_scan_in, // ATPG scan input +input wire [NUM_ATPG_SCAN_CHAIN + NUM_CSR_ATPG_SCAN_CHAIN - 1 : 0] atpg_scan_in, // ATPG scan input + +//output wire [NUM_ATPG_SCAN_CHAIN-1:0] atpg_scan_out, // ATPG scan output +output wire [NUM_ATPG_SCAN_CHAIN + NUM_CSR_ATPG_SCAN_CHAIN - 1 : 0] atpg_scan_out, // ATPG scan output + +output wire csr_out, // Serial CSR output +output wire [DATA_WIDTH*NUM_EXTRA_CSR_REG-1:0] extra_csr, // Extra CSR output + // Only used bits not currently used internally (extra_csr[15:0]) +// DPRIO interface +input wire dprio_rst_n, // DPRIO reset +input wire dprio_clk, // DPRIO clock +input wire write, // write enable input +input wire read, // read enable input +input wire [(DATA_WIDTH/8)-1:0] byte_en, // Byte enable +input wire [ADDR_WIDTH-1:0] reg_addr, // address input +input wire [DATA_WIDTH-1:0] writedata, // write data input +input wire csr_test_mode, // CSR test mode from CSR test mux +input wire mdio_dis, // 1'b1=output CRAM + // 1'b0=output MDIO control register +input wire pma_csr_test_dis, // Disable PMA CSR test + +output wire [DATA_WIDTH-1:0] readdata, // Read data to route back to central Avalon-MM +output wire block_select, // Signal to tell the central interface to select its readdata + +// control and status interface for custom logic +input wire [DATA_WIDTH*NUM_STATUS_REGS-1:0] user_datain, // status from custom logic +input wire [NUM_STATUS_REGS-1:0] write_en_ack, // write data acknowlege from user logic + +output wire [NUM_STATUS_REGS-1:0] write_en, // write data enable to user logic +output wire [DATA_WIDTH*NUM_CTRL_REGS-1:0] user_dataout // CRAM connecting to custom logic +); + +localparam TOTAL_ATPG_SCAN_CHAIN = NUM_ATPG_SCAN_CHAIN + NUM_CSR_ATPG_SCAN_CHAIN; +localparam NUM_CSR_REG_PER_CHAIN = NUM_EXTRA_CSR_REG / NUM_CSR_ATPG_SCAN_CHAIN; +localparam TOTAL_CSR_REG_PER_CHAIN = NUM_CSR_REG_PER_CHAIN * DATA_WIDTH; + +wire [DATA_WIDTH*NUM_STATUS_REGS-1:0] user_datain_int; +wire [NUM_STATUS_REGS-1:0] write_en_ack_int; // write data acknowlege from user logic +wire csr_int; // CSR in +wire [ADDR_WIDTH-1:0] base_addr; // base address value from CSR +wire mdio_dis_int; +wire mdio_dis_int_1; +wire power_iso_en_csr_ctrl; +wire dprio_broadcast_en_csr_ctrl; +wire force_inter_sel_csr_ctrl; +wire cvp_inter_sel_csr_ctrl; +wire hold_csr; +wire gated_cram; +wire dprio_clk_int; +wire dprio_clk_int_sel; +wire interface_sel_int; +wire [NUM_ATPG_SCAN_CHAIN - 1 : 0] csr_chain_out_int; // ATPG scan output +wire [TOTAL_ATPG_SCAN_CHAIN - 1 : 0] csr_chain_out; // ATPG scan output +wire [TOTAL_ATPG_SCAN_CHAIN - 1 : 0] csr_chain_in; // ATPG scan input +wire extra_csr_in; +wire extra_csr_out; +wire csr_clk_int; +wire csr_clk_int_sel; + +// Internet interface selection +assign interface_sel_int = mdio_dis_int | csr_test_mode | (~csr_en); + +// Clock selection +//assign dprio_clk_int_sel = (scan_mode_n == 1'b0) ? dprio_clk: +// (interface_sel_int == 1'b1) ? csr_clk : dprio_clk; + cfg_cmn_clk_mux dprio_clk_mux ( + .clk1 (csr_clk), // Select this clock when sel == 1'b1 + .clk2 (dprio_clk), // Select this clock when sel == 1'b0 + .sel (scan_mode_n & interface_sel_int), + .clk_out (dprio_clk_int_sel) + ); + +//assign csr_clk_int_sel = (scan_mode_n == 1'b0) ? dprio_clk : csr_clk; + cfg_cmn_clk_mux csr_clk_mux ( + .clk1 (csr_clk), // Select this clock when sel == 1'b1 + .clk2 (dprio_clk), // Select this clock when sel == 1'b0 + .sel (scan_mode_n), + .clk_out (csr_clk_int_sel) + ); + +// Bypass clock selecton if using common AVMM Interface. Simlar clock selection existed there +assign dprio_clk_int = (USE_AVMM_INTF == 1) ? dprio_clk : dprio_clk_int_sel; +assign csr_clk_int = (USE_AVMM_INTF == 1) ? csr_clk : csr_clk_int_sel; + + +// Control signal to hold CSR value +assign hold_csr = csr_en & (~csr_test_mode); + +// Control signal to gate CRAM output +assign gated_cram = csr_en & scan_shift_n; + +// Base address for DPRIO +assign base_addr = extra_csr[ADDR_WIDTH-1:0]; + +// Extra CSR control for power ISO and broadcasting +assign power_iso_en_csr_ctrl = extra_csr[15]; +assign dprio_broadcast_en_csr_ctrl = extra_csr[14]; +assign force_inter_sel_csr_ctrl = extra_csr[13]; +assign cvp_inter_sel_csr_ctrl = extra_csr[12]; + +// Forcing mdio_dis using extra CSR +assign mdio_dis_int = (force_inter_sel_csr_ctrl == 1'b1) ? 1'b1 : mdio_dis_int_1; + +// Power isolation for user_datain +assign user_datain_int = (csr_en && !power_iso_en_csr_ctrl) ? user_datain : {(DATA_WIDTH*NUM_STATUS_REGS){1'b0}}; +assign write_en_ack_int= (csr_en && !power_iso_en_csr_ctrl) ? write_en_ack : {NUM_STATUS_REGS{1'b0}}; + +generate + if (FORCE_INTER_SEL_CVP_EN == 1) + begin: ENABLE_CVP_FORCE_LOGIC + // CVP enable to control the mdio_dis + cfg_dprio_dis_ctrl_cvp +#( + .CLK_FREQ_MHZ(DIS_CVP_CLK_FREQ_MHZ), + .TOGGLE_TYPE(DIS_CVP_TOGGLE_TYPE), + .VID(DIS_CVP_VID) + ) + cfg_dprio_dis_ctrl_cvp + ( + .rst_n (csr_en), // reset + .clk (dprio_clk_int), // clock + .dprio_dis_in (mdio_dis), // dprio_dis in + .csr_cvp_en (cvp_inter_sel_csr_ctrl), // CSR enable + .dprio_dis_out(mdio_dis_int_1) // dprio_dis out + ); + end + else + begin: DISABLE_CVP_FORCE_LOGIC + assign mdio_dis_int_1 = mdio_dis; + end +endgenerate + +// DPRIO register module +cfg_dprio_ctrl_stat_reg_chnl +#( + .BINDEX(BINDEX), // Base index + .SEGMENT(SEGMENT), // CSR segment + .DATA_WIDTH(DATA_WIDTH), // Data width + .ADDR_WIDTH(ADDR_WIDTH), // Address width + .NUM_CTRL_REGS(NUM_CTRL_REGS), // Number of n-bit control registers + .NUM_STATUS_REGS(NUM_STATUS_REGS), // Number of n-bit status registers + .BYPASS_STAT_SYNC(BYPASS_STAT_SYNC), // Parameter to bypass the Synchronization SM in case of individual status bits + .NUM_ATPG_SCAN_CHAIN(NUM_ATPG_SCAN_CHAIN), // Number of ATPG scan chains + .CLK_FREQ_MHZ(STAT_REG_CLK_FREQ_MHZ), + .SECTOR_ROW(SECTOR_ROW), + .SECTOR_COL(SECTOR_COL), + .TOGGLE_TYPE(STAT_REG_TOGGLE_TYPE), + .VID(STAT_REG_VID) + ) ctrl_stat_reg_chnl +( + .rst_n(dprio_rst_n), // DPRIO reset + .clk(dprio_clk_int), // clock + .write(write), // write enable input + .read(read), // read enable input + .reg_addr(reg_addr), // address input + .base_addr(base_addr), // base address value from CSR + .writedata(writedata), // write data input + //.csr_in(csr_in), // CSR in + .hold_csr(hold_csr), // Hold CSR value + .gated_cram(gated_cram), // Gating CRAM output + .dprio_sel(interface_sel_int), // 1'b1=select CSR interface + // 1'b0=select AVMM interface + .pma_csr_test_dis(pma_csr_test_dis), // Disable PMA CSR test + .byte_en(byte_en), // Byte enable + .broadcast_en(dprio_broadcast_en_csr_ctrl), // Broadcast enable (controlled by extra CSR bit) + .user_datain(user_datain_int), // status from custom logic + .write_en_ack(write_en_ack_int), // write data acknowlege from user logic + .csr_chain_in(csr_chain_in[NUM_ATPG_SCAN_CHAIN-1:0]), // ATPG scan input + .csr_chain_out(csr_chain_out_int[NUM_ATPG_SCAN_CHAIN-1:0]), // ATPG scan output + .write_en(write_en), // write data enable to user logic + .readdata(readdata), // Read data to route back to central Avalon-MM + .user_dataout(user_dataout), // CRAM connecting to custom logic + //.csr_out(csr_int), // serial CSR output + .block_select(block_select) // Block select +); + +// extra CSR register module +//cfg_dprio_csr_reg_nregs +//#( +// .DATA_WIDTH(DATA_WIDTH), // Data width +// .NUM_EXTRA_CSR_REG(NUM_EXTRA_CSR_REG), // Number of extra 16-bit register for CSR +// .CSR_OUT_NEG_FF_EN(CSR_OUT_NEG_FF_EN) // Enable negative FF on csr_out +// ) csr_reg_nregs +//( +// .clk(csr_clk_int), // clock +// .csr_in(extra_csr_in), // serial CSR in +// .csr_en(csr_en), // CSR enable +// .scan_shift_n(scan_shift_n), // active low scan shift + +// .csr_reg(extra_csr), // CRAM connecting to custom logic +// .csr_out(extra_csr_out) // serial CSR output +//); + +generate + genvar j; + if (NUM_CSR_ATPG_SCAN_CHAIN == 0) + begin: single_csr_chain + cfg_dprio_csr_reg_nregs + #( + .BINDEX (BINDEX + DATA_WIDTH * NUM_CTRL_REGS), + .SEGMENT (SEGMENT), + .DATA_WIDTH(DATA_WIDTH), // Data width + .NUM_EXTRA_CSR_REG(NUM_EXTRA_CSR_REG), // Number of extra 16-bit register for CSR + .CSR_OUT_NEG_FF_EN(CSR_OUT_NEG_FF_EN), // Enable negative FF on csr_out + .SECTOR_ROW(SECTOR_ROW), + .SECTOR_COL(SECTOR_COL) + ) csr_reg_nregs ( + .clk(csr_clk_int), // clock + .csr_in(extra_csr_in), // serial CSR in + .csr_en(csr_en), // CSR enable + .scan_shift_n(scan_shift_n), // active low scan shift + + .csr_reg(extra_csr), // CRAM connecting to custom logic + .csr_out(extra_csr_out) // serial CSR output + ); + end + else + for (j=0; j 1) + begin: MORE_THAN_ONE_ATPG_CHAIN + assign csr_chain_out[NUM_ATPG_SCAN_CHAIN-2:0] = csr_chain_out_int[NUM_ATPG_SCAN_CHAIN-2:0]; + end + end + else + if (NUM_ATPG_SCAN_CHAIN > 0) + begin: MORE_THAN_ONE_ATPG_CHAIN + assign csr_chain_out[NUM_ATPG_SCAN_CHAIN-1:0] = csr_chain_out_int[NUM_ATPG_SCAN_CHAIN-1:0]; + end +endgenerate + +// atpg_scan_in/out, csr_out connection +assign atpg_scan_out = csr_chain_out; +assign csr_out = atpg_scan_out[TOTAL_ATPG_SCAN_CHAIN - 1]; + +generate + genvar i; + assign csr_chain_in[0] = (scan_mode_n == 1'b1) ? csr_in : atpg_scan_in[0]; + for (i=1; i 1) + begin: MORE_THAN_ONE_ATPG_CHAIN + assign csr_chain_out[NUM_ATPG_SCAN_CHAIN-2:0] = csr_chain_out_int[NUM_ATPG_SCAN_CHAIN-2:0]; + end +endgenerate + +// atpg_scan_in/out, csr_out connection +assign atpg_scan_out = csr_chain_out; +assign csr_out = atpg_scan_out[NUM_ATPG_SCAN_CHAIN-1]; + +generate + genvar i; + assign csr_chain_in[0] = (scan_mode_n == 1'b1) ? csr_in : atpg_scan_in[0]; + for (i=1; i= r_full) ? 1'b1 : 1'b0; + // Generate FIFO Almost Full + wr_pfull <= (wr_numdata >= r_pfull) ? 1'b1 : 1'b0; + + end + end + + + + + //******************************************************************** + // READ CLOCK DOMAIN: Generate READ Address & READ Address GREY + //******************************************************************** + // Memory read-address pointer + assign rd_addr_mem = rd_addr_bin[AWIDTH-1:0]; +// assign rd_addr_mem_next = rd_addr_bin_next_item[AWIDTH-1:0]; + always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + rd_addr_bin <= 'd0; + rd_addr_gry <= 'd0; + end + else if (rd_srst_n == 1'b0) begin + rd_addr_bin <= 'd0; + rd_addr_gry <= 'd0; + end + else begin + rd_addr_bin <= rd_addr_bin_nxt; + rd_addr_gry <= rd_addr_gry_nxt; + end + end + + // Binary Next Read Address + assign rd_addr_bin_nxt = rd_addr_bin + (r_stop_read ? (rd_en & ~rd_empty) : rd_en); + + // Grey Next Read Address + cdclib_bintogray + #( + .WIDTH (AWIDTH+1) + ) rd_addr_nxt_bintogray + ( + .data_in (rd_addr_bin_nxt), + .data_out (rd_addr_gry_nxt) + ); + + + + //******************************************************************** + // READ CLOCK DOMAIN: Synchronize Write Address to Read Clock + //******************************************************************** + cdclib_bitsync2 + #( + .DWIDTH (AWIDTH+1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (1), + .VID (1) + ) + cdclib_bitsync2_rd + ( + .clk (rd_clk), + .rst_n (rd_rst_n), + .data_in (wr_addr_gry), + .data_out (wr_addr_gry_sync) + ); + + cdclib_graytobin_inc8 + #( + .WIDTH (AWIDTH+1) + ) wr_addr_graytobin + ( + .data_in (wr_addr_gry_sync), + .data_out (wr_addr_bin_sync) + ); + + + assign rd_numdata = ~r_num_type ? (wr_addr_bin_sync - rd_addr_bin_nxt) : (wr_addr_bin_sync - rd_addr_bin); + + //******************************************************************** + // READ CLOCK DOMAIN: Generate Fifo Number of Data Present + // using Read Address and Synchronized Write Address + //******************************************************************** + always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + rd_empty <= 1'b1; + rd_pempty <= 1'b1; + rd_full <= 1'b0; + rd_pfull <= 1'b0; + end + else if (rd_srst_n == 1'b0) begin + rd_empty <= 1'b1; + rd_pempty <= 1'b1; + rd_full <= 1'b0; + rd_pfull <= 1'b0; + end + else begin + + // Generate FIFO Empty + rd_empty <= (rd_numdata == r_empty) ? 1'b1 : 1'b0; +// rd_empty <= rd_empty_comb; + // Generate FIFO Almost Empty + rd_pempty <= (rd_numdata <= r_pempty) ? 1'b1 : 1'b0; +// rd_pempty <= rd_pempty_comb; + // Generate FIFO Full + rd_full <= (rd_numdata >= r_full) ? 1'b1 : 1'b0; + // Generate FIFO Almost Full + rd_pfull <= (rd_numdata >= r_pfull) ? 1'b1 : 1'b0; + + end + end + +assign rd_empty_comb = (rd_numdata == r_empty) ? 1'b1 : 1'b0; +assign rd_pempty_comb = (rd_numdata <= r_pempty) ? 1'b1 : 1'b0; + + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_cmn_intf.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_cmn_intf.v new file mode 100644 index 0000000..d5dda1b --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_cmn_intf.v @@ -0,0 +1,356 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_avmm_cmn_intf +( +input wire avmm_rst_n, +input wire scan_rst_n, +input wire scan_mode_n, +input wire scan_shift_n, +input wire scan_shift_clk, +input wire csr_clk, +input wire csr_bit_last, +input wire avmm_clk, +input wire avmm_write, +input wire avmm_read, +input wire avmm_request, +input wire [9:0] avmm_reg_addr, +input wire [7:0] avmm_writedata, +input wire [8:0] avmm_reserved_in, +input wire block_select_master, +input wire [7:0] master_pld_avmm_readdata, +input wire [7:0] remote_pld_avmm_readdata, +//input wire [2:0] remote_pld_avmm_reserved_out, +input wire interface_sel, +input wire [9:0] r_avmm_nfhssi_base_addr, +input wire r_avmm_nfhssi_calibration_en, +input wire [9:0] r_avmm_adapt_base_addr, +input wire r_avmm_rd_block_enable, +input wire r_avmm_uc_block_enable, +input wire remote_pld_avmm_busy, +input wire remote_pld_avmm_readdatavalid, +input wire sr_hssi_avmm1_busy, +input wire int_pld_avmm_cmdfifo_wr_pfull, + +output wire [7:0] master_pld_avmm_writedata, +output wire [7:0] master_pld_avmm_reg_addr, +output wire master_pld_avmm_write, +output wire master_pld_avmm_read, + +output wire [7:0] remote_pld_avmm_writedata, +output wire [8:0] remote_pld_avmm_reserved_in, +output wire [9:0] remote_pld_avmm_reg_addr, +output wire remote_pld_avmm_write, +output wire remote_pld_avmm_read, +output wire remote_pld_avmm_request, + +output wire [7:0] avmm_readdata, +output reg avmm_readdatavalid, +//output reg [2:0] avmm_reserved_out, +output wire avmm_pld_avmm_busy, +output wire [10:0] avmm1_cmn_intf_testbus, +output wire pld_avmm1_cmdfifo_wr_pfull_dly, +output wire csr_out +); + +localparam DATA_WIDTH = 8; // Data width +localparam ADDR_WIDTH = 9; // Address width +localparam NUM_CHNL = 2; // Number of DPRIO modules +localparam CSR_OUT_NEG_FF_EN = 1; // Enable negative FF on csr_out + +wire nc_0; +wire nc_1; +wire nc_2; +wire nc_3; +wire nc_4; +wire nc_5; +wire nc_6; +wire nc_7; +wire nc_8; +wire nc_9; +wire nc_10; +wire nc_11; +reg [DATA_WIDTH-1:0] writedata_int; +reg [8:0] avmm_reserved_in_int; +reg [ADDR_WIDTH:0] reg_addr_int; +reg write_int; +reg read_int; +reg avmm_request_int; +reg master_pld_avmm_read_dly1; +reg master_pld_avmm_read_dly2; +wire avmm_readdatavalid_dly2; + +wire msb_avmm_reg_addr; +wire [NUM_CHNL-1:0] block_select; +wire [DATA_WIDTH*NUM_CHNL-1:0] readdata_chnl; +wire hssi_uc_ctrl; +reg uc_blocked_int; +wire uc_blocked; +reg avmm_rd_blocked_int; +wire avmm_rd_blocked; +reg msb_avmm_reg_addr_reg; +reg avmm_request_reg; +reg [8:0] avmm_reserved_in_reg; +wire [DATA_WIDTH-1:0] writedata_chnl; +wire [ADDR_WIDTH-1:0] reg_addr_chnl; +wire write_chnl; +wire read_chnl; + +reg remote_pld_avmm_busy_dly; +wire deassertion_pld_avmm_busy; +wire nd_reg_addr; +wire remote_pld_avmm_busy_selout; +wire sr_hssi_avmm1_busy_sync; +reg remote_pld_avmm_busy_sel; +reg [2:0] avmm_reserved_out; + +assign avmm1_cmn_intf_testbus = {remote_pld_avmm_write, remote_pld_avmm_read, master_pld_avmm_write, master_pld_avmm_read, avmm_rd_blocked, uc_blocked, nd_reg_addr, hssi_uc_ctrl, master_pld_avmm_read_dly2, remote_pld_avmm_readdatavalid, remote_pld_avmm_busy_selout}; + +assign block_select = {~master_pld_avmm_read_dly2,master_pld_avmm_read_dly2}; +assign readdata_chnl = {remote_pld_avmm_readdata,master_pld_avmm_readdata}; +assign msb_avmm_reg_addr = avmm_reg_addr[9]; + +cfg_dprio_ctrl_stat_interface_top +#( + .DATA_WIDTH(DATA_WIDTH), // Data width + .ADDR_WIDTH(ADDR_WIDTH), // Address width + .NUM_CHNL(NUM_CHNL), // Number of DPRIO modules + .CSR_OUT_NEG_FF_EN(CSR_OUT_NEG_FF_EN) // Enable negative FF on csr_out + ) +cfg_dprio_ctrl_stat_interface_top ( + // input + .npor (avmm_rst_n ), // NPOR from CB. + .plniotri (1'b1 ), // PLNIOTRI from CB + .entest (1'b0 ), // ENTEST from CB + .scan_mode_n (1'b1 ), // active low scan mode enable. + .scan_shift_n (scan_shift_n ), // active low scan shift + .refclk_dig (scan_shift_clk ), // scan clock. + .csr_rst_n (1'b1 ), // CSR reset + .csr_clk (csr_clk ), // CSR clock + .csr_in (1'b0 ), // Serial CSR input + .csr_en (1'b1 ), // CSR enable. + .csr_out_chnl (csr_bit_last ), // CSR output from top channel + .csr_cbdin (1'b0 ), // CSR configuration mode data input + .csr_tcsrin (1'b0 ), // CSR test/scan mode data input + .csr_din (1'b0 ), // Previous CSR bit data output + .csr_seg (1'b0 ), // VSS for Seg0(), VCC for seg[31:1] + .csr_entest (1'b0 ), // enable test control input: ECO fix to tie off the csr_entest + .csr_enscan (1'b0 ), // enable scan control input + .csr_tverify (1'b0 ), // test verify control input + .csr_load_csr (1'b0 ), // JTAG scan mode control input + .csr_pipe_in (1'b0 ), // Input to the Pipeline register to suport 200MHz + .interface_sel (1'b0 ), // Interface selection inputs. + .avmm_rst_n (scan_rst_n ), // Avalon-MM reset. + .avmm_clk (avmm_clk ), // Avalon-MM clock. + .avmm_write (avmm_write ), // Avalon-MM write enable input + .avmm_read (avmm_read ), // Avalon-MM read enable input + .avmm_byte_en (1'b1 ), // Avalon-MM Byte enable + .avmm_reg_addr (avmm_reg_addr[8:0] ), // Avalon-MM address input + .avmm_writedata (avmm_writedata ), // Avalon-MM write data input + .block_select (block_select ), // Signal to tell the central interface to select its readdata + .readdata_chnl (readdata_chnl ), // Read data from channels + // output + .dprio_rst_n (nc_10 ), // Active low reset to channel: + .dprio_clk (nc_11 ), // Clock to channel. + .writedata_chnl (writedata_chnl ), // Write data to channel + .reg_addr_chnl (reg_addr_chnl ), // Address to channel + .write_chnl (write_chnl ), // Write enable to channel + .read_chnl (read_chnl ), // Read enable to channel + .avmm_readdata (avmm_readdata ), // Avalon-MM read data output + .csr_out (csr_out ), // Serial CSR output + .scan_mode_n_chnl (nc_0 ), // active low scan mode enable for top channel + .scan_shift_n_chnl (nc_1 ), // active low scan mode enable for top channel + .csr_en_chnl (nc_2 ), // CSR enable to channels + .csr_clk_chnl (nc_3 ), // CSR clock to channels + .csr_in_chnl (nc_4 ), // CSR input to top channel + .csr_dout (nc_5 ), // CSR input MUX Data output + .csr_pipe_out (nc_6 ), // Pipelined register data output + .csr_test_mode (nc_7 ), // CSR test mode + .mdio_dis_chnl (nc_8 ), // 1'b1=CRAM is from CSR + .byte_en_chnl (nc_9 ) +); + +// Flop the MSB of avmm_reg_addr +always @(negedge avmm_rst_n or posedge avmm_clk) + if (avmm_rst_n == 1'b0) + begin + msb_avmm_reg_addr_reg <= 1'b0; + avmm_request_reg <= 1'b0; + avmm_reserved_in_reg <= 9'd0; + end + else + begin + msb_avmm_reg_addr_reg <= msb_avmm_reg_addr; + avmm_request_reg <= avmm_request; + avmm_reserved_in_reg <= avmm_reserved_in; + end + +// AVMM Interface signals during iocsr_rdy assertion and deassertion +always @(*) + begin + case (interface_sel) + 1'b0: // Avalon-MM interface + begin + writedata_int = writedata_chnl; + reg_addr_int = {msb_avmm_reg_addr_reg,reg_addr_chnl}; + write_int = write_chnl; + read_int = read_chnl; + avmm_request_int = avmm_request_reg; + avmm_reserved_in_int = avmm_reserved_in_reg; + end + 1'b1: // CSR interface + begin + writedata_int = {DATA_WIDTH{1'b0}}; + reg_addr_int = {1'b0,{ADDR_WIDTH{1'b0}}}; + write_int = 1'b0; + read_int = 1'b0; + avmm_request_int = 1'b0; + avmm_reserved_in_int = 9'd0; + end + default: // CSR + begin + writedata_int = {DATA_WIDTH{1'b0}}; + reg_addr_int = {1'b0,{ADDR_WIDTH{1'b0}}}; + write_int = 1'b0; + read_int = 1'b0; + avmm_request_int = 1'b0; + avmm_reserved_in_int = 9'd0; + end + endcase + end + +// Select busy bit from SR right after reset until de-assertion of busy bit. After that, always select busy bit from AVMM transfer +cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (1), // Reset value + .CLK_FREQ_MHZ(200), + .TOGGLE_TYPE (2), + .VID (1) + ) cdclib_bitsync2_sr_hssi_avmm1_busy + ( + .clk (avmm_clk), + .rst_n (avmm_rst_n), + .data_in (sr_hssi_avmm1_busy), + .data_out (sr_hssi_avmm1_busy_sync) + ); + +always @(negedge avmm_rst_n or posedge avmm_clk) + if (avmm_rst_n == 1'b0) + begin + remote_pld_avmm_busy_sel <= 1'b1; + end + else + begin + remote_pld_avmm_busy_sel <= deassertion_pld_avmm_busy ? 1'b0 : remote_pld_avmm_busy_sel; + end + +assign remote_pld_avmm_busy_selout = remote_pld_avmm_busy_sel ? sr_hssi_avmm1_busy_sync : remote_pld_avmm_busy; + +// gate read and write in main adapter after AVMM switch control from PLD to uC in NF HSSI +assign hssi_uc_ctrl = write_int & (reg_addr_int[9:0] == r_avmm_nfhssi_base_addr[9:0]) & writedata_int[0] & r_avmm_nfhssi_calibration_en; + +always @(negedge avmm_rst_n or posedge avmm_clk) + if (avmm_rst_n == 1'b0) + begin + remote_pld_avmm_busy_dly <= 1'b1; + end + else + begin + remote_pld_avmm_busy_dly <= remote_pld_avmm_busy_selout; + end + +//assign avmm_pld_avmm_busy = remote_pld_avmm_busy_dly; +assign avmm_pld_avmm_busy = remote_pld_avmm_busy_selout; +assign deassertion_pld_avmm_busy = (remote_pld_avmm_busy_selout == 1'b0) & (remote_pld_avmm_busy_dly == 1'b1); + +assign uc_blocked = uc_blocked_int & r_avmm_uc_block_enable; +always @(negedge avmm_rst_n or posedge avmm_clk) + if (avmm_rst_n == 1'b0) + begin + uc_blocked_int <= 1'b0; + end + else + begin + if (!uc_blocked_int && ( hssi_uc_ctrl || remote_pld_avmm_busy_selout) && !avmm_rd_blocked) begin + uc_blocked_int <= 1'b1; + end + else if (deassertion_pld_avmm_busy) begin + uc_blocked_int <= 1'b0; + end + else begin + uc_blocked_int <= uc_blocked_int; + end + end + +// blocked read command before return of readdatavalid +assign avmm_rd_blocked = avmm_rd_blocked_int & r_avmm_rd_block_enable; +always @(negedge avmm_rst_n or posedge avmm_clk) + if (avmm_rst_n == 1'b0) + begin + avmm_rd_blocked_int <= 1'b0; + end + else + begin + //if (!avmm_rd_blocked_int && read_int && !nd_reg_addr && !uc_blocked) begin + if (!avmm_rd_blocked_int && read_int && !uc_blocked) begin + avmm_rd_blocked_int <= 1'b1; + end + //else if (remote_pld_avmm_readdatavalid || master_pld_avmm_read_dly2) begin + else if (avmm_readdatavalid_dly2) begin + avmm_rd_blocked_int <= 1'b0; + end + else begin + avmm_rd_blocked_int <= avmm_rd_blocked_int; + end + end + +assign nd_reg_addr = (reg_addr_int[9:8] == r_avmm_adapt_base_addr[9:8]) ? 1'b1 : 1'b0; + +// distribute AVMM commands to master and slave +assign remote_pld_avmm_writedata = writedata_int; +assign remote_pld_avmm_reserved_in = avmm_reserved_in_int; +assign remote_pld_avmm_reg_addr = reg_addr_int[9:0]; +assign remote_pld_avmm_write = (nd_reg_addr || avmm_rd_blocked || uc_blocked) ? 1'b0 : write_int; // add uc_blocked component +assign remote_pld_avmm_read = (nd_reg_addr || avmm_rd_blocked || uc_blocked) ? 1'b0 : read_int; // add uc_blocked component +assign remote_pld_avmm_request = avmm_request_int; +//assign remote_pld_avmm_read = (nd_reg_addr || avmm_rd_blocked) ? 1'b0 : read_int; // add uc_blocked component + +assign master_pld_avmm_writedata = writedata_int; +assign master_pld_avmm_reg_addr = reg_addr_int[7:0]; +assign master_pld_avmm_write = (!nd_reg_addr || avmm_rd_blocked || uc_blocked) ? 1'b0 : write_int; +assign master_pld_avmm_read = (!nd_reg_addr || avmm_rd_blocked || uc_blocked) ? 1'b0 : read_int; + +// Additional 2 flops +always @(negedge avmm_rst_n or posedge avmm_clk) + if (avmm_rst_n == 1'b0) + begin + master_pld_avmm_read_dly1 <= 1'b0; + master_pld_avmm_read_dly2 <= 1'b0; + end + else + begin + master_pld_avmm_read_dly1 <= master_pld_avmm_read; + master_pld_avmm_read_dly2 <= master_pld_avmm_read_dly1; + end + + +// MUX readdataoutvalid from either master or slave +always @(negedge avmm_rst_n or posedge avmm_clk) + if (avmm_rst_n == 1'b0) + begin + avmm_readdatavalid <= 1'b0; + avmm_reserved_out <= 3'd0; + end + else + begin + avmm_readdatavalid <= master_pld_avmm_read_dly2 ? 1'b1 : remote_pld_avmm_readdatavalid; + //avmm_reserved_out <= remote_pld_avmm_reserved_out; + avmm_reserved_out[0] <= avmm_readdatavalid; + avmm_reserved_out[1] <= avmm_reserved_out[0]; + avmm_reserved_out[2] <= int_pld_avmm_cmdfifo_wr_pfull; + end + +assign avmm_readdatavalid_dly2 = avmm_reserved_out[1]; +assign pld_avmm1_cmdfifo_wr_pfull_dly = avmm_reserved_out[2]; + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_dprio_reg.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_dprio_reg.v new file mode 100644 index 0000000..7c23b0c --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_dprio_reg.v @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_avmm_dprio_reg +( +input wire csr_clk, // CSR clock +input wire avmm_clk, +input wire scan_mode_n, +input wire scan_shift_n, +input wire csr_in_ds, +input wire [3:0] scan_in, +input wire csr_en, +input wire avmm_rst_n, +input wire write, +input wire read, +input wire [7:0] reg_addr, +input wire [7:0] writedata, +input wire csr_test_mode, +input wire mdio_dis, +input wire [15:0] user_datain, +input wire [1:0] write_en_ack, + +output wire csr_out, // last csr_in +output wire [3:0] scan_out, +output wire [7:0] readdata, +output wire block_select, +output wire [383:0] user_dataout, +output wire [1:0] write_en, +output wire [639:0] extra_csr_out +); + +localparam DATA_WIDTH = 8; // Data width +localparam ADDR_WIDTH = 8; // Address width +localparam NUM_CTRL_REGS = 8'd48; // Number of n-bit TX control registers. +localparam NUM_EXTRA_CSR_REG = 8'd80; // Number of extra 8-bit register for CSR. +localparam NUM_STATUS_REGS = 2; // Number of n-bit status registers. +localparam CSR_OUT_NEG_FF_EN = 0; // Enable negative FF on csr_out +localparam BYPASS_STAT_SYNC = 0; // to bypass the Synchronization SM in case of individual status bits +localparam USE_AVMM_INTF = 1; // Specify if AVMM Interface is used. Bypass clock selection if using AVMM Interface. +localparam FORCE_INTER_SEL_CVP_EN = 0; // Enable logic to force interface_sel in CVP mode +localparam NUM_ATPG_SCAN_CHAIN = 2; // Specify number of scan chain +localparam NUM_CSR_ATPG_SCAN_CHAIN= 2; // Specify number of scan chain +localparam STAT_REG_CLK_FREQ_MHZ = 200; +localparam STAT_REG_TOGGLE_TYPE = 2; +localparam STAT_REG_VID = 1; + + cfg_dprio_ctrl_stat_reg_top + #( + .DATA_WIDTH (DATA_WIDTH), + .ADDR_WIDTH (ADDR_WIDTH), + .NUM_CTRL_REGS (NUM_CTRL_REGS), + .NUM_EXTRA_CSR_REG (NUM_EXTRA_CSR_REG), + .NUM_STATUS_REGS (NUM_STATUS_REGS), + .CSR_OUT_NEG_FF_EN (CSR_OUT_NEG_FF_EN), + .BYPASS_STAT_SYNC (BYPASS_STAT_SYNC), + .USE_AVMM_INTF (USE_AVMM_INTF), + .FORCE_INTER_SEL_CVP_EN (FORCE_INTER_SEL_CVP_EN), + .NUM_CSR_ATPG_SCAN_CHAIN (NUM_CSR_ATPG_SCAN_CHAIN), + .STAT_REG_CLK_FREQ_MHZ (STAT_REG_CLK_FREQ_MHZ), + .STAT_REG_TOGGLE_TYPE (STAT_REG_TOGGLE_TYPE), + .STAT_REG_VID (STAT_REG_VID), + .NUM_ATPG_SCAN_CHAIN (NUM_ATPG_SCAN_CHAIN) + ) + cfg_dprio_ctrl_stat_reg_top + ( + // input + .scan_mode_n (scan_mode_n), + .scan_shift_n (scan_shift_n), + .csr_clk (csr_clk), + .csr_in (csr_in_ds), + .atpg_scan_in (scan_in), + .csr_en (csr_en), + .dprio_rst_n (avmm_rst_n), + .dprio_clk (avmm_clk), + .write (write), + .read (read), + .byte_en (1'b1), + .reg_addr (reg_addr), + .writedata (writedata), + .csr_test_mode (csr_test_mode), + .mdio_dis (mdio_dis), + .user_datain (user_datain), + .write_en_ack (write_en_ack), + .pma_csr_test_dis (1'b1), + // output + .csr_out (csr_out), + .atpg_scan_out (scan_out), + .readdata (readdata), + .block_select (block_select), + .user_dataout (user_dataout), + .write_en (write_en), + .extra_csr (extra_csr_out) + ); + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_rdfifo.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_rdfifo.v new file mode 100644 index 0000000..b9fc255 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_rdfifo.v @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// (C) 2009 Altera Corporation. All rights reserved. +// +//------------------------------------------------------------------------ +// File: $RCSfile: hd_pcs10g_async_fifo.v.rca $ +// Revision: $Revision: #4 $ +// Date: $Date: 2015/03/22 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ + + +module hdpldadapt_avmm_rdfifo + #( + parameter DWIDTH = 'd2, // FIFO Input data width + parameter AWIDTH = 'd6 // FIFO Depth (address width) + ) + ( + input wire wr_rst_n, // Write Domain Active low Reset + input wire wr_srst_n, // Write Domain Active low Reset Synchronous + input wire wr_clk, // Write Domain Clock + input wire wr_en, // Write Data Enable + input wire [DWIDTH-1:0] wr_data, // Write Data In + input wire rd_rst_n, // Read Domain Active low Reset + input wire rd_srst_n, // Read Domain Active low Reset Synchronous + input wire rd_clk, // Read Domain Clock + input wire rd_en, // Read Data Enable + input wire [AWIDTH-1:0] r_pempty, // FIFO partially empty threshold + input wire [AWIDTH-1:0] r_pfull, // FIFO partially full threshold + input wire [AWIDTH-1:0] r_empty, // FIFO empty threshold + input wire [AWIDTH-1:0] r_full, // FIFO full threshold +// input wire r_oct_write, // FIFO double write mode + + input wire r_stop_read, // Disable/enable reading when FIFO is empty + input wire r_stop_write, // Disable/enable writing when FIFO is full + + output wire [DWIDTH-1:0] rd_data, // Read Data Out + output wire [DWIDTH-1:0] rd_data1, // Read Data Out + output wire [DWIDTH-1:0] rd_data2, // Read Data Out + output wire [DWIDTH-1:0] rd_data3, // Read Data Out + output wire [DWIDTH-1:0] rd_data4, // Read Data Out + output wire [DWIDTH-1:0] rd_data5, // Read Data Out + output wire [DWIDTH-1:0] rd_data6, // Read Data Out + output wire [DWIDTH-1:0] rd_data7, // Read Data Out +// output wire [DWIDTH-1:0] rd_data_next, // Read Data Out Next +// output wire [AWIDTH-1:0] rd_numdata, // Number of Data available in Read clock +// output wire [AWIDTH-1:0] wr_numdata, // Number of Data available in Write clock +// output wire wr_addr_msb, // Write address MSB +// output wire rd_addr_msb, // Write address MSB + + output reg wr_empty, // FIFO Empty + output reg wr_pempty, // FIFO Partial Empty + output reg wr_full, // FIFO Full + output reg wr_pfull, // FIFO Parial Full + output reg rd_empty, // FIFO Empty + output reg rd_pempty, // FIFO Partial Empty +// output wire rd_empty_comb, // FIFO Empty +// output wire rd_pempty_comb, // FIFO Partial Empty + output reg rd_full, // FIFO Full + output reg rd_pfull // FIFO Partial Full + ); + + //******************************************************************** + // Define Parameters + //******************************************************************** +//`include "hd_pcs10g_params.v" + + //******************************************************************** + // Define variables + //******************************************************************** + integer m; + // Regs + reg [DWIDTH-1:0] fifo_mem [((1<= r_full) ? 1'b1 : 1'b0; +// wr_full <= ({wr_addr_bin_nxt[AWIDTH], wr_addr_bin_nxt[AWIDTH-1:0]} == {~rd_addr_bin_sync[AWIDTH], rd_addr_bin_sync[AWIDTH-1:0]}); + + // Generate FIFO Almost Full + wr_pfull <= (wr_numdata >= r_pfull) ? 1'b1 : 1'b0; + + end + end + + + + + //******************************************************************** + // READ CLOCK DOMAIN: Generate READ Address & READ Address GREY + //******************************************************************** + // Memory read-address pointer + assign rd_addr_mem = rd_addr_bin[AWIDTH-1:0]; +// assign rd_addr_mem_next = rd_addr_bin_next_item[AWIDTH-1:0]; + always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + rd_addr_bin <= 'd0; + rd_addr_gry <= 'd0; + end + else if (rd_srst_n == 1'b0) begin + rd_addr_bin <= 'd0; + rd_addr_gry <= 'd0; + end + else begin + rd_addr_bin <= rd_addr_bin_nxt; + rd_addr_gry <= rd_addr_gry_nxt; + end + end + + // Binary Next Read Address + assign rd_addr_bin_nxt = rd_addr_bin + (r_stop_read ? 8*(rd_en & ~rd_empty) : 8*rd_en); + + // Grey Next Read Address + cdclib_bintogray_inc8 + #( + .WIDTH (AWIDTH+1) + ) rd_addr_nxt_bintogray_inc8 + ( + .data_in (rd_addr_bin_nxt), + .data_out (rd_addr_gry_nxt) + ); + + + + //******************************************************************** + // READ CLOCK DOMAIN: Synchronize Write Address to Read Clock + //******************************************************************** + cdclib_bitsync2 + #( + .DWIDTH (AWIDTH+1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(200), + .TOGGLE_TYPE (1), + .VID (1) + ) + cdclib_bitsync2_rd + ( + .clk (rd_clk), + .rst_n (rd_rst_n), + .data_in (wr_addr_gry), + .data_out (wr_addr_gry_sync) + ); + + cdclib_graytobin + #( + .WIDTH (AWIDTH+1) + ) wr_addr_graytobin + ( + .data_in (wr_addr_gry_sync), + .data_out (wr_addr_bin_sync) + ); + + + assign rd_numdata = ~r_num_type ? (wr_addr_bin_sync - rd_addr_bin_nxt) : (wr_addr_bin_sync - rd_addr_bin); + + //******************************************************************** + // READ CLOCK DOMAIN: Generate Fifo Number of Data Present + // using Read Address and Synchronized Write Address + //******************************************************************** + always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + rd_empty <= 1'b1; + rd_pempty <= 1'b1; + rd_full <= 1'b0; + rd_pfull <= 1'b0; + end + else if (rd_srst_n == 1'b0) begin + rd_empty <= 1'b1; + rd_pempty <= 1'b1; + rd_full <= 1'b0; + rd_pfull <= 1'b0; + end + else begin + + // Generate FIFO Empty +// rd_empty <= (rd_numdata == r_empty) ? 1'b1 : 1'b0; + rd_empty <= rd_empty_comb; + // Generate FIFO Almost Empty +// rd_pempty <= (rd_numdata <= r_pempty) ? 1'b1 : 1'b0; + rd_pempty <= rd_pempty_comb; + // Generate FIFO Full + rd_full <= (rd_numdata >= r_full) ? 1'b1 : 1'b0; +// rd_full <= {wr_addr_bin_sync[AWIDTH], wr_addr_bin_sync[AWIDTH-1:0]} == {rd_addr_bin_nxt[AWIDTH], rd_addr_bin_nxt[AWIDTH-1:0]}; + // Generate FIFO Almost Full + rd_pfull <= (rd_numdata >= r_pfull) ? 1'b1 : 1'b0; + + end + end + +assign rd_empty_comb = (rd_numdata <= r_empty) ? 1'b1 : 1'b0; +assign rd_pempty_comb = (rd_numdata <= r_pempty) ? 1'b1 : 1'b0; + + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmmclk_ctl.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmmclk_ctl.v new file mode 100644 index 0000000..27cd8ff --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmmclk_ctl.v @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_avmmclk_ctl +( + input wire csr_rdy_in, + input wire csr_rdy_dly_in, + input wire csr_clk_in, + input wire aib_fabric_rx_sr_clk_in, + input wire aib_fabric_tx_sr_clk_in, + input wire pld_avmm_clk_rowclk, + input wire nfrzdrv_in, + input wire avmm_reset_avmm_rst_n, + input wire r_avmm_osc_clk_scg_en, + input wire r_avmm_avmm_clk_scg_en, + input wire dft_adpt_aibiobsr_fastclkn, + input wire adapter_scan_mode_n, + input wire adapter_scan_shift_n, + input wire adapter_scan_shift_clk, + input wire adapter_scan_user_clk0, // 125MHz + input wire adapter_scan_user_clk3, // 1GHz + input wire adapter_clk_sel_n, + input wire adapter_occ_enable, + output wire avmm_clock_reset_rx_osc_clk, + output wire avmm_clock_reset_tx_osc_clk, + output wire avmm_clock_reset_avmm_clk, + output wire avmm_clock_rx_osc_clk, + output wire avmm_clock_tx_osc_clk, + output wire avmm_clock_avmm_clk, + output wire avmm_clock_dprio_clk, + output wire pld_avmm_clk_out +); + + //wire adapter_scan_mode; + wire adapter_scan_shift; + wire avmm_clock_dft_scg_bypass; + wire avmm_clock_dft_clk_sel_n; + wire avmm_clock_dft_occ_atpg_mode; + + wire frz_2one_by_nfrzdrv; + + wire avmm_clock_rx_osc_clk_mux1; + wire avmm_clock_rx_osc_clk_occ; + wire avmm_osc_clk_en; + + wire avmm_clock_tx_osc_clk_mux1; + wire avmm_clock_tx_osc_clk_occ; + + wire avmm_clock_dprio_clk_mux1; + wire avmm_clock_dprio_clk_mux2; + wire avmm_clock_dprio_clk_occ; + wire avmm_dprio_clk_sel1; + wire avmm_dprio_clk_sel2; + wire avmm_clock_avmm_clk_gate; + reg avmm_clk_gate; + + wire avmm_clock_avmm_clk_mux1; + wire avmm_clock_avmm_clk_occ; + wire avmm_avmm_clk_en; + + + assign adapter_scan_shift = ~adapter_scan_shift_n; + assign avmm_clock_dft_scg_bypass = ~dft_adpt_aibiobsr_fastclkn | ~adapter_scan_mode_n; + assign avmm_clock_dft_clk_sel_n = dft_adpt_aibiobsr_fastclkn & adapter_scan_mode_n; + + assign avmm_clock_dft_occ_atpg_mode = ~adapter_scan_mode_n; + + + +assign frz_2one_by_nfrzdrv = ~(nfrzdrv_in); + +hdpldadapt_cmn_clkor2 hdpldadapt_cmn_clkor2_pld_avmm_clk_rowclk + ( + .clkout(pld_avmm_clk_out), + .clk(pld_avmm_clk_rowclk), + .en(frz_2one_by_nfrzdrv) + ); + +////////////////// +// Clock muxing // +////////////////// + +////////// Rx Oscillator Clock ////////// + +assign avmm_clock_reset_rx_osc_clk = avmm_clock_rx_osc_clk_mux1; + +assign avmm_osc_clk_en = avmm_clock_dft_scg_bypass | ~r_avmm_osc_clk_scg_en; + +hdpldadapt_cmn_clkand2 hdpldadapt_cmn_clkand2_avmm_rx_osc_clk_scg + ( + .clkout(avmm_clock_rx_osc_clk), + .clk(avmm_clock_rx_osc_clk_mux1), + .en(avmm_osc_clk_en) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_avmm_rx_osc_clk_mux1 + ( + .clk_o(avmm_clock_rx_osc_clk_mux1), + .clk_0(avmm_clock_rx_osc_clk_occ), + .clk_1(aib_fabric_rx_sr_clk_in), + .clk_sel(avmm_clock_dft_clk_sel_n) + ); + +hdpldadapt_cmn_dft_clock_controller + #( + .CONTROL_REGISTER_PRESENT(1) + ) hdpldadapt_cmn_dft_clock_controller_avmm_rx_osc_clk_occ + ( + .user_clk(adapter_scan_user_clk3), //User clock + .test_clk(adapter_scan_shift_clk), //Test clock + .rst_n(1'b0), //Reset (active low) + .clk_sel_n(adapter_clk_sel_n), //Mux sel between user or test clock, Active low + .scan_enable(adapter_scan_shift), //Scan enable control signal, Active high in IP, Active low in top level + .occ_enable(adapter_occ_enable), //Control signal to enable OCC, Active high in IP, Active low in top level + .atpg_mode(avmm_clock_dft_occ_atpg_mode), //Control signal for test mode, Active high in IP, Active low in top level + .out_clk(avmm_clock_rx_osc_clk_occ) //Output clock + ); + +////////// Tx Oscillator Clock ////////// + +assign avmm_clock_reset_tx_osc_clk = avmm_clock_tx_osc_clk_mux1; + +hdpldadapt_cmn_clkand2 hdpldadapt_cmn_clkand2_avmm_tx_osc_clk_scg + ( + .clkout(avmm_clock_tx_osc_clk), + .clk(avmm_clock_tx_osc_clk_mux1), + .en(avmm_osc_clk_en) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_avmm_tx_osc_clk_mux1 + ( + .clk_o(avmm_clock_tx_osc_clk_mux1), + .clk_0(avmm_clock_tx_osc_clk_occ), + .clk_1(aib_fabric_tx_sr_clk_in), + .clk_sel(avmm_clock_dft_clk_sel_n) + ); + +hdpldadapt_cmn_dft_clock_controller + #( + .CONTROL_REGISTER_PRESENT(1) + ) hdpldadapt_cmn_dft_clock_controller_avmm_tx_osc_clk_occ + ( + .user_clk(adapter_scan_user_clk3), //User clock + .test_clk(adapter_scan_shift_clk), //Test clock + .rst_n(1'b0), //Reset (active low) + .clk_sel_n(adapter_clk_sel_n), //Mux sel between user or test clock, Active low + .scan_enable(adapter_scan_shift), //Scan enable control signal, Active high in IP, Active low in top level + .occ_enable(adapter_occ_enable), //Control signal to enable OCC, Active high in IP, Active low in top level + .atpg_mode(avmm_clock_dft_occ_atpg_mode), //Control signal for test mode, Active high in IP, Active low in top level + .out_clk(avmm_clock_tx_osc_clk_occ) //Output clock + ); + +////////// DPRIO Clock ////////// + +assign avmm_clock_dprio_clk = avmm_clock_dprio_clk_mux1; + +assign avmm_dprio_clk_sel1 = avmm_clock_dft_clk_sel_n && (csr_rdy_dly_in == 1'b0); +assign avmm_dprio_clk_sel2 = avmm_clock_dft_clk_sel_n && (csr_rdy_in == 1'b1); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_avmm_dprio_clk_mux1 + ( + .clk_o(avmm_clock_dprio_clk_mux1), + .clk_0(avmm_clock_dprio_clk_mux2), + .clk_1(csr_clk_in), + .clk_sel(avmm_dprio_clk_sel1) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_avmm_dprio_clk_mux2 + ( + .clk_o(avmm_clock_dprio_clk_mux2), + //.clk_0(adapter_scan_shift_clk), + .clk_0(avmm_clock_dprio_clk_occ), + .clk_1(avmm_clock_avmm_clk_gate), + .clk_sel(avmm_dprio_clk_sel2) + ); + +hdpldadapt_cmn_clkor2 hdpldadapt_cmn_clkor2_avmm_clock_avmm_clk_gate + ( + .clkout(avmm_clock_avmm_clk_gate), + .clk(avmm_clock_avmm_clk), + .en(avmm_clk_gate) + ); + +always @(negedge avmm_reset_avmm_rst_n or posedge avmm_clock_avmm_clk) +begin + if (~avmm_reset_avmm_rst_n) + begin + avmm_clk_gate <= 1'b1; + end + else + begin + avmm_clk_gate <= 1'b0; + end +end + +hdpldadapt_cmn_dft_clock_controller + #( + .CONTROL_REGISTER_PRESENT(1) + ) hdpldadapt_cmn_dft_clock_controller_avmm_dprio_clk_occ + ( + .user_clk(adapter_scan_user_clk0), //User clock + .test_clk(adapter_scan_shift_clk), //Test clock + .rst_n(1'b0), //Reset (active low) + .clk_sel_n(adapter_clk_sel_n), //Mux sel between user or test clock, Active low + .scan_enable(adapter_scan_shift), //Scan enable control signal, Active high in IP, Active low in top level + .occ_enable(adapter_occ_enable), //Control signal to enable OCC, Active high in IP, Active low in top level + .atpg_mode(avmm_clock_dft_occ_atpg_mode), //Control signal for test mode, Active high in IP, Active low in top level + .out_clk(avmm_clock_dprio_clk_occ) //Output clock + ); + +////////// AVMM Clock ////////// + +assign avmm_clock_reset_avmm_clk = avmm_clock_avmm_clk_mux1; + +assign avmm_avmm_clk_en = avmm_clock_dft_scg_bypass | ~r_avmm_avmm_clk_scg_en; + +hdpldadapt_cmn_clkand2 hdpldadapt_cmn_clkand2_avmm_avmm_clk_scg + ( + .clkout(avmm_clock_avmm_clk), + .clk(avmm_clock_avmm_clk_mux1), + .en(avmm_avmm_clk_en) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_avmm_avmm_clk_mux1 + ( + .clk_o(avmm_clock_avmm_clk_mux1), + .clk_0(avmm_clock_avmm_clk_occ), + .clk_1(pld_avmm_clk_rowclk), + .clk_sel(avmm_clock_dft_clk_sel_n) + ); + +hdpldadapt_cmn_dft_clock_controller + #( + .CONTROL_REGISTER_PRESENT(1) + ) hdpldadapt_cmn_dft_clock_controller_avmm_avmm_clk_occ + ( + .user_clk(adapter_scan_user_clk0), //User clock + .test_clk(adapter_scan_shift_clk), //Test clock + .rst_n(1'b0), //Reset (active low) + .clk_sel_n(adapter_clk_sel_n), //Mux sel between user or test clock, Active low + .scan_enable(adapter_scan_shift), //Scan enable control signal, Active high in IP, Active low in top level + .occ_enable(adapter_occ_enable), //Control signal to enable OCC, Active high in IP, Active low in top level + .atpg_mode(avmm_clock_dft_occ_atpg_mode), //Control signal for test mode, Active high in IP, Active low in top level + .out_clk(avmm_clock_avmm_clk_occ) //Output clock + ); + +endmodule // hdpldadapt_avmmclk_ctl diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmmrst_ctl.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmmrst_ctl.v new file mode 100644 index 0000000..a7fe0fc --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmmrst_ctl.v @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_avmmrst_ctl +( + input wire csr_rdy_dly_in, + input wire avmm_clock_reset_rx_osc_clk, + input wire avmm_clock_reset_tx_osc_clk, + input wire avmm_clock_reset_avmm_clk, + input wire adapter_scan_rst_n, + input wire adapter_scan_mode_n, + output wire avmm_reset_rx_osc_clk_rst_n, + output wire avmm_reset_tx_osc_clk_rst_n, + output wire avmm_reset_avmm_rst_n +); + + wire int_avmm_hrd_rst_n; + +assign int_avmm_hrd_rst_n = (adapter_scan_mode_n & csr_rdy_dly_in) | (~adapter_scan_mode_n & adapter_scan_rst_n); + +cdclib_rst_n_sync cdclib_rst_n_sync_rx_osc_clk + ( + .rst_n(int_avmm_hrd_rst_n), + .rst_n_bypass(adapter_scan_rst_n), + .clk (avmm_clock_reset_rx_osc_clk), + .scan_mode_n(adapter_scan_mode_n), + .rst_n_sync(avmm_reset_rx_osc_clk_rst_n) + ); + +cdclib_rst_n_sync cdclib_rst_n_sync_tx_osc_clk + ( + .rst_n(int_avmm_hrd_rst_n), + .rst_n_bypass(adapter_scan_rst_n), + .clk (avmm_clock_reset_tx_osc_clk), + .scan_mode_n(adapter_scan_mode_n), + .rst_n_sync(avmm_reset_tx_osc_clk_rst_n) + ); + +cdclib_rst_n_sync cdclib_rst_n_sync_avmm_clk + ( + .rst_n(int_avmm_hrd_rst_n), + .rst_n_bypass(adapter_scan_rst_n), + .clk (avmm_clock_reset_avmm_clk), + .scan_mode_n(adapter_scan_mode_n), + .rst_n_sync(avmm_reset_avmm_rst_n) + ); + +endmodule // hdpldadapt_avmmrst_ctl diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_hrdrst_clkctl.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_hrdrst_clkctl.v new file mode 100644 index 0000000..0f3a0a0 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_hrdrst_clkctl.v @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_hrdrst_clkctl +( + input wire aib_fabric_rx_sr_clk_in, + input wire aib_fabric_tx_sr_clk_in, + input wire csr_clk_in, + input wire r_avmm_hrdrst_osc_clk_scg_en, + input wire dft_adpt_aibiobsr_fastclkn, + input wire adapter_scan_mode_n, + input wire adapter_scan_shift_n, + input wire adapter_scan_shift_clk, + input wire adapter_scan_user_clk3, // 1GHz + input wire adapter_clk_sel_n, + input wire adapter_occ_enable, + output wire avmm_clock_reset_hrdrst_rx_osc_clk, + output wire avmm_clock_reset_hrdrst_tx_osc_clk, + output wire avmm_clock_hrdrst_rx_osc_clk, + output wire avmm_clock_hrdrst_tx_osc_clk, + output wire avmm_clock_csr_clk, + output wire avmm_clock_csr_clk_n, + output wire csr_clk_out +); + + //wire adapter_scan_mode; + wire adapter_scan_shift; + wire avmm_clock_dft_scg_bypass; + wire avmm_clock_dft_clk_sel_n; + wire avmm_clock_dft_occ_atpg_mode; + + wire avmm_clock_csr_clk_mux1; + wire avmm_clock_csr_clk_n_mux1; + wire csr_clk_in_n; + + wire avmm_clock_hrdrst_rx_osc_clk_mux1; + wire avmm_clock_hrdrst_rx_osc_clk_occ; + wire avmm_hrdrst_osc_clk_en; + + wire avmm_clock_hrdrst_tx_osc_clk_mux1; + wire avmm_clock_hrdrst_tx_osc_clk_occ; + + // DFX + //assign adapter_scan_mode = ~adapter_scan_mode_n; + assign adapter_scan_shift = ~adapter_scan_shift_n; + assign avmm_clock_dft_scg_bypass = ~dft_adpt_aibiobsr_fastclkn | ~adapter_scan_mode_n; + assign avmm_clock_dft_clk_sel_n = dft_adpt_aibiobsr_fastclkn & adapter_scan_mode_n; + + assign avmm_clock_dft_occ_atpg_mode = ~adapter_scan_mode_n; + + // Feedthrough + assign csr_clk_out = csr_clk_in; + +////////////////// +// Clock muxing // +////////////////// + +assign avmm_clock_csr_clk = avmm_clock_csr_clk_mux1; +assign avmm_clock_csr_clk_n = avmm_clock_csr_clk_n_mux1; + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_avmm_clock_csr_clk_mux1 + ( + .clk_o(avmm_clock_csr_clk_mux1), + .clk_0(adapter_scan_shift_clk), + .clk_1(csr_clk_in), + .clk_sel(adapter_scan_mode_n) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_avmm_clock_csr_clk_n_mux1 + ( + .clk_o(avmm_clock_csr_clk_n_mux1), + .clk_0(adapter_scan_shift_clk), + .clk_1(csr_clk_in_n), + .clk_sel(adapter_scan_mode_n) + ); + +hdpldadapt_cmn_clkinv hdpldadapt_cmn_clkinv_csr_clk_in_inv + ( + .clkout(csr_clk_in_n), + .clk(csr_clk_in) + ); + +////////// Rx Oscillator Clock ////////// + +assign avmm_clock_reset_hrdrst_rx_osc_clk = avmm_clock_hrdrst_rx_osc_clk_mux1; + +assign avmm_hrdrst_osc_clk_en = avmm_clock_dft_scg_bypass | ~r_avmm_hrdrst_osc_clk_scg_en; + +hdpldadapt_cmn_clkand2 hdpldadapt_cmn_clkand2_avmm_hrdrst_rx_osc_clk_scg + ( + .clkout(avmm_clock_hrdrst_rx_osc_clk), + .clk(avmm_clock_hrdrst_rx_osc_clk_mux1), + .en(avmm_hrdrst_osc_clk_en) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_avmm_hrdrst_rx_osc_clk_mux1 + ( + .clk_o(avmm_clock_hrdrst_rx_osc_clk_mux1), + .clk_0(avmm_clock_hrdrst_rx_osc_clk_occ), + .clk_1(aib_fabric_rx_sr_clk_in), + .clk_sel(avmm_clock_dft_clk_sel_n) + ); + +hdpldadapt_cmn_dft_clock_controller + #( + .CONTROL_REGISTER_PRESENT(1) + ) hdpldadapt_cmn_dft_clock_controller_avmm_hrdrst_rx_osc_clk_occ14 + ( + .user_clk(adapter_scan_user_clk3), //User clock + .test_clk(adapter_scan_shift_clk), //Test clock + .rst_n(1'b0), //Reset (active low) + .clk_sel_n(adapter_clk_sel_n), //Mux sel between user or test clock, Active low + .scan_enable(adapter_scan_shift), //Scan enable control signal, Active high in IP, Active low in top level + .occ_enable(adapter_occ_enable), //Control signal to enable OCC, Active high in IP, Active low in top level + .atpg_mode(avmm_clock_dft_occ_atpg_mode), //Control signal for test mode, Active high in IP, Active low in top level + .out_clk(avmm_clock_hrdrst_rx_osc_clk_occ) //Output clock + ); + +////////// Tx Oscillator Clock ////////// + +assign avmm_clock_reset_hrdrst_tx_osc_clk = avmm_clock_hrdrst_tx_osc_clk_mux1; + +hdpldadapt_cmn_clkand2 hdpldadapt_cmn_clkand2_avmm_hrdrst_tx_osc_clk_scg + ( + .clkout(avmm_clock_hrdrst_tx_osc_clk), + .clk(avmm_clock_hrdrst_tx_osc_clk_mux1), + .en(avmm_hrdrst_osc_clk_en) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_avmm_hrdrst_tx_osc_clk_mux1 + ( + .clk_o(avmm_clock_hrdrst_tx_osc_clk_mux1), + .clk_0(avmm_clock_hrdrst_tx_osc_clk_occ), + .clk_1(aib_fabric_tx_sr_clk_in), + .clk_sel(avmm_clock_dft_clk_sel_n) + ); + +hdpldadapt_cmn_dft_clock_controller + #( + .CONTROL_REGISTER_PRESENT(1) + ) hdpldadapt_cmn_dft_clock_controller_avmm_hrdrst_tx_osc_clk_occ15 + ( + .user_clk(adapter_scan_user_clk3), //User clock + .test_clk(adapter_scan_shift_clk), //Test clock + .rst_n(1'b0), //Reset (active low) + .clk_sel_n(adapter_clk_sel_n), //Mux sel between user or test clock, Active low + .scan_enable(adapter_scan_shift), //Scan enable control signal, Active high in IP, Active low in top level + .occ_enable(adapter_occ_enable), //Control signal to enable OCC, Active high in IP, Active low in top level + .atpg_mode(avmm_clock_dft_occ_atpg_mode), //Control signal for test mode, Active high in IP, Active low in top level + .out_clk(avmm_clock_hrdrst_tx_osc_clk_occ) //Output clock + ); + +endmodule // hdpldadapt_hrdrst_clkctl diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_hrdrst_rstctrl.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_hrdrst_rstctrl.v new file mode 100644 index 0000000..52db7e4 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_hrdrst_rstctrl.v @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_hrdrst_rstctrl +( + input wire csr_rdy_in, + input wire csr_rdy_dly_in, + input wire usermode_in, + input wire nfrzdrv_in, + input wire pr_channel_freeze_n, + input wire avmm_clock_reset_hrdrst_rx_osc_clk, + input wire avmm_clock_reset_hrdrst_tx_osc_clk, + input wire avmm_clock_hrdrst_rx_osc_clk, + //input wire aib_fabric_osc_dll_lock, + input wire sr_hssi_osc_transfer_en, + //input wire r_avmm_hrdrst_osc_dll_lock_bypass, + input wire adapter_scan_rst_n, + input wire adapter_scan_mode_n, + output wire csr_rdy_out, + output wire csr_rdy_dly_out, + output wire usermode_out, + output wire nfrzdrv_out, + //output reg aib_fabric_osc_dll_lock_req, + output wire aib_fabric_csr_rdy_dly_in, + output wire pld_hssi_osc_transfer_en, + output wire avmm_reset_hrdrst_rx_osc_clk_rst_n, + output wire avmm_reset_hrdrst_tx_osc_clk_rst_n, + output reg avmm_hrdrst_fabric_osc_transfer_en, + output wire avmm_hrdrst_testbus +); + + +/* +//******************************************************************** +// Define Parameters +//******************************************************************** + localparam WAIT_RX_OSC_CLK_READY = 2'b00; + localparam SEND_OCS_DLL_LOCK_REQ = 2'b01; + localparam WAIT_OSC_DLL_LOCK = 2'b10; + localparam OSC_TRANSFER_EN = 2'b11; + +//******************************************************************** +//******************************************************************** + + reg [1:0] osc_rst_sm_cs; + reg [1:0] osc_rst_sm_ns; + + reg avmm_hrdrst_osc_dll_lock_req_comb; + reg avmm_hrdrst_fabric_osc_transfer_en_comb; + + reg [3:0] avmm_hrdrst_counter; + reg avmm_hrdrst_counter_done; + reg avmm_hrdrst_reset_count; + reg avmm_hrdrst_count_wait_for_clk_rdy; +*/ + + wire int_avmm_hrd_rst_n; + wire frz_2one_by_nfrzdrv_or_pr_channel_freeze_n; + +//******************************************************************** +// Feedthrough +//******************************************************************** + assign csr_rdy_out = csr_rdy_in; + assign csr_rdy_dly_out = csr_rdy_dly_in; + assign aib_fabric_csr_rdy_dly_in = csr_rdy_dly_in; + assign usermode_out = usermode_in; + assign nfrzdrv_out = nfrzdrv_in; + +//******************************************************************** +// Reset Synchronizer +//******************************************************************** +assign int_avmm_hrd_rst_n = (adapter_scan_mode_n & csr_rdy_dly_in) | (~adapter_scan_mode_n & adapter_scan_rst_n); + +cdclib_rst_n_sync cdclib_rst_n_sync_avmm_hrdrst_rx_osc_clk + ( + .rst_n(int_avmm_hrd_rst_n), + .rst_n_bypass(adapter_scan_rst_n), + .clk (avmm_clock_reset_hrdrst_rx_osc_clk), + .scan_mode_n(adapter_scan_mode_n), + .rst_n_sync(avmm_reset_hrdrst_rx_osc_clk_rst_n) + ); + +cdclib_rst_n_sync cdclib_rst_n_sync_avmm_hrdrst_tx_osc_clk + ( + .rst_n(int_avmm_hrd_rst_n), + .rst_n_bypass(adapter_scan_rst_n), + .clk (avmm_clock_reset_hrdrst_tx_osc_clk), + .scan_mode_n(adapter_scan_mode_n), + .rst_n_sync(avmm_reset_hrdrst_tx_osc_clk_rst_n) + ); + +//******************************************************************** +// Test bus +//******************************************************************** +//assign avmm_hrdrst_testbus[3:0] = {avmm_hrdrst_fabric_osc_transfer_en,aib_fabric_osc_dll_lock_req,osc_rst_sm_cs[1:0]}; +assign avmm_hrdrst_testbus = avmm_hrdrst_fabric_osc_transfer_en; + +//******************************************************************** +// PLD +//******************************************************************** +assign frz_2one_by_nfrzdrv_or_pr_channel_freeze_n = ~(nfrzdrv_in & pr_channel_freeze_n); +assign pld_hssi_osc_transfer_en = frz_2one_by_nfrzdrv_or_pr_channel_freeze_n | sr_hssi_osc_transfer_en; + +//******************************************************************** +// Osc Reset State Machine Output +//******************************************************************** + +always @ (negedge avmm_reset_hrdrst_rx_osc_clk_rst_n or posedge avmm_clock_hrdrst_rx_osc_clk) +begin + if (~avmm_reset_hrdrst_rx_osc_clk_rst_n) + begin + avmm_hrdrst_fabric_osc_transfer_en <= 1'b0; + end + else + begin + avmm_hrdrst_fabric_osc_transfer_en <= sr_hssi_osc_transfer_en; + end + end +/* +//******************************************************************** +// Counters for Osc Reset SM +//******************************************************************** +always @ (negedge avmm_reset_hrdrst_rx_osc_clk_rst_n or posedge avmm_clock_hrdrst_rx_osc_clk) +begin + if (~avmm_reset_hrdrst_rx_osc_clk_rst_n) + begin + avmm_hrdrst_counter[3:0] <= 4'h0; + avmm_hrdrst_counter_done <= 1'b0; + end + else if (avmm_hrdrst_reset_count) + begin + avmm_hrdrst_counter[3:0] <= 4'h0; + avmm_hrdrst_counter_done <= 1'b0; + end + else + begin + avmm_hrdrst_counter <= avmm_hrdrst_counter + 4'h1; + if (~avmm_hrdrst_counter_done) + begin + if(avmm_hrdrst_count_wait_for_clk_rdy) + begin + avmm_hrdrst_counter_done <= (avmm_hrdrst_counter[3:0] == 4'b1000) ? 1'b1 : 1'b0; + end + end + end +end + +//******************************************************************** +// Osc Reset State Machine Output +//******************************************************************** + +always @ (negedge avmm_reset_hrdrst_rx_osc_clk_rst_n or posedge avmm_clock_hrdrst_rx_osc_clk) +begin + if (~avmm_reset_hrdrst_rx_osc_clk_rst_n) + begin + aib_fabric_osc_dll_lock_req <= 1'b0; + avmm_hrdrst_fabric_osc_transfer_en <= 1'b0; + end + else + begin + aib_fabric_osc_dll_lock_req <= avmm_hrdrst_osc_dll_lock_req_comb; + avmm_hrdrst_fabric_osc_transfer_en <= avmm_hrdrst_fabric_osc_transfer_en_comb; + end + end + +//******************************************************************** +// Osc Reset State Machine +//******************************************************************** +always @(negedge avmm_reset_hrdrst_rx_osc_clk_rst_n or posedge avmm_clock_hrdrst_rx_osc_clk) +begin + if (~avmm_reset_hrdrst_rx_osc_clk_rst_n) + begin + osc_rst_sm_cs <= WAIT_RX_OSC_CLK_READY; + end + else + begin + osc_rst_sm_cs <= osc_rst_sm_ns; + end +end + + +always @ (*) +begin + osc_rst_sm_ns = osc_rst_sm_cs; + avmm_hrdrst_osc_dll_lock_req_comb = 1'b0; + avmm_hrdrst_fabric_osc_transfer_en_comb = 1'b0; + avmm_hrdrst_reset_count = 1'b1; + avmm_hrdrst_count_wait_for_clk_rdy = 1'b0; + + case(osc_rst_sm_cs) + WAIT_RX_OSC_CLK_READY: + begin + avmm_hrdrst_reset_count = 1'b0; + avmm_hrdrst_count_wait_for_clk_rdy = 1'b1; + if(avmm_hrdrst_counter_done) + begin + osc_rst_sm_ns = SEND_OCS_DLL_LOCK_REQ; + end + end + + SEND_OCS_DLL_LOCK_REQ: + begin + avmm_hrdrst_osc_dll_lock_req_comb = 1'b1; + osc_rst_sm_ns = WAIT_OSC_DLL_LOCK; + end + + WAIT_OSC_DLL_LOCK: + begin + avmm_hrdrst_osc_dll_lock_req_comb = 1'b1; + if (sr_hssi_osc_transfer_en && (aib_fabric_osc_dll_lock || r_avmm_hrdrst_osc_dll_lock_bypass)) + begin + osc_rst_sm_ns = OSC_TRANSFER_EN; + end + end + + OSC_TRANSFER_EN: + begin + avmm_hrdrst_osc_dll_lock_req_comb = 1'b1; + avmm_hrdrst_fabric_osc_transfer_en_comb = 1'b1; + end + + default: + begin + osc_rst_sm_ns = WAIT_RX_OSC_CLK_READY; + avmm_hrdrst_osc_dll_lock_req_comb = 1'b0; + avmm_hrdrst_fabric_osc_transfer_en_comb = 1'b0; + avmm_hrdrst_reset_count = 1'b1; + avmm_hrdrst_count_wait_for_clk_rdy = 1'b0; + end + endcase + end +*/ + + +endmodule // hdpldadapt_hrdrst_rstctrl + diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_async_capture_bit.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_async_capture_bit.v new file mode 100644 index 0000000..9b8f774 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_async_capture_bit.v @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #5 $ +// Date: $Date: 2015/03/23 $ +//----------------------------------------------------------------------------- +// Description : Adpater async bit sampling +//----------------------------------------------------------------------------- +module hdpldadapt_cmn_async_capture_bit + #( + parameter RESET_VAL = 0, // 1: Active high; 0: Active low + parameter SYNC_STAGE = 4, + parameter CLK_FREQ_MHZ = 1, + parameter TOGGLE_TYPE = 1 // Toggle type: 1 --> 5 + + ) + ( + // Inputs + input wire clk, // clock + input wire rst_n, // async reset + input wire data_in, // data in + input wire unload, // unload data out + // Outputs + output wire data_in_sync_out, + output reg data_out // data out + ); + +//****************************************************************************** +// Define regs +//****************************************************************************** +reg data_in_sync_d0; +wire data_in_sync; +reg sample; + +localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0; // To eliminate truncating warning + + + +generate +if (SYNC_STAGE == 2) begin +cdclib_bitsync2 +#( +.DWIDTH (1'b1), // Sync Data input +.RESET_VAL (reset_value), // Reset value +.CLK_FREQ_MHZ (CLK_FREQ_MHZ), // Freq in MHz +.TOGGLE_TYPE (TOGGLE_TYPE), +.VID (1) +) +cdclib_bitsync2 + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in), + .data_out (data_in_sync) + ); +end +else begin +cdclib_bitsync4 +#( +.DWIDTH (1'b1), // Sync Data input +.RESET_VAL (reset_value), // Reset value +.CLK_FREQ_MHZ (CLK_FREQ_MHZ), // Freq in MHz +.TOGGLE_TYPE (TOGGLE_TYPE), +.VID (1) +) +cdclib_bitsync4 + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in), + .data_out (data_in_sync) + ); +end +endgenerate + +assign data_in_sync_out = data_in_sync; + +always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + begin + sample <= 1'b0; + data_out <= reset_value; + end + end + else begin + // No sample during unload + if (unload) begin + sample <= 1'b0; + end + // Sample on the first data change after unload + else if (sample == 1'b0 && data_in_sync != data_out) begin + sample <= 1'b1; + data_out <= data_in_sync; + end + end +end + +endmodule + diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_async_capture_bus.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_async_capture_bus.v new file mode 100644 index 0000000..ef8fb9b --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_async_capture_bus.v @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #5 $ +// Date: $Date: 2015/03/23 $ +//----------------------------------------------------------------------------- +// Description : Adpater async bus capture +//----------------------------------------------------------------------------- +module hdpldadapt_cmn_async_capture_bus + #( + parameter RESET_VAL = 1, // 1: Active high; 0: Active low + parameter DWIDTH = 2, // Sync Data input + parameter SYNC_STAGE = 4, + parameter CLK_FREQ_MHZ = 1, + parameter TOGGLE_TYPE = 1 // Toggle type: 1 --> 5 + ) + ( + // Inputs + input wire clk, // clock + input wire rst_n, // async reset + input wire [DWIDTH-1:0] data_in, // data in + input wire unload, // unload data out + input wire r_capt_mode, // capture mode + // Outputs + output reg [DWIDTH-1:0] data_out // data out + ); + +//****************************************************************************** +// Define regs +//****************************************************************************** +reg [DWIDTH-1:0] data_in_sync_d0; +reg [DWIDTH-1:0] data_in_sync_d1; +wire [DWIDTH-1:0] data_in_sync; +reg sample; + + localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0; // To eliminate truncating warning + + +generate +if (SYNC_STAGE == 2) begin +cdclib_bitsync2 +#( +.DWIDTH (DWIDTH), // Sync Data input +.RESET_VAL (reset_value), // Reset value +.CLK_FREQ_MHZ (CLK_FREQ_MHZ), // Freq in MHz +.TOGGLE_TYPE (TOGGLE_TYPE), +.VID (1) +) +cdclib_bitsync2 + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in), + .data_out (data_in_sync) + ); +end +else begin +cdclib_bitsync4 +#( +.DWIDTH (DWIDTH), // Sync Data input +.RESET_VAL (reset_value), // Reset value +.CLK_FREQ_MHZ (CLK_FREQ_MHZ), // Freq in MHz +.TOGGLE_TYPE (TOGGLE_TYPE), +.VID (1) +) +cdclib_bitsync4 + ( + .clk (clk), + .rst_n (rst_n), + .data_in (data_in), + .data_out (data_in_sync) + ); +end +endgenerate + + always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + begin + data_in_sync_d0 <= {DWIDTH{reset_value}}; + data_in_sync_d1 <= {DWIDTH{reset_value}}; + end + end + else begin + data_in_sync_d0 <= data_in_sync; + data_in_sync_d1 <= data_in_sync_d0; + end + end + + + + always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + begin + sample <= 1'b0; + data_out <= {DWIDTH{reset_value}}; + end + end + else begin + // No sample during unload + if (unload) begin + sample <= 1'b0; + end + // Sample on the first data change after unload + else begin + if (r_capt_mode) begin + if (~sample) + sample <= 1'b1; + data_out <= data_in_sync; + end + else begin + if (~sample && data_in_sync == data_in_sync_d0 && data_in_sync_d0 == data_in_sync_d1) begin + sample <= 1'b1; + data_out <= data_in_sync_d1; + end + end + + end + end + end + +endmodule + diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkand2.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkand2.v new file mode 100644 index 0000000..8ec27c8 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkand2.v @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_cmn_clkand2 +( + output wire clkout, + input wire clk, + input wire en +); + + assign clkout = clk & en; + +endmodule // hdpldadapt_cmn_clkand2 diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay.v new file mode 100644 index 0000000..3c695bc --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay.v @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_cmn_clkdelay +( + output wire clkout, + input wire rsel0, + input wire rsel1, + input wire rsel2, + input wire rsel3, + input wire rsel4, + input wire rsel5, + input wire rsel6, + input wire rsel7, + input wire rsel8, + input wire rsel9, + input wire rsel10, + input wire rsel11, + input wire rsel12, + input wire rsel13, + input wire rsel14, + input wire clk +); + +hdpldadapt_cmn_clkdelay_cell hdpldadapt_cmn_clkdelay_cell + ( + .rsel0(rsel0), + .rsel1(rsel1), + .rsel2(rsel2), + .rsel3(rsel3), + .rsel4(rsel4), + .rsel5(rsel5), + .rsel6(rsel6), + .rsel7(rsel7), + .rsel8(rsel8), + .rsel9(rsel9), + .rsel10(rsel10), + .rsel11(rsel11), + .rsel12(rsel12), + .rsel13(rsel13), + .rsel14(rsel14), + .clk(clk), + .clkout(clkout) + ); + +endmodule // hdpldadapt_cmn_clkdelay_cell diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay_cell.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay_cell.v new file mode 100644 index 0000000..bb043af --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay_cell.v @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_cmn_clkdelay_cell +( + output reg clkout, + input wire rsel0, + input wire rsel1, + input wire rsel2, + input wire rsel3, + input wire rsel4, + input wire rsel5, + input wire rsel6, + input wire rsel7, + input wire rsel8, + input wire rsel9, + input wire rsel10, + input wire rsel11, + input wire rsel12, + input wire rsel13, + input wire rsel14, + input wire clk +); + + wire clk_delay0; + wire clk_delay1; + wire clk_delay2; + wire clk_delay3; + wire clk_delay4; + wire clk_delay5; + wire clk_delay6; + wire clk_delay7; + wire clk_delay8; + wire clk_delay9; + wire clk_delay10; + wire clk_delay11; + wire clk_delay12; + wire clk_delay13; + wire clk_delay14; + wire clk_delay15; + + assign clk_delay0 = clk; + assign clk_delay1 = clk; + assign clk_delay2 = clk; + assign clk_delay3 = clk; + assign clk_delay4 = clk; + assign clk_delay5 = clk; + assign clk_delay6 = clk; + assign clk_delay7 = clk; + assign clk_delay8 = clk; + assign clk_delay9 = clk; + assign clk_delay10 = clk; + assign clk_delay11 = clk; + assign clk_delay12 = clk; + assign clk_delay13 = clk; + assign clk_delay14 = clk; + assign clk_delay15 = clk; + +always @* +begin + casez({rsel0,rsel1,rsel2,rsel3,rsel4,rsel5,rsel6,rsel7,rsel8,rsel9,rsel10,rsel11,rsel12,rsel13,rsel14}) + 15'b0??_????_????_????: clkout = clk_delay0; + 15'b10?_????_????_????: clkout = clk_delay1; + 15'b110_????_????_????: clkout = clk_delay2; + 15'b111_0???_????_????: clkout = clk_delay3; + 15'b111_10??_????_????: clkout = clk_delay4; + 15'b111_110?_????_????: clkout = clk_delay5; + 15'b111_1110_????_????: clkout = clk_delay6; + 15'b111_1111_0???_????: clkout = clk_delay7; + 15'b111_1111_10??_????: clkout = clk_delay8; + 15'b111_1111_110?_????: clkout = clk_delay9; + 15'b111_1111_1110_????: clkout = clk_delay10; + 15'b111_1111_1111_0???: clkout = clk_delay11; + 15'b111_1111_1111_10??: clkout = clk_delay12; + 15'b111_1111_1111_110?: clkout = clk_delay13; + 15'b111_1111_1111_1110: clkout = clk_delay14; + 15'b111_1111_1111_1111: clkout = clk_delay15; + default clkout = clk; + endcase + +end + + +endmodule // hdpldadapt_cmn_clkdelay_cell diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay_map.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay_map.v new file mode 100644 index 0000000..0d6f83e --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay_map.v @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_cmn_clkdelay_map +( + output wire clkout, + input wire [3:0] r_clk_delay_sel, + input wire clk +); + + reg [14:0] rsel; + wire rsel0; + wire rsel1; + wire rsel2; + wire rsel3; + wire rsel4; + wire rsel5; + wire rsel6; + wire rsel7; + wire rsel8; + wire rsel9; + wire rsel10; + wire rsel11; + wire rsel12; + wire rsel13; + wire rsel14; + +always @* +begin + case(r_clk_delay_sel) + 4'b0000: rsel = 15'b000_0000_0000_0000; + 4'b0001: rsel = 15'b000_0000_0000_0001; + 4'b0010: rsel = 15'b000_0000_0000_0011; + 4'b0011: rsel = 15'b000_0000_0000_0111; + 4'b0100: rsel = 15'b000_0000_0000_1111; + 4'b0101: rsel = 15'b000_0000_0001_1111; + 4'b0110: rsel = 15'b000_0000_0011_1111; + 4'b0111: rsel = 15'b000_0000_0111_1111; + 4'b1000: rsel = 15'b000_0000_1111_1111; + 4'b1001: rsel = 15'b000_0001_1111_1111; + 4'b1010: rsel = 15'b000_0011_1111_1111; + 4'b1011: rsel = 15'b000_0111_1111_1111; + 4'b1100: rsel = 15'b000_1111_1111_1111; + 4'b1101: rsel = 15'b001_1111_1111_1111; + 4'b1110: rsel = 15'b011_1111_1111_1111; + 4'b1111: rsel = 15'b111_1111_1111_1111; + default rsel = 15'b000_0000_0000_0000; + endcase + +end + +assign rsel0 = rsel[0]; +assign rsel1 = rsel[1]; +assign rsel2 = rsel[2]; +assign rsel3 = rsel[3]; +assign rsel4 = rsel[4]; +assign rsel5 = rsel[5]; +assign rsel6 = rsel[6]; +assign rsel7 = rsel[7]; +assign rsel8 = rsel[8]; +assign rsel9 = rsel[9]; +assign rsel10 = rsel[10]; +assign rsel11 = rsel[11]; +assign rsel12 = rsel[12]; +assign rsel13 = rsel[13]; +assign rsel14 = rsel[14]; + +hdpldadapt_cmn_clkdelay hdpldadapt_cmn_clkdelay + ( + .rsel0(rsel0), + .rsel1(rsel1), + .rsel2(rsel2), + .rsel3(rsel3), + .rsel4(rsel4), + .rsel5(rsel5), + .rsel6(rsel6), + .rsel7(rsel7), + .rsel8(rsel8), + .rsel9(rsel9), + .rsel10(rsel10), + .rsel11(rsel11), + .rsel12(rsel12), + .rsel13(rsel13), + .rsel14(rsel14), + .clk(clk), + .clkout(clkout) + ); + +endmodule // hdpldadapt_cmn_clkdelay_map diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkgate.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkgate.v new file mode 100644 index 0000000..1d2c390 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkgate.v @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_cmn_clkgate +( + input wire clk, + input wire en, + input wire te, + output wire clkout +); + + wire clk_n; + wire clken; + reg latch_clken; + + assign clk_n = ~clk; + assign clken = en || te; + + always @(clk_n or clken) + begin + if (clk_n) + begin + latch_clken <= clken; + end + end + + assign clkout = clk & latch_clken; + +endmodule // hdpldadapt_cmn_clkgate diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkinv.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkinv.v new file mode 100644 index 0000000..c3cd7b5 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkinv.v @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_cmn_clkinv +( + output wire clkout, + input wire clk +); + + assign clkout = ~clk; + +endmodule // hdpldadapt_cmn_clkinv diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkmux2.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkmux2.v new file mode 100644 index 0000000..89a4314 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkmux2.v @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_cmn_clkmux2 +( + output wire clk_o, + input wire clk_0, + input wire clk_1, + input wire clk_sel +); + +hdpldadapt_cmn_clkmux2_cell hdpldadapt_cmn_clkmux2_cell + ( + .s(clk_sel), + .clk2(clk_0), + .clk1(clk_1), + .clkout(clk_o) + ); + +endmodule // hdpldadapt_cmn_clkmux2 diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkmux2_cell.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkmux2_cell.v new file mode 100644 index 0000000..6c9c6e4 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkmux2_cell.v @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_cmn_clkmux2_cell +( + output wire clkout, + input wire clk2, + input wire clk1, + input wire s +); + + assign clkout = s ? clk1 : clk2; + +endmodule // hdpldadapt_cmn_clkmux2_cell diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkor2.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkor2.v new file mode 100644 index 0000000..d6c5796 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkor2.v @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_cmn_clkor2 +( + output wire clkout, + input wire clk, + input wire en +); + + assign clkout = clk | en; + +endmodule // hdpldadapt_cmn_clkor2 diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_comp_cntr.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_comp_cntr.v new file mode 100644 index 0000000..c699611 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_comp_cntr.v @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// (C) 2009 Altera Corporation. All rights reserved. +// +//------------------------------------------------------------------------ +// File: $RCSfile: hdpldadapt_cmn_cp_comp_cntr.v.rca $ +// Revision: $Revision: #4 $ +// Date: $Date: 2015/06/19 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ + +module hdpldadapt_cmn_cp_comp_cntr + #( + parameter CNTWIDTH = 'd8 + ) + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire srst_n, // async reset + input wire data_enable, // data enable / data valid + input wire master_in_en, + input wire us_tap_en, + input wire ds_tap_en, + input wire [1:0] r_compin_sel, // CRAM input select + input wire [CNTWIDTH-1:0] r_comp_cnt, // CRAM timeout value + output reg comp_cnt_match, // output signal for match + output wire compin_sel + ); + + localparam MASTER = 2'd0; + localparam SLAVE_ABOVE = 2'd1; + localparam SLAVE_BELOW = 2'd2; + + reg [CNTWIDTH-1:0] cnt, cnt_ns; + reg cnt_co; + reg cnt_enable; +// reg cnt_enable_reg; +// wire cnt_enable_neg_edge; + + always @* + begin + cnt_enable = master_in_en; + cnt_ns = cnt; + cnt_co = 1'b0; + comp_cnt_match = 1'b0; + + case (r_compin_sel) + MASTER: begin + cnt_enable = master_in_en; + end + SLAVE_ABOVE: begin + cnt_enable = us_tap_en; + end + SLAVE_BELOW: begin + cnt_enable = ds_tap_en; + end + default: begin + cnt_enable = master_in_en; + end + endcase // case(r_compin_sel) + + + if (cnt == r_comp_cnt && cnt_enable) + begin + comp_cnt_match = 1'b1; + end + else if (data_enable && cnt_enable && cnt != r_comp_cnt) + begin + {cnt_co,cnt_ns} = cnt + 1'b1; + end + + end // always @ * + +assign compin_sel = cnt_enable; + +// always @(negedge rst_n or posedge clk) +// begin +// if (~rst_n) +// begin +// cnt_enable_reg <= 1'b0; +// end +// else if (~srst_n) +// begin +// cnt_enable_reg <= 1'b0; +// end +// else +// begin +// cnt_enable_reg <= cnt_enable; +// end +// end // always @ (negedge rst_n or posedge clk) + +//assign cnt_enable_neg_edge = ~cnt_enable && cnt_enable_reg; + + always @(negedge rst_n or posedge clk) + begin + if (~rst_n) + begin + cnt <= {CNTWIDTH{1'b0}}; + end +// else if (~srst_n || cnt_enable_neg_edge) + else if (~srst_n) + begin + cnt <= {CNTWIDTH{1'b0}}; + end + else + begin + cnt <= cnt_ns; + end + end // always @ (negedge rst_n or posedge clk) + +endmodule // hdpldadapt_cmn_cp_comp_cntr diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist.v new file mode 100644 index 0000000..a2268df --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist.v @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// (C) 2009 Altera Corporation. All rights reserved. +// +//------------------------------------------------------------------------ +// File: $RCSfile: hdpldadapt_cmn_cp_dist.v.rca $ +// Revision: $Revision: #2 $ +// Date: $Date: 2014/09/05 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ + + +module hdpldadapt_cmn_cp_dist + #( + parameter ASYNC_RESET_VAL = 'd0, // Asynchronous reset value + parameter WIDTH = 'd1 // Control width + ) + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire srst_n, // sync reset + input wire data_enable, // data enable / data valid + input wire [WIDTH-1:0] master_in, // master control signal + input wire [WIDTH-1:0] dist_in, // CP distributed signal in + input wire r_dist_master, // CRAM to control master or distributed + input wire r_dist_bypass_pipeln, // CRAM combo or registered + output wire [WIDTH-1:0] dist_out, // CP distributed signal out + output wire [WIDTH-1:0] dist_tap // CP output for this channel + ); + + reg [WIDTH-1:0] dist_1; + reg [WIDTH-1:0] dist_2; + + reg [WIDTH-1:0] dist_1_in; + reg [WIDTH-1:0] dist_2_in; + reg [WIDTH-1:0] dist_1_out; + reg [WIDTH-1:0] dist_2_out; + + + // module outputs + assign dist_tap = dist_1_out; + assign dist_out = dist_2_out; + + + always @* + begin + // default FF inputs to FF outputs + dist_1_in = dist_1; + dist_2_in = dist_2; + + // default stage outputs to FF outputs + dist_1_out = dist_1; + dist_2_out = dist_2; + + // set FF inputs + if (data_enable) + begin + dist_1_in = dist_in; + if (r_dist_master) + begin + dist_2_in = master_in; + end + else + begin + dist_2_in = dist_1_out; + end + end // if (data_enable) + + // set stage outputs + if (r_dist_bypass_pipeln) + begin + dist_1_out = dist_in; + if (r_dist_master) + begin + dist_2_out = master_in; + end + else + begin + dist_2_out = dist_1_out; + end + end // if (r_dist_bypass_pipeln) + else + begin + dist_1_out = dist_1; + dist_2_out = dist_2; + end + + end // always @ * + + + always @(negedge rst_n or posedge clk) + begin + if (~rst_n) + begin + dist_1 <= {WIDTH{ASYNC_RESET_VAL}}; + dist_2 <= {WIDTH{ASYNC_RESET_VAL}}; + end + else if (~srst_n) + begin + dist_1 <= {WIDTH{ASYNC_RESET_VAL}}; + dist_2 <= {WIDTH{ASYNC_RESET_VAL}}; + end + else + begin + dist_1 <= dist_1_in; + dist_2 <= dist_2_in; + end + end // always @ (negedge rst_n or posedge clk) + + +endmodule // hdpldadapt_cmn_cp_dist + + + diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_dw.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_dw.v new file mode 100644 index 0000000..0ed192e --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_dw.v @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// (C) 2009 Altera Corporation. All rights reserved. +// +//------------------------------------------------------------------------ +// File: $RCSfile: hdpldadapt_cmn_cp_dist.v.rca $ +// Revision: $Revision: #2 $ +// Date: $Date: 2014/09/05 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ + + +module hdpldadapt_cmn_cp_dist_dw + #( + parameter ASYNC_RESET_VAL = 'd0, // Asynchronous reset value + parameter WIDTH = 'd1 // Control width + ) + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire srst_n, // sync reset + input wire data_enable, // data enable / data valid + input wire [WIDTH-1:0] master_in, // master control signal + input wire [WIDTH-1:0] dist_in, // CP distributed signal in + input wire r_dist_master, // CRAM to control master or distributed + input wire r_dist_bypass_pipeln, // CRAM combo or registered + input wire r_double_en, // CRAM double mode enable + output wire [WIDTH-1:0] dist_out, // CP distributed signal out + output wire [WIDTH-1:0] dist_tap // CP output for this channel + ); + + reg [WIDTH-1:0] dist_1; + reg [WIDTH-1:0] dist_2; + reg [WIDTH-1:0] dist_1_reg; + reg [WIDTH-1:0] dist_2_reg; + + reg [WIDTH-1:0] dist_1_in; + reg [WIDTH-1:0] dist_2_in; + reg [WIDTH-1:0] dist_1_out; + reg [WIDTH-1:0] dist_2_out; + reg [WIDTH-1:0] dist_1_reg_in; + reg [WIDTH-1:0] dist_2_reg_in; + + + // module outputs + assign dist_tap = dist_1_out; + assign dist_out = dist_2_out; + + + always @* + begin + // default FF inputs to FF outputs + dist_1_in = dist_1; + dist_2_in = dist_2; + + dist_1_reg_in = dist_1_reg; + dist_2_reg_in = dist_2_reg; + + // default stage outputs to FF outputs + dist_1_out = dist_1; + dist_2_out = dist_2; + + // set FF inputs + if (data_enable) + begin + dist_1_in = dist_in; + dist_1_reg_in = dist_1; + dist_2_reg_in = dist_2; + if (r_dist_master) + begin + dist_2_in = master_in; + end + else + begin + dist_2_in = r_double_en ? dist_1_reg : dist_1; + end + end // if (data_enable) + + // set stage outputs + if (r_dist_bypass_pipeln) + begin + dist_1_out = dist_in; + if (r_dist_master) + begin + dist_2_out = master_in; + end + else + begin + dist_2_out = dist_1_out; + end + end // if (r_dist_bypass_pipeln) + else if (r_double_en) + begin + dist_1_out = dist_1_reg; + dist_2_out = dist_2_reg; + end + else + begin + dist_1_out = dist_1; + dist_2_out = dist_2; + end + + + end // always @ * + + + always @(negedge rst_n or posedge clk) + begin + if (~rst_n) + begin + dist_1 <= {WIDTH{ASYNC_RESET_VAL}}; + dist_1_reg <= {WIDTH{ASYNC_RESET_VAL}}; + dist_2 <= {WIDTH{ASYNC_RESET_VAL}}; + dist_2_reg <= {WIDTH{ASYNC_RESET_VAL}}; + end + else if (~srst_n) + begin + dist_1 <= {WIDTH{ASYNC_RESET_VAL}}; + dist_1_reg <= {WIDTH{ASYNC_RESET_VAL}}; + dist_2 <= {WIDTH{ASYNC_RESET_VAL}}; + dist_2_reg <= {WIDTH{ASYNC_RESET_VAL}}; + end + else + begin + dist_1 <= dist_1_in; + dist_1_reg <= dist_1_reg_in; + dist_2 <= dist_2_in; + dist_2_reg <= dist_2_reg_in; + end + end // always @ (negedge rst_n or posedge clk) + + +endmodule // hdpldadapt_cmn_cp_dist + + + diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_pair.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_pair.v new file mode 100644 index 0000000..4f729de --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_pair.v @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// (C) 2009 Altera Corporation. All rights reserved. +// +//------------------------------------------------------------------------ +// File: $RCSfile: hdpldadapt_cmn_cp_dist_pair.v.rca $ +// Revision: $Revision: #2 $ +// Date: $Date: 2014/09/05 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ + + +module hdpldadapt_cmn_cp_dist_pair + #( + parameter ASYNC_RESET_VAL = 'd0, // Asynchronous reset value + parameter WIDTH = 'd1 // Control width + ) + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire srst_n, // sync reset + input wire data_enable, // data enable / data valid + input wire [WIDTH-1:0] master_in, // master control signal + input wire [WIDTH-1:0] us_in, // CP distributed signal in up + input wire [WIDTH-1:0] ds_in, // CP distributed signal in dwn + input wire r_us_master, // CRAM to control master or distributed up + input wire r_ds_master, // CRAM to control master or distributed dwn + input wire r_us_bypass_pipeln, // CRAM combo or registered up + input wire r_ds_bypass_pipeln, // CRAM combo or registered dwn + output wire [WIDTH-1:0] us_out, // CP distributed signal out up + output wire [WIDTH-1:0] ds_out, // CP distributed signal out dwn + output wire [WIDTH-1:0] ds_tap, // CP output for this channel dwn + output wire [WIDTH-1:0] us_tap // CP output for this channel up + ); + + hdpldadapt_cmn_cp_dist + #( + .ASYNC_RESET_VAL (ASYNC_RESET_VAL), + .WIDTH (WIDTH) + ) + hdpldadapt_cmn_cp_dist_dwn + ( + .clk (clk), + .rst_n (rst_n), + .srst_n (srst_n), + .data_enable (data_enable), + .master_in (master_in), + .dist_in (us_in), + .r_dist_master (r_ds_master), + .r_dist_bypass_pipeln (r_ds_bypass_pipeln), + .dist_out (ds_out), + .dist_tap (ds_tap) + ); + + hdpldadapt_cmn_cp_dist + #( + .ASYNC_RESET_VAL (ASYNC_RESET_VAL), + .WIDTH (WIDTH) + ) + hdpldadapt_cmn_cp_dist_up + ( + .clk (clk), + .rst_n (rst_n), + .srst_n (srst_n), + .data_enable (data_enable), + .master_in (master_in), + .dist_in (ds_in), + .r_dist_master (r_us_master), + .r_dist_bypass_pipeln (r_us_bypass_pipeln), + .dist_out (us_out), + .dist_tap (us_tap) + ); + + +endmodule // hdpldadapt_cmn_cp_dist_pair + + + + + diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_pair_dw.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_pair_dw.v new file mode 100644 index 0000000..cdf6b9b --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_pair_dw.v @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// (C) 2009 Altera Corporation. All rights reserved. +// +//------------------------------------------------------------------------ +// File: $RCSfile: hdpldadapt_cmn_cp_dist_pair.v.rca $ +// Revision: $Revision: #2 $ +// Date: $Date: 2014/09/05 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ + + +module hdpldadapt_cmn_cp_dist_pair_dw + #( + parameter ASYNC_RESET_VAL = 'd0, // Asynchronous reset value + parameter WIDTH = 'd1 // Control width + ) + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire srst_n, // sync reset + input wire data_enable, // data enable / data valid + input wire [WIDTH-1:0] master_in, // master control signal + input wire [WIDTH-1:0] us_in, // CP distributed signal in up + input wire [WIDTH-1:0] ds_in, // CP distributed signal in dwn + input wire r_us_master, // CRAM to control master or distributed up + input wire r_ds_master, // CRAM to control master or distributed dwn + input wire r_us_bypass_pipeln, // CRAM combo or registered up + input wire r_ds_bypass_pipeln, // CRAM combo or registered dwn + input wire r_double_en, // CRAM double mode enable + output wire [WIDTH-1:0] us_out, // CP distributed signal out up + output wire [WIDTH-1:0] ds_out, // CP distributed signal out dwn + output wire [WIDTH-1:0] ds_tap, // CP output for this channel dwn + output wire [WIDTH-1:0] us_tap // CP output for this channel up + ); + + hdpldadapt_cmn_cp_dist_dw + #( + .ASYNC_RESET_VAL (ASYNC_RESET_VAL), + .WIDTH (WIDTH) + ) + hdpldadapt_cmn_cp_dist_dw_dwn + ( + .clk (clk), + .rst_n (rst_n), + .srst_n (srst_n), + .data_enable (data_enable), + .master_in (master_in), + .dist_in (us_in), + .r_dist_master (r_ds_master), + .r_dist_bypass_pipeln (r_ds_bypass_pipeln), + .r_double_en (r_double_en), + .dist_out (ds_out), + .dist_tap (ds_tap) + ); + + hdpldadapt_cmn_cp_dist_dw + #( + .ASYNC_RESET_VAL (ASYNC_RESET_VAL), + .WIDTH (WIDTH) + ) + hdpldadapt_cmn_cp_dist_dw_up + ( + .clk (clk), + .rst_n (rst_n), + .srst_n (srst_n), + .data_enable (data_enable), + .master_in (master_in), + .dist_in (ds_in), + .r_dist_master (r_us_master), + .r_dist_bypass_pipeln (r_us_bypass_pipeln), + .r_double_en (r_double_en), + .dist_out (us_out), + .dist_tap (us_tap) + ); + + +endmodule // hdpldadapt_cmn_cp_dist_pair + + + + + diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_dft_clock_controller.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_dft_clock_controller.v new file mode 100644 index 0000000..eca0d0b --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_dft_clock_controller.v @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// DFT_clock_controller.v +// +// Clock switch-over between func clock and test clock +// Provide burst counter support (use gray-code counter) + +module hdpldadapt_cmn_dft_clock_controller ( + user_clk, //User clock + test_clk, //Test clock + rst_n, //Reset (active low) + clk_sel_n, //Mux sel between user or test clock, Active low + scan_enable, //Scan enable control signal, Active high in IP, Active low in top level + occ_enable, //Control signal to enable OCC, Active high in IP, Active low in top level + atpg_mode, //Control signal for test mode, Active high in IP, Active low in top level + out_clk //Output clock +); + +parameter CONTROL_REGISTER_PRESENT = 0; + +input user_clk; +input test_clk; +input rst_n; +input clk_sel_n; +input scan_enable; +input atpg_mode; +input occ_enable; +output out_clk; + +wire int_test_clk; +wire int_user_clk; +wire [1:0] burst_cnt; //may required more bus width if more pulse needed. Current is 2 pulses +wire clk_sel; +wire occ_enable_nand; +wire occ_user_clken; +wire occ_rst_n; + +//Inversion for the clock selection control signal +assign clk_sel = ~clk_sel_n; + +// Reset logic +assign occ_rst_n = (atpg_mode == 1'b1)? 1'b1 : rst_n; + + +// clock mux (between user and test clock) - use clock MUX +//altr_hps_ckmux21 altr_ckmux21_inst( +hdpldadapt_cmn_clkmux2 altr_ckmux21_inst( + .clk_0 (int_user_clk), + .clk_1 (int_test_clk), + .clk_sel (clk_sel), + .clk_o (out_clk) +); + +// scan control registers +hdpldadapt_cmn_occ_test_control_register ctrl_reg ( + .clk (test_clk), + .rst_n (occ_rst_n), + .ctrl (burst_cnt) +// .clken (test_clk_en) +); + +//test clock enable +generate +if(CONTROL_REGISTER_PRESENT == 1) begin : CONTROL_REG + reg test_clken /* synopsys preserve_sequential */; + always @(posedge test_clk) + test_clken <= test_clken; + + //altr_hps_clkgate altr_clkgate_test_inst( + hdpldadapt_cmn_occ_clkgate altr_clkgate_test_inst ( + .clk (test_clk), + .clk_enable_i (test_clken), + .clk_o (int_test_clk) + ); +end +else begin + assign int_test_clk = test_clk; +end + +endgenerate + +// user clock enable +//altr_hps_clkgate altr_clkgate_user_inst( +hdpldadapt_cmn_occ_clkgate altr_clkgate_user_inst( + .clk (user_clk), + .clk_enable_i (occ_user_clken), + .clk_o (int_user_clk) +); + +hdpldadapt_cmn_occ_enable_logic occ_enable_logic_inst( + + .user_clk (user_clk), + .scan_enable (scan_enable), + .occ_enable (occ_enable), + .atpg_mode (atpg_mode), + .burst_cnt (burst_cnt), + .occ_user_clken (occ_user_clken) +); + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_latency_measure.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_latency_measure.v new file mode 100644 index 0000000..d25dbf1 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_latency_measure.v @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_cmn_latency_measure + ( + // Inputs + input wire s_clk, // clock + input wire s_rst_n, // async reset + input wire [2:0] r_fifo_power_mode, + input wire wr_addr_msb, // Write address MSB + input wire rd_addr_msb, // Read address MSB + input wire ps_wr_addr_msb, // Write address MSB + input wire ps_rd_addr_msb, // Read address MSB + input wire ps_dw_wr_addr_msb, // Write address MSB + input wire ps_dw_rd_addr_msb, // Read address MSB + + // Outputs + output reg latency_pulse // Latency pulse + ); + + +wire rd_addr_msb_sync; +wire wr_addr_msb_sync; + +wire ps_rd_addr_msb_sync; +wire ps_wr_addr_msb_sync; + +wire ps_dw_rd_addr_msb_sync; +wire ps_dw_wr_addr_msb_sync; + +cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .CLK_FREQ_MHZ(500), + .TOGGLE_TYPE (2), + .RESET_VAL (0) // Reset Value + ) + cdclib_bitsync2_wr + ( + .clk (s_clk), + .rst_n (s_rst_n), + .data_in (wr_addr_msb), + .data_out (wr_addr_msb_sync) + ); + +cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .CLK_FREQ_MHZ(500), + .TOGGLE_TYPE (2), + .RESET_VAL (0) // Reset Value + ) + cdclib_bitsync2_rd + ( + .clk (s_clk), + .rst_n (s_rst_n), + .data_in (rd_addr_msb), + .data_out (rd_addr_msb_sync) + ); + + +cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .CLK_FREQ_MHZ(500), + .TOGGLE_TYPE (2), + .RESET_VAL (0) // Reset Value + ) + hd_dpcmn_bitsync2_ps_wr_msb + ( + .clk (s_clk), + .rst_n (s_rst_n), + .data_in (ps_wr_addr_msb), + .data_out (ps_wr_addr_msb_sync) + ); + +cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .CLK_FREQ_MHZ(500), + .TOGGLE_TYPE (2), + .RESET_VAL (0) // Reset Value + ) + hd_dpcmn_bitsync2_ps_rd_msb + ( + .clk (s_clk), + .rst_n (s_rst_n), + .data_in (ps_rd_addr_msb), + .data_out (ps_rd_addr_msb_sync) + ); + +cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .CLK_FREQ_MHZ(500), + .TOGGLE_TYPE (2), + .RESET_VAL (0) // Reset Value + ) + hd_dpcmn_bitsync2_ps_dw_wr_msb + ( + .clk (s_clk), + .rst_n (s_rst_n), + .data_in (ps_dw_wr_addr_msb), + .data_out (ps_dw_wr_addr_msb_sync) + ); + +cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .CLK_FREQ_MHZ(500), + .TOGGLE_TYPE (2), + .RESET_VAL (0) // Reset Value + ) + hd_dpcmn_bitsync2_ps_dw_rd_msb + ( + .clk (s_clk), + .rst_n (s_rst_n), + .data_in (ps_dw_rd_addr_msb), + .data_out (ps_dw_rd_addr_msb_sync) + ); + +always @(negedge s_rst_n or posedge s_clk) begin + if (~s_rst_n) begin + latency_pulse <= 1'b0; + end + else begin + latency_pulse <= r_fifo_power_mode[2] ? wr_addr_msb_sync ^ rd_addr_msb_sync : r_fifo_power_mode[1] ? ps_dw_wr_addr_msb_sync ^ ps_dw_rd_addr_msb_sync : ps_wr_addr_msb_sync ^ ps_rd_addr_msb_sync ; + end +end + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_clkgate.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_clkgate.v new file mode 100644 index 0000000..fad655e --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_clkgate.v @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_cmn_occ_clkgate +( + input wire clk, + input wire clk_enable_i, + output wire clk_o +); + +hdpldadapt_cmn_clkgate hdpldadapt_cmn_clkgate + ( + .clk(clk), + .en(clk_enable_i), + .te(1'b0), + .clkout(clk_o) + ); + +endmodule // hdpldadapt_cmn_occ_clkgate diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_enable_logic.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_enable_logic.v new file mode 100644 index 0000000..7e0b1e8 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_enable_logic.v @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//On chip clock controller enable logic + +module hdpldadapt_cmn_occ_enable_logic( + + user_clk, + scan_enable, + occ_enable, + atpg_mode, + burst_cnt, + occ_user_clken +); + +input user_clk; +input scan_enable; +input atpg_mode; +input occ_enable; +input [1:0] burst_cnt; +output occ_user_clken; + +wire [1:0] gc_counter; +wire cmp; +wire reset; +reg occ_user_clk_en_reg; +wire occ_user_clk_en_buf; +wire sync_out; +wire scan_enable; +wire atpg_mode; +wire occ_enable; +wire occ_clken; +wire gc_counter_en; +reg enable_reg; + +//Inversion for all the control signal +//assign scan_enable = ~scan_enable_n; +//assign atpg_mode = ~atpg_mode_n; +//assign occ_enable = ~occ_enable_n; + +assign reset = ~scan_enable; +assign cmp = |(gc_counter ^ burst_cnt); //comparison of the gc counter versus the burst cnt +assign gc_counter_en = sync_out & cmp; //enabling the gc counter +assign occ_user_clken = (atpg_mode == 1'b1)? occ_user_clk_en_reg : 1'b1; + + + +always @(posedge occ_enable or negedge reset) +begin + if(~reset) + enable_reg <= 1'b0; + else + enable_reg <= 1'b1; +end + + +always @(posedge user_clk or negedge reset ) +begin + if(~reset) + occ_user_clk_en_reg <= 1'b0; + else + occ_user_clk_en_reg <= gc_counter_en; +end + +//sycnronization register +//altr_hps_bitsync4 altr_bitsync4_inst( +cdclib_bitsync4 +#( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset value + .CLK_FREQ_MHZ(1000), // Clock frequency (in MHz) + .TOGGLE_TYPE (2), // Toggle type: 1 --> 5 + .VID (1) // 1: VID, 0: preVID + +) altr_bitsync4_inst ( + .clk (user_clk), + .rst_n (reset), + .data_in (enable_reg), + .data_out (sync_out) +); + +//gray code counter +hdpldadapt_cmn_occ_gray_code_counter counter_inst ( + .clk (user_clk), + .rst_n (reset), + .en (gc_counter_en), + .cout (gc_counter) +); + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_gray_code_counter.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_gray_code_counter.v new file mode 100644 index 0000000..2e13a40 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_gray_code_counter.v @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//gray code counter +module hdpldadapt_cmn_occ_gray_code_counter ( + clk, + rst_n, + en, + cout +); + + +input clk; +input rst_n; +input en; +output [1:0] cout; + +reg [1:0] counter_reg; + +always @(posedge clk or negedge rst_n) +begin + if(rst_n == 1'b0) + counter_reg <= 2'b00; + else + begin + if(en == 1'b1) + counter_reg <= counter_reg + 1; + else + counter_reg <= counter_reg; + end +end + +// need auto-code generator for different WIDTH +assign cout = {counter_reg[1],counter_reg[1]^counter_reg[0]}; + +endmodule + diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_test_control_register.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_test_control_register.v new file mode 100644 index 0000000..36aec77 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_test_control_register.v @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//test control register (clock chain) +module hdpldadapt_cmn_occ_test_control_register ( + clk, + rst_n, + ctrl +// clken +); + +input clk; +input rst_n; +output [1:0] ctrl; +//output clken; + +// test clock enable +//reg clken /* synopsys preserve_sequential */; + +//always @(posedge clk) +//begin +// clken <= clken; +//end + +// counter logic +reg [1:0] ctrl /* synopsys preserve_sequential */; + +always @(posedge clk or negedge rst_n) +begin + if(rst_n == 1'b0) + ctrl <= 2'b00; + else + ctrl <= ctrl; +end + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_parity_checker.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_parity_checker.v new file mode 100644 index 0000000..edb420c --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_parity_checker.v @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_cmn_parity_checker + #( + parameter WIDTH = 'd0 + ) + ( + output reg parity_error, + input wire clk, + input wire rst_n, + input wire [WIDTH-1:0] data, + input wire parity_checker_ena, + input wire parity_received + ); + + wire parity_calculated; + + assign parity_calculated = ^data[WIDTH-1:0]; + + always @(negedge rst_n or posedge clk) + begin + if (~rst_n) + begin + parity_error <= 1'b0; + end + else + begin + parity_error <= parity_error || ( (parity_calculated != parity_received) && parity_checker_ena); + end + end + +endmodule // hdpldadapt_cmn_parity_checker diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_parity_gen.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_parity_gen.v new file mode 100644 index 0000000..959ade5 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_parity_gen.v @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_cmn_parity_gen + #( + parameter WIDTH = 'd0 + ) + ( + output wire parity, + input wire [WIDTH-1:0] data + ); + + assign parity = ^data[WIDTH-1:0]; + +endmodule // hdpldadapt_cmn_parity_gen diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_pulse_stretch.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_pulse_stretch.v new file mode 100644 index 0000000..d58a02d --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_pulse_stretch.v @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// (C) 2009 Altera Corporation. All rights reserved. +// +//------------------------------------------------------------------------ +// File: $RCSfile: hdpldadapt_cmn_pulse_stretch.v.rca $ +// Revision: $Revision: #1 $ +// Date: $Date: 2014/09/23 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ + +module hdpldadapt_cmn_pulse_stretch + #( + parameter RESET_VAL = 'd0 // reset value + ) + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire [2:0] num_stages, // number of stages required + input wire data_in, // data in + output reg data_out // stretched data out + ); + + reg data_d1, data_d2, data_d3, data_d4; + reg data_d5, data_d6, data_d7; + reg data_out_comb; + + localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0; // To eliminate truncating warning + + always @* begin + data_out_comb = data_in; + + case (num_stages) + 3'b000: data_out_comb = data_in; + 3'b001: data_out_comb = data_d1 | data_in; + 3'b010: data_out_comb = data_d2 | data_d1 | data_in; + 3'b011: data_out_comb = data_d3 | data_d2 | data_d1 | data_in; + 3'b100: data_out_comb = data_d4 | data_d3 | data_d2 | data_d1 | data_in; + 3'b101: data_out_comb = data_d5 | data_d4 | data_d3 | data_d2 | data_d1 | data_in; + 3'b110: data_out_comb = data_d6 | data_d5 | data_d4 | data_d3 | data_d2 | data_d1 | data_in; + 3'b111: data_out_comb = data_d7 | data_d6 | data_d5 | data_d4 | data_d3 | data_d2 | data_d1 | data_in; + default: data_out_comb = data_in; + endcase // case(num_stages) + end // always @ * + + always @(negedge rst_n or posedge clk) begin + if (~rst_n) begin + data_d1 <= reset_value; + data_d2 <= reset_value; + data_d3 <= reset_value; + data_d4 <= reset_value; + data_d5 <= reset_value; + data_d6 <= reset_value; + data_d7 <= reset_value; + data_out <= reset_value; + end + else begin + data_d1 <= data_in; + data_d2 <= data_d1; + data_d3 <= data_d2; + data_d4 <= data_d3; + data_d5 <= data_d4; + data_d6 <= data_d5; + data_d7 <= data_d6; + data_out <= data_out_comb; + end + end // always @ (negedge rst_n or posedge clk) + +endmodule // hdpldadapt_cmn_pulse_stretch diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async.v new file mode 100644 index 0000000..6e4cb53 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async.v @@ -0,0 +1,370 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_rx_async ( +// DPRIO +input wire r_rx_async_pld_ltr_rst_val, +input wire r_rx_async_pld_pma_ltd_b_rst_val, +input wire r_rx_async_pld_8g_signal_detect_out_rst_val, +input wire r_rx_async_pld_10g_rx_crc32_err_rst_val, +input wire r_rx_async_pld_rx_fifo_align_clr_rst_val, +input wire r_rx_async_prbs_flags_sr_enable, +input wire r_rx_pld_8g_eidleinfersel_polling_bypass, +input wire r_rx_pld_pma_eye_monitor_polling_bypass, +input wire r_rx_pld_pma_pcie_switch_polling_bypass, +input wire r_rx_pld_pma_reser_out_polling_bypass, + +input wire nfrzdrv_in, +input wire usermode_in, + +// PLD IF +input wire pr_channel_freeze_n, +input wire pld_ltr, +input wire pld_pma_ltd_b, +input wire pld_10g_krfec_rx_clr_errblk_cnt, +input wire pld_10g_rx_clr_ber_count, +input wire pld_8g_a1a2_size, +input wire pld_8g_bitloc_rev_en, +input wire pld_8g_byte_rev_en, +input wire [2:0] pld_8g_eidleinfersel, +input wire pld_8g_encdt, +input wire pld_bitslip, +input wire pld_pma_adapt_start, +input wire pld_pma_early_eios, +input wire [5:0] pld_pma_eye_monitor, +input wire [1:0] pld_pma_pcie_switch, +input wire pld_pma_ppm_lock, +input wire [4:0] pld_pma_reserved_out, +input wire pld_pma_rs_lpbk_b, +input wire pld_pmaif_rxclkslip, +input wire pld_polinv_rx, +input wire pld_rx_prbs_err_clr, +input wire pld_syncsm_en, +input wire pld_rx_fabric_fifo_align_clr, +input wire pld_rx_dll_lock_req, +input wire pld_rx_fifo_latency_adj_en, +input wire pld_aib_hssi_rx_dcd_cal_req, +input wire [1:0] pld_rx_ssr_reserved_in, + +// RXRST_CTL +input wire rx_reset_async_rx_osc_clk_rst_n, +input wire rx_reset_async_tx_osc_clk_rst_n, + +// RXCLK_CTL +input wire rx_clock_async_rx_osc_clk, +input wire rx_clock_async_tx_osc_clk, + +// SR +input wire rx_async_hssi_fabric_fsr_load, +input wire rx_async_hssi_fabric_ssr_load, +input wire [1:0] rx_async_hssi_fabric_fsr_data, +input wire [62:0] rx_async_hssi_fabric_ssr_data, +input wire rx_async_fabric_hssi_fsr_load, +input wire rx_async_fabric_hssi_ssr_load, +input wire [1:0] rx_async_hssi_fabric_ssr_reserved, +input wire [19:0] sr_testbus, + +// AIB IF +input wire aib_fabric_pld_8g_rxelecidle, +input wire aib_fabric_pld_pma_rxpll_lock, +input wire aib_fabric_pld_pma_pfdmode_lock, + +// Reset SM +input wire rx_hrdrst_fabric_rx_dll_lock, +input wire rx_hrdrst_fabric_rx_transfer_en, + +// RX FIFO +//input wire [1:0] pld_rx_fabric_data_out, + +// PLD IF +output wire pld_pma_pfdmode_lock, +output wire pld_8g_rxelecidle, +output wire pld_pma_rxpll_lock, +output wire pld_8g_signal_detect_out, +output wire pld_10g_krfec_rx_blk_lock, +output wire [1:0] pld_10g_krfec_rx_diag_data_status, +output wire pld_10g_rx_crc32_err, +output wire pld_10g_rx_frame_lock, +output wire pld_10g_rx_hi_ber, +output wire [3:0] pld_8g_a1a2_k1k2_flag, +output wire pld_8g_empty_rmf, +output wire pld_8g_full_rmf, +output wire [4:0] pld_8g_wa_boundary, +output wire pld_pma_adapt_done, +output wire [1:0] pld_pma_pcie_sw_done, +output wire [4:0] pld_pma_reserved_in, +output wire pld_pma_rx_detect_valid, +output wire pld_pma_signal_ok, +output wire [7:0] pld_pma_testbus, +output wire pld_rx_prbs_done, +output wire pld_rx_prbs_err, +output wire pld_pma_rx_found, +output wire [19:0] pld_test_data, +output wire [19:0] sr_test_data, +input wire [19:0] pld_test_data_int, + +output wire pld_10g_krfec_rx_frame, +output wire pld_rx_hssi_fifo_full, +output wire pld_rx_hssi_fifo_empty, +output wire pld_fsr_load, +output wire pld_ssr_load, +output wire pld_aib_hssi_rx_dcd_cal_done, +output wire [1:0] pld_rx_ssr_reserved_out, + +// ASN +output wire [1:0] rx_ssr_pcie_sw_done, + +// Reset SM +output wire sr_hssi_rx_dcd_cal_done, +output wire sr_hssi_rx_transfer_en, + +// testbus +output wire [19:0] sr_testbus_int, + +// SR +output wire [1:0] rx_fsr_parity_checker_in, +output wire [64:0] rx_ssr_parity_checker_in, + +output wire [2:0] rx_async_fabric_hssi_fsr_data, +output wire [35:0] rx_async_fabric_hssi_ssr_data, +output wire [1:0] rx_async_fabric_hssi_ssr_reserved + +); + +// capture +//assign r_rx_async_pld_ltr_rst_val = avmm_rx_user_datain[0] +//assign r_rx_async_pld_pma_ltd_b_rst_val = avmm_rx_user_datain[1] +// update +//assign r_rx_async_pld_8g_signal_detect_out_rst_val = avmm_rx_user_datain[2] +//assign r_rx_async_pld_10g_rx_crc32_err_rst_val = avmm_rx_user_datain[3] + +wire pld_8g_rxelecidle_int; +wire pld_pma_rxpll_lock_int; +wire pld_8g_signal_detect_out_int; +wire pld_10g_krfec_rx_blk_lock_int; +wire [1:0] pld_10g_krfec_rx_diag_data_status_int; +wire pld_10g_rx_crc32_err_int; +wire pld_10g_rx_frame_lock_int; +wire pld_10g_rx_hi_ber_int; +wire [3:0] pld_8g_a1a2_k1k2_flag_int; +wire pld_8g_empty_rmf_int; +wire pld_8g_full_rmf_int; +wire [4:0] pld_8g_wa_boundary_int; +wire pld_pma_adapt_done_int; +wire [1:0] pld_pma_pcie_sw_done_int; +wire [4:0] pld_pma_reserved_in_int; +wire pld_pma_rx_detect_valid_int; +wire pld_pma_signal_ok_int; +wire [7:0] pld_pma_testbus_int; +wire pld_rx_prbs_done_int; +wire pld_rx_prbs_err_int; +//wire [19:0] pld_test_data_int; +wire pld_10g_krfec_rx_frame_int; +wire pld_rx_hssi_fifo_full_int; +wire pld_rx_hssi_fifo_empty_int; +wire nfrz_output_2one; +wire pld_pma_rx_found_int; +wire pld_aib_hssi_rx_dcd_cal_done_int; +wire [1:0] pld_rx_ssr_reserved_out_int; +wire pld_pma_pfdmode_lock_int; +wire [62:0] rx_ssr_parity_checker_in_int; +reg ssr_load_int; +reg fsr_load_int; +reg [14:0] sr_testbus_internal; +wire pld_rx_dll_lock_req_int; +wire pld_aib_hssi_rx_dcd_cal_req_int; + +assign nfrz_output_2one = nfrzdrv_in & pr_channel_freeze_n; + +assign pld_8g_rxelecidle = nfrz_output_2one ? pld_8g_rxelecidle_int : 1'b1; +assign pld_pma_rxpll_lock = nfrz_output_2one ? pld_pma_rxpll_lock_int : 1'b1; +assign pld_8g_signal_detect_out = nfrz_output_2one ? pld_8g_signal_detect_out_int : 1'b1; +assign pld_10g_krfec_rx_blk_lock = nfrz_output_2one ? pld_10g_krfec_rx_blk_lock_int : 1'b1; +assign pld_10g_krfec_rx_diag_data_status = nfrz_output_2one ? pld_10g_krfec_rx_diag_data_status_int : 2'b11; +assign pld_10g_rx_crc32_err = nfrz_output_2one ? pld_10g_rx_crc32_err_int : 1'b1; +assign pld_10g_rx_frame_lock = nfrz_output_2one ? pld_10g_rx_frame_lock_int : 1'b1; +assign pld_10g_rx_hi_ber = nfrz_output_2one ? pld_10g_rx_hi_ber_int : 1'b1; +assign pld_8g_a1a2_k1k2_flag = nfrz_output_2one ? pld_8g_a1a2_k1k2_flag_int : 4'b1111; +assign pld_8g_empty_rmf = nfrz_output_2one ? pld_8g_empty_rmf_int : 1'b1; +assign pld_8g_full_rmf = nfrz_output_2one ? pld_8g_full_rmf_int : 1'b1; +assign pld_8g_wa_boundary = nfrz_output_2one ? pld_8g_wa_boundary_int : 5'b11111; +assign pld_pma_adapt_done = nfrz_output_2one ? pld_pma_adapt_done_int : 1'b1; +assign pld_pma_pcie_sw_done = nfrz_output_2one ? pld_pma_pcie_sw_done_int : 2'b11; +assign pld_pma_reserved_in = nfrz_output_2one ? pld_pma_reserved_in_int : 5'b11111; +assign pld_pma_rx_detect_valid = nfrz_output_2one ? pld_pma_rx_detect_valid_int : 1'b1; +assign pld_pma_signal_ok = nfrz_output_2one ? pld_pma_signal_ok_int : 1'b1; +assign pld_pma_testbus = nfrz_output_2one ? pld_pma_testbus_int : 8'hFF; +assign pld_rx_prbs_done = nfrz_output_2one ? pld_rx_prbs_done_int : 1'b1; +assign pld_rx_prbs_err = nfrz_output_2one ? pld_rx_prbs_err_int : 1'b1; +assign pld_pma_rx_found = nfrz_output_2one ? pld_pma_rx_found_int : 1'b1; +assign pld_test_data = nfrz_output_2one ? pld_test_data_int : 20'hFFFFF; +assign pld_10g_krfec_rx_frame = nfrz_output_2one ? pld_10g_krfec_rx_frame_int : 1'b1; +assign pld_rx_hssi_fifo_full = nfrz_output_2one ? pld_rx_hssi_fifo_full_int : 1'b1; +assign pld_rx_hssi_fifo_empty = nfrz_output_2one ? pld_rx_hssi_fifo_empty_int : 1'b1; +assign pld_aib_hssi_rx_dcd_cal_done = nfrz_output_2one ? pld_aib_hssi_rx_dcd_cal_done_int : 1'b1; +assign pld_fsr_load = nfrz_output_2one ? fsr_load_int : 1'b1; +assign pld_ssr_load = nfrz_output_2one ? ssr_load_int : 1'b1; +assign pld_rx_ssr_reserved_out = nfrz_output_2one ? pld_rx_ssr_reserved_out_int : 2'b11; +assign pld_pma_pfdmode_lock = nfrz_output_2one ? pld_pma_pfdmode_lock_int : 1'b1; + +//assign pld_rx_prbs_done_internal = r_rx_async_prbs_flags_sr_enable ? pld_rx_prbs_done_int : pld_rx_fabric_data_out[1]; +//assign pld_rx_prbs_done_internal = r_rx_async_prbs_flags_sr_enable ? pld_rx_prbs_done_int : pld_rx_fabric_data_out[1]; + +assign rx_ssr_parity_checker_in = {pld_rx_ssr_reserved_out_int, rx_ssr_parity_checker_in_int}; + +assign pld_rx_dll_lock_req_int = usermode_in & pld_rx_dll_lock_req; +assign pld_aib_hssi_rx_dcd_cal_req_int = usermode_in & pld_aib_hssi_rx_dcd_cal_req; + +always @(negedge rx_reset_async_tx_osc_clk_rst_n or posedge rx_clock_async_tx_osc_clk) begin + if (rx_reset_async_tx_osc_clk_rst_n == 1'b0) begin + ssr_load_int <= 1'b1; + fsr_load_int <= 1'b1; + end + else + begin + ssr_load_int <= rx_async_fabric_hssi_ssr_load; + fsr_load_int <= rx_async_fabric_hssi_fsr_load; + end + end + +assign sr_testbus_int = {5'd0, sr_testbus_internal}; + +always @(negedge rx_reset_async_tx_osc_clk_rst_n or posedge rx_clock_async_tx_osc_clk) begin + if (rx_reset_async_tx_osc_clk_rst_n == 1'b0) begin + sr_testbus_internal[12:0] <= 13'b1_0010_0000_0000; + end + else + begin + sr_testbus_internal[12:0] <= sr_testbus[12:0]; + end + end + +always @(negedge rx_reset_async_rx_osc_clk_rst_n or posedge rx_clock_async_rx_osc_clk) begin + if (rx_reset_async_rx_osc_clk_rst_n == 1'b0) begin + sr_testbus_internal[14:13] <= 2'b10; + end + else + begin + sr_testbus_internal[14:13] <= sr_testbus[14:13]; + end + end + + +hdpldadapt_rx_async_reserved_capture hdpldadapt_rx_async_reserved_capture ( + // input + .rx_async_fabric_hssi_ssr_load (rx_async_fabric_hssi_ssr_load), + .rx_clock_async_tx_osc_clk (rx_clock_async_tx_osc_clk), + .rx_reset_async_tx_osc_clk_rst_n (rx_reset_async_tx_osc_clk_rst_n), + .pld_rx_ssr_reserved_in (pld_rx_ssr_reserved_in), + // output + .rx_async_fabric_hssi_ssr_reserved(rx_async_fabric_hssi_ssr_reserved) +); + +hdpldadapt_rx_async_reserved_update hdpldadapt_rx_async_reserved_update ( + // input + .rx_clock_async_rx_osc_clk (rx_clock_async_rx_osc_clk), + .rx_reset_async_rx_osc_clk_rst_n (rx_reset_async_rx_osc_clk_rst_n), + .rx_async_hssi_fabric_ssr_load (rx_async_hssi_fabric_ssr_load), + .rx_async_hssi_fabric_ssr_reserved(rx_async_hssi_fabric_ssr_reserved), + // output + .pld_rx_ssr_reserved_out (pld_rx_ssr_reserved_out_int) +); + +hdpldadapt_rx_async_capture hdpldadapt_rx_async_capture ( + // input + .rx_async_fabric_hssi_fsr_load (rx_async_fabric_hssi_fsr_load), + .rx_async_fabric_hssi_ssr_load (rx_async_fabric_hssi_ssr_load), + .rx_clock_async_tx_osc_clk (rx_clock_async_tx_osc_clk), + .rx_reset_async_tx_osc_clk_rst_n (rx_reset_async_tx_osc_clk_rst_n), + .pld_10g_krfec_rx_clr_errblk_cnt (pld_10g_krfec_rx_clr_errblk_cnt), + .pld_10g_rx_clr_ber_count (pld_10g_rx_clr_ber_count), + .pld_8g_a1a2_size (pld_8g_a1a2_size), + .pld_8g_bitloc_rev_en (pld_8g_bitloc_rev_en), + .pld_8g_byte_rev_en (pld_8g_byte_rev_en), + .pld_8g_eidleinfersel (pld_8g_eidleinfersel), + .pld_8g_encdt (pld_8g_encdt), + .pld_bitslip (pld_bitslip), + .pld_ltr (pld_ltr), + .pld_pma_adapt_start (pld_pma_adapt_start), + .pld_pma_early_eios (pld_pma_early_eios), + .pld_pma_eye_monitor (pld_pma_eye_monitor), + .pld_pma_ltd_b (pld_pma_ltd_b), + .pld_pma_pcie_switch (pld_pma_pcie_switch), + .pld_pma_ppm_lock (pld_pma_ppm_lock), + .pld_pma_reserved_out (pld_pma_reserved_out), + .pld_pma_rs_lpbk_b (pld_pma_rs_lpbk_b), + .pld_pmaif_rxclkslip (pld_pmaif_rxclkslip), + .pld_polinv_rx (pld_polinv_rx), + .pld_rx_prbs_err_clr (pld_rx_prbs_err_clr), + .pld_syncsm_en (pld_syncsm_en), + .pld_rx_fifo_latency_adj_en (pld_rx_fifo_latency_adj_en), + .pld_rx_fabric_fifo_align_clr (pld_rx_fabric_fifo_align_clr), + .pld_rx_dll_lock_req (pld_rx_dll_lock_req_int), + .pld_aib_hssi_rx_dcd_cal_req (pld_aib_hssi_rx_dcd_cal_req_int), + .rx_hrdrst_fabric_rx_dll_lock (rx_hrdrst_fabric_rx_dll_lock), + .rx_hrdrst_fabric_rx_transfer_en (rx_hrdrst_fabric_rx_transfer_en), + .r_rx_async_pld_ltr_rst_val (r_rx_async_pld_ltr_rst_val), + .r_rx_async_pld_pma_ltd_b_rst_val (r_rx_async_pld_pma_ltd_b_rst_val), + .r_rx_async_pld_rx_fifo_align_clr_rst_val (r_rx_async_pld_rx_fifo_align_clr_rst_val), + .r_rx_pld_8g_eidleinfersel_polling_bypass (r_rx_pld_8g_eidleinfersel_polling_bypass), + .r_rx_pld_pma_eye_monitor_polling_bypass (r_rx_pld_pma_eye_monitor_polling_bypass), + .r_rx_pld_pma_pcie_switch_polling_bypass (r_rx_pld_pma_pcie_switch_polling_bypass), + .r_rx_pld_pma_reser_out_polling_bypass (r_rx_pld_pma_reser_out_polling_bypass), + // output + .rx_async_fabric_hssi_fsr_data (rx_async_fabric_hssi_fsr_data), + .rx_async_fabric_hssi_ssr_data (rx_async_fabric_hssi_ssr_data) +); + +hdpldadapt_rx_async_update hdpldadapt_rx_async_update ( + // input + .rx_clock_async_rx_osc_clk (rx_clock_async_rx_osc_clk), + .rx_reset_async_rx_osc_clk_rst_n (rx_reset_async_rx_osc_clk_rst_n), + .rx_async_hssi_fabric_fsr_data (rx_async_hssi_fabric_fsr_data), + .rx_async_hssi_fabric_fsr_load (rx_async_hssi_fabric_fsr_load), + .rx_async_hssi_fabric_ssr_data (rx_async_hssi_fabric_ssr_data), + .rx_async_hssi_fabric_ssr_load (rx_async_hssi_fabric_ssr_load), + .r_rx_async_pld_8g_signal_detect_out_rst_val (r_rx_async_pld_8g_signal_detect_out_rst_val), + .r_rx_async_pld_10g_rx_crc32_err_rst_val (r_rx_async_pld_10g_rx_crc32_err_rst_val), + // output + .rx_fsr_parity_checker_in (rx_fsr_parity_checker_in), + .rx_ssr_parity_checker_in (rx_ssr_parity_checker_in_int), + .pld_10g_krfec_rx_blk_lock (pld_10g_krfec_rx_blk_lock_int), + .pld_10g_krfec_rx_diag_data_status(pld_10g_krfec_rx_diag_data_status_int), + .pld_10g_krfec_rx_frame (pld_10g_krfec_rx_frame_int), + .pld_10g_rx_crc32_err (pld_10g_rx_crc32_err_int), + .pld_10g_rx_frame_lock (pld_10g_rx_frame_lock_int), + .pld_10g_rx_hi_ber (pld_10g_rx_hi_ber_int), + .pld_8g_a1a2_k1k2_flag (pld_8g_a1a2_k1k2_flag_int), + .pld_8g_empty_rmf (pld_8g_empty_rmf_int), + .pld_8g_full_rmf (pld_8g_full_rmf_int), + .pld_8g_signal_detect_out (pld_8g_signal_detect_out_int), + .pld_8g_wa_boundary (pld_8g_wa_boundary_int), + .pld_pma_adapt_done (pld_pma_adapt_done_int), + .pld_pma_pcie_sw_done (pld_pma_pcie_sw_done_int), + .rx_ssr_pcie_sw_done (rx_ssr_pcie_sw_done), + .pld_pma_reserved_in (pld_pma_reserved_in_int), + .pld_pma_rx_detect_valid (pld_pma_rx_detect_valid_int), + .pld_pma_signal_ok (pld_pma_signal_ok_int), + .pld_pma_testbus (pld_pma_testbus_int), + .pld_rx_prbs_done (pld_rx_prbs_done_int), + .pld_rx_prbs_err (pld_rx_prbs_err_int), + .pld_test_data (sr_test_data), + .pld_pma_rx_found (pld_pma_rx_found_int), + .pld_rx_hssi_fifo_empty (pld_rx_hssi_fifo_empty_int), + .pld_rx_hssi_fifo_full (pld_rx_hssi_fifo_full_int), + .pld_aib_hssi_rx_dcd_cal_done (pld_aib_hssi_rx_dcd_cal_done_int), + .sr_hssi_rx_dcd_cal_done (sr_hssi_rx_dcd_cal_done), + .sr_hssi_rx_transfer_en (sr_hssi_rx_transfer_en) +); + +hdpldadapt_rx_async_direct hdpldadapt_rx_async_direct ( + // input + .aib_fabric_pld_8g_rxelecidle (aib_fabric_pld_8g_rxelecidle), + .aib_fabric_pld_pma_rxpll_lock(aib_fabric_pld_pma_rxpll_lock), + .aib_fabric_pld_pma_pfdmode_lock(aib_fabric_pld_pma_pfdmode_lock), + // output + .pld_pma_pfdmode_lock (pld_pma_pfdmode_lock_int), + .pld_8g_rxelecidle (pld_8g_rxelecidle_int), + .pld_pma_rxpll_lock (pld_pma_rxpll_lock_int) +); + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_capture.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_capture.v new file mode 100644 index 0000000..0fbd3b4 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_capture.v @@ -0,0 +1,686 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_rx_async_capture ( +// DPRIO +input wire r_rx_async_pld_ltr_rst_val, +input wire r_rx_async_pld_pma_ltd_b_rst_val, +input wire r_rx_async_pld_rx_fifo_align_clr_rst_val, +input wire r_rx_pld_8g_eidleinfersel_polling_bypass, +input wire r_rx_pld_pma_eye_monitor_polling_bypass, +input wire r_rx_pld_pma_pcie_switch_polling_bypass, +input wire r_rx_pld_pma_reser_out_polling_bypass, + +// SR +input wire rx_async_fabric_hssi_fsr_load, +input wire rx_async_fabric_hssi_ssr_load, + +// RXCLK_CTL +input wire rx_clock_async_tx_osc_clk, + +// RXRST_CTL +input wire rx_reset_async_tx_osc_clk_rst_n, + +// PCS_IF +input wire pld_10g_krfec_rx_clr_errblk_cnt, +input wire pld_10g_rx_clr_ber_count, +input wire pld_8g_a1a2_size, +input wire pld_8g_bitloc_rev_en, +input wire pld_8g_byte_rev_en, +input wire [2:0] pld_8g_eidleinfersel, +input wire pld_8g_encdt, +input wire pld_bitslip, +input wire pld_ltr, +input wire pld_pma_adapt_start, +input wire pld_pma_early_eios, +input wire [5:0] pld_pma_eye_monitor, +input wire pld_pma_ltd_b, +input wire [1:0] pld_pma_pcie_switch, +input wire pld_pma_ppm_lock, +input wire [4:0] pld_pma_reserved_out, +input wire pld_pma_rs_lpbk_b, +input wire pld_pmaif_rxclkslip, +input wire pld_polinv_rx, +input wire pld_rx_prbs_err_clr, +input wire pld_syncsm_en, +input wire pld_rx_fifo_latency_adj_en, +input wire pld_rx_fabric_fifo_align_clr, +input wire pld_rx_dll_lock_req, +input wire pld_aib_hssi_rx_dcd_cal_req, + +// Reset SM +input wire rx_hrdrst_fabric_rx_dll_lock, +input wire rx_hrdrst_fabric_rx_transfer_en, + +output wire [2:0] rx_async_fabric_hssi_fsr_data, +output wire [35:0] rx_async_fabric_hssi_ssr_data +); + +wire pld_10g_krfec_rx_clr_errblk_cnt_int; +wire pld_10g_rx_clr_ber_count_int; +wire pld_8g_a1a2_size_int; +wire pld_8g_bitloc_rev_en_int; +wire pld_8g_byte_rev_en_int; +wire [2:0] pld_8g_eidleinfersel_int; +wire pld_8g_encdt_int; +wire pld_bitslip_int; +wire pld_ltr_rst1_int; +wire pld_ltr_rst0_int; +wire pld_pma_adapt_start_int; +wire pld_pma_early_eios_int; +wire [5:0] pld_pma_eye_monitor_int; +wire pld_pma_ltd_b_rst1_int; +wire pld_pma_ltd_b_rst0_int; +wire [1:0] pld_pma_pcie_switch_int; +wire pld_pma_ppm_lock_int; +wire [4:0] pld_pma_reserved_out_int; +wire pld_pma_rs_lpbk_b_int; +wire pld_pmaif_rxclkslip_int; +wire pld_polinv_rx_int; +wire pld_rx_prbs_err_clr_int; +wire pld_syncsm_en_int; +wire pld_rx_fifo_latency_adj_en_int; +wire pld_rx_dll_lock_req_int; +wire pld_aib_hssi_rx_dcd_cal_req_int; +wire rx_hrdrst_fabric_rx_dll_lock_int; +wire rx_hrdrst_fabric_rx_transfer_en_int; +wire pld_rx_fabric_fifo_align_clr_rst1_int; +wire pld_rx_fabric_fifo_align_clr_rst0_int; + +wire nc_0; +wire nc_1; +wire nc_2; +wire nc_3; +wire nc_4; +wire nc_5; +wire nc_6; +wire nc_7; +wire nc_8; +wire nc_9; +wire nc_10; +wire nc_11; +wire nc_12; +wire nc_13; +wire nc_14; +wire nc_15; +wire nc_16; +wire nc_17; +wire nc_18; +wire nc_19; +wire nc_20; +wire nc_21; +wire nc_22; +wire nc_23; +wire nc_24; +wire nc_25; +wire nc_26; + +// FAST SR: +assign rx_async_fabric_hssi_fsr_data[0] = r_rx_async_pld_ltr_rst_val ? pld_ltr_rst1_int : pld_ltr_rst0_int; +assign rx_async_fabric_hssi_fsr_data[1] = r_rx_async_pld_pma_ltd_b_rst_val ? pld_pma_ltd_b_rst1_int : pld_pma_ltd_b_rst0_int; +assign rx_async_fabric_hssi_fsr_data[2] = r_rx_async_pld_rx_fifo_align_clr_rst_val ? pld_rx_fabric_fifo_align_clr_rst1_int : pld_rx_fabric_fifo_align_clr_rst0_int; + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (3), + .SYNC_STAGE (4) + ) + async_pld_ltr_rst1 + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_ltr), + .unload (rx_async_fabric_hssi_fsr_load), + .data_in_sync_out (nc_0), + .data_out (pld_ltr_rst1_int) + ); + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (0), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (3), + .SYNC_STAGE (4) + ) + async_pld_ltr_rst0 + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_ltr), + .unload (rx_async_fabric_hssi_fsr_load), + .data_in_sync_out (nc_1), + .data_out (pld_ltr_rst0_int) + ); + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (3), + .SYNC_STAGE (4) + ) + async_pld_pma_ltd_b_rst1 + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_pma_ltd_b), + .unload (rx_async_fabric_hssi_fsr_load), + .data_in_sync_out (nc_2), + .data_out (pld_pma_ltd_b_rst1_int) + ); + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (0), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (3), + .SYNC_STAGE (4) + ) + async_pld_pma_ltd_b_rst0 + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_pma_ltd_b), + .unload (rx_async_fabric_hssi_fsr_load), + .data_in_sync_out (nc_3), + .data_out (pld_pma_ltd_b_rst0_int) + ); + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (4), + .SYNC_STAGE (2) + ) + async_pld_rx_fabric_fifo_align_clr_rst1 + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_rx_fabric_fifo_align_clr), + .unload (rx_async_fabric_hssi_fsr_load), + .data_in_sync_out (nc_4), + .data_out (pld_rx_fabric_fifo_align_clr_rst1_int) + ); + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (0), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (4), + .SYNC_STAGE (2) + ) + async_pld_rx_fabric_fifo_align_clr_rst0 + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_rx_fabric_fifo_align_clr), + .unload (rx_async_fabric_hssi_fsr_load), + .data_in_sync_out (nc_5), + .data_out (pld_rx_fabric_fifo_align_clr_rst0_int) + ); + + + +// SLOW SR: AR: to check reset value +assign rx_async_fabric_hssi_ssr_data[0] = pld_8g_a1a2_size_int; +assign rx_async_fabric_hssi_ssr_data[1] = pld_8g_bitloc_rev_en_int; +assign rx_async_fabric_hssi_ssr_data[2] = pld_8g_byte_rev_en_int; +assign rx_async_fabric_hssi_ssr_data[5:3] = pld_8g_eidleinfersel_int; +assign rx_async_fabric_hssi_ssr_data[6] = pld_8g_encdt_int; + +assign rx_async_fabric_hssi_ssr_data[7] = pld_10g_krfec_rx_clr_errblk_cnt_int; +assign rx_async_fabric_hssi_ssr_data[8] = pld_10g_rx_clr_ber_count_int; + +assign rx_async_fabric_hssi_ssr_data[9] = pld_pma_adapt_start_int; +assign rx_async_fabric_hssi_ssr_data[10] = pld_pma_early_eios_int; +assign rx_async_fabric_hssi_ssr_data[16:11] = pld_pma_eye_monitor_int; +assign rx_async_fabric_hssi_ssr_data[18:17] = pld_pma_pcie_switch_int; +assign rx_async_fabric_hssi_ssr_data[19] = pld_pma_ppm_lock_int; +assign rx_async_fabric_hssi_ssr_data[24:20] = pld_pma_reserved_out_int; +assign rx_async_fabric_hssi_ssr_data[25] = pld_pma_rs_lpbk_b_int; +assign rx_async_fabric_hssi_ssr_data[26] = pld_pmaif_rxclkslip_int; + +assign rx_async_fabric_hssi_ssr_data[27] = pld_bitslip_int; +assign rx_async_fabric_hssi_ssr_data[28] = pld_polinv_rx_int; +assign rx_async_fabric_hssi_ssr_data[29] = pld_rx_prbs_err_clr_int; +assign rx_async_fabric_hssi_ssr_data[30] = pld_syncsm_en_int; +assign rx_async_fabric_hssi_ssr_data[31] = pld_rx_fifo_latency_adj_en_int; + +assign rx_async_fabric_hssi_ssr_data[32] = rx_hrdrst_fabric_rx_dll_lock_int; +assign rx_async_fabric_hssi_ssr_data[33] = pld_rx_dll_lock_req_int; +assign rx_async_fabric_hssi_ssr_data[34] = rx_hrdrst_fabric_rx_transfer_en_int; +assign rx_async_fabric_hssi_ssr_data[35] = pld_aib_hssi_rx_dcd_cal_req_int; + + +// 8G ASYNC +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (5), + .SYNC_STAGE (2) + ) + async_pld_8g_a1a2_size + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_8g_a1a2_size), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_6), + .data_out (pld_8g_a1a2_size_int) + ); + + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (5), + .SYNC_STAGE (2) + ) + async_pld_8g_bitloc_rev_en + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_8g_bitloc_rev_en), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_7), + .data_out (pld_8g_bitloc_rev_en_int) + ); + + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (5), + .SYNC_STAGE (2) + ) + async_pld_8g_byte_rev_en + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_8g_byte_rev_en), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_8), + .data_out (pld_8g_byte_rev_en_int) + ); + +hdpldadapt_cmn_async_capture_bus + #( + .DWIDTH (3), + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (3), + .SYNC_STAGE (4) + ) + async_pld_8g_eidleinfersel + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_8g_eidleinfersel), + .unload (rx_async_fabric_hssi_ssr_load), + .r_capt_mode (r_rx_pld_8g_eidleinfersel_polling_bypass), + .data_out (pld_8g_eidleinfersel_int) + ); + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (3), + .SYNC_STAGE (2) + ) + async_pld_8g_encdt + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_8g_encdt), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_9), + .data_out (pld_8g_encdt_int) + ); + + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (5), + .SYNC_STAGE (2) + ) + async_pld_10g_krfec_rx_clr_errblk_cnt + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_10g_krfec_rx_clr_errblk_cnt), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_10), + .data_out (pld_10g_krfec_rx_clr_errblk_cnt_int) + ); + + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (5), + .SYNC_STAGE (2) + ) + async_pld_10g_rx_clr_ber_count + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_10g_rx_clr_ber_count), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_11), + .data_out (pld_10g_rx_clr_ber_count_int) + ); + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (3), + .SYNC_STAGE (4) + ) + async_pld_pma_adapt_start + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_pma_adapt_start), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_12), + .data_out (pld_pma_adapt_start_int) + ); + + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (3), + .SYNC_STAGE (4) + ) + async_pld_pma_early_eios + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_pma_early_eios), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_13), + .data_out (pld_pma_early_eios_int) + ); + +hdpldadapt_cmn_async_capture_bus + #( + .DWIDTH (6), + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (3), + .SYNC_STAGE (4) + ) + async_pld_pma_eye_monitor + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_pma_eye_monitor), + .unload (rx_async_fabric_hssi_ssr_load), + .r_capt_mode (r_rx_pld_pma_eye_monitor_polling_bypass), + .data_out (pld_pma_eye_monitor_int) + ); + + +hdpldadapt_cmn_async_capture_bus + #( + .DWIDTH (2), + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (3), + .SYNC_STAGE (4) + ) + async_pld_pma_pcie_switch + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_pma_pcie_switch), + .unload (rx_async_fabric_hssi_ssr_load), + .r_capt_mode (r_rx_pld_pma_pcie_switch_polling_bypass), + .data_out (pld_pma_pcie_switch_int) + ); + + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (3), + .SYNC_STAGE (4) + ) + async_pld_pma_ppm_lock + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_pma_ppm_lock), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_14), + .data_out (pld_pma_ppm_lock_int) + ); + +hdpldadapt_cmn_async_capture_bus + #( + .DWIDTH (5), + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (3), + .SYNC_STAGE (4) + ) + async_pld_pma_reserved_out + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_pma_reserved_out), + .unload (rx_async_fabric_hssi_ssr_load), + .r_capt_mode (r_rx_pld_pma_reser_out_polling_bypass), + .data_out (pld_pma_reserved_out_int) + ); + + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (3), + .SYNC_STAGE (4) + ) + async_pld_pma_rs_lpbk_b + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_pma_rs_lpbk_b), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_15), + .data_out (pld_pma_rs_lpbk_b_int) + ); + + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (3), + .SYNC_STAGE (4) + ) + async_pld_pmaif_rxclkslip + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_pmaif_rxclkslip), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_16), + .data_out (pld_pmaif_rxclkslip_int) + ); + + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (4), + .SYNC_STAGE (2) + ) + async_pld_bitslip + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_bitslip), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_17), + .data_out (pld_bitslip_int) + ); + + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (5), + .SYNC_STAGE (2) + ) + async_pld_polinv_rx + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_polinv_rx), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_18), + .data_out (pld_polinv_rx_int) + ); + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (5), + .SYNC_STAGE (2) + ) + async_pld_rx_prbs_err_clr + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_rx_prbs_err_clr), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_19), + .data_out (pld_rx_prbs_err_clr_int) + ); + + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (5), + .SYNC_STAGE (2) + ) + async_pld_syncsm_en + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_syncsm_en), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_20), + .data_out (pld_syncsm_en_int) + ); + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (5), + .SYNC_STAGE (2) + ) + async_pld_rx_fifo_latency_adj_en + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_rx_fifo_latency_adj_en), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_21), + .data_out (pld_rx_fifo_latency_adj_en_int) + ); + + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (0), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (2), + .SYNC_STAGE (4) + ) + async_pld_rx_dll_lock_req + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_rx_dll_lock_req), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_22), + .data_out (pld_rx_dll_lock_req_int) + ); + + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (0), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (2), + .SYNC_STAGE (4) + ) + async_rx_hrdrst_fabric_rx_dll_lock + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (rx_hrdrst_fabric_rx_dll_lock), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_24), + .data_out (rx_hrdrst_fabric_rx_dll_lock_int) + ); + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (0), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (2), + .SYNC_STAGE (4) + ) + async_rx_hrdrst_fabric_rx_transfer_en + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (rx_hrdrst_fabric_rx_transfer_en), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_25), + .data_out (rx_hrdrst_fabric_rx_transfer_en_int) + ); + +hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (0), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (2), + .SYNC_STAGE (4) + ) + async_pld_aib_hssi_rx_dcd_cal_req + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_aib_hssi_rx_dcd_cal_req), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_26), + .data_out (pld_aib_hssi_rx_dcd_cal_req_int) + ); + + + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_direct.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_direct.v new file mode 100644 index 0000000..7259771 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_direct.v @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_rx_async_direct ( +// AIB IF +input wire aib_fabric_pld_8g_rxelecidle, +input wire aib_fabric_pld_pma_rxpll_lock, +input wire aib_fabric_pld_pma_pfdmode_lock, + +// PLD IF +output wire pld_pma_pfdmode_lock, +output wire pld_8g_rxelecidle, +output wire pld_pma_rxpll_lock + +); + +assign pld_8g_rxelecidle = aib_fabric_pld_8g_rxelecidle; +assign pld_pma_rxpll_lock = aib_fabric_pld_pma_rxpll_lock; +assign pld_pma_pfdmode_lock = aib_fabric_pld_pma_pfdmode_lock; + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_reserved_capture.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_reserved_capture.v new file mode 100644 index 0000000..89294f5 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_reserved_capture.v @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_rx_async_reserved_capture ( +// SR +input wire rx_async_fabric_hssi_ssr_load, + +// RXCLK_CTL +input wire rx_clock_async_tx_osc_clk, + +// RXRST_CTL +input wire rx_reset_async_tx_osc_clk_rst_n, + +// PCS_IF +input wire [1:0] pld_rx_ssr_reserved_in, + +output wire [1:0] rx_async_fabric_hssi_ssr_reserved +); + +wire [1:0] nc_0; + +//generate +// genvar i; +// for (i=0; i < 2; i=i+1) begin: hdpldadapt_cmn_async_capture_bit +// hdpldadapt_cmn_async_capture_bit +// #( +// .RESET_VAL (1), +// .CLK_FREQ_MHZ(1200), +// .TOGGLE_TYPE (3), +// .SYNC_STAGE (4) +// ) +// async_rx_reserved_ssr_in +// ( +// .clk (rx_clock_async_tx_osc_clk), +// .rst_n (rx_reset_async_tx_osc_clk_rst_n), +// .data_in (pld_rx_ssr_reserved_in[i]), +// .unload (rx_async_fabric_hssi_ssr_load), +// .data_in_sync_out (nc_0[i]), +// .data_out (rx_async_fabric_hssi_ssr_reserved[i]) +// ); +// end +//endgenerate + + hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (1), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (3), + .SYNC_STAGE (4) + ) + async_rx_pld_rx_ssr_reserved_in0 + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_rx_ssr_reserved_in[0]), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_0[0]), + .data_out (rx_async_fabric_hssi_ssr_reserved[0]) + ); + + + hdpldadapt_cmn_async_capture_bit + #( + .RESET_VAL (0), + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (3), + .SYNC_STAGE (4) + ) + async_rx_pld_rx_ssr_reserved_in1 + ( + .clk (rx_clock_async_tx_osc_clk), + .rst_n (rx_reset_async_tx_osc_clk_rst_n), + .data_in (pld_rx_ssr_reserved_in[1]), + .unload (rx_async_fabric_hssi_ssr_load), + .data_in_sync_out (nc_0[1]), + .data_out (rx_async_fabric_hssi_ssr_reserved[1]) + ); + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_reserved_update.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_reserved_update.v new file mode 100644 index 0000000..4161ffb --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_reserved_update.v @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_rx_async_reserved_update ( +// RXCLK_CTL +input wire rx_clock_async_rx_osc_clk, + +// RXRST_CTL +input wire rx_reset_async_rx_osc_clk_rst_n, + +// SR +input wire [1:0] rx_async_hssi_fabric_ssr_reserved, +input wire rx_async_hssi_fabric_ssr_load, + +// PLD IF +output wire [1:0] pld_rx_ssr_reserved_out +); + +// SLOW SR +hdpldadapt_async_update + #( .AWIDTH (2), + .RESET_VAL (0) + ) async_rx_reserved_ssr_out + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (rx_async_hssi_fabric_ssr_reserved), + .async_data_out (pld_rx_ssr_reserved_out) + ); + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_update.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_update.v new file mode 100644 index 0000000..301ee31 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_update.v @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_rx_async_update ( +// DPRIO +input wire r_rx_async_pld_8g_signal_detect_out_rst_val, +input wire r_rx_async_pld_10g_rx_crc32_err_rst_val, + +// RXCLK_CTL +input wire rx_clock_async_rx_osc_clk, + +// RXRST_CTL +input wire rx_reset_async_rx_osc_clk_rst_n, + +// SR +input wire [1:0] rx_async_hssi_fabric_fsr_data, +input wire rx_async_hssi_fabric_fsr_load, +input wire [62:0] rx_async_hssi_fabric_ssr_data, +input wire rx_async_hssi_fabric_ssr_load, + +// PLD IF +output wire pld_10g_krfec_rx_blk_lock, +output wire [1:0] pld_10g_krfec_rx_diag_data_status, +output wire pld_10g_krfec_rx_frame, +output wire pld_10g_rx_crc32_err, +output wire pld_10g_rx_frame_lock, +output wire pld_10g_rx_hi_ber, +output wire [3:0] pld_8g_a1a2_k1k2_flag, +output wire pld_8g_empty_rmf, +output wire pld_8g_full_rmf, +output wire pld_8g_signal_detect_out, +output wire [4:0] pld_8g_wa_boundary, +output wire pld_pma_adapt_done, +output wire [1:0] pld_pma_pcie_sw_done, +output wire [1:0] rx_ssr_pcie_sw_done, +output wire [4:0] pld_pma_reserved_in, +output wire pld_pma_rx_detect_valid, +output wire pld_pma_signal_ok, +output wire [7:0] pld_pma_testbus, +output wire pld_rx_prbs_done, +output wire pld_rx_prbs_err, +output wire [19:0] pld_test_data, +output wire pld_pma_rx_found, +output wire pld_rx_hssi_fifo_empty, +output wire pld_rx_hssi_fifo_full, + +// SR +output wire [1:0] rx_fsr_parity_checker_in, +output wire [62:0] rx_ssr_parity_checker_in, + +// Reset SM +output wire sr_hssi_rx_dcd_cal_done, +output wire sr_hssi_rx_transfer_en, +output wire pld_aib_hssi_rx_dcd_cal_done +); + +wire pld_10g_krfec_rx_blk_lock_int; +wire [1:0] pld_10g_krfec_rx_diag_data_status_int; +wire pld_10g_krfec_rx_frame_int; +wire pld_10g_rx_crc32_err_int; +wire pld_10g_rx_frame_lock_int; +wire pld_10g_rx_hi_ber_int; +wire [3:0] pld_8g_a1a2_k1k2_flag_int; +wire pld_8g_empty_rmf_int; +wire pld_8g_full_rmf_int; +wire pld_8g_signal_detect_out_int; +wire [4:0] pld_8g_wa_boundary_int; +wire pld_pma_adapt_done_int; +wire [1:0] pld_pma_pcie_sw_done_int; +wire [4:0] pld_pma_reserved_in_int; +wire pld_pma_rx_detect_valid_int; +wire pld_pma_signal_ok_int; +wire [7:0] pld_pma_testbus_int; +wire pld_rx_prbs_done_int; +wire pld_rx_prbs_err_int; +wire [19:0] pld_test_data_int; +wire pld_pma_rx_found_int; +wire pld_rx_hssi_fifo_empty_int; +wire pld_rx_hssi_fifo_full_int; +wire sr_hssi_rx_dcd_cal_done_int; +wire sr_hssi_rx_transfer_en_int; +wire pld_aib_hssi_rx_dcd_cal_done_int; +wire pld_8g_signal_detect_out_rst1; +wire pld_8g_signal_detect_out_rst0; +wire pld_10g_rx_crc32_err_rst1; +wire pld_10g_rx_crc32_err_rst0; + +// FAST SR: +assign pld_8g_signal_detect_out_int = rx_async_hssi_fabric_fsr_data[0]; +assign pld_10g_rx_crc32_err_int = rx_async_hssi_fabric_fsr_data[1]; + +assign rx_fsr_parity_checker_in = {pld_10g_rx_crc32_err, pld_8g_signal_detect_out}; +// 8G +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (1) + ) async_pld_8g_signal_detect_out_rst1 + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_fsr_load), + .async_data_in (pld_8g_signal_detect_out_int), + .async_data_out (pld_8g_signal_detect_out_rst1) + ); + +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (0) + ) async_pld_8g_signal_detect_out_rst0 + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_fsr_load), + .async_data_in (pld_8g_signal_detect_out_int), + .async_data_out (pld_8g_signal_detect_out_rst0) + ); + +assign pld_8g_signal_detect_out = r_rx_async_pld_8g_signal_detect_out_rst_val ? pld_8g_signal_detect_out_rst1 : pld_8g_signal_detect_out_rst0; + +// 10G +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (1) + ) async_pld_10g_rx_crc32_err_rst1 + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_fsr_load), + .async_data_in (pld_10g_rx_crc32_err_int), + .async_data_out (pld_10g_rx_crc32_err_rst1) + ); + +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (0) + ) async_pld_10g_rx_crc32_err_rst0 + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_fsr_load), + .async_data_in (pld_10g_rx_crc32_err_int), + .async_data_out (pld_10g_rx_crc32_err_rst0) + ); + +assign pld_10g_rx_crc32_err = r_rx_async_pld_10g_rx_crc32_err_rst_val ? pld_10g_rx_crc32_err_rst1 : pld_10g_rx_crc32_err_rst0; + +// PMA IF +// PLD IF + +// SLOW SR: +assign pld_8g_a1a2_k1k2_flag_int = rx_async_hssi_fabric_ssr_data[3:0]; +assign pld_8g_empty_rmf_int = rx_async_hssi_fabric_ssr_data[4]; +assign pld_8g_full_rmf_int = rx_async_hssi_fabric_ssr_data[5]; +assign pld_8g_wa_boundary_int = rx_async_hssi_fabric_ssr_data[10:6]; + +assign pld_10g_krfec_rx_blk_lock_int = rx_async_hssi_fabric_ssr_data[11]; +assign pld_10g_krfec_rx_diag_data_status_int = rx_async_hssi_fabric_ssr_data[13:12]; +assign pld_10g_krfec_rx_frame_int = rx_async_hssi_fabric_ssr_data[14]; +assign pld_10g_rx_frame_lock_int = rx_async_hssi_fabric_ssr_data[15]; +assign pld_10g_rx_hi_ber_int = rx_async_hssi_fabric_ssr_data[16]; + +assign pld_pma_adapt_done_int = rx_async_hssi_fabric_ssr_data[17]; +assign pld_pma_pcie_sw_done_int = rx_async_hssi_fabric_ssr_data[19:18]; +assign pld_pma_reserved_in_int = rx_async_hssi_fabric_ssr_data[24:20]; +assign pld_pma_rx_detect_valid_int = rx_async_hssi_fabric_ssr_data[25]; +assign pld_pma_signal_ok_int = rx_async_hssi_fabric_ssr_data[26]; +assign pld_pma_testbus_int = rx_async_hssi_fabric_ssr_data[34:27]; + +assign pld_rx_prbs_done_int = rx_async_hssi_fabric_ssr_data[35]; +assign pld_rx_prbs_err_int = rx_async_hssi_fabric_ssr_data[36]; +assign pld_test_data_int = rx_async_hssi_fabric_ssr_data[56:37]; +assign pld_pma_rx_found_int = rx_async_hssi_fabric_ssr_data[57]; +assign pld_rx_hssi_fifo_empty_int = rx_async_hssi_fabric_ssr_data[58]; +assign pld_rx_hssi_fifo_full_int = rx_async_hssi_fabric_ssr_data[59]; + +assign sr_hssi_rx_dcd_cal_done_int = rx_async_hssi_fabric_ssr_data[60]; +assign sr_hssi_rx_transfer_en_int = rx_async_hssi_fabric_ssr_data[61]; +assign pld_aib_hssi_rx_dcd_cal_done_int = rx_async_hssi_fabric_ssr_data[62]; + +assign rx_ssr_parity_checker_in = {pld_aib_hssi_rx_dcd_cal_done, sr_hssi_rx_transfer_en, sr_hssi_rx_dcd_cal_done, pld_rx_hssi_fifo_full, pld_rx_hssi_fifo_empty, pld_pma_rx_found, pld_test_data, pld_rx_prbs_err, pld_rx_prbs_done, pld_pma_testbus, pld_pma_signal_ok, pld_pma_rx_detect_valid, pld_pma_reserved_in, pld_pma_pcie_sw_done, pld_pma_adapt_done, pld_10g_rx_hi_ber, pld_10g_rx_frame_lock, pld_10g_krfec_rx_frame, pld_10g_krfec_rx_diag_data_status, pld_10g_krfec_rx_blk_lock, pld_8g_wa_boundary, pld_8g_full_rmf, pld_8g_empty_rmf, pld_8g_a1a2_k1k2_flag}; + +// 8G ASYNC +hdpldadapt_async_update + #( .AWIDTH (4), + .RESET_VAL (0) + ) async_pld_8g_a1a2_k1k2_flag + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_8g_a1a2_k1k2_flag_int), + .async_data_out (pld_8g_a1a2_k1k2_flag) + ); + +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (0) + ) async_pld_8g_empty_rmf + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_8g_empty_rmf_int), + .async_data_out (pld_8g_empty_rmf) + ); + +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (0) + ) async_pld_8g_full_rmf + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_8g_full_rmf_int), + .async_data_out (pld_8g_full_rmf) + ); + +hdpldadapt_async_update + #( .AWIDTH (5), + .RESET_VAL (0) + ) async_pld_8g_wa_boundary + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_8g_wa_boundary_int), + .async_data_out (pld_8g_wa_boundary) + ); + +// 10G ASYNC +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (0) + ) async_pld_10g_krfec_rx_blk_lock + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_10g_krfec_rx_blk_lock_int), + .async_data_out (pld_10g_krfec_rx_blk_lock) + ); + +hdpldadapt_async_update + #( .AWIDTH (2), + .RESET_VAL (0) + ) async_pld_10g_krfec_rx_diag_data_status + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_10g_krfec_rx_diag_data_status_int), + .async_data_out (pld_10g_krfec_rx_diag_data_status) + ); + +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (0) + ) async_pld_10g_krfec_rx_frame + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_10g_krfec_rx_frame_int), + .async_data_out (pld_10g_krfec_rx_frame) + ); + +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (0) + ) async_pld_10g_rx_frame_lock + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_10g_rx_frame_lock_int), + .async_data_out (pld_10g_rx_frame_lock) + ); + +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (0) + ) async_pld_10g_rx_hi_ber + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_10g_rx_hi_ber_int), + .async_data_out (pld_10g_rx_hi_ber) + ); + +// PMA IF ASYNC +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (0) + ) async_pld_pma_adapt_done + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_pma_adapt_done_int), + .async_data_out (pld_pma_adapt_done) + ); + +hdpldadapt_async_update + #( .AWIDTH (2), + .RESET_VAL (0) + ) async_pld_pma_pcie_sw_done + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_pma_pcie_sw_done_int), + .async_data_out (pld_pma_pcie_sw_done) + ); +assign rx_ssr_pcie_sw_done = pld_pma_pcie_sw_done; + +hdpldadapt_async_update + #( .AWIDTH (5), + .RESET_VAL (0) + ) async_pld_pma_reserved_in + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_pma_reserved_in_int), + .async_data_out (pld_pma_reserved_in) + ); + +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (0) + ) async_pld_pma_rx_detect_valid + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_pma_rx_detect_valid_int), + .async_data_out (pld_pma_rx_detect_valid) + ); + +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (0) + ) async_pld_pma_signal_ok + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_pma_signal_ok_int), + .async_data_out (pld_pma_signal_ok) + ); + +hdpldadapt_async_update + #( .AWIDTH (8), + .RESET_VAL (0) + ) async_pld_pma_testbus + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_pma_testbus_int), + .async_data_out (pld_pma_testbus) + ); + +// PLD IF ASYNC +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (0) + ) async_pld_rx_prbs_done + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_rx_prbs_done_int), + .async_data_out (pld_rx_prbs_done) + ); + +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (0) + ) async_pld_rx_prbs_err + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_rx_prbs_err_int), + .async_data_out (pld_rx_prbs_err) + ); + +hdpldadapt_async_update + #( .AWIDTH (20), + .RESET_VAL (0) + ) async_pld_test_data + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_test_data_int), + .async_data_out (pld_test_data) + ); + +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (0) + ) async_pld_pma_rx_found + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_pma_rx_found_int), + .async_data_out (pld_pma_rx_found) + ); + + + +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (1) + ) async_pld_rx_hssi_fifo_empty + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_rx_hssi_fifo_empty_int), + .async_data_out (pld_rx_hssi_fifo_empty) + ); + +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (0) + ) async_pld_rx_hssi_fifo_full + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_rx_hssi_fifo_full_int), + .async_data_out (pld_rx_hssi_fifo_full) + ); + +// DLL Lock +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (0) + ) async_sr_hssi_rx_dcd_cal_done + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (sr_hssi_rx_dcd_cal_done_int), + .async_data_out (sr_hssi_rx_dcd_cal_done) + ); + +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (0) + ) async_sr_hssi_rx_transfer_en + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (sr_hssi_rx_transfer_en_int), + .async_data_out (sr_hssi_rx_transfer_en) + ); + +hdpldadapt_async_update + #( .AWIDTH (1), + .RESET_VAL (0) + ) async_pld_aib_hssi_rx_dcd_cal_done + ( .clk (rx_clock_async_rx_osc_clk), + .rst_n (rx_reset_async_rx_osc_clk_rst_n), + .sr_load (rx_async_hssi_fabric_ssr_load), + .async_data_in (pld_aib_hssi_rx_dcd_cal_done_int), + .async_data_out (pld_aib_hssi_rx_dcd_cal_done) + ); + + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_chnl.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_chnl.v new file mode 100644 index 0000000..3e13cfe --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_chnl.v @@ -0,0 +1,1053 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_rx_chnl(/*AUTOARG*/ + // Outputs + rx_fsr_parity_checker_in, rx_ssr_parity_checker_in, + rx_async_fabric_hssi_ssr_data, rx_async_fabric_hssi_fsr_data, pld_aib_hssi_rx_dcd_cal_done, + pld_rx_fifo_ready, rx_clock_pld_sclk, + rx_asn_rate_change_in_progress, rx_asn_dll_lock_en, //rx_asn_gen3_sel, //rx_asn_fifo_srst, + rx_asn_fifo_hold, pld_test_data, pld_rx_prbs_err, pld_rx_prbs_done, + pld_rx_hssi_fifo_full, pld_rx_hssi_fifo_empty, pld_pma_rx_found, + pld_rx_fabric_fifo_pfull, pld_rx_fabric_fifo_pempty, + pld_rx_fabric_fifo_latency_pulse, pld_rx_fabric_fifo_insert, + pld_rx_fabric_fifo_full, pld_rx_fabric_fifo_empty, + pld_rx_fabric_data_out, pld_rx_fabric_align_done, pld_pma_testbus, + pld_pma_signal_ok, pld_pma_rxpll_lock, pld_pma_rx_detect_valid, + pld_pma_reserved_in, pld_pma_pcie_sw_done, + pld_pma_internal_clk2_hioint, //pld_pma_internal_clk2_dcm, + pld_pma_internal_clk1_hioint, //pld_pma_internal_clk1_dcm, + pld_pma_hclk_hioint, //pld_pma_hclk_dcm, + pld_pma_adapt_done, + pld_pcs_rx_clk_out2_hioint, pld_pcs_rx_clk_out2_dcm, + pld_pcs_rx_clk_out1_hioint, pld_pcs_rx_clk_out1_dcm, + pld_8g_wa_boundary, pld_8g_signal_detect_out, pld_8g_rxelecidle, + pld_8g_full_rmf, pld_8g_empty_rmf, pld_8g_a1a2_k1k2_flag, + pld_10g_rx_hi_ber, pld_10g_rx_frame_lock, pld_10g_rx_crc32_err, + pld_10g_krfec_rx_frame, pld_10g_krfec_rx_diag_data_status, + pld_10g_krfec_rx_blk_lock, bond_rx_fifo_us_out_wren, + bond_rx_fifo_us_out_rden, bond_rx_fifo_ds_out_wren, + bond_rx_fifo_ds_out_rden, + bond_rx_hrdrst_ds_out_fabric_rx_dll_lock, + bond_rx_hrdrst_us_out_fabric_rx_dll_lock, + bond_rx_hrdrst_ds_out_fabric_rx_dll_lock_req, + bond_rx_hrdrst_us_out_fabric_rx_dll_lock_req, + aib_fabric_pld_sclk, + aib_fabric_pld_pma_rxpma_rstb, aib_fabric_pld_pma_coreclkin, + aib_fabric_pcs_rx_pld_rst_n, aib_fabric_adapter_rx_pld_rst_n, + rx_chnl_dprio_status, rx_chnl_dprio_status_write_en_ack, + bond_rx_asn_ds_out_fifo_hold, + //bond_rx_asn_ds_out_dll_lock_en, + bond_rx_asn_us_out_fifo_hold, + //bond_rx_asn_us_out_dll_lock_en, + pld_hssi_asn_dll_lock_en, + pld_fabric_asn_dll_lock_en, + pld_hssi_rx_transfer_en, + pld_aib_fabric_rx_dll_lock, pld_rx_ssr_reserved_out, rx_async_fabric_hssi_ssr_reserved, + adapter_scan_out_occ1, + adapter_scan_out_occ2, + adapter_scan_out_occ3, + adapter_scan_out_occ4, + adapter_scan_out_occ5, + adapter_scan_out_occ6, + adapter_scan_out_occ7, + adapter_scan_out_occ8, + adapter_scan_out_occ9, + adapter_scan_out_occ10, + adapter_scan_out_occ11, + adapter_scan_out_occ12, + adapter_scan_out_occ13, + adapter_scan_out_occ14, + adapter_scan_out_occ15, + adapter_scan_out_occ16, + adapter_scan_out_occ17, + adapter_scan_out_occ18, + adapter_scan_out_occ19, + adapter_scan_out_occ20, + adapter_scan_out_occ21, + adapter_non_occ_scan_out, + adapter_occ_scan_out, + dft_fabric_oaibdftdll2core, + pld_pma_pfdmode_lock, + // Inputs +// new inputs for ECO8 +r_rx_wren_fastbond, +r_rx_rden_fastbond, + sr_parity_error_flag, + aib_fabric_pld_pma_pfdmode_lock, + r_rx_pld_8g_eidleinfersel_polling_bypass, + r_rx_pld_pma_eye_monitor_polling_bypass, + r_rx_pld_pma_pcie_switch_polling_bypass, + r_rx_pld_pma_reser_out_polling_bypass, + oaibdftdll2core, + dft_adpt_aibiobsr_fastclkn, + adapter_scan_rst_n, adapter_scan_mode_n, + adapter_scan_shift_n, adapter_scan_shift_clk, + adapter_scan_user_clk0, adapter_scan_user_clk1, adapter_scan_user_clk2, adapter_scan_user_clk3, + adapter_clk_sel_n, adapter_occ_enable, + pld_clk_dft_sel, + rx_fsr_mask_tx_pll, rx_async_hssi_fabric_ssr_load, pld_aib_hssi_rx_dcd_cal_req, + rx_async_hssi_fabric_ssr_data, rx_async_hssi_fabric_fsr_load, + rx_async_hssi_fabric_fsr_data, rx_async_fabric_hssi_ssr_load, + rx_async_fabric_hssi_fsr_load, r_rx_wa_en, r_rx_us_master, + r_rx_us_bypass_pipeln, r_rx_osc_clk_scg_en, r_rx_truebac2bac, + r_rx_fifo_wr_clk_del_sm_scg_en, r_rx_fifo_rd_clk_ins_sm_scg_en, + r_rx_stop_write, r_rx_stop_read, r_rx_sclk_sel, + r_rx_pma_hclk_scg_en, //r_rx_pld_clk2_sel, + r_rx_pld_clk1_sel, r_rx_phcomp_rd_delay, r_rx_indv, r_rx_gb_dv_en, + r_rx_fifo_wr_clk_sel, r_rx_fifo_wr_clk_scg_en, + r_rx_fifo_rd_clk_sel, r_rx_fifo_rd_clk_scg_en, r_rx_fifo_pfull, + r_rx_fifo_pempty, r_rx_fifo_mode, r_rx_fifo_full, r_rx_fifo_empty, + r_rx_ds_master, r_rx_ds_bypass_pipeln, r_rx_double_read, + //r_rx_coreclkin_sel, + r_rx_internal_clk1_sel1, + r_rx_internal_clk1_sel2, + r_rx_txfiford_post_ct_sel, + r_rx_txfifowr_post_ct_sel, + r_rx_internal_clk2_sel1, + r_rx_internal_clk2_sel2, + r_rx_rxfifowr_post_ct_sel, + r_rx_rxfiford_post_ct_sel, + r_rx_pld_clk1_delay_en, r_rx_pld_clk1_delay_sel, r_rx_pld_clk1_inv_en, + r_rx_compin_sel, r_rx_comp_cnt, + //r_rx_chnl_datapath_asn_4, r_rx_chnl_datapath_asn_3, + //r_rx_chnl_datapath_asn_2, r_rx_chnl_datapath_asn_1, + r_rx_asn_en, + r_rx_asn_bypass_pma_pcie_sw_done, + r_rx_asn_wait_for_fifo_flush_cnt, + r_rx_asn_wait_for_dll_reset_cnt, + r_rx_asn_wait_for_pma_pcie_sw_done_cnt, r_rx_usertest_sel, + r_rx_bonding_dft_in_en, + r_rx_bonding_dft_in_value, + //r_rx_bonding_dft_in_value, r_rx_bonding_dft_in_en, + r_rx_async_pld_rx_fifo_align_clr_rst_val, + r_rx_async_prbs_flags_sr_enable, + r_rx_async_pld_pma_ltd_b_rst_val, r_rx_async_pld_ltr_rst_val, + r_rx_async_pld_8g_signal_detect_out_rst_val, + r_rx_async_pld_10g_rx_crc32_err_rst_val, r_rx_aib_clk2_sel, + r_rx_aib_clk1_sel, pld_syncsm_en, pld_sclk1_rowclk, pld_sclk2_rowclk, + r_rx_hip_en, + pld_rx_prbs_err_clr, pld_rx_fabric_fifo_rd_en, + pld_rx_fabric_fifo_align_clr, pld_rx_clk2_rowclk, //pld_rx_clk2_dcm, + pld_rx_clk1_rowclk, pld_rx_clk1_dcm, pld_polinv_rx, + pld_pmaif_rxclkslip, pld_pma_rxpma_rstb, pld_pma_rs_lpbk_b, + pld_pma_reserved_out, pld_pma_ppm_lock, pld_pma_pcie_switch, + pld_pma_ltd_b, pld_pma_eye_monitor, pld_pma_early_eios, + pld_pma_coreclkin_rowclk, //pld_pma_coreclkin_dcm, + pld_pma_adapt_start, pld_pcs_rx_pld_rst_n, pld_ltr, pld_bitslip, + pld_adapter_rx_pld_rst_n, pld_8g_encdt, pld_8g_eidleinfersel, + pld_8g_byte_rev_en, pld_8g_bitloc_rev_en, pld_8g_a1a2_size, + pld_10g_rx_clr_ber_count, pld_10g_krfec_rx_clr_errblk_cnt, + nfrzdrv_in, csr_rdy_dly_in, usermode_in, bond_rx_fifo_us_in_wren, pr_channel_freeze_n, + tx_hrdrst_fabric_tx_transfer_en, + tx_clock_fifo_wr_clk, tx_clock_fifo_rd_clk, + avmm_hrdrst_fabric_osc_transfer_en, + bond_rx_fifo_us_in_rden, bond_rx_fifo_ds_in_wren, + bond_rx_fifo_ds_in_rden, //avmm_hrdrst_data_transfer_en, + bond_rx_asn_ds_in_fifo_hold, + //bond_rx_asn_ds_in_dll_lock_en, + //bond_rx_asn_ds_in_gen3_sel, + bond_rx_asn_us_in_fifo_hold, + //bond_rx_asn_us_in_dll_lock_en, + //bond_rx_asn_us_in_gen3_sel, + bond_rx_hrdrst_ds_in_fabric_rx_dll_lock, + bond_rx_hrdrst_us_in_fabric_rx_dll_lock, + bond_rx_hrdrst_ds_in_fabric_rx_dll_lock_req, + bond_rx_hrdrst_us_in_fabric_rx_dll_lock_req, + aib_fabric_tx_transfer_clk, aib_fabric_tx_sr_clk_in, + aib_fabric_rx_transfer_clk, aib_fabric_rx_sr_clk_in, + aib_fabric_rx_dll_lock_req, aib_fabric_rx_dll_lock, + aib_fabric_rx_data_in, aib_fabric_pld_pma_rxpll_lock, + aib_fabric_pld_pma_internal_clk2, aib_fabric_pld_pma_internal_clk1, + aib_fabric_pld_pma_hclk, aib_fabric_pld_pma_clkdiv_rx_user, + aib_fabric_pld_pcs_rx_clk_out, aib_fabric_pld_8g_rxelecidle, pld_fsr_load, pld_ssr_load, + pld_aib_fabric_rx_dll_lock_req, + pld_fabric_rx_fifo_srst, pld_fabric_rx_asn_data_transfer_en, + rx_chnl_dprio_status_write_en, pld_rx_dll_lock_req, + r_rx_hrdrst_rx_osc_clk_scg_en, r_rx_free_run_div_clk, r_rx_hrdrst_rst_sm_dis, r_rx_hrdrst_dll_lock_bypass, r_rx_hrdrst_align_bypass, r_rx_hrdrst_user_ctl_en, +// r_rx_hrdrst_master_sel, r_rx_hrdrst_dist_master_sel, + r_rx_ds_last_chnl, r_rx_us_last_chnl, + r_rx_write_ctrl, + r_rx_fifo_power_mode, + r_rx_stretch_num_stages, + r_rx_datapath_tb_sel, + r_rx_wr_adj_en, + r_rx_rd_adj_en, + aib_fabric_pld_rx_hssi_fifo_latency_pulse, + pld_rx_hssi_fifo_latency_pulse, + pld_rx_fifo_latency_adj_en, + r_rx_pipe_en, + r_rx_lpbk_en, + aib_fabric_tx_data_lpbk, + rx_pld_rate, rx_async_hssi_fabric_ssr_reserved, pld_rx_ssr_reserved_in, + sr_testbus, + avmm_testbus, + tx_chnl_testbus, + pld_rx_fabric_fifo_del + ); + + +/*AUTOINPUT*/ +// Beginning of automatic inputs (from unused autoinst inputs) + +// new inputs for ECO8 + input wire [1:0] r_rx_wren_fastbond; + input wire [1:0] r_rx_rden_fastbond; + +input [12:0] oaibdftdll2core; +input dft_adpt_aibiobsr_fastclkn; +input adapter_scan_rst_n; +input adapter_scan_mode_n; +input adapter_scan_shift_n; +input adapter_scan_shift_clk; +input adapter_scan_user_clk0; // 125MHz +input adapter_scan_user_clk1; // 250MHz +input adapter_scan_user_clk2; // 500MHz +input adapter_scan_user_clk3; // 1GHz +input adapter_clk_sel_n; +input adapter_occ_enable; +input pld_clk_dft_sel; +input aib_fabric_pld_8g_rxelecidle;// To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input aib_fabric_pld_pcs_rx_clk_out;// To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input aib_fabric_pld_pma_clkdiv_rx_user;// To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input aib_fabric_pld_pma_hclk;// To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v, ... +input aib_fabric_pld_pma_internal_clk1;// To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input aib_fabric_pld_pma_internal_clk2;// To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input aib_fabric_pld_pma_rxpll_lock;// To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input [39:0] aib_fabric_rx_data_in; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input aib_fabric_rx_dll_lock; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input aib_fabric_rx_sr_clk_in;// To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input aib_fabric_rx_transfer_clk;// To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input aib_fabric_tx_sr_clk_in;// To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input aib_fabric_tx_transfer_clk;// To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input aib_fabric_pld_rx_hssi_fifo_latency_pulse; +input pld_aib_fabric_rx_dll_lock_req; +input pld_rx_dll_lock_req; +input pld_fabric_rx_fifo_srst; +input pld_fabric_rx_asn_data_transfer_en; +//input avmm_hrdrst_data_transfer_en;// To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input tx_hrdrst_fabric_tx_transfer_en; +input tx_clock_fifo_wr_clk; +input tx_clock_fifo_rd_clk; +input avmm_hrdrst_fabric_osc_transfer_en; +input bond_rx_fifo_ds_in_rden;// To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input bond_rx_fifo_ds_in_wren;// To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input bond_rx_fifo_us_in_rden;// To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input bond_rx_fifo_us_in_wren;// To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input bond_rx_hrdrst_ds_in_fabric_rx_dll_lock; +input bond_rx_hrdrst_us_in_fabric_rx_dll_lock; +input bond_rx_hrdrst_ds_in_fabric_rx_dll_lock_req; +input bond_rx_hrdrst_us_in_fabric_rx_dll_lock_req; +input csr_rdy_dly_in; // To hdpldadapt_rxrst_ctl of hdpldadapt_rxrst_ctl.v +input usermode_in; +input nfrzdrv_in; // To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input aib_fabric_pld_pma_pfdmode_lock; +input pr_channel_freeze_n; +input pld_10g_krfec_rx_clr_errblk_cnt;// To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input pld_10g_rx_clr_ber_count;// To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input pld_8g_a1a2_size; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input pld_8g_bitloc_rev_en; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input pld_8g_byte_rev_en; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input [2:0] pld_8g_eidleinfersel; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input pld_8g_encdt; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input pld_adapter_rx_pld_rst_n;// To hdpldadapt_rxrst_ctl of hdpldadapt_rxrst_ctl.v +input pld_bitslip; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input pld_ltr; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input pld_pcs_rx_pld_rst_n; // To hdpldadapt_rxrst_ctl of hdpldadapt_rxrst_ctl.v +input pld_pma_adapt_start; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +//input pld_pma_coreclkin_dcm; // To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input pld_pma_coreclkin_rowclk;// To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input pld_pma_early_eios; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input [5:0] pld_pma_eye_monitor; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input pld_pma_ltd_b; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input [1:0] pld_pma_pcie_switch; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input pld_pma_ppm_lock; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input [4:0] pld_pma_reserved_out; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input pld_pma_rs_lpbk_b; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input pld_pma_rxpma_rstb; // To hdpldadapt_rxrst_ctl of hdpldadapt_rxrst_ctl.v +input pld_pmaif_rxclkslip; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input pld_polinv_rx; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input pld_rx_clk1_dcm; // To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input pld_rx_clk1_rowclk; // To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +//input pld_rx_clk2_dcm; // To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input pld_rx_clk2_rowclk; // To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input pld_rx_fabric_fifo_align_clr;// To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v, ... +input pld_rx_fabric_fifo_rd_en;// To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input pld_rx_prbs_err_clr; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input pld_sclk2_rowclk; // To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input pld_sclk1_rowclk; // To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input pld_syncsm_en; // To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input pld_aib_hssi_rx_dcd_cal_req; +input [1:0] r_rx_aib_clk1_sel; // To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input [1:0] r_rx_aib_clk2_sel; // To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input r_rx_async_pld_10g_rx_crc32_err_rst_val;// To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input r_rx_async_pld_8g_signal_detect_out_rst_val;// To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input r_rx_async_pld_ltr_rst_val;// To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input r_rx_async_pld_pma_ltd_b_rst_val;// To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input r_rx_async_pld_rx_fifo_align_clr_rst_val;// To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input r_rx_async_prbs_flags_sr_enable;// To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input r_rx_bonding_dft_in_en; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input r_rx_bonding_dft_in_value;// To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input bond_rx_asn_ds_in_fifo_hold; +//input bond_rx_asn_ds_in_dll_lock_en; +//input bond_rx_asn_ds_in_gen3_sel; +input bond_rx_asn_us_in_fifo_hold; +//input bond_rx_asn_us_in_dll_lock_en; +//input bond_rx_asn_us_in_gen3_sel; +input r_rx_asn_en; +input r_rx_usertest_sel; +input r_rx_asn_bypass_pma_pcie_sw_done; +input [7:0] r_rx_asn_wait_for_fifo_flush_cnt; +input [7:0] r_rx_asn_wait_for_dll_reset_cnt; +input [7:0] r_rx_asn_wait_for_pma_pcie_sw_done_cnt; +//input r_rx_bonding_dft_in_en; +//input r_rx_bonding_dft_in_value; +//input [7:0] r_rx_chnl_datapath_asn_1;// To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +//input [7:0] r_rx_chnl_datapath_asn_2;// To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +//input [7:0] r_rx_chnl_datapath_asn_3;// To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +//input [7:0] r_rx_chnl_datapath_asn_4;// To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input [7:0] r_rx_comp_cnt; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input [1:0] r_rx_compin_sel; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +//input r_rx_coreclkin_sel; // To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input r_rx_double_read; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input r_rx_ds_bypass_pipeln; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input r_rx_ds_master; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input [5:0] r_rx_fifo_empty; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input [5:0] r_rx_fifo_full; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input [2:0] r_rx_fifo_mode; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input [5:0] r_rx_fifo_pempty; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input [5:0] r_rx_fifo_pfull; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input r_rx_fifo_rd_clk_scg_en;// To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input [1:0] r_rx_fifo_rd_clk_sel; // To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input r_rx_fifo_wr_clk_scg_en;// To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input r_rx_fifo_wr_clk_sel; // To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input r_rx_gb_dv_en; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input r_rx_indv; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input [2:0] r_rx_phcomp_rd_delay; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input r_rx_pld_clk1_sel; // To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +//input r_rx_pld_clk2_sel; // To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input r_rx_pma_hclk_scg_en; // To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input r_rx_osc_clk_scg_en; // To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input r_rx_fifo_wr_clk_del_sm_scg_en; +input r_rx_fifo_rd_clk_ins_sm_scg_en; +input r_rx_sclk_sel; // To hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +input r_rx_internal_clk1_sel1; +input r_rx_internal_clk1_sel2; +input r_rx_txfiford_post_ct_sel; +input r_rx_txfifowr_post_ct_sel; +input r_rx_internal_clk2_sel1; +input r_rx_internal_clk2_sel2; +input r_rx_rxfifowr_post_ct_sel; +input r_rx_rxfiford_post_ct_sel; +input r_rx_pld_clk1_delay_en; +input [3:0] r_rx_pld_clk1_delay_sel; +input r_rx_pld_clk1_inv_en; +input r_rx_stop_read; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input r_rx_stop_write; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input r_rx_truebac2bac; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input r_rx_us_bypass_pipeln; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input r_rx_us_master; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input r_rx_wa_en; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input r_rx_pld_8g_eidleinfersel_polling_bypass; +input r_rx_pld_pma_eye_monitor_polling_bypass; +input r_rx_pld_pma_pcie_switch_polling_bypass; +input r_rx_pld_pma_reser_out_polling_bypass; +input rx_async_fabric_hssi_fsr_load;// To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input rx_async_fabric_hssi_ssr_load;// To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input [1:0] rx_async_hssi_fabric_fsr_data;// To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input rx_async_hssi_fabric_fsr_load;// To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input [62:0] rx_async_hssi_fabric_ssr_data;// To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input rx_async_hssi_fabric_ssr_load;// To hdpldadapt_rx_async of hdpldadapt_rx_async.v +input rx_fsr_mask_tx_pll; // To hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +input r_rx_hrdrst_rx_osc_clk_scg_en; +input r_rx_free_run_div_clk; +input r_rx_hrdrst_rst_sm_dis; +input r_rx_hrdrst_dll_lock_bypass; +input r_rx_hrdrst_align_bypass; +input r_rx_hrdrst_user_ctl_en; +//input [1:0] r_rx_hrdrst_master_sel; +//input r_rx_hrdrst_dist_master_sel; +input r_rx_ds_last_chnl; +input r_rx_us_last_chnl; + +input r_rx_write_ctrl; +input [2:0] r_rx_fifo_power_mode; +input [2:0] r_rx_stretch_num_stages; +input [3:0] r_rx_datapath_tb_sel; +input r_rx_wr_adj_en; +input r_rx_rd_adj_en; +input r_rx_hip_en; +input pld_rx_fifo_latency_adj_en; +input r_rx_pipe_en; +input r_rx_lpbk_en; +input [39:0] aib_fabric_tx_data_lpbk; +input [1:0] rx_pld_rate; +input [1:0] pld_rx_ssr_reserved_in; +input [1:0] rx_async_hssi_fabric_ssr_reserved; +input [19:0] sr_testbus; +input [19:0] avmm_testbus; +input [19:0] tx_chnl_testbus; +input [19:0] sr_parity_error_flag; + + + +// End of automatics +/*AUTOOUTPUT*/ +// Beginning of automatic outputs (from unused autoinst outputs) + +output [12:0] dft_fabric_oaibdftdll2core; +output pld_hssi_asn_dll_lock_en; +output pld_fabric_asn_dll_lock_en; +output pld_hssi_rx_transfer_en; +output pld_aib_fabric_rx_dll_lock; +output aib_fabric_adapter_rx_pld_rst_n;// From hdpldadapt_rxrst_ctl of hdpldadapt_rxrst_ctl.v +output aib_fabric_pcs_rx_pld_rst_n;// From hdpldadapt_rxrst_ctl of hdpldadapt_rxrst_ctl.v +output aib_fabric_pld_pma_coreclkin;// From hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +output aib_fabric_pld_pma_rxpma_rstb;// From hdpldadapt_rxrst_ctl of hdpldadapt_rxrst_ctl.v +output aib_fabric_pld_sclk; // From hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +output aib_fabric_rx_dll_lock_req;// To hdpldadapt_rx_async of hdpldadapt_rx_async.v +output bond_rx_asn_ds_out_fifo_hold; +//output bond_rx_asn_ds_out_dll_lock_en; +output bond_rx_asn_us_out_fifo_hold; +//output bond_rx_asn_us_out_dll_lock_en; +output bond_rx_fifo_ds_out_rden;// From hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +output bond_rx_fifo_ds_out_wren;// From hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +output bond_rx_fifo_us_out_rden;// From hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +output bond_rx_fifo_us_out_wren;// From hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +output bond_rx_hrdrst_ds_out_fabric_rx_dll_lock; +output bond_rx_hrdrst_us_out_fabric_rx_dll_lock; +output bond_rx_hrdrst_ds_out_fabric_rx_dll_lock_req; +output bond_rx_hrdrst_us_out_fabric_rx_dll_lock_req; +output pld_10g_krfec_rx_blk_lock;// From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output [1:0] pld_10g_krfec_rx_diag_data_status;// From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output pld_10g_krfec_rx_frame; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output pld_10g_rx_crc32_err; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output pld_10g_rx_frame_lock; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output pld_10g_rx_hi_ber; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output [3:0] pld_8g_a1a2_k1k2_flag; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output pld_8g_empty_rmf; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output pld_8g_full_rmf; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output pld_8g_rxelecidle; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output pld_8g_signal_detect_out;// From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output [4:0] pld_8g_wa_boundary; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output pld_pcs_rx_clk_out1_dcm;// From hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +output pld_pcs_rx_clk_out1_hioint;// From hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +output pld_pcs_rx_clk_out2_dcm;// From hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +output pld_pcs_rx_clk_out2_hioint;// From hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +output pld_pma_adapt_done; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +//output pld_pma_hclk_dcm; // From hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +output pld_pma_hclk_hioint; // From hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +//output pld_pma_internal_clk1_dcm;// From hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +output pld_pma_internal_clk1_hioint;// From hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +//output pld_pma_internal_clk2_dcm;// From hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +output pld_pma_internal_clk2_hioint;// From hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +output [1:0] pld_pma_pcie_sw_done; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output [4:0] pld_pma_reserved_in; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output pld_pma_rx_detect_valid;// From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output pld_pma_rxpll_lock; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output pld_pma_signal_ok; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output [7:0] pld_pma_testbus; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output pld_rx_fabric_align_done;// From hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +output [79:0] pld_rx_fabric_data_out; // From hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +output pld_rx_fabric_fifo_empty;// From hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +output pld_rx_fabric_fifo_full;// From hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +output pld_rx_fabric_fifo_insert;// From hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +output pld_rx_fabric_fifo_latency_pulse;// From hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +output pld_rx_fabric_fifo_pempty;// From hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +output pld_rx_fabric_fifo_pfull;// From hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +output pld_rx_hssi_fifo_empty; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output pld_rx_hssi_fifo_full; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output pld_rx_prbs_done; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output pld_rx_prbs_err; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output [19:0] pld_test_data; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output rx_clock_pld_sclk; +output rx_asn_fifo_hold; // From hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +//output rx_asn_fifo_srst; // From hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +//output rx_asn_gen3_sel; // From hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +output rx_asn_rate_change_in_progress; +output rx_asn_dll_lock_en; // From hdpldadapt_rx_datapath of hdpldadapt_rx_datapath.v +output [2:0] rx_async_fabric_hssi_fsr_data;// From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output [35:0] rx_async_fabric_hssi_ssr_data;// From hdpldadapt_rx_async of hdpldadapt_rx_async.v +output pld_fsr_load; +output pld_ssr_load; +output pld_rx_hssi_fifo_latency_pulse; +output pld_aib_hssi_rx_dcd_cal_done; +output [1:0] pld_rx_ssr_reserved_out; +output [1:0] rx_async_fabric_hssi_ssr_reserved; +output pld_pma_pfdmode_lock; +output [1:0] rx_fsr_parity_checker_in; +output [64:0] rx_ssr_parity_checker_in; +output pld_rx_fifo_ready; +// End of automatics + +output [1:0] adapter_scan_out_occ1; +output [4:0] adapter_scan_out_occ2; +output adapter_scan_out_occ3; +output adapter_scan_out_occ4; +output [1:0] adapter_scan_out_occ5; +output [10:0] adapter_scan_out_occ6; +output adapter_scan_out_occ7; +output adapter_scan_out_occ8; +output adapter_scan_out_occ9; +output adapter_scan_out_occ10; +output adapter_scan_out_occ11; +output adapter_scan_out_occ12; +output adapter_scan_out_occ13; +output adapter_scan_out_occ14; +output adapter_scan_out_occ15; +output adapter_scan_out_occ16; +output adapter_scan_out_occ17; +output [1:0] adapter_scan_out_occ18; +output adapter_scan_out_occ19; +output adapter_scan_out_occ20; +output [1:0] adapter_scan_out_occ21; +output adapter_non_occ_scan_out; +output adapter_occ_scan_out; + +// temp +output [7:0] rx_chnl_dprio_status; // To hdpldadapt_avmm1 of hdpldadapt_avmm1.v +output rx_chnl_dprio_status_write_en_ack;// To hdpldadapt_avmm1 of hdpldadapt_avmm1.v +input rx_chnl_dprio_status_write_en;// From hdpldadapt_avmm1 of hdpldadapt_avmm1.v + +output pld_rx_fabric_fifo_del; +output pld_pma_rx_found; +//assign rx_chnl_dprio_status = 8'h0; +//assign rx_chnl_dprio_status_write_en_ack = 1'b0; + + + +/*AUTOWIRE*/ +// Beginning of automatic wires (for undeclared instantiated-module outputs) +wire rx_clock_asn_pma_hclk; // From hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +wire rx_clock_async_rx_osc_clk;// From hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +wire rx_clock_async_tx_osc_clk;// From hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +wire rx_clock_fifo_rd_clk_ins_sm; +wire rx_clock_fifo_rd_clk; // From hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +wire rx_clock_fifo_sclk; // From hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +wire rx_clock_fifo_wr_clk_del_sm; +wire rx_clock_fifo_wr_clk; // From hdpldadapt_rxclk_ctl of hdpldadapt_rxclk_ctl.v +wire rx_reset_asn_pma_hclk_rst_n;// From hdpldadapt_rxrst_ctl of hdpldadapt_rxrst_ctl.v +wire rx_reset_async_rx_osc_clk_rst_n;// From hdpldadapt_rxrst_ctl of hdpldadapt_rxrst_ctl.v +wire rx_reset_async_tx_osc_clk_rst_n;// From hdpldadapt_rxrst_ctl of hdpldadapt_rxrst_ctl.v +wire rx_reset_fifo_rd_rst_n; // From hdpldadapt_rxrst_ctl of hdpldadapt_rxrst_ctl.v +wire rx_reset_fifo_sclk_rst_n;// From hdpldadapt_rxrst_ctl of hdpldadapt_rxrst_ctl.v +wire rx_reset_fifo_wr_rst_n; // From hdpldadapt_rxrst_ctl of hdpldadapt_rxrst_ctl.v +wire rx_reset_pld_pma_hclk_rst_n;// From hdpldadapt_rxrst_ctl of hdpldadapt_rxrst_ctl.v +wire [1:0] rx_ssr_pcie_sw_done; // From hdpldadapt_rx_async of hdpldadapt_rx_async.v +// End of automatics +wire rx_hrdrst_rx_fifo_srst; +wire rx_hrdrst_fabric_rx_dll_lock; +wire rx_hrdrst_fabric_rx_transfer_en; +wire rx_hrdrst_asn_data_transfer_en; +wire sr_hssi_rx_dcd_cal_done; +wire sr_hssi_rx_transfer_en; +//wire [1:0] r_rx_master_sel = 2'b00; +//wire r_rx_dist_master_sel = 1'b0; +//wire r_rx_ds_last_chnl = 1'b0; +//wire r_rx_us_last_chnl = 1'b0; + +wire rx_fabric_align_done_raw; +wire rx_fifo_ready; +wire wa_error; +wire [3:0] wa_error_cnt; +wire [39:0] aib_fabric_rx_data_in_int = r_rx_lpbk_en ? aib_fabric_tx_data_lpbk : aib_fabric_rx_data_in; + +wire [19:0] rx_fifo_testbus1; // RX FIFO +wire [19:0] rx_fifo_testbus2; // RX FIFO +wire [19:0] rx_cp_bond_testbus; +wire [19:0] rx_asn_testbus; +wire [19:0] deletion_sm_testbus; +wire [19:0] insertion_sm_testbus; +wire [19:0] word_align_testbus; +wire [19:0] rx_hrdrst_testbus; +wire [19:0] rx_chnl_testbus; +wire [19:0] sr_test_data; +wire rd_align_clr_reg; +wire [19:0] sr_testbus_int; + +assign dft_fabric_oaibdftdll2core = nfrzdrv_in ? oaibdftdll2core : 13'b1111_1111_1111; + +assign adapter_scan_out_occ1[1:0] = 2'b00; +assign adapter_scan_out_occ2[4:0] = 5'b00000; +assign adapter_scan_out_occ3 = 1'b0; +assign adapter_scan_out_occ4 = 1'b0; +assign adapter_scan_out_occ5[1:0] = 2'b00; +assign adapter_scan_out_occ6[10:0] = 11'b000_0000_0000; +assign adapter_scan_out_occ7 = 1'b0; +assign adapter_scan_out_occ8 = 1'b0; +assign adapter_scan_out_occ9 = 1'b0; +assign adapter_scan_out_occ10 = 1'b0; +assign adapter_scan_out_occ11 = 1'b0; +assign adapter_scan_out_occ12 = 1'b0; +assign adapter_scan_out_occ13 = 1'b0; +assign adapter_scan_out_occ14 = 1'b0; +assign adapter_scan_out_occ15 = 1'b0; +assign adapter_scan_out_occ16 = 1'b0; +assign adapter_scan_out_occ17 = 1'b0; +assign adapter_scan_out_occ18[1:0] = 2'b00; +assign adapter_scan_out_occ19 = 1'b0; +assign adapter_scan_out_occ20 = 1'b0; +assign adapter_scan_out_occ21[1:0] = 2'b00; +assign adapter_non_occ_scan_out = 1'b0; +//assign adapter_occ_scan_out = 1'b0; + +assign adapter_occ_scan_out = nfrzdrv_in ? 1'b0 : 1'b1; + + +/* REMOVED FOR ECO8 + +// Separate HIP and non-HIP bonding paths for TIMING closure purpose +assign bond_rx_fifo_ds_in_wren_hip = bond_rx_fifo_ds_in_wren; +assign bond_rx_fifo_ds_in_wren_non_hip = bond_rx_fifo_ds_in_wren; +assign bond_rx_fifo_us_in_wren_hip = bond_rx_fifo_us_in_wren; +assign bond_rx_fifo_us_in_wren_non_hip = bond_rx_fifo_us_in_wren; + +assign bond_rx_fifo_ds_in_wren_int = r_rx_hip_en ? bond_rx_fifo_ds_in_wren_hip: bond_rx_fifo_ds_in_wren_non_hip; +assign bond_rx_fifo_us_in_wren_int = r_rx_hip_en ? bond_rx_fifo_us_in_wren_hip: bond_rx_fifo_us_in_wren_non_hip; + +*/ + +hdpldadapt_rx_datapath hdpldadapt_rx_datapath(/*AUTOINST*/ + // Outputs + .pld_rx_fabric_data_out(pld_rx_fabric_data_out[79:0]), + .pld_fabric_asn_dll_lock_en(pld_fabric_asn_dll_lock_en), + .rx_fabric_align_done_raw(rx_fabric_align_done_raw), + .rx_asn_rate_change_in_progress(rx_asn_rate_change_in_progress), + .rx_asn_dll_lock_en(rx_asn_dll_lock_en), + .rx_asn_fifo_hold (rx_asn_fifo_hold), + .pld_rx_hssi_fifo_latency_pulse (pld_rx_hssi_fifo_latency_pulse), + //.rx_asn_fifo_srst (rx_asn_fifo_srst), + //.rx_asn_gen3_sel (rx_asn_gen3_sel), + .pld_rx_fabric_fifo_full(pld_rx_fabric_fifo_full), + .pld_rx_fabric_fifo_empty(pld_rx_fabric_fifo_empty), + .pld_rx_fabric_fifo_pfull(pld_rx_fabric_fifo_pfull), + .pld_rx_fabric_fifo_pempty(pld_rx_fabric_fifo_pempty), + .pld_rx_fabric_fifo_latency_pulse(pld_rx_fabric_fifo_latency_pulse), + .pld_rx_fabric_fifo_insert(pld_rx_fabric_fifo_insert), + .pld_rx_fabric_fifo_del(pld_rx_fabric_fifo_del), + .pld_rx_fabric_align_done(pld_rx_fabric_align_done), + .pld_rx_fifo_ready(pld_rx_fifo_ready), + .bond_rx_fifo_ds_out_rden(bond_rx_fifo_ds_out_rden), + .bond_rx_fifo_ds_out_wren(bond_rx_fifo_ds_out_wren), + .bond_rx_fifo_us_out_rden(bond_rx_fifo_us_out_rden), + .bond_rx_fifo_us_out_wren(bond_rx_fifo_us_out_wren), + .bond_rx_asn_ds_out_fifo_hold(bond_rx_asn_ds_out_fifo_hold), + //.bond_rx_asn_ds_out_dll_lock_en(bond_rx_asn_ds_out_dll_lock_en), + .bond_rx_asn_us_out_fifo_hold(bond_rx_asn_us_out_fifo_hold), + //.bond_rx_asn_us_out_dll_lock_en(bond_rx_asn_us_out_dll_lock_en), + .wa_error (wa_error), + .wa_error_cnt (wa_error_cnt[3:0]), + .rd_align_clr_reg (rd_align_clr_reg), + .rx_fifo_ready (rx_fifo_ready), + + // Inputs + // new inputs for ECO8 + .r_rx_wren_fastbond (r_rx_wren_fastbond), + .r_rx_rden_fastbond (r_rx_rden_fastbond), + .aib_fabric_rx_data_in(aib_fabric_rx_data_in_int[39:0]), + .aib_fabric_pld_rx_hssi_fifo_latency_pulse (aib_fabric_pld_rx_hssi_fifo_latency_pulse), + .r_rx_usertest_sel(r_rx_usertest_sel), + //.avmm_hrdrst_data_transfer_en(avmm_hrdrst_data_transfer_en), + .rx_hrdrst_asn_data_transfer_en(rx_hrdrst_asn_data_transfer_en), + .rx_hrdrst_rx_fifo_srst(rx_hrdrst_rx_fifo_srst), + .r_rx_hrdrst_user_ctl_en(r_rx_hrdrst_user_ctl_en), + .r_rx_bonding_dft_in_en(r_rx_bonding_dft_in_en), + .r_rx_bonding_dft_in_value(r_rx_bonding_dft_in_value), + .r_rx_comp_cnt (r_rx_comp_cnt[7:0]), + .r_rx_compin_sel (r_rx_compin_sel[1:0]), + .r_rx_double_read (r_rx_double_read), + .r_rx_ds_bypass_pipeln(r_rx_ds_bypass_pipeln), + .r_rx_ds_master (r_rx_ds_master), + .r_rx_fifo_empty (r_rx_fifo_empty[5:0]), + .r_rx_fifo_mode (r_rx_fifo_mode[2:0]), + .r_rx_fifo_full (r_rx_fifo_full[5:0]), + .r_rx_indv (r_rx_indv), + .r_rx_fifo_pempty (r_rx_fifo_pempty[5:0]), + .r_rx_fifo_pfull (r_rx_fifo_pfull[5:0]), + .r_rx_phcomp_rd_delay(r_rx_phcomp_rd_delay[2:0]), + .bond_rx_asn_ds_in_fifo_hold(bond_rx_asn_ds_in_fifo_hold), + //.bond_rx_asn_ds_in_dll_lock_en(bond_rx_asn_ds_in_dll_lock_en), + //.bond_rx_asn_ds_in_gen3_sel(bond_rx_asn_ds_in_gen3_sel), + .bond_rx_asn_us_in_fifo_hold(bond_rx_asn_us_in_fifo_hold), + //.bond_rx_asn_us_in_dll_lock_en(bond_rx_asn_us_in_dll_lock_en), + //.bond_rx_asn_us_in_gen3_sel(bond_rx_asn_us_in_gen3_sel), + .r_rx_asn_en(r_rx_asn_en), + .r_rx_asn_bypass_pma_pcie_sw_done(r_rx_asn_bypass_pma_pcie_sw_done), + .r_rx_asn_wait_for_fifo_flush_cnt(r_rx_asn_wait_for_fifo_flush_cnt), + .r_rx_asn_wait_for_dll_reset_cnt(r_rx_asn_wait_for_dll_reset_cnt), + .r_rx_asn_wait_for_pma_pcie_sw_done_cnt(r_rx_asn_wait_for_pma_pcie_sw_done_cnt), +// .r_rx_master_sel(r_rx_compin_sel[1:0]), +// .r_rx_dist_master_sel(r_rx_ds_master), + //.r_rx_bonding_dft_in_en(r_rx_bonding_dft_in_en), + //.r_rx_bonding_dft_in_value(r_rx_bonding_dft_in_value), + //.r_rx_chnl_datapath_asn_1(r_rx_chnl_datapath_asn_1[7:0]), + //.r_rx_chnl_datapath_asn_2(r_rx_chnl_datapath_asn_2[7:0]), + //.r_rx_chnl_datapath_asn_3(r_rx_chnl_datapath_asn_3[7:0]), + //.r_rx_chnl_datapath_asn_4(r_rx_chnl_datapath_asn_4[7:0]), + .r_rx_stop_read (r_rx_stop_read), + .r_rx_stop_write (r_rx_stop_write), + .r_rx_truebac2bac (r_rx_truebac2bac), + .r_rx_us_bypass_pipeln(r_rx_us_bypass_pipeln), + .r_rx_us_master (r_rx_us_master), + .r_rx_gb_dv_en (r_rx_gb_dv_en), + .r_rx_wa_en (r_rx_wa_en), + .r_rx_write_ctrl (r_rx_write_ctrl), + .r_rx_fifo_power_mode (r_rx_fifo_power_mode), + .r_rx_stretch_num_stages (r_rx_stretch_num_stages), +// .r_rx_datapath_tb_sel (r_rx_datapath_tb_sel), + .r_rx_wr_adj_en (r_rx_wr_adj_en), + .r_rx_rd_adj_en (r_rx_rd_adj_en), + .r_rx_pipe_en (r_rx_pipe_en), + .r_rx_ds_last_chnl(r_rx_ds_last_chnl), + .r_rx_us_last_chnl(r_rx_us_last_chnl), + .rx_pld_rate (rx_pld_rate), + .pr_channel_freeze_n(pr_channel_freeze_n), + .nfrzdrv_in (nfrzdrv_in), + .rx_fifo_testbus1 (rx_fifo_testbus1), + .rx_fifo_testbus2 (rx_fifo_testbus2), + .rx_cp_bond_testbus (rx_cp_bond_testbus), + .rx_asn_testbus (rx_asn_testbus), + .word_align_testbus (word_align_testbus), + .deletion_sm_testbus (deletion_sm_testbus), + .insertion_sm_testbus (insertion_sm_testbus), + + .rx_clock_asn_pma_hclk(rx_clock_asn_pma_hclk), + .rx_reset_asn_pma_hclk_rst_n(rx_reset_asn_pma_hclk_rst_n), + .rx_fsr_mask_tx_pll(rx_fsr_mask_tx_pll), + .rx_ssr_pcie_sw_done(rx_ssr_pcie_sw_done[1:0]), + .rx_clock_fifo_rd_clk(rx_clock_fifo_rd_clk), + .rx_clock_fifo_wr_clk(rx_clock_fifo_wr_clk), + .rx_clock_fifo_wr_clk_del_sm(rx_clock_fifo_wr_clk_del_sm), + .rx_clock_fifo_rd_clk_ins_sm(rx_clock_fifo_rd_clk_ins_sm), + .q1_rx_clock_fifo_wr_clk(q1_rx_clock_fifo_wr_clk), + .q2_rx_clock_fifo_wr_clk(q2_rx_clock_fifo_wr_clk), + .q3_rx_clock_fifo_wr_clk(q3_rx_clock_fifo_wr_clk), + .q4_rx_clock_fifo_wr_clk(q4_rx_clock_fifo_wr_clk), + .q5_rx_clock_fifo_wr_clk(q5_rx_clock_fifo_wr_clk), + .q6_rx_clock_fifo_wr_clk(q6_rx_clock_fifo_wr_clk), + .rx_reset_fifo_wr_rst_n(rx_reset_fifo_wr_rst_n), + .rx_reset_fifo_sclk_rst_n(rx_reset_fifo_sclk_rst_n), + .rx_reset_fifo_rd_rst_n(rx_reset_fifo_rd_rst_n), + .rx_clock_fifo_sclk(rx_clock_fifo_sclk), + .bond_rx_fifo_ds_in_rden(bond_rx_fifo_ds_in_rden), + .bond_rx_fifo_ds_in_wren(bond_rx_fifo_ds_in_wren), + .bond_rx_fifo_us_in_rden(bond_rx_fifo_us_in_rden), + .bond_rx_fifo_us_in_wren(bond_rx_fifo_us_in_wren), + .pld_fabric_rx_asn_data_transfer_en(pld_fabric_rx_asn_data_transfer_en), + .pld_rx_fabric_fifo_rd_en(pld_rx_fabric_fifo_rd_en), + .pld_rx_fifo_latency_adj_en (pld_rx_fifo_latency_adj_en), + .pld_rx_fabric_fifo_align_clr(pld_rx_fabric_fifo_align_clr)); +hdpldadapt_rx_async hdpldadapt_rx_async(/*AUTOINST*/ + // Outputs + .pld_pma_pfdmode_lock (pld_pma_pfdmode_lock), + .pld_rx_ssr_reserved_out (pld_rx_ssr_reserved_out), + .rx_async_fabric_hssi_ssr_reserved (rx_async_fabric_hssi_ssr_reserved), + .pld_8g_rxelecidle(pld_8g_rxelecidle), + .pld_pma_rxpll_lock(pld_pma_rxpll_lock), + .pld_8g_signal_detect_out(pld_8g_signal_detect_out), + .pld_10g_krfec_rx_blk_lock(pld_10g_krfec_rx_blk_lock), + .pld_10g_krfec_rx_diag_data_status(pld_10g_krfec_rx_diag_data_status[1:0]), + .pld_10g_rx_crc32_err(pld_10g_rx_crc32_err), + .pld_10g_rx_frame_lock(pld_10g_rx_frame_lock), + .pld_10g_rx_hi_ber(pld_10g_rx_hi_ber), + .pld_8g_a1a2_k1k2_flag(pld_8g_a1a2_k1k2_flag[3:0]), + .pld_8g_empty_rmf(pld_8g_empty_rmf), + .pld_8g_full_rmf(pld_8g_full_rmf), + .pld_8g_wa_boundary(pld_8g_wa_boundary[4:0]), + .pld_pma_adapt_done(pld_pma_adapt_done), + .pld_pma_pcie_sw_done(pld_pma_pcie_sw_done[1:0]), + .pld_pma_reserved_in(pld_pma_reserved_in[4:0]), + .pld_pma_rx_detect_valid(pld_pma_rx_detect_valid), + .pld_pma_signal_ok(pld_pma_signal_ok), + .pld_pma_testbus(pld_pma_testbus[7:0]), + .pld_rx_prbs_done(pld_rx_prbs_done), + .pld_rx_prbs_err(pld_rx_prbs_err), + .pld_test_data (pld_test_data[19:0]), + .pld_10g_krfec_rx_frame(pld_10g_krfec_rx_frame), + .pld_rx_hssi_fifo_full(pld_rx_hssi_fifo_full), + .pld_rx_hssi_fifo_empty(pld_rx_hssi_fifo_empty), + .rx_ssr_pcie_sw_done(rx_ssr_pcie_sw_done[1:0]), + .rx_async_fabric_hssi_fsr_data(rx_async_fabric_hssi_fsr_data[2:0]), + .rx_async_fabric_hssi_ssr_data(rx_async_fabric_hssi_ssr_data[35:0]), + .pld_fsr_load(pld_fsr_load), + .pld_ssr_load(pld_ssr_load), + .sr_hssi_rx_dcd_cal_done(sr_hssi_rx_dcd_cal_done), + .sr_hssi_rx_transfer_en(sr_hssi_rx_transfer_en), + .pld_aib_hssi_rx_dcd_cal_done(pld_aib_hssi_rx_dcd_cal_done), + .sr_test_data (sr_test_data), + .pld_pma_rx_found (pld_pma_rx_found), + .rx_fsr_parity_checker_in (rx_fsr_parity_checker_in), + .rx_ssr_parity_checker_in (rx_ssr_parity_checker_in), + .sr_testbus_int (sr_testbus_int), + // Inputs + .usermode_in (usermode_in), + .sr_testbus (sr_testbus), + .aib_fabric_pld_pma_pfdmode_lock (aib_fabric_pld_pma_pfdmode_lock), + .r_rx_pld_8g_eidleinfersel_polling_bypass (r_rx_pld_8g_eidleinfersel_polling_bypass), + .r_rx_pld_pma_eye_monitor_polling_bypass (r_rx_pld_pma_eye_monitor_polling_bypass), + .r_rx_pld_pma_pcie_switch_polling_bypass (r_rx_pld_pma_pcie_switch_polling_bypass), + .r_rx_pld_pma_reser_out_polling_bypass (r_rx_pld_pma_reser_out_polling_bypass), + .pld_test_data_int (rx_chnl_testbus), + .pld_rx_ssr_reserved_in (pld_rx_ssr_reserved_in), + .rx_async_hssi_fabric_ssr_reserved (rx_async_hssi_fabric_ssr_reserved), + //.pld_rx_fabric_data_out (pld_rx_fabric_data_out[1:0]), + .pld_rx_fifo_latency_adj_en (pld_rx_fifo_latency_adj_en), + .pld_aib_hssi_rx_dcd_cal_req (pld_aib_hssi_rx_dcd_cal_req), + .rx_hrdrst_fabric_rx_dll_lock(rx_hrdrst_fabric_rx_dll_lock), + .rx_hrdrst_fabric_rx_transfer_en(rx_hrdrst_fabric_rx_transfer_en), + .pld_rx_dll_lock_req (pld_rx_dll_lock_req), + .pr_channel_freeze_n(pr_channel_freeze_n), + .nfrzdrv_in (nfrzdrv_in), + .r_rx_async_pld_ltr_rst_val(r_rx_async_pld_ltr_rst_val), + .r_rx_async_pld_pma_ltd_b_rst_val(r_rx_async_pld_pma_ltd_b_rst_val), + .r_rx_async_pld_8g_signal_detect_out_rst_val(r_rx_async_pld_8g_signal_detect_out_rst_val), + .r_rx_async_pld_10g_rx_crc32_err_rst_val(r_rx_async_pld_10g_rx_crc32_err_rst_val), + .r_rx_async_pld_rx_fifo_align_clr_rst_val(r_rx_async_pld_rx_fifo_align_clr_rst_val), + .r_rx_async_prbs_flags_sr_enable(r_rx_async_prbs_flags_sr_enable), + .pld_ltr (pld_ltr), + .pld_pma_ltd_b (pld_pma_ltd_b), + .pld_10g_krfec_rx_clr_errblk_cnt(pld_10g_krfec_rx_clr_errblk_cnt), + .pld_10g_rx_clr_ber_count(pld_10g_rx_clr_ber_count), + .pld_8g_a1a2_size(pld_8g_a1a2_size), + .pld_8g_bitloc_rev_en(pld_8g_bitloc_rev_en), + .pld_8g_byte_rev_en(pld_8g_byte_rev_en), + .pld_8g_eidleinfersel(pld_8g_eidleinfersel[2:0]), + .pld_8g_encdt (pld_8g_encdt), + .pld_bitslip (pld_bitslip), + .pld_pma_adapt_start(pld_pma_adapt_start), + .pld_pma_early_eios(pld_pma_early_eios), + .pld_pma_eye_monitor(pld_pma_eye_monitor[5:0]), + .pld_pma_pcie_switch(pld_pma_pcie_switch[1:0]), + .pld_pma_ppm_lock(pld_pma_ppm_lock), + .pld_pma_reserved_out(pld_pma_reserved_out[4:0]), + .pld_pma_rs_lpbk_b(pld_pma_rs_lpbk_b), + .pld_pmaif_rxclkslip(pld_pmaif_rxclkslip), + .pld_polinv_rx (pld_polinv_rx), + .pld_rx_prbs_err_clr(pld_rx_prbs_err_clr), + .pld_syncsm_en (pld_syncsm_en), +// .pld_rx_fabric_fifo_align_clr(pld_rx_fabric_fifo_align_clr), // To reg version to avoid glitching + .pld_rx_fabric_fifo_align_clr(rd_align_clr_reg), + .rx_reset_async_rx_osc_clk_rst_n(rx_reset_async_rx_osc_clk_rst_n), + .rx_reset_async_tx_osc_clk_rst_n(rx_reset_async_tx_osc_clk_rst_n), + .rx_clock_async_rx_osc_clk(rx_clock_async_rx_osc_clk), + .rx_clock_async_tx_osc_clk(rx_clock_async_tx_osc_clk), + .rx_async_hssi_fabric_fsr_load(rx_async_hssi_fabric_fsr_load), + .rx_async_hssi_fabric_ssr_load(rx_async_hssi_fabric_ssr_load), + .rx_async_hssi_fabric_fsr_data(rx_async_hssi_fabric_fsr_data[1:0]), + .rx_async_hssi_fabric_ssr_data(rx_async_hssi_fabric_ssr_data[62:0]), + .rx_async_fabric_hssi_fsr_load(rx_async_fabric_hssi_fsr_load), + .rx_async_fabric_hssi_ssr_load(rx_async_fabric_hssi_ssr_load), + .aib_fabric_pld_8g_rxelecidle(aib_fabric_pld_8g_rxelecidle), + .aib_fabric_pld_pma_rxpll_lock(aib_fabric_pld_pma_rxpll_lock)); +hdpldadapt_rxclk_ctl hdpldadapt_rxclk_ctl(/*AUTOINST*/ + // Outputs + .aib_fabric_pld_pma_coreclkin(aib_fabric_pld_pma_coreclkin), + .aib_fabric_pld_sclk (aib_fabric_pld_sclk), + .pld_pcs_rx_clk_out1_hioint(pld_pcs_rx_clk_out1_hioint), + .pld_pcs_rx_clk_out1_dcm(pld_pcs_rx_clk_out1_dcm), + .pld_pcs_rx_clk_out2_hioint(pld_pcs_rx_clk_out2_hioint), + .pld_pcs_rx_clk_out2_dcm(pld_pcs_rx_clk_out2_dcm), + .pld_pma_internal_clk1_hioint(pld_pma_internal_clk1_hioint), + //.pld_pma_internal_clk1_dcm(pld_pma_internal_clk1_dcm), + .pld_pma_internal_clk2_hioint(pld_pma_internal_clk2_hioint), + //.pld_pma_internal_clk2_dcm(pld_pma_internal_clk2_dcm), + .pld_pma_hclk_hioint (pld_pma_hclk_hioint), + //.pld_pma_hclk_dcm (pld_pma_hclk_dcm), + .rx_clock_pld_sclk(rx_clock_pld_sclk), + .rx_clock_reset_hrdrst_rx_osc_clk(rx_clock_reset_hrdrst_rx_osc_clk), + .rx_clock_reset_fifo_wr_clk(rx_clock_reset_fifo_wr_clk), + .rx_clock_reset_fifo_rd_clk(rx_clock_reset_fifo_rd_clk), + .rx_clock_fifo_sclk(rx_clock_fifo_sclk), + .rx_clock_reset_asn_pma_hclk(rx_clock_reset_asn_pma_hclk), + .rx_clock_reset_async_rx_osc_clk(rx_clock_reset_async_rx_osc_clk), + .rx_clock_reset_async_tx_osc_clk(rx_clock_reset_async_tx_osc_clk), + .rx_clock_pld_pma_hclk(rx_clock_pld_pma_hclk), + .rx_clock_fifo_wr_clk_del_sm(rx_clock_fifo_wr_clk_del_sm), + .rx_clock_fifo_wr_clk(rx_clock_fifo_wr_clk), + .q1_rx_clock_fifo_wr_clk(q1_rx_clock_fifo_wr_clk), + .q2_rx_clock_fifo_wr_clk(q2_rx_clock_fifo_wr_clk), + .q3_rx_clock_fifo_wr_clk(q3_rx_clock_fifo_wr_clk), + .q4_rx_clock_fifo_wr_clk(q4_rx_clock_fifo_wr_clk), + .q5_rx_clock_fifo_wr_clk(q5_rx_clock_fifo_wr_clk), + .q6_rx_clock_fifo_wr_clk(q6_rx_clock_fifo_wr_clk), + .rx_clock_fifo_rd_clk_ins_sm(rx_clock_fifo_rd_clk_ins_sm), + .rx_clock_fifo_rd_clk(rx_clock_fifo_rd_clk), + .rx_clock_asn_pma_hclk(rx_clock_asn_pma_hclk), + .rx_clock_hrdrst_rx_osc_clk(rx_clock_hrdrst_rx_osc_clk), + .rx_clock_async_rx_osc_clk(rx_clock_async_rx_osc_clk), + .rx_clock_async_tx_osc_clk(rx_clock_async_tx_osc_clk), + // Inputs + .dft_adpt_aibiobsr_fastclkn(dft_adpt_aibiobsr_fastclkn), + .adapter_scan_mode_n(adapter_scan_mode_n), + .adapter_scan_shift_n(adapter_scan_shift_n), + .adapter_scan_shift_clk(adapter_scan_shift_clk), + .adapter_scan_user_clk0(adapter_scan_user_clk0), // 125MHz + .adapter_scan_user_clk1(adapter_scan_user_clk1), // 250MHz + .adapter_scan_user_clk2(adapter_scan_user_clk2), // 500MHz + .adapter_scan_user_clk3(adapter_scan_user_clk3), // 1GHz + .adapter_clk_sel_n(adapter_clk_sel_n), + .adapter_occ_enable(adapter_occ_enable), + .aib_fabric_rx_transfer_clk(aib_fabric_rx_transfer_clk), + .aib_fabric_tx_transfer_clk(aib_fabric_tx_transfer_clk), + .aib_fabric_pld_pcs_rx_clk_out(aib_fabric_pld_pcs_rx_clk_out), + .aib_fabric_pld_pma_clkdiv_rx_user(aib_fabric_pld_pma_clkdiv_rx_user), + .aib_fabric_pld_pma_internal_clk1(aib_fabric_pld_pma_internal_clk1), + .aib_fabric_pld_pma_internal_clk2(aib_fabric_pld_pma_internal_clk2), + .aib_fabric_pld_pma_hclk(aib_fabric_pld_pma_hclk), + .aib_fabric_rx_sr_clk_in(aib_fabric_rx_sr_clk_in), + .aib_fabric_tx_sr_clk_in(aib_fabric_tx_sr_clk_in), + .pld_pma_coreclkin_rowclk(pld_pma_coreclkin_rowclk), + //.pld_pma_coreclkin_dcm(pld_pma_coreclkin_dcm), + .pld_rx_clk1_rowclk (pld_rx_clk1_rowclk), + .pld_rx_clk1_dcm (pld_rx_clk1_dcm), + .pld_rx_clk2_rowclk (pld_rx_clk2_rowclk), + //.pld_rx_clk2_dcm (pld_rx_clk2_dcm), + .pld_sclk1_rowclk (pld_sclk1_rowclk), + .pld_sclk2_rowclk (pld_sclk2_rowclk), + .nfrzdrv_in (nfrzdrv_in), + .pr_channel_freeze_n(pr_channel_freeze_n), + .pld_clk_dft_sel(pld_clk_dft_sel), + .tx_clock_fifo_wr_clk(tx_clock_fifo_wr_clk), + .tx_clock_fifo_rd_clk(tx_clock_fifo_rd_clk), + //.r_rx_coreclkin_sel (r_rx_coreclkin_sel), + .r_rx_aib_clk1_sel (r_rx_aib_clk1_sel[1:0]), + .r_rx_aib_clk2_sel (r_rx_aib_clk2_sel[1:0]), + .r_rx_fifo_wr_clk_sel (r_rx_fifo_wr_clk_sel), + .r_rx_fifo_rd_clk_sel (r_rx_fifo_rd_clk_sel[1:0]), + .r_rx_pld_clk1_sel (r_rx_pld_clk1_sel), + //.r_rx_pld_clk2_sel (r_rx_pld_clk2_sel), + .r_rx_sclk_sel (r_rx_sclk_sel), + .r_rx_internal_clk1_sel1(r_rx_internal_clk1_sel1), + .r_rx_internal_clk1_sel2(r_rx_internal_clk1_sel2), + .r_rx_txfiford_post_ct_sel(r_rx_txfiford_post_ct_sel), + .r_rx_txfifowr_post_ct_sel(r_rx_txfifowr_post_ct_sel), + .r_rx_internal_clk2_sel1(r_rx_internal_clk2_sel1), + .r_rx_internal_clk2_sel2(r_rx_internal_clk2_sel2), + .r_rx_rxfifowr_post_ct_sel(r_rx_rxfifowr_post_ct_sel), + .r_rx_rxfiford_post_ct_sel(r_rx_rxfiford_post_ct_sel), + .r_rx_fifo_wr_clk_scg_en(r_rx_fifo_wr_clk_scg_en), + .r_rx_fifo_rd_clk_scg_en(r_rx_fifo_rd_clk_scg_en), + .r_rx_pma_hclk_scg_en (r_rx_pma_hclk_scg_en), + .r_rx_hrdrst_rx_osc_clk_scg_en(r_rx_hrdrst_rx_osc_clk_scg_en), + .r_rx_osc_clk_scg_en(r_rx_osc_clk_scg_en), + .r_rx_fifo_wr_clk_del_sm_scg_en(r_rx_fifo_wr_clk_del_sm_scg_en), + .r_rx_fifo_rd_clk_ins_sm_scg_en(r_rx_fifo_rd_clk_ins_sm_scg_en), + .r_rx_fifo_power_mode(r_rx_fifo_power_mode[2:0]), + .r_rx_pld_clk1_delay_en(r_rx_pld_clk1_delay_en), + .r_rx_pld_clk1_delay_sel(r_rx_pld_clk1_delay_sel[3:0]), + .r_rx_pld_clk1_inv_en(r_rx_pld_clk1_inv_en), + .rx_reset_pld_pma_hclk_rst_n(rx_reset_pld_pma_hclk_rst_n)); + +hdpldadapt_rxrst_ctl hdpldadapt_rxrst_ctl(/*AUTOINST*/ + // Outputs + .aib_fabric_pcs_rx_pld_rst_n(aib_fabric_pcs_rx_pld_rst_n), + .aib_fabric_adapter_rx_pld_rst_n(aib_fabric_adapter_rx_pld_rst_n), + .aib_fabric_pld_pma_rxpma_rstb(aib_fabric_pld_pma_rxpma_rstb), + .aib_fabric_rx_dll_lock_req(aib_fabric_rx_dll_lock_req), + .bond_rx_hrdrst_ds_out_fabric_rx_dll_lock(bond_rx_hrdrst_ds_out_fabric_rx_dll_lock), + .bond_rx_hrdrst_us_out_fabric_rx_dll_lock(bond_rx_hrdrst_us_out_fabric_rx_dll_lock), + .bond_rx_hrdrst_ds_out_fabric_rx_dll_lock_req(bond_rx_hrdrst_ds_out_fabric_rx_dll_lock_req), + .bond_rx_hrdrst_us_out_fabric_rx_dll_lock_req(bond_rx_hrdrst_us_out_fabric_rx_dll_lock_req), + .pld_hssi_rx_transfer_en(pld_hssi_rx_transfer_en), + .pld_aib_fabric_rx_dll_lock(pld_aib_fabric_rx_dll_lock), + .pld_hssi_asn_dll_lock_en(pld_hssi_asn_dll_lock_en), + .rx_hrdrst_rx_fifo_srst(rx_hrdrst_rx_fifo_srst), + .rx_hrdrst_fabric_rx_dll_lock(rx_hrdrst_fabric_rx_dll_lock), + .rx_hrdrst_fabric_rx_transfer_en(rx_hrdrst_fabric_rx_transfer_en), + .rx_hrdrst_asn_data_transfer_en(rx_hrdrst_asn_data_transfer_en), + .rx_hrdrst_testbus(rx_hrdrst_testbus), + .rx_reset_fifo_wr_rst_n(rx_reset_fifo_wr_rst_n), + .rx_reset_fifo_rd_rst_n(rx_reset_fifo_rd_rst_n), + .rx_reset_fifo_sclk_rst_n(rx_reset_fifo_sclk_rst_n), + .rx_reset_pld_pma_hclk_rst_n(rx_reset_pld_pma_hclk_rst_n), + .rx_reset_asn_pma_hclk_rst_n(rx_reset_asn_pma_hclk_rst_n), + .rx_reset_async_rx_osc_clk_rst_n(rx_reset_async_rx_osc_clk_rst_n), + .rx_reset_async_tx_osc_clk_rst_n(rx_reset_async_tx_osc_clk_rst_n), + // Inputs + .adapter_scan_rst_n(adapter_scan_rst_n), + .adapter_scan_mode_n(adapter_scan_mode_n), + .csr_rdy_dly_in (csr_rdy_dly_in), + .nfrzdrv_in (nfrzdrv_in), + .pr_channel_freeze_n(pr_channel_freeze_n), + .usermode_in (usermode_in), + .pld_pcs_rx_pld_rst_n (pld_pcs_rx_pld_rst_n), + .pld_adapter_rx_pld_rst_n(pld_adapter_rx_pld_rst_n), + .pld_pma_rxpma_rstb (pld_pma_rxpma_rstb), + .pld_aib_fabric_rx_dll_lock_req(pld_aib_fabric_rx_dll_lock_req), + .pld_fabric_rx_fifo_srst(pld_fabric_rx_fifo_srst), + .aib_fabric_rx_dll_lock(aib_fabric_rx_dll_lock), + .bond_rx_hrdrst_ds_in_fabric_rx_dll_lock(bond_rx_hrdrst_ds_in_fabric_rx_dll_lock), + .bond_rx_hrdrst_us_in_fabric_rx_dll_lock(bond_rx_hrdrst_us_in_fabric_rx_dll_lock), + .bond_rx_hrdrst_ds_in_fabric_rx_dll_lock_req(bond_rx_hrdrst_ds_in_fabric_rx_dll_lock_req), + .bond_rx_hrdrst_us_in_fabric_rx_dll_lock_req(bond_rx_hrdrst_us_in_fabric_rx_dll_lock_req), + .avmm_hrdrst_fabric_osc_transfer_en(avmm_hrdrst_fabric_osc_transfer_en), + .sr_hssi_rx_dcd_cal_done(sr_hssi_rx_dcd_cal_done), + .sr_hssi_rx_transfer_en(sr_hssi_rx_transfer_en), + .tx_hrdrst_fabric_tx_transfer_en(tx_hrdrst_fabric_tx_transfer_en), + .rx_fabric_align_done(rx_fabric_align_done_raw), + .rx_asn_rate_change_in_progress(rx_asn_rate_change_in_progress), + .rx_asn_dll_lock_en(rx_asn_dll_lock_en), + .rx_asn_fifo_hold(rx_asn_fifo_hold), + .rx_fifo_ready(rx_fifo_ready), + .r_rx_free_run_div_clk(r_rx_free_run_div_clk), + .r_rx_hrdrst_rst_sm_dis(r_rx_hrdrst_rst_sm_dis), + .r_rx_hrdrst_dll_lock_bypass(r_rx_hrdrst_dll_lock_bypass), + .r_rx_hrdrst_align_bypass(r_rx_hrdrst_align_bypass), + .r_rx_hrdrst_user_ctl_en(r_rx_hrdrst_user_ctl_en), + .r_rx_master_sel(r_rx_compin_sel[1:0]), + .r_rx_dist_master_sel(r_rx_ds_master), + .r_rx_ds_last_chnl(r_rx_ds_last_chnl), + .r_rx_us_last_chnl(r_rx_us_last_chnl), + .r_rx_bonding_dft_in_en(r_rx_bonding_dft_in_en), + .r_rx_bonding_dft_in_value(r_rx_bonding_dft_in_value), + .rx_clock_reset_hrdrst_rx_osc_clk(rx_clock_reset_hrdrst_rx_osc_clk), + .rx_clock_reset_fifo_wr_clk(rx_clock_reset_fifo_wr_clk), + .rx_clock_reset_fifo_rd_clk(rx_clock_reset_fifo_rd_clk), + .rx_clock_fifo_sclk(rx_clock_fifo_sclk), + .rx_clock_reset_asn_pma_hclk(rx_clock_reset_asn_pma_hclk), + .rx_clock_reset_async_rx_osc_clk(rx_clock_reset_async_rx_osc_clk), + .rx_clock_reset_async_tx_osc_clk(rx_clock_reset_async_tx_osc_clk), + .rx_clock_pld_pma_hclk(rx_clock_pld_pma_hclk), + .rx_clock_hrdrst_rx_osc_clk(rx_clock_hrdrst_rx_osc_clk)); + + +// Status Register + cfg_dprio_shadow_status_regs + #( + .DATA_WIDTH (8), + .CLK_FREQ_MHZ (1000), // Clock freq in MHz + .TOGGLE_TYPE (3), + .VID (1) + ) + cfg_dprio_shadow_status_regs0 + ( + .rst_n (rx_reset_fifo_rd_rst_n), // reset + .clk (rx_clock_fifo_rd_clk), // clock + .stat_data_in ({3'b000,wa_error_cnt, wa_error}), // status data input + .write_en (rx_chnl_dprio_status_write_en), // write data enable from DPRIO + .write_en_ack (rx_chnl_dprio_status_write_en_ack), // write data enable acknowlege to DPRIO + .stat_data_out (rx_chnl_dprio_status) // status data output + ); + +// Testbus +// Testbus +hdpldadapt_rx_chnl_testbus hdpldadapt_rx_chnl_testbus ( + .r_rx_datapath_tb_sel (r_rx_datapath_tb_sel), + .rx_fifo_testbus1 (rx_fifo_testbus1), + .rx_fifo_testbus2 (rx_fifo_testbus2), + .rx_cp_bond_testbus (rx_cp_bond_testbus), + .rx_hrdrst_testbus (rx_hrdrst_testbus), + .rx_asn_testbus (rx_asn_testbus), + .word_align_testbus (word_align_testbus), + .deletion_sm_testbus (deletion_sm_testbus), + .insertion_sm_testbus (insertion_sm_testbus), + .tx_chnl_testbus (tx_chnl_testbus), + .avmm_testbus (avmm_testbus), + .sr_testbus (sr_testbus_int), + .sr_test_data (sr_test_data), + .sr_parity_error_flag (sr_parity_error_flag), + .rx_chnl_testbus (rx_chnl_testbus) // Go to async block for frz logic + ); + +endmodule + + diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_chnl_testbus.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_chnl_testbus.v new file mode 100644 index 0000000..f01ff35 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_chnl_testbus.v @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// (C) 2009 Altera Corporation. All rights reserved. +// +//------------------------------------------------------------------------ +// File: +// Revision: +// Date: +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ + +module hdpldadapt_rx_chnl_testbus + ( + input wire [3:0] r_rx_datapath_tb_sel, // testbus sel + input wire [19:0] rx_fifo_testbus1, // RX FIFO + input wire [19:0] rx_fifo_testbus2, // RX FIFO + input wire [19:0] rx_cp_bond_testbus, + input wire [19:0] rx_asn_testbus, + input wire [19:0] deletion_sm_testbus, + input wire [19:0] insertion_sm_testbus, + input wire [19:0] word_align_testbus, + input wire [19:0] rx_hrdrst_testbus, + input wire [19:0] sr_testbus, + input wire [19:0] avmm_testbus, + input wire [19:0] tx_chnl_testbus, + input wire [19:0] sr_test_data, + input wire [19:0] sr_parity_error_flag, + + output reg [19:0] rx_chnl_testbus + ); + + always @* begin + case (r_rx_datapath_tb_sel) + 4'b0000: rx_chnl_testbus = rx_fifo_testbus1; + 4'b0001: rx_chnl_testbus = rx_fifo_testbus2; + 4'b0010: rx_chnl_testbus = rx_cp_bond_testbus; + 4'b0011: rx_chnl_testbus = deletion_sm_testbus; + 4'b0100: rx_chnl_testbus = insertion_sm_testbus; + 4'b0101: rx_chnl_testbus = rx_asn_testbus; + 4'b0110: rx_chnl_testbus = word_align_testbus; + 4'b1011: rx_chnl_testbus = rx_hrdrst_testbus; + 4'b1010: rx_chnl_testbus = sr_testbus; + 4'b1001: rx_chnl_testbus = avmm_testbus; + 4'b1000: rx_chnl_testbus = tx_chnl_testbus; + 4'b1100: rx_chnl_testbus = sr_test_data; + 4'b1101: rx_chnl_testbus = sr_parity_error_flag; + default: rx_chnl_testbus = {20{1'b0}}; + endcase // case(r_rx_testbus_sel) + end // always @ * + +endmodule // hdpldadapt_rx_chnl_testbus diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath.v new file mode 100644 index 0000000..120894f --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath.v @@ -0,0 +1,694 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// (C) 2009 Altera Corporation. All rights reserved. +// +//------------------------------------------------------------------------ +// File: $RCSfile: hdpldadapt_rx_datapath.v.rca $ +// Revision: $Revision: #53 $ +// Date: $Date: 2015/09/09 $ +//------------------------------------------------------------------------ +// Description: Integration using emacs verilog then manual edit +// +//------------------------------------------------------------------------ +module hdpldadapt_rx_datapath ( + +/*AUTOINPUT*/ + +// new inputs for ECO8 + input wire [1:0] r_rx_wren_fastbond, + input wire [1:0] r_rx_rden_fastbond, + +// Beginning of automatic input wires (from unused autoinst input wires) +input wire [39:0] aib_fabric_rx_data_in, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v, ..., Couldn't Merge +//input wire avmm_hrdrst_data_transfer_en,// To hdpldadapt_rx_datapath_asn of hdpldadapt_rx_datapath_asn.v +input wire pld_fabric_rx_asn_data_transfer_en, +input wire rx_hrdrst_asn_data_transfer_en, +input wire rx_hrdrst_rx_fifo_srst, +//input wire comp_rden_en, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//input wire comp_wren_en, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//input wire ds_in_rden, // To hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +//input wire ds_in_wren, // To hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +//input wire master_in_rden, // To hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +//input wire master_in_wren, // To hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +input wire r_rx_bonding_dft_in_en, // To hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +input wire r_rx_bonding_dft_in_value, // To hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +input wire [7:0] r_rx_comp_cnt, // To hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +input wire [1:0] r_rx_compin_sel, // To hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +input wire r_rx_double_read, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v, ... +input wire r_rx_ds_bypass_pipeln, // To hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +input wire r_rx_ds_master, // To hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +input wire [5:0] r_rx_fifo_empty, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//input wire r_rx_empty_type, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +input wire [2:0] r_rx_fifo_mode, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +input wire [5:0] r_rx_fifo_full, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//input wire r_rx_full_type, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +input wire r_rx_indv, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +input wire [5:0] r_rx_fifo_pempty, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//input wire r_rx_pempty_type, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +input wire [5:0] r_rx_fifo_pfull, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//input wire r_rx_pfull_type, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +input wire [2:0] r_rx_phcomp_rd_delay, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +input wire r_rx_asn_en, +input wire r_rx_asn_bypass_pma_pcie_sw_done, +input wire [7:0] r_rx_asn_wait_for_fifo_flush_cnt, +input wire [7:0] r_rx_asn_wait_for_dll_reset_cnt, +input wire [7:0] r_rx_asn_wait_for_pma_pcie_sw_done_cnt, +input wire r_rx_hrdrst_user_ctl_en, +//input wire [1:0] r_rx_master_sel, +//input wire r_rx_dist_master_sel, +input wire r_rx_ds_last_chnl, +input wire r_rx_us_last_chnl, +//input wire r_rx_bonding_dft_in_en, +//input wire r_rx_bonding_dft_in_value, +/* +input wire [7:0] r_rx_chnl_datapath_asn_1,// To hdpldadapt_rx_datapath_asn of hdpldadapt_rx_datapath_asn.v +input wire [7:0] r_rx_chnl_datapath_asn_2,// To hdpldadapt_rx_datapath_asn of hdpldadapt_rx_datapath_asn.v +input wire [7:0] r_rx_chnl_datapath_asn_3,// To hdpldadapt_rx_datapath_asn of hdpldadapt_rx_datapath_asn.v +input wire [7:0] r_rx_chnl_datapath_asn_4,// To hdpldadapt_rx_datapath_asn of hdpldadapt_rx_datapath_asn.v +*/ +input wire r_rx_stop_read, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +input wire r_rx_usertest_sel, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +input wire r_rx_stop_write, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +input wire r_rx_truebac2bac, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v, ... +input wire r_rx_us_bypass_pipeln, // To hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +input wire r_rx_us_master, // To hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +input wire r_rx_gb_dv_en, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +input wire r_rx_wa_en, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v, ... +//input wire rd_clk, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v, ... +//input wire rd_en, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//input wire rd_rst_n, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v, ... +//input wire rd_srst_n, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v, ... +input wire rx_clock_asn_pma_hclk, // To hdpldadapt_rx_datapath_asn of hdpldadapt_rx_datapath_asn.v +input wire rx_reset_asn_pma_hclk_rst_n, // To hdpldadapt_rx_datapath_asn of hdpldadapt_rx_datapath_asn.v +input wire rx_fsr_mask_tx_pll, // To hdpldadapt_rx_datapath_asn of hdpldadapt_rx_datapath_asn.v +input wire [1:0] rx_pld_rate, // To hdpldadapt_rx_datapath_asn of hdpldadapt_rx_datapath_asn.v +//input wire rx_rdfifo_clk, // To hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +//input wire rx_rdfifo_clk_rst_n, // To hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +input wire [1:0] rx_ssr_pcie_sw_done, // To hdpldadapt_rx_datapath_asn of hdpldadapt_rx_datapath_asn.v +//input wire rx_wrfifo_clk, // To hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +//input wire rx_wrfifo_clk_rst_n, // To hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +//input wire s_clk, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//input wire s_rst_n, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//input wire us_in_rden, // To hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +//input wire us_in_wren, // To hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +//input wire wr_clk, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v, ... +//input wire wr_empty_stretch, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//input wire wr_full_stretch, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//input wire wr_pempty_stretch, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//input wire wr_pfull_stretch, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//input wire wr_rst_n, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v, ... +//input wire wr_srst_n, // To hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v, ... +// End of automatics + +input wire rx_clock_fifo_rd_clk, +input wire rx_clock_fifo_wr_clk, +input wire q1_rx_clock_fifo_wr_clk, +input wire q2_rx_clock_fifo_wr_clk, +input wire q3_rx_clock_fifo_wr_clk, +input wire q4_rx_clock_fifo_wr_clk, +input wire q5_rx_clock_fifo_wr_clk, +input wire q6_rx_clock_fifo_wr_clk, +input wire rx_reset_fifo_wr_rst_n, +input wire rx_reset_fifo_sclk_rst_n, +input wire rx_reset_fifo_rd_rst_n, +input wire rx_clock_fifo_sclk, +input wire rx_clock_fifo_rd_clk_ins_sm, +input wire rx_clock_fifo_wr_clk_del_sm, + + +input wire bond_rx_asn_ds_in_fifo_hold, +//input wire bond_rx_asn_ds_in_gen3_sel, +input wire bond_rx_asn_us_in_fifo_hold, +//input wire bond_rx_asn_us_in_gen3_sel, + +input wire bond_rx_fifo_ds_in_rden, +input wire bond_rx_fifo_ds_in_wren, + +input wire bond_rx_fifo_us_in_rden, +input wire bond_rx_fifo_us_in_wren, + +input wire pld_rx_fabric_fifo_rd_en, +input wire pld_rx_fabric_fifo_align_clr, // To be connected to RX FIFO + +input wire r_rx_write_ctrl, +input wire [2:0] r_rx_fifo_power_mode, +input wire [2:0] r_rx_stretch_num_stages, +//input wire [2:0] r_rx_datapath_tb_sel, +input wire r_rx_wr_adj_en, +input wire r_rx_rd_adj_en, +input wire r_rx_pipe_en, + +input wire nfrzdrv_in, +input wire pr_channel_freeze_n, +input wire aib_fabric_pld_rx_hssi_fifo_latency_pulse, +input wire pld_rx_fifo_latency_adj_en, + + +/*AUTOoutput wire wire*/ +// Beginning of automatic output wire wires (from unused autoinst output wire wires) +//output wire comp_out_dv_en, // From hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +//output wire comp_out_rden_en, // From hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +//output wire comp_out_wren_en, // From hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +//output wire ds_out_rden, // From hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +//output wire ds_out_wren, // From hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +//output wire fifo_empty, // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//output wire fifo_full, // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//output wire fifo_insert, // From hdpldadapt_rx_datapath_ of hdpldadapt_rx_datapath_insert_sm.v +//output wire fifo_pempty, // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//output wire fifo_pfull, // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//output wire latency_pulse, // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//output wire phcomp_rden, // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//output wire phcomp_wren, // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +output wire [79:0] pld_rx_fabric_data_out, // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//output wire rd_full, // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//output wire rd_pfull, // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +output wire pld_fabric_asn_dll_lock_en, +output wire rx_fabric_align_done_raw, +output wire rx_asn_rate_change_in_progress, +output wire rx_asn_dll_lock_en,// From hdpldadapt_rx_datapath_asn of hdpldadapt_rx_datapath_asn.v +output wire rx_asn_fifo_hold, // From hdpldadapt_rx_datapath_asn of hdpldadapt_rx_datapath_asn.v +//output wire rx_asn_fifo_srst, // From hdpldadapt_rx_datapath_asn of hdpldadapt_rx_datapath_asn.v +//output wire rx_asn_gen3_sel, // From hdpldadapt_rx_datapath_asn of hdpldadapt_rx_datapath_asn.v +//output wire [1:0] rx_asn_rate, // From hdpldadapt_rx_datapath_asn of hdpldadapt_rx_datapath_asn.v +//output wire [19:0] rx_cp_bond_testbus, // From hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +//output wire [19:0] testbus1, // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//output wire [19:0] testbus2, // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//output wire us_out_rden, // From hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +//output wire us_out_wren, // From hdpldadapt_rx_datapath_cp_bond of hdpldadapt_rx_datapath_cp_bond.v +//output wire wr_full_comb, // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +//output wire wr_pfull_comb // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +// End of automatics +output wire pld_rx_fabric_fifo_full, +output wire pld_rx_fabric_fifo_empty, +output wire pld_rx_fabric_fifo_pfull, +output wire pld_rx_fabric_fifo_pempty, +output wire pld_rx_fabric_fifo_latency_pulse, +output wire pld_rx_fabric_fifo_insert, +output wire pld_rx_fabric_fifo_del, +output wire pld_rx_fabric_align_done, +output wire wa_error, // To status reg +output wire [3:0] wa_error_cnt, // Go to status reg + + +output wire pld_rx_hssi_fifo_latency_pulse, + +output wire bond_rx_asn_ds_out_fifo_hold, +output wire bond_rx_asn_us_out_fifo_hold, + +output wire bond_rx_fifo_ds_out_rden, +output wire bond_rx_fifo_ds_out_wren, + +output wire bond_rx_fifo_us_out_rden, +output wire bond_rx_fifo_us_out_wren, + +output wire rx_fifo_ready, +output wire pld_rx_fifo_ready, +output wire rd_align_clr_reg, + +output wire [19:0] rx_fifo_testbus1, // RX FIFO +output wire [19:0] rx_fifo_testbus2, // RX FIFO +output wire [19:0] rx_cp_bond_testbus, +output wire [19:0] rx_asn_testbus, +output wire [19:0] deletion_sm_testbus, +output wire [19:0] insertion_sm_testbus, +output wire [19:0] word_align_testbus + +); + + +localparam DWIDTH = 40; +localparam CNTWIDTH = 8; +localparam AWIDTH = 6; +localparam PCSCWIDTH = 10; +localparam PCSDWIDTH = 64; + +/*AUTOWIRE*/ +// Beginning of automatic wires (for undeclared instantiated-module outputs) +wire baser_data_valid; // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +wire [73:0] baser_fifo_data; // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +wire [73:0] baser_fifo_data2; // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +wire [PCSCWIDTH-1:0] insert_sm_control_out; // From hdpldadapt_rx_datapath_ of hdpldadapt_rx_datapath_insert_sm.v +wire [PCSDWIDTH-1:0] insert_sm_data_out; // From hdpldadapt_rx_datapath_ of hdpldadapt_rx_datapath_insert_sm.v +wire insert_sm_rd_en; // From hdpldadapt_rx_datapath_ of hdpldadapt_rx_datapath_insert_sm.v +wire insert_sm_rd_en_lt; // From hdpldadapt_rx_datapath_ of hdpldadapt_rx_datapath_insert_sm.v +wire rd_empty; // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +wire rd_pempty; // From hdpldadapt_rx_datapath_fifo of hdpldadapt_rx_datapath_fifo.v +wire wa_lock; // From hdpldadapt_rx_datapath_word_align of hdpldadapt_rx_datapath_word_align.v +// End of automatics + +wire asn_fifo_srst; +//wire asn_gen3_sel; +wire rx_asn_phystatus; + +wire comp_out_rden_en; +wire comp_out_wren_en; + +wire comp_rden_en; +wire comp_wren_en; + +//wire [PCSCWIDTH-1:0] control_in; +//wire [PCSDWIDTH-1:0] data_in; +//wire data_valid_in; + +wire double_read; +wire double_read_int; + +wire phcomp_rden; +wire phcomp_wren; + +wire master_in_rden; +wire master_in_wren; + +wire ds_in_rden; +wire ds_in_wren; +wire us_in_rden; +wire us_in_wren; + +wire ds_out_rden; +wire ds_out_wren; +wire us_out_rden; +wire us_out_wren; + +wire rd_clk; +wire rd_rst_n; +wire rd_srst_n = 1'b1; // Tie sync reset to 1 for now +wire rx_rdfifo_clk; +wire rx_rdfifo_clk_rst_n; +wire rx_wrfifo_clk; +wire rx_wrfifo_clk_rst_n; +wire s_clk; +wire s_rst_n; +wire wr_clk; +wire q1_wr_clk; +wire q2_wr_clk; +wire q3_wr_clk; +wire q4_wr_clk; +wire q5_wr_clk; +wire q6_wr_clk; +wire wr_srst_n = 1'b1; // Tie sync reset to 1 for now +wire wr_rst_n; + + +wire rd_en; +//wire [1:0] rx_pld_rate = 2'b00; // Tie off for now. To be connected to mapping + +wire wr_empty_stretch = 1'b0; // Tie off: since r_empty_type =0 +//wire wr_full_stretch = 1'b0; +wire wr_pempty_stretch = 1'b0; // Tie off: since r_pempty_type =0 +//wire wr_pfull_stretch = 1'b0; + +wire fifo_empty; +wire fifo_full; +wire fifo_insert; +wire fifo_pempty; +wire fifo_pfull; +wire align_done; +wire latency_pulse; + +//wire [19:0] rx_cp_bond_testbus; +//wire [19:0] rx_fifo_testbus1; +//wire [19:0] rx_fifo_testbus2; + +wire r_empty_type = 1'b0; +wire r_pempty_type = 1'b0; +wire r_full_type = 1'b1; +wire r_pfull_type = 1'b1; + +wire r_bonding_dft_in_en = r_rx_bonding_dft_in_en; +wire r_bonding_dft_in_value = r_rx_bonding_dft_in_value; +wire [8-1:0] r_comp_cnt = r_rx_comp_cnt; +wire [1:0] r_compin_sel = r_rx_compin_sel; +wire r_double_read = r_rx_double_read; +wire r_ds_bypass_pipeln = r_rx_ds_bypass_pipeln; +wire r_ds_master = r_rx_ds_master; +wire [6-1:0] r_empty = r_rx_fifo_empty; +wire [2:0] r_fifo_mode = r_rx_fifo_mode; +wire [6-1:0] r_full = r_rx_fifo_full; +wire r_indv = r_rx_indv; +wire [6-1:0] r_pempty = r_rx_fifo_pempty; +wire [6-1:0] r_pfull = r_rx_fifo_pfull; +wire [2:0] r_phcomp_rd_delay = r_rx_phcomp_rd_delay; +wire r_stop_read = r_rx_stop_read; +wire r_stop_write = r_rx_stop_write; +wire r_truebac2bac = r_rx_truebac2bac; +wire r_us_bypass_pipeln = r_rx_us_bypass_pipeln; +wire r_us_master = r_rx_us_master; +wire r_gb_dv_en = r_rx_gb_dv_en; +wire r_wa_en = r_rx_wa_en; + +wire [39:0] del_sm_data_out; +wire wr_full_raw; +wire wr_pfull_raw; + +wire rx_fifo_del_raw; +wire rx_fifo_del; + +wire nfrz_output_2one; + +wire [79:0] pld_rx_fabric_data_out_int; +wire pld_rx_fabric_fifo_empty_int; +wire pld_rx_fabric_fifo_full_int; +wire pld_rx_fabric_fifo_insert_int; +wire pld_rx_fabric_fifo_pempty_int; +wire pld_rx_fabric_fifo_pfull_int; +wire pld_rx_fabric_fifo_latency_pulse_int; +wire pld_rx_fabric_align_done_int; +reg pld_rx_hssi_fifo_latency_pulse_int; +wire pld_rx_fabric_fifo_del_int; + +wire rd_align_clr = pld_rx_fabric_fifo_align_clr; + +wire block_lock; +wire block_lock_lt; +wire fifo_srst_n_wr_clk; +wire fifo_srst_n_rd_clk; +wire del_sm_wr_en; +wire compin_sel_wren; +wire compin_sel_rden; +wire wa_srst_n_wr_clk; + +assign asn_fifo_srst = rx_hrdrst_rx_fifo_srst; +//assign asn_gen3_sel = rx_asn_gen3_sel; +assign asn_fifo_hold = rx_asn_fifo_hold; + +assign comp_rden_en = comp_out_rden_en; +assign comp_wren_en = comp_out_wren_en; + +assign double_read = double_read_int; + +assign master_in_rden = phcomp_rden; +assign master_in_wren = phcomp_wren; + + +// ECO8 +assign ds_in_rden = (!r_rx_ds_last_chnl && r_rx_rden_fastbond[0]) ? bond_rx_fifo_ds_in_rden : (!r_rx_ds_last_chnl && !r_rx_rden_fastbond[0]) ? bond_rx_fifo_ds_in_rden : 1'b0; +assign ds_in_wren = (!r_rx_ds_last_chnl && r_rx_wren_fastbond[0]) ? bond_rx_fifo_ds_in_wren : (!r_rx_ds_last_chnl && !r_rx_wren_fastbond[0]) ? bond_rx_fifo_ds_in_wren : 1'b0; + +assign us_in_rden = (!r_rx_us_last_chnl && r_rx_rden_fastbond[1]) ? bond_rx_fifo_us_in_rden : (!r_rx_us_last_chnl && !r_rx_rden_fastbond[1]) ? bond_rx_fifo_us_in_rden : 1'b0; +assign us_in_wren = (!r_rx_us_last_chnl && r_rx_wren_fastbond[1]) ? bond_rx_fifo_us_in_wren : (!r_rx_us_last_chnl && !r_rx_wren_fastbond[1]) ? bond_rx_fifo_us_in_wren : 1'b0; + +/* ECO8 +assign ds_in_rden = r_rx_ds_last_chnl ? 1'b0 : bond_rx_fifo_ds_in_rden; +assign ds_in_wren = r_rx_ds_last_chnl ? 1'b0 : bond_rx_fifo_ds_in_wren; + +assign us_in_rden = r_rx_us_last_chnl ? 1'b0 : bond_rx_fifo_us_in_rden; +assign us_in_wren = r_rx_us_last_chnl ? 1'b0 : bond_rx_fifo_us_in_wren; +*/ + +assign bond_rx_fifo_ds_out_rden = ds_out_rden; +assign bond_rx_fifo_ds_out_wren = ds_out_wren; + +assign bond_rx_fifo_us_out_rden = us_out_rden; +assign bond_rx_fifo_us_out_wren = us_out_wren; + + +assign rd_clk = rx_clock_fifo_rd_clk; +assign rx_rdfifo_clk = rx_clock_fifo_rd_clk; + +assign wr_clk = rx_clock_fifo_wr_clk; +assign q1_wr_clk = q1_rx_clock_fifo_wr_clk; +assign q2_wr_clk = q2_rx_clock_fifo_wr_clk; +assign q3_wr_clk = q3_rx_clock_fifo_wr_clk; +assign q4_wr_clk = q4_rx_clock_fifo_wr_clk; +assign q5_wr_clk = q5_rx_clock_fifo_wr_clk; +assign q6_wr_clk = q6_rx_clock_fifo_wr_clk; +assign rx_wrfifo_clk = rx_clock_fifo_wr_clk; + +assign s_clk = rx_clock_fifo_sclk; + +assign rd_rst_n = rx_reset_fifo_rd_rst_n; +assign wr_rst_n = rx_reset_fifo_wr_rst_n; +assign rx_rdfifo_clk_rst_n = rx_reset_fifo_rd_rst_n; +assign rx_wrfifo_clk_rst_n = rx_reset_fifo_wr_rst_n; + +assign s_rst_n = rx_reset_fifo_sclk_rst_n; + +assign rd_en = pld_rx_fabric_fifo_rd_en; + +assign pld_rx_fabric_fifo_empty_int = fifo_empty; +assign pld_rx_fabric_fifo_full_int = fifo_full; +assign pld_rx_fabric_fifo_insert_int = fifo_insert; +assign pld_rx_fabric_fifo_pempty_int = fifo_pempty; +assign pld_rx_fabric_fifo_pfull_int = fifo_pfull; +assign pld_rx_fabric_fifo_latency_pulse_int = latency_pulse; +assign rx_fabric_align_done_raw = align_done; +assign pld_rx_fabric_align_done_int = align_done; +assign pld_rx_fabric_fifo_del_int = rx_fifo_del; + + +assign rx_asn_phystatus = pld_rx_fabric_data_out_int[32]; + + +// BaseR deletion SM +hdpldadapt_rx_datapath_del_sm hdpldadapt_rx_datapath_del_sm ( +.wr_rst_n (wr_rst_n), +.wr_clk (rx_clock_fifo_wr_clk_del_sm), +.r_write_ctrl (r_rx_write_ctrl), +.aib_fabric_rx_data_in (aib_fabric_rx_data_in), +.wr_pfull (wr_pfull_raw), +.wr_full (wr_full_raw), +.wa_lock (wa_lock), +.base_r_clkcomp_mode (base_r_clkcomp_mode), +.data_out (del_sm_data_out), +.fifo_del (rx_fifo_del_raw), +.block_lock (block_lock), +.block_lock_lt (block_lock_lt), +.del_sm_wr_en (del_sm_wr_en), +.deletion_sm_testbus (deletion_sm_testbus) + ); + + +hdpldadapt_rx_datapath_fifo hdpldadapt_rx_datapath_fifo(/*AUTOINST*/ + // Outputs + .phcomp_wren (phcomp_wren), + .phcomp_rden (phcomp_rden), + .baser_fifo_data(baser_fifo_data[73:0]), + .baser_fifo_data2(baser_fifo_data2[73:0]), + .baser_data_valid(baser_data_valid), + .pld_rx_fabric_data_out(pld_rx_fabric_data_out_int[79:0]), + .rd_pfull (rd_pfull), + .rd_empty (rd_empty), + .rd_pempty (rd_pempty), + .rd_full (rd_full), + .wr_full_comb (wr_full_comb), + .wr_pfull_comb (wr_pfull_comb), + .wr_full (wr_full_raw), + .wr_pfull (wr_pfull_raw), + .fifo_empty (fifo_empty), + .fifo_pempty (fifo_pempty), + .fifo_pfull (fifo_pfull), + .fifo_full (fifo_full), + .latency_pulse (latency_pulse), + .testbus1 (rx_fifo_testbus1[19:0]), + .testbus2 (rx_fifo_testbus2[19:0]), + .double_read_int (double_read_int), + .fifo_srst_n_wr_clk(fifo_srst_n_wr_clk), + .fifo_srst_n_rd_clk(fifo_srst_n_rd_clk), + .wa_srst_n_wr_clk (wa_srst_n_wr_clk), + .align_done (align_done), + .base_r_clkcomp_mode (base_r_clkcomp_mode), + .wa_error (wa_error), + .wa_error_cnt (wa_error_cnt[3:0]), + + // Inputs + .wr_rst_n (wr_rst_n), + .rd_rst_n (rd_rst_n), +// .wr_srst_n (wr_srst_n), +// .rd_srst_n (rd_srst_n), + .wr_clk (wr_clk), + .q1_wr_clk (q1_wr_clk), + .q2_wr_clk (q2_wr_clk), + .q3_wr_clk (q3_wr_clk), + .q4_wr_clk (q4_wr_clk), + .q5_wr_clk (q5_wr_clk), + .q6_wr_clk (q6_wr_clk), + .rd_clk (rd_clk), + .s_clk (s_clk), + .s_rst_n (s_rst_n), + .r_fifo_mode (r_fifo_mode[2:0]), + .r_pempty (r_pempty), + .r_pfull (r_pfull), + .r_empty (r_empty), + .r_full (r_full), + .r_indv (r_indv), + .r_phcomp_rd_delay(r_phcomp_rd_delay[2:0]), + .r_pempty_type (r_pempty_type), + .r_pfull_type (r_pfull_type), + .r_empty_type (r_empty_type), + .r_full_type (r_full_type), + .r_stop_read (r_stop_read), + .r_stop_write (r_stop_write), + .r_double_read (r_double_read), + .r_gb_dv_en (r_gb_dv_en), + .r_truebac2bac (r_truebac2bac), + .r_wa_en (r_wa_en), + .r_fifo_power_mode (r_rx_fifo_power_mode), + .r_wr_adj_en (r_rx_wr_adj_en), + .r_rd_adj_en (r_rx_rd_adj_en), + .r_pipe_en (r_rx_pipe_en), + .r_write_ctrl (r_rx_write_ctrl), + .fifo_latency_adj (pld_rx_fifo_latency_adj_en), + .aib_fabric_rx_data_in(del_sm_data_out), + .rd_en (rd_en), + .rd_align_clr (rd_align_clr), + .rd_align_clr_reg (rd_align_clr_reg), + .comp_wren_en (comp_wren_en), + .comp_rden_en (comp_rden_en), + .compin_sel_wren (compin_sel_wren), + .compin_sel_rden (compin_sel_rden), + .wr_pfull_stretch(wr_pfull_stretch), + .wr_empty_stretch(wr_empty_stretch), + .wr_pempty_stretch(wr_pempty_stretch), + .wr_full_stretch(wr_full_stretch), + .wa_lock (wa_lock), + .block_lock (block_lock), + .block_lock_lt (block_lock_lt), + .del_sm_wr_en (del_sm_wr_en), + .asn_fifo_hold (asn_fifo_hold), + .asn_fifo_srst (asn_fifo_srst), + .asn_gen3_sel (1'b0), + .fifo_ready (rx_fifo_ready), + .insert_sm_control_out(insert_sm_control_out[9:0]), + .insert_sm_data_out(insert_sm_data_out[63:0]), + .insert_sm_rd_en(insert_sm_rd_en), + .insert_sm_rd_en_lt(insert_sm_rd_en_lt)); +hdpldadapt_rx_datapath_word_align hdpldadapt_rx_datapath_word_align(/*AUTOINST*/ + // Outputs + .wa_lock (wa_lock), + .word_align_testbus (word_align_testbus), + // Inputs + .wr_clk (wr_clk), + .wr_rst_n (wr_rst_n), + .wr_srst_n (wa_srst_n_wr_clk), + .r_wa_en (r_wa_en), + .aib_fabric_rx_data_in(aib_fabric_rx_data_in)); +hdpldadapt_rx_datapath_cp_bond hdpldadapt_rx_datapath_cp_bond(/*AUTOINST*/ + // Outputs + .us_out_wren (us_out_wren), + .ds_out_wren (ds_out_wren), + .us_out_rden (us_out_rden), + .ds_out_rden (ds_out_rden), +// .comp_out_dv_en (comp_out_dv_en), + .comp_out_wren_en (comp_out_wren_en), + .comp_out_rden_en (comp_out_rden_en), + .compin_sel_wren (compin_sel_wren), + .compin_sel_rden (compin_sel_rden), + .rx_cp_bond_testbus(rx_cp_bond_testbus[19:0]), + // Inputs + .rx_wrfifo_clk (rx_wrfifo_clk), + .rx_rdfifo_clk (rx_rdfifo_clk), + .rx_rdfifo_clk_rst_n(rx_rdfifo_clk_rst_n), + .rx_wrfifo_clk_rst_n(rx_wrfifo_clk_rst_n), + .wr_srst_n (fifo_srst_n_wr_clk), + .rd_srst_n (fifo_srst_n_rd_clk), + .r_us_master (r_us_master), + .r_ds_master (r_ds_master), + .r_us_bypass_pipeln(r_us_bypass_pipeln), + .r_ds_bypass_pipeln(r_ds_bypass_pipeln), + .r_compin_sel (r_compin_sel[1:0]), + .r_comp_cnt (r_comp_cnt), + .r_bonding_dft_in_en(r_bonding_dft_in_en), + .r_bonding_dft_in_value(r_bonding_dft_in_value), + .r_double_read (double_read), + .master_in_wren (master_in_wren), + .us_in_wren (us_in_wren), + .ds_in_wren (ds_in_wren), + .master_in_rden (master_in_rden), + .us_in_rden (us_in_rden), + .ds_in_rden (ds_in_rden)); +hdpldadapt_rx_datapath_insert_sm hdpldadapt_rx_datapath_insert_sm(/*AUTOINST*/ + // Outputs + .insert_sm_control_out (insert_sm_control_out), + .insert_sm_data_out (insert_sm_data_out), + .fifo_insert (fifo_insert), + .insert_sm_rd_en (insert_sm_rd_en), + .insert_sm_rd_en_lt (insert_sm_rd_en_lt), + .insertion_sm_testbus (insertion_sm_testbus), + // Inputs + .rd_rst_n (rd_rst_n), + .rd_srst_n (rd_srst_n), + .rd_clk (rx_clock_fifo_rd_clk_ins_sm), + .baser_fifo_data (baser_fifo_data[73:0]), + .baser_fifo_data2 (baser_fifo_data2[73:0]), + .rd_pempty (rd_pempty), + .rd_empty (rd_empty), + .baser_data_valid (baser_data_valid), + .r_truebac2bac (r_truebac2bac)); +hdpldadapt_rx_datapath_asn hdpldadapt_rx_datapath_asn(/*AUTOINST*/ + // Outputs + .pld_fabric_asn_dll_lock_en(pld_fabric_asn_dll_lock_en), + .rx_asn_rate_change_in_progress(rx_asn_rate_change_in_progress), + .rx_asn_dll_lock_en(rx_asn_dll_lock_en), + .rx_asn_fifo_hold (rx_asn_fifo_hold), + .bond_rx_asn_ds_out_fifo_hold(bond_rx_asn_ds_out_fifo_hold), + .bond_rx_asn_us_out_fifo_hold(bond_rx_asn_us_out_fifo_hold), + .rx_asn_testbus (rx_asn_testbus), + // Inputs + .rx_clock_asn_pma_hclk(rx_clock_asn_pma_hclk), + .rx_clock_fifo_rd_clk(rx_clock_fifo_rd_clk), + .rx_reset_asn_pma_hclk_rst_n(rx_reset_asn_pma_hclk_rst_n), + .rx_reset_fifo_rd_rst_n(rx_reset_fifo_rd_rst_n), + .rx_pld_rate (rx_pld_rate[1:0]), + .rx_fsr_mask_tx_pll(rx_fsr_mask_tx_pll), + .rx_ssr_pcie_sw_done(rx_ssr_pcie_sw_done[1:0]), + .rx_hrdrst_asn_data_transfer_en(rx_hrdrst_asn_data_transfer_en), + .rx_asn_phystatus(rx_asn_phystatus), + .nfrzdrv_in(nfrzdrv_in), + .pr_channel_freeze_n(pr_channel_freeze_n), + .pld_fabric_rx_asn_data_transfer_en(pld_fabric_rx_asn_data_transfer_en), + .bond_rx_asn_ds_in_fifo_hold(bond_rx_asn_ds_in_fifo_hold), + .bond_rx_asn_us_in_fifo_hold(bond_rx_asn_us_in_fifo_hold), + .r_rx_asn_en(r_rx_asn_en), + .r_rx_asn_bypass_pma_pcie_sw_done(r_rx_asn_bypass_pma_pcie_sw_done), + .r_rx_asn_wait_for_fifo_flush_cnt(r_rx_asn_wait_for_fifo_flush_cnt), + .r_rx_asn_wait_for_dll_reset_cnt(r_rx_asn_wait_for_dll_reset_cnt), + .r_rx_asn_wait_for_pma_pcie_sw_done_cnt(r_rx_asn_wait_for_pma_pcie_sw_done_cnt), + .r_rx_master_sel(r_rx_compin_sel), + .r_rx_dist_master_sel(r_rx_ds_master), + .r_rx_bonding_dft_in_en(r_rx_bonding_dft_in_en), + .r_rx_bonding_dft_in_value(r_rx_bonding_dft_in_value), + .r_rx_hrdrst_user_ctl_en(r_rx_hrdrst_user_ctl_en)); + +hdpldadapt_rx_datapath_pulse_stretch hdpldadapt_rx_datapath_pulse_stretch ( + .clk (wr_clk), + .rst_n (wr_rst_n), + .wr_pfull_raw (wr_pfull_raw), + .wr_full_raw (wr_full_raw), + .rx_fifo_del_raw (rx_fifo_del_raw), + .r_stretch_num_stages (r_rx_stretch_num_stages), + .wr_pfull_stretch (wr_pfull_stretch), + .wr_full_stretch (wr_full_stretch), + .rx_fifo_del (rx_fifo_del)); + + +// Pipeline hssi_latency_pulse +always @(negedge rx_reset_fifo_sclk_rst_n or posedge rx_clock_fifo_sclk) begin + if (rx_reset_fifo_sclk_rst_n == 1'b0) begin + pld_rx_hssi_fifo_latency_pulse_int <= 1'b0; + end + else begin + pld_rx_hssi_fifo_latency_pulse_int <= aib_fabric_pld_rx_hssi_fifo_latency_pulse; + end +end + +// Freeze outputs to PLD +assign nfrz_output_2one = nfrzdrv_in & pr_channel_freeze_n; + +assign pld_rx_fabric_data_out = nfrz_output_2one ? pld_rx_fabric_data_out_int : {80{1'b1}}; +assign pld_rx_fabric_fifo_empty = nfrz_output_2one ? pld_rx_fabric_fifo_empty_int : 1'b1; +assign pld_rx_fabric_fifo_full = nfrz_output_2one ? pld_rx_fabric_fifo_full_int : 1'b1; +assign pld_rx_fabric_fifo_insert = nfrz_output_2one ? pld_rx_fabric_fifo_insert_int : 1'b1; +assign pld_rx_fabric_fifo_pempty = nfrz_output_2one ? pld_rx_fabric_fifo_pempty_int : 1'b1; +assign pld_rx_fabric_fifo_pfull = nfrz_output_2one ? pld_rx_fabric_fifo_pfull_int : 1'b1; +assign pld_rx_fabric_fifo_latency_pulse = nfrz_output_2one ? pld_rx_fabric_fifo_latency_pulse_int : 1'b1; +assign pld_rx_fabric_align_done = nfrz_output_2one ? pld_rx_fabric_align_done_int : 1'b1; +assign pld_rx_hssi_fifo_latency_pulse = nfrz_output_2one ? (r_rx_usertest_sel ? pld_rx_hssi_fifo_latency_pulse_int : aib_fabric_pld_rx_hssi_fifo_latency_pulse ) : 1'b1; +assign pld_rx_fabric_fifo_del = nfrz_output_2one ? pld_rx_fabric_fifo_del_int : 1'b1; +assign pld_rx_fifo_ready = nfrz_output_2one ? rx_fifo_ready : 1'b1; + + + + + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_asn.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_asn.v new file mode 100644 index 0000000..f278fa4 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_asn.v @@ -0,0 +1,838 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_rx_datapath_asn +( + input wire rx_clock_asn_pma_hclk, + input wire rx_clock_fifo_rd_clk, + input wire rx_reset_asn_pma_hclk_rst_n, + input wire rx_reset_fifo_rd_rst_n, + input wire [1:0] rx_pld_rate, + input wire rx_fsr_mask_tx_pll, //pld_pmaif_mask_tx_pll + input wire [1:0] rx_ssr_pcie_sw_done, //pld_pma_pcie_sw_done + input wire rx_hrdrst_asn_data_transfer_en, + input wire rx_asn_phystatus, + input wire nfrzdrv_in, + input wire pr_channel_freeze_n, + input wire pld_fabric_rx_asn_data_transfer_en, + input wire bond_rx_asn_ds_in_fifo_hold, + //input wire bond_rx_asn_ds_in_fifo_srst, + //input wire bond_rx_asn_ds_in_dll_lock_en, + //input wire bond_rx_asn_ds_in_gen3_sel, + input wire bond_rx_asn_us_in_fifo_hold, + //input wire bond_rx_asn_us_in_fifo_srst, + //input wire bond_rx_asn_us_in_dll_lock_en, + //input wire bond_rx_asn_us_in_gen3_sel, + input wire r_rx_asn_en, + //input wire r_rx_asn_bypass_wait_clock_idle, + input wire r_rx_asn_bypass_pma_pcie_sw_done, + //input wire r_rx_asn_bypass_data_transfer_en, + input wire [7:0] r_rx_asn_wait_for_fifo_flush_cnt, + input wire [7:0] r_rx_asn_wait_for_dll_reset_cnt, + input wire [7:0] r_rx_asn_wait_for_pma_pcie_sw_done_cnt, + //input wire [7:0] r_rx_asn_wait_for_data_transfer_ready_cnt, + //input wire [6:0] r_rx_asn_wait_for_fifo_ready_cnt, + input wire [1:0] r_rx_master_sel, + input wire r_rx_dist_master_sel, + input wire r_rx_bonding_dft_in_en, + input wire r_rx_bonding_dft_in_value, + input wire r_rx_hrdrst_user_ctl_en, + output wire pld_fabric_asn_dll_lock_en, + output wire bond_rx_asn_ds_out_fifo_hold, + //output wire bond_rx_asn_ds_out_fifo_srst, + //output wire bond_rx_asn_ds_out_dll_lock_en, + //output wire bond_rx_asn_ds_out_gen3_sel, + output wire bond_rx_asn_us_out_fifo_hold, + //output wire bond_rx_asn_us_out_fifo_srst, + //output wire bond_rx_asn_us_out_dll_lock_en, + //output wire bond_rx_asn_us_out_gen3_sel, + output reg rx_asn_rate_change_in_progress, + //output wire [1:0] rx_asn_rate, + output wire rx_asn_fifo_hold, // Bonded + //output wire rx_asn_fifo_srst, // Bonded + output reg rx_asn_dll_lock_en, // Bonded + //output wire rx_asn_gen3_sel, // Bonded + output wire [19:0] rx_asn_testbus +); + +//******************************************************************** +// Define Parameters +//******************************************************************** + localparam WAIT_RATE_CHANGE = 4'b0000; + localparam HOLD_FIFO_DATA = 4'b0001; + localparam RESET_DLL = 4'b0010; + localparam WAIT_DLL_RESET = 4'b0011; + localparam WAIT_SWITCH_REQUEST = 4'b0100; + localparam WAIT_SWITCH_DONE = 4'b0101; + localparam ENABLE_DLL_LOCK = 4'b0110; + localparam WAIT_DLL_LOCK_DONE = 4'b0111; + //localparam DEASSERT_FIFO_RESET = 4'b1000; + //localparam WAIT_FIFO_READY = 4'b1001; + localparam SPEED_CHANGE_DONE = 4'b1000; + +//******************************************************************** +// Define variables +//******************************************************************** + + wire frz_2one_by_nfrzdrv_or_pr_channel_freeze_n; + + reg [3:0] asn_sm_cs; + reg [3:0] asn_sm_ns; + + wire [1:0] rx_pld_rate_sync; + reg [1:0] rx_pld_rate_sync_reg1; + reg [1:0] rx_pld_rate_sync_reg2; + wire rx_asn_allow_rate_update; + reg [1:0] rx_asn_rate_update; + wire rx_asn_rate_change_pulse; + /* + //reg rx_asn_rate_change_g1_g2; + //reg rx_asn_rate_change_g2_g1; + reg rx_asn_rate_change_g1_g3; + reg rx_asn_rate_change_g3_g1; + reg rx_asn_rate_change_g2_g3; + reg rx_asn_rate_change_g3_g2; + wire rx_asn_from_to_g3; + */ + + /* + wire [1:0] rx_asn_rate_int_sync; + reg [1:0] rx_asn_rate_int_sync_reg1; + reg [1:0] rx_asn_rate_int_sync_reg2; + */ + + wire [1:0] rx_ssr_pcie_sw_done_sync; + reg [1:0] rx_ssr_pcie_sw_done_sync_reg; + reg rx_asn_pma_pcie_sw_done_change_mem; + + wire rx_fsr_mask_tx_pll_sync; + wire rx_hrdrst_asn_data_transfer_en_int; + wire rx_hrdrst_asn_data_transfer_en_sync; + + reg rx_asn_phystatus_reg; + reg rx_asn_phystatus_rise_mem; + wire rx_asn_phystatus_rise_mem_sync; + + reg [7:0] rx_asn_counter; + reg rx_asn_counter_done; + + reg rx_asn_fifo_hold_comb; + reg rx_asn_fifo_hold_reg; + //reg rx_asn_fifo_srst_comb; + //reg rx_asn_fifo_srst_reg; + reg rx_asn_dll_lock_en_comb; + //reg rx_asn_dll_lock_en_reg; + reg rx_asn_wait_pma_pcie_sw_done_comb; + reg rx_asn_wait_pma_pcie_sw_done; + reg rx_asn_wait_phystatus_comb; + reg rx_asn_wait_phystatus; + wire rx_asn_wait_phystatus_sync; + //reg rx_asn_send_rate_change; + //reg rx_asn_switch_mux; + //reg rx_asn_gen3_sel_reg; + + reg rx_asn_reset_count; + reg rx_asn_count_wait_for_fifo_flush; + reg rx_asn_count_wait_for_dll_reset; + reg rx_asn_count_wait_for_pma_pcie_sw_done; + //reg rx_asn_count_wait_for_data_transfer_ready; + //reg rx_asn_count_wait_for_fifo_ready; + + wire bond_rx_asn_ds_in_fifo_hold_int; + //wire bond_rx_asn_ds_in_fifo_srst_int; + //wire bond_rx_asn_ds_in_dll_lock_en_int; + //wire bond_rx_asn_ds_in_gen3_sel_int; + wire bond_rx_asn_us_in_fifo_hold_int; + //wire bond_rx_asn_us_in_fifo_srst_int; + //wire bond_rx_asn_us_in_dll_lock_en_int; + //wire bond_rx_asn_us_in_gen3_sel_int; + + wire rx_asn_fifo_hold_chnl_down; + wire rx_asn_fifo_hold_chnl_up; + //wire rx_asn_fifo_srst_chnl_down; + //wire rx_asn_fifo_srst_chnl_up; + //wire rx_asn_dll_lock_en_chnl_down; + //wire rx_asn_dll_lock_en_chnl_up; + //wire rx_asn_gen3_sel_chnl_down; + //wire rx_asn_gen3_sel_chnl_up; + +//******************************************************************** +// Test bus +//******************************************************************** +assign rx_asn_testbus[19:0] = {2'b00,rx_hrdrst_asn_data_transfer_en, rx_asn_phystatus_rise_mem_sync,rx_hrdrst_asn_data_transfer_en_sync,rx_asn_pma_pcie_sw_done_change_mem,rx_ssr_pcie_sw_done_sync[1:0],rx_fsr_mask_tx_pll_sync,rx_asn_dll_lock_en,rx_asn_fifo_hold,rx_asn_fifo_hold_reg,rx_asn_rate_update[1:0],rx_pld_rate[1:0],asn_sm_cs[3:0]}; + +//******************************************************************** +// PLD +//******************************************************************** +assign frz_2one_by_nfrzdrv_or_pr_channel_freeze_n = ~(nfrzdrv_in & pr_channel_freeze_n); +assign pld_fabric_asn_dll_lock_en = frz_2one_by_nfrzdrv_or_pr_channel_freeze_n | rx_asn_dll_lock_en; + +//******************************************************************** +//******************************************************************** +//assign rx_asn_rate_change_in_progress = (asn_sm_cs[3:0] != WAIT_RATE_CHANGE); + +always @(negedge rx_reset_asn_pma_hclk_rst_n or posedge rx_clock_asn_pma_hclk) +begin + if (~rx_reset_asn_pma_hclk_rst_n) + begin + rx_asn_rate_change_in_progress <= 1'b0; + end + else + begin + rx_asn_rate_change_in_progress <= (asn_sm_cs[3:0] != WAIT_RATE_CHANGE); + end +end + +// Rate change detection in hclk domain +cdclib_bitsync2 + #( + .DWIDTH (2), // Sync Data input + .RESET_VAL (0), // Reset value + .CLK_FREQ_MHZ(250), + .TOGGLE_TYPE (2), + .VID (1) + ) cdclib_bitsync2_pld_rate + ( + .clk (rx_clock_asn_pma_hclk), + .rst_n (rx_reset_asn_pma_hclk_rst_n), + .data_in (rx_pld_rate[1:0]), + .data_out (rx_pld_rate_sync[1:0]) + ); + +always @(negedge rx_reset_asn_pma_hclk_rst_n or posedge rx_clock_asn_pma_hclk) +begin + if (~rx_reset_asn_pma_hclk_rst_n) + begin + rx_pld_rate_sync_reg1[1:0] <= {2{1'b0}}; + rx_pld_rate_sync_reg2[1:0] <= {2{1'b0}}; + end + else + begin + rx_pld_rate_sync_reg1[1:0] <= rx_pld_rate_sync[1:0]; + rx_pld_rate_sync_reg2[1:0] <= rx_pld_rate_sync_reg1[1:0]; + end +end + +assign rx_asn_allow_rate_update = (asn_sm_cs[3:0] == WAIT_RATE_CHANGE) && + (rx_pld_rate_sync[1:0] == rx_pld_rate_sync_reg1[1:0]) && + (rx_pld_rate_sync_reg1[1:0] == rx_pld_rate_sync_reg2[1:0]); + +always @(negedge rx_reset_asn_pma_hclk_rst_n or posedge rx_clock_asn_pma_hclk) +begin + if (~rx_reset_asn_pma_hclk_rst_n) + begin + rx_asn_rate_update[1:0] <= {2{1'b0}}; + end + else + begin + if (rx_asn_allow_rate_update) + begin + rx_asn_rate_update[1:0] <= rx_pld_rate_sync_reg2[1:0]; + end + end +end + +assign rx_asn_rate_change_pulse = rx_asn_allow_rate_update && (rx_asn_rate_update[1:0] != rx_pld_rate_sync_reg2[1:0]); + +/* +always @(negedge rx_reset_asn_pma_hclk_rst_n or posedge rx_clock_asn_pma_hclk) +begin + if (~rx_reset_asn_pma_hclk_rst_n) + begin + //rx_asn_rate_change_g1_g2 <= 1'b0; + //rx_asn_rate_change_g2_g1 <= 1'b0; + rx_asn_rate_change_g1_g3 <= 1'b0; + rx_asn_rate_change_g3_g1 <= 1'b0; + rx_asn_rate_change_g2_g3 <= 1'b0; + rx_asn_rate_change_g3_g2 <= 1'b0; + end + else + begin + if (rx_asn_rate_change_pulse) + begin + //rx_asn_rate_change_g1_g2 <= ((rx_asn_rate_update == 2'b00) && (rx_pld_rate_sync_reg2 == 2'b01)); + //rx_asn_rate_change_g2_g1 <= ((rx_asn_rate_update == 2'b01) && (rx_pld_rate_sync_reg2 == 2'b00)); + rx_asn_rate_change_g1_g3 <= ((rx_asn_rate_update == 2'b00) && (rx_pld_rate_sync_reg2 == 2'b10)); + rx_asn_rate_change_g3_g1 <= ((rx_asn_rate_update == 2'b10) && (rx_pld_rate_sync_reg2 == 2'b00)); + rx_asn_rate_change_g2_g3 <= ((rx_asn_rate_update == 2'b01) && (rx_pld_rate_sync_reg2 == 2'b10)); + rx_asn_rate_change_g3_g2 <= ((rx_asn_rate_update == 2'b10) && (rx_pld_rate_sync_reg2 == 2'b01)); + end + end +end + +// Rate change from/to GEN3 +assign rx_asn_from_to_g3 = rx_asn_rate_change_g1_g3 | rx_asn_rate_change_g3_g1 | rx_asn_rate_change_g2_g3 | rx_asn_rate_change_g3_g2; +*/ + +//assign rx_asn_rate[1:0] = rx_asn_rate_update[1:0]; + +/* +// Rate change generation in PIPE clock domain +cdclib_bitsync2 + #( + .DWIDTH (2), // Sync Data input + .RESET_VAL (0) // Reset value + ) cdclib_bitsync2_rx_asn_rate_int_sync + ( + .clk (tx_clock_fifo_wr_clk), + .rst_n (tx_reset_fifo_wr_rst_n), + .data_in (rx_asn_rate_int[1:0]), + .data_out (rx_asn_rate_int_sync[1:0]) + ); + +always @(negedge tx_reset_fifo_wr_rst_n or posedge tx_clock_fifo_wr_clk) +begin + if (~tx_reset_fifo_wr_rst_n) + begin + rx_asn_rate_int_sync_reg1[1:0] <= {2{1'b0}}; + rx_asn_rate_int_sync_reg2[1:0] <= {2{1'b0}}; + end + else + begin + rx_asn_rate_int_sync_reg1[1:0] <= rx_asn_rate_int_sync[1:0]; + rx_asn_rate_int_sync_reg2[1:0] <= rx_asn_rate_int_sync_reg1[1:0]; + end +end + +always @(negedge tx_reset_fifo_wr_rst_n or posedge tx_clock_fifo_wr_clk) +begin + if (~tx_reset_fifo_wr_rst_n) + begin + rx_asn_rate[1:0] <= {2{1'b0}}; + end + else + begin + if ((rx_asn_rate_int_sync[1:0] == rx_asn_rate_int_sync_reg1[1:0]) && (rx_asn_rate_int_sync_reg1[1:0] == rx_asn_rate_int_sync_reg2[1:0])) + begin + rx_asn_rate[1:0] <= rx_asn_rate_int_sync_reg2[1:0]; + end + end +end +*/ + +// PMA pcie_sw_done change detection +cdclib_bitsync2 + #( + .DWIDTH (2), // Sync Data input + .RESET_VAL (0), // Reset value + .CLK_FREQ_MHZ(250), + .TOGGLE_TYPE (2), + .VID (1) + ) cdclib_bitsync2_pma_pcie_sw_done + ( + .clk (rx_clock_asn_pma_hclk), + .rst_n (rx_reset_asn_pma_hclk_rst_n), + .data_in (rx_ssr_pcie_sw_done[1:0]), + .data_out (rx_ssr_pcie_sw_done_sync[1:0]) + ); + + +always @(negedge rx_reset_asn_pma_hclk_rst_n or posedge rx_clock_asn_pma_hclk) +begin + if (~rx_reset_asn_pma_hclk_rst_n) + begin + rx_ssr_pcie_sw_done_sync_reg[1:0] <= 2'b00; + end + else + begin + rx_ssr_pcie_sw_done_sync_reg[1:0] <= rx_ssr_pcie_sw_done_sync[1:0]; + end +end + +// Store the change of PMA pcie_sw_done at any time after RESET_DLL state. +always @(negedge rx_reset_asn_pma_hclk_rst_n or posedge rx_clock_asn_pma_hclk) +begin + if (~rx_reset_asn_pma_hclk_rst_n) + begin + rx_asn_pma_pcie_sw_done_change_mem <= 1'b0; + end + else if (rx_asn_wait_pma_pcie_sw_done == 1'b1) + begin + rx_asn_pma_pcie_sw_done_change_mem <= (rx_ssr_pcie_sw_done_sync_reg[1:0] != rx_ssr_pcie_sw_done_sync[1:0]) || rx_asn_pma_pcie_sw_done_change_mem; + end + else + begin + rx_asn_pma_pcie_sw_done_change_mem <= 1'b0; + end +end + +// PMA IF mask_tx_pll +cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset value + .CLK_FREQ_MHZ(250), + .TOGGLE_TYPE (2), + .VID (1) + ) cdclib_bitsync2_rx_fsr_mask_tx_pll + ( + .clk (rx_clock_asn_pma_hclk), + .rst_n (rx_reset_asn_pma_hclk_rst_n), + .data_in (rx_fsr_mask_tx_pll), + .data_out (rx_fsr_mask_tx_pll_sync) + ); + +assign rx_hrdrst_asn_data_transfer_en_int = r_rx_hrdrst_user_ctl_en ? pld_fabric_rx_asn_data_transfer_en : rx_hrdrst_asn_data_transfer_en; + +cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset value + .CLK_FREQ_MHZ(250), + .TOGGLE_TYPE (2), + .VID (1) + ) cdclib_bitsync2_rx_hrdrst_asn_data_transfer_en + ( + .clk (rx_clock_asn_pma_hclk), + .rst_n (rx_reset_asn_pma_hclk_rst_n), + .data_in (rx_hrdrst_asn_data_transfer_en_int), + .data_out (rx_hrdrst_asn_data_transfer_en_sync) + ); + +// PCS phystatus rising edge detection +cdclib_bitsync4 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (2), + .VID (1) + ) cdclib_bitsync4_rx_asn_wait_phystatus + ( + .clk (rx_clock_fifo_rd_clk), + .rst_n (rx_reset_fifo_rd_rst_n), + .data_in (rx_asn_wait_phystatus), + .data_out (rx_asn_wait_phystatus_sync) + ); + +always @(negedge rx_reset_fifo_rd_rst_n or posedge rx_clock_fifo_rd_clk) +begin + if (~rx_reset_fifo_rd_rst_n) + begin + rx_asn_phystatus_reg <= 1'b1; + end + else + begin + rx_asn_phystatus_reg <= rx_asn_phystatus; + end +end + +// Store the rising edge of PCS phystatus at any time after RESET_DLL state. +always @(negedge rx_reset_fifo_rd_rst_n or posedge rx_clock_fifo_rd_clk) +begin + if (~rx_reset_fifo_rd_rst_n) + begin + rx_asn_phystatus_rise_mem <= 1'b0; + end + else if (rx_asn_wait_phystatus_sync) + begin + rx_asn_phystatus_rise_mem <= (rx_asn_phystatus && ~rx_asn_phystatus_reg) || rx_asn_phystatus_rise_mem; + end + else + begin + rx_asn_phystatus_rise_mem <= 1'b0; + end +end + +cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset value + .CLK_FREQ_MHZ(250), + .TOGGLE_TYPE (2), + .VID (1) + ) cdclib_bitsync2_rx_asn_phystatus_rise_mem + ( + .clk (rx_clock_asn_pma_hclk), + .rst_n (rx_reset_asn_pma_hclk_rst_n), + .data_in (rx_asn_phystatus_rise_mem), + .data_out (rx_asn_phystatus_rise_mem_sync) + ); + +//******************************************************************** +// Multiple counters for ASN SM +//******************************************************************** +always @ (negedge rx_reset_asn_pma_hclk_rst_n or posedge rx_clock_asn_pma_hclk) +begin + if (~rx_reset_asn_pma_hclk_rst_n) + begin + rx_asn_counter[7:0] <= 8'h00; + rx_asn_counter_done <= 1'b0; + end + else if (rx_asn_reset_count) + begin + rx_asn_counter[7:0] <= 8'h00; + rx_asn_counter_done <= 1'b0; + end + else + begin + rx_asn_counter <= rx_asn_counter + 8'h01; + if (~rx_asn_counter_done) + begin + if(rx_asn_count_wait_for_fifo_flush) + begin + rx_asn_counter_done <= (rx_asn_counter[7:0] == r_rx_asn_wait_for_fifo_flush_cnt[7:0]) ? 1'b1 : 1'b0; + end + else if (rx_asn_count_wait_for_dll_reset) + begin + rx_asn_counter_done <= (rx_asn_counter[7:0] == r_rx_asn_wait_for_dll_reset_cnt[7:0]) ? 1'b1 : 1'b0; + end + else if (rx_asn_count_wait_for_pma_pcie_sw_done) + begin + rx_asn_counter_done <= (rx_asn_counter[7:0] == r_rx_asn_wait_for_pma_pcie_sw_done_cnt[7:0]) ? 1'b1 : 1'b0; + end + //else if (rx_asn_count_wait_for_data_transfer_ready) + //begin + // rx_asn_counter_done <= (rx_asn_counter[7:0] == r_rx_asn_wait_for_data_transfer_ready_cnt[7:0]) ? 1'b1 : 1'b0; + //end + //else if (rx_asn_count_wait_for_fifo_ready) + //begin + // rx_asn_counter_done <= (rx_asn_counter[6:0] == r_rx_asn_wait_for_fifo_ready_cnt[6:0]) ? 1'b1 : 1'b0; + //end + end + end +end + +//******************************************************************** +// Output generation +//******************************************************************** + +/* +// rate output +always @(negedge rx_reset_asn_pma_hclk_rst_n or posedge rx_clock_asn_pma_hclk) +begin + if (~rx_reset_asn_pma_hclk_rst_n) + begin + rx_asn_rate[1:0] <= {2{1'b0}}; + end + else if (rx_asn_send_rate_change) + begin + rx_asn_rate[1:0] <= rx_asn_rate_update[1:0]; + end +end +*/ + +/* +// gen3_sel output +always @ (negedge rx_reset_asn_pma_hclk_rst_n or posedge rx_clock_asn_pma_hclk) +begin + if (~rx_reset_asn_pma_hclk_rst_n) + begin + rx_asn_gen3_sel_reg <= 1'b0; + end + else if (rx_asn_switch_mux) + begin + rx_asn_gen3_sel_reg <= (rx_asn_rate_update == 2'b10) ? 1'b1: 1'b0; + end +end +*/ + +// Other outputs +always @ (negedge rx_reset_asn_pma_hclk_rst_n or posedge rx_clock_asn_pma_hclk) +begin + if (~rx_reset_asn_pma_hclk_rst_n) + begin + rx_asn_fifo_hold_reg <= 1'b0; + //rx_asn_fifo_srst_reg <= 1'b0; + rx_asn_dll_lock_en <= 1'b1; + rx_asn_wait_pma_pcie_sw_done <= 1'b0; + rx_asn_wait_phystatus <= 1'b0; + end + else + begin + rx_asn_fifo_hold_reg <= rx_asn_fifo_hold_comb; + //rx_asn_fifo_srst_reg <= rx_asn_fifo_srst_comb; + rx_asn_dll_lock_en <= rx_asn_dll_lock_en_comb; + rx_asn_wait_pma_pcie_sw_done <= rx_asn_wait_pma_pcie_sw_done_comb; + rx_asn_wait_phystatus <= rx_asn_wait_phystatus_comb; + end + end + +//******************************************************************** +// ASN State Machine +//******************************************************************** +always @(negedge rx_reset_asn_pma_hclk_rst_n or posedge rx_clock_asn_pma_hclk) +begin + if (~rx_reset_asn_pma_hclk_rst_n) + begin + asn_sm_cs <= WAIT_RATE_CHANGE; + end + else if (r_rx_asn_en == 1'b0) + begin + asn_sm_cs <= WAIT_RATE_CHANGE; + end + else + begin + asn_sm_cs <= asn_sm_ns; + end +end + + +always @ (*) +begin + asn_sm_ns = asn_sm_cs; + rx_asn_fifo_hold_comb = 1'b0; + //rx_asn_fifo_srst_comb = 1'b0; + rx_asn_dll_lock_en_comb = 1'b1; + rx_asn_wait_pma_pcie_sw_done_comb = 1'b0; + rx_asn_wait_phystatus_comb = 1'b0; + //rx_asn_send_rate_change = 1'b0; + //rx_asn_switch_mux = 1'b0; + rx_asn_reset_count = 1'b1; + rx_asn_count_wait_for_fifo_flush = 1'b0; + rx_asn_count_wait_for_dll_reset = 1'b0; + rx_asn_count_wait_for_pma_pcie_sw_done = 1'b0; + //rx_asn_count_wait_for_data_transfer_ready = 1'b0; + //rx_asn_count_wait_for_fifo_ready = 1'b0; + + case(asn_sm_cs) + WAIT_RATE_CHANGE: + begin + if (rx_asn_rate_change_pulse) + begin + asn_sm_ns = HOLD_FIFO_DATA; + end + end + + HOLD_FIFO_DATA: + begin + rx_asn_fifo_hold_comb = 1'b1; + rx_asn_reset_count = 1'b0; + rx_asn_count_wait_for_fifo_flush = 1'b1; + if(rx_asn_counter_done) + begin + asn_sm_ns = RESET_DLL; + end + end + + RESET_DLL: + begin + rx_asn_fifo_hold_comb = 1'b1; + //rx_asn_fifo_srst_comb = 1'b1; + rx_asn_dll_lock_en_comb = 1'b0; + rx_asn_wait_pma_pcie_sw_done_comb = 1'b1; + rx_asn_wait_phystatus_comb = 1'b1; + //rx_asn_send_rate_change = 1'b1; + asn_sm_ns = WAIT_DLL_RESET; + end + + WAIT_DLL_RESET: + begin + rx_asn_fifo_hold_comb = 1'b1; + //rx_asn_fifo_srst_comb = 1'b1; + rx_asn_dll_lock_en_comb = 1'b0; + rx_asn_wait_pma_pcie_sw_done_comb = 1'b1; + rx_asn_wait_phystatus_comb = 1'b1; + rx_asn_reset_count = 1'b0; + rx_asn_count_wait_for_dll_reset = 1'b1; + if (rx_asn_counter_done) + begin + asn_sm_ns = WAIT_SWITCH_REQUEST; + end + end + + WAIT_SWITCH_REQUEST: + begin + rx_asn_fifo_hold_comb = 1'b1; + //rx_asn_fifo_srst_comb = 1'b1; + rx_asn_dll_lock_en_comb = 1'b0; + rx_asn_wait_pma_pcie_sw_done_comb = 1'b1; + rx_asn_wait_phystatus_comb = 1'b1; + //rx_asn_switch_mux = 1'b1; + if (rx_fsr_mask_tx_pll_sync) + begin + asn_sm_ns = WAIT_SWITCH_DONE; + end + end + + WAIT_SWITCH_DONE: + begin + rx_asn_fifo_hold_comb = 1'b1; + //rx_asn_fifo_srst_comb = 1'b1; + rx_asn_dll_lock_en_comb = 1'b0; + rx_asn_wait_pma_pcie_sw_done_comb = 1'b1; + rx_asn_wait_phystatus_comb = 1'b1; + rx_asn_reset_count = 1'b0; + rx_asn_count_wait_for_pma_pcie_sw_done = 1'b1; + if (rx_asn_counter_done) + begin + if (rx_asn_pma_pcie_sw_done_change_mem || r_rx_asn_bypass_pma_pcie_sw_done) + begin + asn_sm_ns = ENABLE_DLL_LOCK; + end + end + end + + ENABLE_DLL_LOCK: + begin + rx_asn_fifo_hold_comb = 1'b1; + //rx_asn_fifo_srst_comb = 1'b1; + rx_asn_wait_phystatus_comb = 1'b1; + asn_sm_ns = WAIT_DLL_LOCK_DONE; + end + + WAIT_DLL_LOCK_DONE: + begin + rx_asn_fifo_hold_comb = 1'b1; + //rx_asn_fifo_srst_comb = 1'b1; + rx_asn_wait_phystatus_comb = 1'b1; + //rx_asn_reset_count = 1'b0; + //rx_asn_count_wait_for_data_transfer_ready = 1'b1; + //if (rx_asn_counter_done && rx_hrdrst_asn_data_transfer_en_sync && ~rx_fsr_mask_tx_pll_sync) + if (rx_hrdrst_asn_data_transfer_en_sync && ~rx_fsr_mask_tx_pll_sync) + begin + asn_sm_ns = SPEED_CHANGE_DONE; + end + end + + SPEED_CHANGE_DONE: + begin + rx_asn_wait_phystatus_comb = 1'b1; + if (rx_asn_phystatus_rise_mem_sync) + begin + asn_sm_ns = WAIT_RATE_CHANGE; + end + end + + default: + begin + asn_sm_ns = WAIT_RATE_CHANGE; + rx_asn_fifo_hold_comb = 1'b0; + //rx_asn_fifo_srst_comb = 1'b0; + rx_asn_dll_lock_en_comb = 1'b1; + rx_asn_wait_pma_pcie_sw_done_comb = 1'b0; + rx_asn_wait_phystatus_comb = 1'b0; + //rx_asn_send_rate_change = 1'b0; + //rx_asn_switch_mux = 1'b0; + rx_asn_reset_count = 1'b1; + rx_asn_count_wait_for_fifo_flush = 1'b0; + rx_asn_count_wait_for_dll_reset = 1'b0; + rx_asn_count_wait_for_pma_pcie_sw_done = 1'b0; + //rx_asn_count_wait_for_data_transfer_ready = 1'b0; + //rx_asn_count_wait_for_fifo_ready = 1'b0; + end + endcase + end + + +// ASN Output with Bonding + assign bond_rx_asn_ds_in_fifo_hold_int = r_rx_bonding_dft_in_en ? r_rx_bonding_dft_in_value : bond_rx_asn_ds_in_fifo_hold; + assign bond_rx_asn_us_in_fifo_hold_int = r_rx_bonding_dft_in_en ? r_rx_bonding_dft_in_value : bond_rx_asn_us_in_fifo_hold; + + //assign bond_rx_asn_ds_in_fifo_srst_int = r_rx_bonding_dft_in_en ? r_rx_bonding_dft_in_value : bond_rx_asn_ds_in_fifo_srst; + //assign bond_rx_asn_us_in_fifo_srst_int = r_rx_bonding_dft_in_en ? r_rx_bonding_dft_in_value : bond_rx_asn_us_in_fifo_srst; + + //assign bond_rx_asn_ds_in_dll_lock_en_int = r_rx_bonding_dft_in_en ? r_rx_bonding_dft_in_value : bond_rx_asn_ds_in_dll_lock_en; + //assign bond_rx_asn_us_in_dll_lock_en_int = r_rx_bonding_dft_in_en ? r_rx_bonding_dft_in_value : bond_rx_asn_us_in_dll_lock_en; + + //assign bond_rx_asn_ds_in_gen3_sel_int = r_rx_bonding_dft_in_en ? r_rx_bonding_dft_in_value : bond_rx_asn_ds_in_gen3_sel; + //assign bond_rx_asn_us_in_gen3_sel_int = r_rx_bonding_dft_in_en ? r_rx_bonding_dft_in_value : bond_rx_asn_us_in_gen3_sel; + +hdpldadapt_cmn_cp_dist_pair + #( + .ASYNC_RESET_VAL(0), + .WIDTH(1) // Control width + ) hdpldadapt_cmn_cp_dist_pair_fifo_hold + ( + .clk(1'b0), // clock + .rst_n(1'b1), // async reset + .srst_n(1'b1), // sync reset + .data_enable(1'b1), // data enable / data valid + .master_in(rx_asn_fifo_hold_reg), // master control signal + .us_in(bond_rx_asn_us_in_fifo_hold_int), // CP distributed signal in up + .ds_in(bond_rx_asn_ds_in_fifo_hold_int), // CP distributed signal in dwn + .r_us_master(r_rx_dist_master_sel), // CRAM to control master or distributed up + .r_ds_master(r_rx_dist_master_sel), // CRAM to control master or distributed dwn + .r_us_bypass_pipeln(1'b1), // CRAM combo or registered up + .r_ds_bypass_pipeln(1'b1), // CRAM combo or registered dwn + .us_out(bond_rx_asn_us_out_fifo_hold), // CP distributed signal out up + .ds_out(bond_rx_asn_ds_out_fifo_hold), // CP distributed signal out dwn + .ds_tap(rx_asn_fifo_hold_chnl_down), // CP output for this channel dwn + .us_tap(rx_asn_fifo_hold_chnl_up) // CP output for this channel up + ); + +/* +hdpldadapt_cmn_cp_dist_pair + #( + .ASYNC_RESET_VAL(0), + .WIDTH(1) // Control width + ) hdpldadapt_cmn_cp_dist_pair_fifo_srst + ( + .clk(1'b0), // clock + .rst_n(1'b1), // async reset + .srst_n(1'b1), // sync reset + .data_enable(1'b1), // data enable / data valid + .master_in(rx_asn_fifo_srst_reg), // master control signal + .us_in(bond_rx_asn_us_in_fifo_srst_int), // CP distributed signal in up + .ds_in(bond_rx_asn_ds_in_fifo_srst_int), // CP distributed signal in dwn + .r_us_master(r_rx_dist_master_sel), // CRAM to control master or distributed up + .r_ds_master(r_rx_dist_master_sel), // CRAM to control master or distributed dwn + .r_us_bypass_pipeln(1'b1), // CRAM combo or registered up + .r_ds_bypass_pipeln(1'b1), // CRAM combo or registered dwn + .us_out(bond_rx_asn_us_out_fifo_srst), // CP distributed signal out up + .ds_out(bond_rx_asn_ds_out_fifo_srst), // CP distributed signal out dwn + .ds_tap(rx_asn_fifo_srst_chnl_down), // CP output for this channel dwn + .us_tap(rx_asn_fifo_srst_chnl_up) // CP output for this channel up + ); +*/ + +/* +hdpldadapt_cmn_cp_dist_pair + #( + .ASYNC_RESET_VAL(0), + .WIDTH(1) // Control width + ) hdpldadapt_cmn_cp_dist_pair_dll_lock_en + ( + .clk(1'b0), // clock + .rst_n(1'b1), // async reset + .srst_n(1'b1), // sync reset + .data_enable(1'b1), // data enable / data valid + .master_in(rx_asn_dll_lock_en_reg), // master control signal + .us_in(bond_rx_asn_us_in_dll_lock_en_int), // CP distributed signal in up + .ds_in(bond_rx_asn_ds_in_dll_lock_en_int), // CP distributed signal in dwn + .r_us_master(r_rx_dist_master_sel), // CRAM to control master or distributed up + .r_ds_master(r_rx_dist_master_sel), // CRAM to control master or distributed dwn + .r_us_bypass_pipeln(1'b1), // CRAM combo or registered up + .r_ds_bypass_pipeln(1'b1), // CRAM combo or registered dwn + .us_out(bond_rx_asn_us_out_dll_lock_en), // CP distributed signal out up + .ds_out(bond_rx_asn_ds_out_dll_lock_en), // CP distributed signal out dwn + .ds_tap(rx_asn_dll_lock_en_chnl_down), // CP output for this channel dwn + .us_tap(rx_asn_dll_lock_en_chnl_up) // CP output for this channel up + ); +*/ + +/* +hdpldadapt_cmn_cp_dist_pair + #( + .ASYNC_RESET_VAL(0), + .WIDTH(1) // Control width + ) hdpldadapt_cmn_cp_dist_pair_gen3_sel + ( + .clk(1'b0), // clock + .rst_n(1'b1), // async reset + .srst_n(1'b1), // sync reset + .data_enable(1'b1), // data enable / data valid + .master_in(rx_asn_gen3_sel_reg), // master control signal + .us_in(bond_rx_asn_us_in_gen3_sel_int), // CP distributed signal in up + .ds_in(bond_rx_asn_ds_in_gen3_sel_int), // CP distributed signal in dwn + .r_us_master(r_rx_dist_master_sel), // CRAM to control master or distributed up + .r_ds_master(r_rx_dist_master_sel), // CRAM to control master or distributed dwn + .r_us_bypass_pipeln(1'b1), // CRAM combo or registered up + .r_ds_bypass_pipeln(1'b1), // CRAM combo or registered dwn + .us_out(bond_rx_asn_us_out_gen3_sel), // CP distributed signal out up + .ds_out(bond_rx_asn_ds_out_gen3_sel), // CP distributed signal out dwn + .ds_tap(rx_asn_gen3_sel_chnl_down), // CP output for this channel dwn + .us_tap(rx_asn_gen3_sel_chnl_up) // CP output for this channel up + ); +*/ + //assign rx_asn_fifo_hold = (~r_rx_master_sel[1]) ? (rx_asn_fifo_hold_reg) : (r_rx_master_sel[0] ? rx_asn_fifo_hold_chnl_up : rx_asn_fifo_hold_chnl_down); + //assign rx_asn_fifo_hold = (~r_rx_master_sel[1]) ? (rx_asn_fifo_hold_reg) : (r_rx_master_sel[0] ? rx_asn_fifo_hold_chnl_down : rx_asn_fifo_hold_chnl_up); + assign rx_asn_fifo_hold = (r_rx_master_sel == 2'b00) ? rx_asn_fifo_hold_reg : + (r_rx_master_sel == 2'b01) ? rx_asn_fifo_hold_chnl_up : + (r_rx_master_sel == 2'b10) ? rx_asn_fifo_hold_chnl_down : + rx_asn_fifo_hold_reg ; + + //assign rx_asn_fifo_srst = (~r_rx_master_sel[1]) ? (rx_asn_fifo_srst_reg) : (r_rx_master_sel[0] ? rx_asn_fifo_srst_chnl_up : rx_asn_fifo_srst_chnl_down); + //assign rx_asn_dll_lock_en = (~r_rx_master_sel[1]) ? (rx_asn_dll_lock_en_reg) : (r_rx_master_sel[0] ? rx_asn_dll_lock_en_chnl_up : rx_asn_dll_lock_en_chnl_down); + //assign rx_asn_gen3_sel = (~r_rx_master_sel[1]) ? (rx_asn_gen3_sel_reg) : (r_rx_master_sel[0] ? rx_asn_gen3_sel_chnl_up : rx_asn_gen3_sel_chnl_down); + +endmodule // hdpldadapt_rx_datapath_asn diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_async_fifo.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_async_fifo.v new file mode 100644 index 0000000..27fe0d6 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_async_fifo.v @@ -0,0 +1,653 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// (C) 2009 Altera Corporation. All rights reserved. +// +//------------------------------------------------------------------------ +// File: $RCSfile: hdpldadapt_rx_chnl_async_fifo.v.rca $ +// Revision: $Revision: #10 $ +// Date: $Date: 2015/05/20 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ + + +module hdpldadapt_rx_datapath_async_fifo + #( + parameter DWIDTH = 'd40, // FIFO Input data width + parameter AWIDTH = 'd6 // FIFO Depth (address width) + ) + ( + input wire wr_rst_n, // Write Domain Active low Reset + input wire wr_srst_n, // Write Domain Active low Reset Synchronous + input wire wr_clk, // Write Domain Clock + input wire q1_wr_clk, // Write Domain Clock + input wire q2_wr_clk, // Write Domain Clock + input wire q3_wr_clk, // Write Domain Clock + input wire q4_wr_clk, // Write Domain Clock + input wire q5_wr_clk, // Write Domain Clock + input wire q6_wr_clk, // Write Domain Clock + input wire wr_en, // Write Data Enable + input wire [DWIDTH-1:0] wr_data, // Write Data In + input wire rd_rst_n, // Read Domain Active low Reset + input wire rd_srst_n, // Read Domain Active low Reset Synchronous + input wire rd_clk, // Read Domain Clock + input wire rd_en, // Read Data Enable + input wire [AWIDTH-1:0] r_pempty, // FIFO partially empty threshold + input wire [AWIDTH-1:0] r_pfull, // FIFO partially full threshold + input wire [AWIDTH-1:0] r_empty, // FIFO empty threshold + input wire [AWIDTH-1:0] r_full, // FIFO full threshold + input wire r_double_read, // FIFO double write mode + input wire [2:0] r_fifo_power_mode, // FIFO double write mode + +// input wire r_pempty_type, // FIFO partially empty flag type +// input wire r_pfull_type, // FIFO partially full flag type +// input wire r_empty_type, // FIFO empty flag type +// input wire r_full_type, // FIFO full flag type + input wire r_stop_read, // Disable/enable reading when FIFO is empty + input wire r_stop_write, // Disable/enable writing when FIFO is full + + output wire [DWIDTH-1:0] rd_data, // Read Data Out + output wire [DWIDTH-1:0] rd_data_next, // Read Data Out Next + output wire [DWIDTH-1:0] rd_data2, // Read Data Out + output wire [DWIDTH-1:0] rd_data2_next, // Read Data Out Next + + output wire [AWIDTH-1:0] rd_numdata, // Number of Data available in Read clock + output wire [AWIDTH-1:0] wr_numdata, // Number of Data available in Write clock + output wire wr_addr_msb, // Write address MSB + output wire rd_addr_msb, // Write address MSB + output wire ps_wr_addr_msb, // Power-saving Write address MSB + output wire ps_rd_addr_msb, // Power-saving Write address MSB + output wire ps_dw_wr_addr_msb, // Power-saving Write address MSB + output wire ps_dw_rd_addr_msb, // Power-saving Write address MSB + + + output reg wr_empty, // FIFO Empty + output reg wr_pempty, // FIFO Partial Empty + output reg wr_full, // FIFO Full + output reg wr_pfull, // FIFO Parial Full + output wire wr_full_comb, // FIFO Full + output wire wr_pfull_comb, // FIFO Parial Full + output reg rd_empty, // FIFO Empty + output reg rd_pempty, // FIFO Partial Empty + output reg rd_full, // FIFO Full + output reg rd_pfull // FIFO Partial Full + ); + + //******************************************************************** + // Define Parameters + //******************************************************************** + + localparam DEPTH = (1<= r_full) ? 1'b1 : 1'b0; + wr_full <= wr_full_comb; + // Generate FIFO Almost Full +// wr_pfull <= (wr_numdata >= r_pfull) ? 1'b1 : 1'b0; + wr_pfull <= wr_pfull_comb; + + end + end + + assign wr_full_comb = (wr_numdata >= r_full) ? 1'b1 : 1'b0; + assign wr_pfull_comb = (wr_numdata >= r_pfull) ? 1'b1 : 1'b0; + + + //******************************************************************** + // READ CLOCK DOMAIN: Generate Fifo Number of Data Present + // using Read Address and Synchronized Write Address + //******************************************************************** + always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + rd_empty <= 1'b1; + rd_pempty <= 1'b1; + rd_full <= 1'b0; + rd_pfull <= 1'b0; + end + else if (rd_srst_n == 1'b0) begin + rd_empty <= 1'b1; + rd_pempty <= 1'b1; + rd_full <= 1'b0; + rd_pfull <= 1'b0; + end + else begin + + // Generate FIFO Empty + rd_empty <= (rd_numdata == r_empty) ? 1'b1 : 1'b0; + // Generate FIFO Almost Empty + rd_pempty <= (rd_numdata <= r_pempty) ? 1'b1 : 1'b0; + // Generate FIFO Full + rd_full <= (rd_numdata >= r_full) ? 1'b1 : 1'b0; + // Generate FIFO Almost Full + rd_pfull <= (rd_numdata >= r_pfull) ? 1'b1 : 1'b0; + + end + end + + + //******************************************************************** + // FIFO Mapping + //******************************************************************** +// assign q1_wr_en = r_fifo_power_mode[1] ? wr_en : |full_wr_ptr_one_hot[PS_DEPTH-1:0]; + assign q1_wr_en = wr_en; +// assign q1_wr_ptr = r_fifo_power_mode[1] ? top_wr_ptr_one_hot : full_wr_ptr_one_hot[PS_DEPTH-1:0]; +// assign q1_rd_ptr = r_fifo_power_mode[1] ? top_rd_ptr_one_hot : full_rd_ptr_one_hot[PS_DEPTH-1:0]; + assign q1_wr_ptr = full_wr_ptr_one_hot[PS_DEPTH-1:0]; + assign q1_rd_ptr = full_rd_ptr_one_hot[PS_DEPTH-1:0]; + assign q1_wr_data = wr_data[PS_DWIDTH-1:0]; + + assign q2_wr_en = q1_wr_en; + assign q2_wr_ptr = q1_wr_ptr; + assign q2_rd_ptr = q1_rd_ptr; + assign q2_wr_data = wr_data[DWIDTH-1:PS_DWIDTH]; + +// assign q3_wr_en = |full_wr_ptr_one_hot[2*PS_DEPTH-1:PS_DEPTH]; + assign q3_wr_en = wr_en; + assign q3_wr_ptr = full_wr_ptr_one_hot[2*PS_DEPTH-1:PS_DEPTH]; + assign q3_rd_ptr = full_rd_ptr_one_hot[2*PS_DEPTH-1:PS_DEPTH]; + assign q3_wr_data = wr_data[PS_DWIDTH-1:0]; + + assign q4_wr_en = q3_wr_en; + assign q4_wr_ptr = q3_wr_ptr; + assign q4_rd_ptr = q3_rd_ptr; + assign q4_wr_data = wr_data[DWIDTH-1:PS_DWIDTH]; + + assign q5_wr_en = wr_en; + assign q5_wr_ptr = full_wr_ptr_one_hot[DEPTH-1:2*PS_DEPTH]; + assign q5_rd_ptr = full_rd_ptr_one_hot[DEPTH-1:2*PS_DEPTH]; + assign q5_wr_data = wr_data[PS_DWIDTH-1:0]; + + assign q6_wr_en = q5_wr_en; + assign q6_wr_ptr = q5_wr_ptr; + assign q6_rd_ptr = q5_rd_ptr; + assign q6_wr_data = wr_data[DWIDTH-1:PS_DWIDTH]; + + +// assign top_wr_clk = q1_wr_clk; +// assign top_rd_clk = q1_rd_clk; + assign top_wr_en = wr_en; + assign top_rd_en = rd_en; + assign top_rd_empty = rd_empty; + assign top_wr_full = wr_full; + + assign full_wr_clk = q1_wr_clk; +// assign full_rd_clk = q1_rd_clk; + assign full_wr_en = wr_en; + assign full_rd_en = rd_en; + assign full_rd_empty = rd_empty; + assign full_wr_full = wr_full; + + +// assign wr_numdata = ~r_fifo_power_mode[1] ? {{AWIDTH-PS_AWIDTH{1'b0}},full_wr_numdata[PS_AWIDTH-1:0]} : full_wr_numdata; +// assign rd_numdata = ~r_fifo_power_mode[1] ? {{AWIDTH-PS_AWIDTH{1'b0}},full_rd_numdata[PS_AWIDTH-1:0]} : full_rd_numdata; + assign wr_numdata = ~r_fifo_power_mode[1] ? {{AWIDTH-PS_AWIDTH{1'b0}},full_wr_numdata[PS_AWIDTH-1:0]} : + ~r_fifo_power_mode[2] ? {{AWIDTH-PS_AWIDTH-1{1'b0}},full_wr_numdata[PS_AWIDTH:0]} : + full_wr_numdata; + + assign rd_numdata = ~r_fifo_power_mode[1] ? {{AWIDTH-PS_AWIDTH{1'b0}},full_rd_numdata[PS_AWIDTH-1:0]} : + ~r_fifo_power_mode[2] ? {{AWIDTH-PS_AWIDTH-1{1'b0}},full_rd_numdata[PS_AWIDTH:0]} : + full_rd_numdata; + + assign wr_addr_msb = full_wr_addr_msb; + assign rd_addr_msb = full_rd_addr_msb; + + assign top_rd_data = {q2_rd_data, q1_rd_data}; +// assign bot_rd_data = {q4_rd_data, q3_rd_data}; + assign top_rd_data2 = {q2_rd_data2, q1_rd_data2}; +// assign bot_rd_data2 = {q4_rd_data2, q3_rd_data2}; + + +assign full_rd_ptr2_bin = full_rd_ptr_bin + 1'b1; +assign full_rd_ptr_bin_next = full_rd_ptr_bin + 'd2; +assign full_rd_ptr2_bin_next = full_rd_ptr_bin_next + 1'b1; +//assign full_rd_ptr_bin_next = full_rd_ptr_bin + 'd1; +//assign full_rd_ptr2_bin_next = full_rd_ptr2_bin + 1'b1; + +// Read data: concatenate data from multiple FIFOs + +integer i, j; + +always @ * begin + for (i='d0; i<= DEPTH-1; i=i+1'b1) begin + if (i<=PS_DEPTH-1) + mem_comb[i] = {q2_rd_data, q1_rd_data}; + else if (i<=2*PS_DEPTH-1) + mem_comb[i] = {q4_rd_data, q3_rd_data}; + else + mem_comb[i] = {q6_rd_data, q5_rd_data}; + end +end + +always @ * begin + for (i='d0; i<= DEPTH-1; i=i+1'b1) begin + if (i<=PS_DEPTH-1) + mem2_comb[i] = {q2_rd_data2, q1_rd_data2}; + else if (i<=2*PS_DEPTH-1) + mem2_comb[i] = {q4_rd_data2, q3_rd_data2}; + else + mem2_comb[i] = {q6_rd_data2, q5_rd_data2}; + end +end + + +always @ * begin + for (i='d0; i<= DEPTH-1; i=i+1'b1) begin + if (i<=PS_DEPTH-1) + mem3_comb[i] = {q2_rd_data_next, q1_rd_data_next}; + else if (i<=2*PS_DEPTH-1) + mem3_comb[i] = {q4_rd_data_next, q3_rd_data_next}; + else + mem3_comb[i] = {q6_rd_data_next, q5_rd_data_next}; + end +end + +always @ * begin + for (i='d0; i<= DEPTH-1; i=i+1'b1) begin + if (i<=PS_DEPTH-1) + mem4_comb[i] = {q2_rd_data2_next, q1_rd_data2_next}; + else if (i<=2*PS_DEPTH-1) + mem4_comb[i] = {q4_rd_data2_next, q3_rd_data2_next}; + else + mem4_comb[i] = {q6_rd_data2_next, q5_rd_data2_next}; + end +end + + +assign full_rd_data = mem_comb[full_rd_ptr_bin]; +assign full_rd_data2 = mem2_comb[full_rd_ptr2_bin]; + +assign mid_rd_data = mem_comb[full_rd_ptr_bin[PS_AWIDTH:0]]; +assign mid_rd_data2 = mem2_comb[full_rd_ptr2_bin[PS_AWIDTH:0]]; + + +assign rd_data = ~r_fifo_power_mode[1] ? top_rd_data : + ~r_fifo_power_mode[2] ? mid_rd_data : + full_rd_data; + +assign rd_data_next = ~r_fifo_power_mode[1] ? top_rd_data2 : + ~r_fifo_power_mode[2] ? mid_rd_data2 : + full_rd_data2; + +//assign full_rd_data_next = mem3_comb[full_rd_ptr_bin_next]; +//assign full_rd_data2_next = mem4_comb[full_rd_ptr2_bin_next]; + +assign full_rd_data_next = mem3_comb[full_rd_ptr_bin_next]; +assign full_rd_data2_next = mem4_comb[full_rd_ptr2_bin_next]; + +assign rd_data2 = full_rd_data_next; +assign rd_data2_next = full_rd_data2_next; + +endmodule // hdpldadapt_rx_chnl_async_fifo diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_cp_bond.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_cp_bond.v new file mode 100644 index 0000000..85a7c79 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_cp_bond.v @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// (C) 2009 Altera Corporation. All rights reserved. +// +//------------------------------------------------------------------------ +// File: $RCSfile: hdpldadapt_rx_datapath_cp_bond.v.rca $ +// Revision: $Revision: #6 $ +// Date: $Date: 2015/06/19 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ + + +module hdpldadapt_rx_datapath_cp_bond + #( + parameter CNTWIDTH = 'd8 + ) + ( + input wire rx_wrfifo_clk, // TX PCS clock clock + input wire rx_rdfifo_clk, // TX RD clock clock + input wire rx_rdfifo_clk_rst_n, // TX PCS rst output + input wire rx_wrfifo_clk_rst_n, // TX RD rst output + input wire wr_srst_n, // Write sync rst_n + input wire rd_srst_n, // Read sync rst_n +// input wire double_read, // FIFO double write option + + input wire r_us_master, // CP up master sel + input wire r_ds_master, // CP dwn master sel + input wire r_us_bypass_pipeln, // CP up comb or seq sel + input wire r_ds_bypass_pipeln, // CP dwn comb or seq sel + input wire [1:0] r_compin_sel, // Comp input sel + input wire [CNTWIDTH-1:0] r_comp_cnt, // Comp timeout value + input wire r_bonding_dft_in_en, // Gate bonding signal during scan + input wire r_bonding_dft_in_value, // Gate bonding signal during scan + input wire r_double_read, // FIFO double write option + + input wire master_in_wren, // PC wren master in + input wire us_in_wren, // PC wren up in + input wire ds_in_wren, // PC wren dwn in + input wire master_in_rden, // PC rden master in + input wire us_in_rden, // PC rden up in + input wire ds_in_rden, // PC rden dwn in + + output wire us_out_wren, // PC wren up out + output wire ds_out_wren, // PC wren dwn out + output wire us_out_rden, // PC rden up out + output wire ds_out_rden, // PC rden dwn out +// output wire comp_out_dv_en, // data valid comp out + output wire comp_out_wren_en, // PC wren comp out + output wire comp_out_rden_en, // PC rden comp out + output wire compin_sel_rden, + output wire compin_sel_wren, + output wire [19:0] rx_cp_bond_testbus // testbus + ); + + + wire ds_tap_wren; + wire us_tap_wren; + wire ds_tap_rden; + wire us_tap_rden; + + wire ds_in_wren_int; + wire us_in_wren_int; + wire ds_in_rden_int; + wire us_in_rden_int; + + wire [CNTWIDTH-1:0] comp_cnt_int; +// wire double_write_int; + + + assign ds_in_wren_int = r_bonding_dft_in_en ? r_bonding_dft_in_value : ds_in_wren; + assign us_in_wren_int = r_bonding_dft_in_en ? r_bonding_dft_in_value : us_in_wren; + assign ds_in_rden_int = r_bonding_dft_in_en ? r_bonding_dft_in_value : ds_in_rden; + assign us_in_rden_int = r_bonding_dft_in_en ? r_bonding_dft_in_value : us_in_rden; + + hdpldadapt_cmn_cp_dist_pair_dw + #( + .ASYNC_RESET_VAL (0), + .WIDTH (1) // Control width + ) + hdpldadapt_cmn_cp_dist_pair_dw_wren + ( + .clk (rx_wrfifo_clk), + .rst_n (rx_wrfifo_clk_rst_n), + .srst_n (wr_srst_n), + .data_enable (1'b1), + .master_in (master_in_wren), + .us_in (us_in_wren_int), + .ds_in (ds_in_wren_int), + .r_us_master (r_us_master), + .r_ds_master (r_ds_master), + .r_us_bypass_pipeln (1'b0), + .r_ds_bypass_pipeln (1'b0), + .r_double_en (r_double_read), + .us_out (us_out_wren), + .ds_out (ds_out_wren), + .ds_tap (ds_tap_wren), + .us_tap (us_tap_wren) + ); + + hdpldadapt_cmn_cp_comp_cntr + #( + .CNTWIDTH (8) + ) + hdpldadapt_cmn_cp_comp_cntr_wren + ( + .clk (rx_wrfifo_clk), + .rst_n (rx_wrfifo_clk_rst_n), + .srst_n (wr_srst_n), + .data_enable (1'b1), + .master_in_en (master_in_wren), + .us_tap_en (us_tap_wren), + .ds_tap_en (ds_tap_wren), + .r_compin_sel (r_compin_sel), + .r_comp_cnt (comp_cnt_int), + .comp_cnt_match (comp_out_wren_en), + .compin_sel (compin_sel_wren) + ); + + hdpldadapt_cmn_cp_dist_pair + #( + .ASYNC_RESET_VAL (0), + .WIDTH (1) // Control width + ) + hdpldadapt_cmn_cp_dist_pair_dw_rden + ( + .clk (rx_rdfifo_clk), + .rst_n (rx_rdfifo_clk_rst_n), + .srst_n (rd_srst_n), + .data_enable (1'b1), + .master_in (master_in_rden), + .us_in (us_in_rden_int), + .ds_in (ds_in_rden_int), + .r_us_master (r_us_master), + .r_ds_master (r_ds_master), + .r_us_bypass_pipeln (1'b0), + .r_ds_bypass_pipeln (1'b0), +// .r_double_en (r_double_read), + .us_out (us_out_rden), + .ds_out (ds_out_rden), + .ds_tap (ds_tap_rden), + .us_tap (us_tap_rden) + ); + + hdpldadapt_cmn_cp_comp_cntr + #( + .CNTWIDTH (8) + ) + hdpldadapt_cmn_cp_comp_cntr_rden + ( + .clk (rx_rdfifo_clk), + .rst_n (rx_rdfifo_clk_rst_n), + .srst_n (rd_srst_n), + .data_enable (1'b1), + .master_in_en (master_in_rden), + .us_tap_en (us_tap_rden), + .ds_tap_en (ds_tap_rden), + .r_compin_sel (r_compin_sel), + .r_comp_cnt (r_comp_cnt), + .comp_cnt_match (comp_out_rden_en), + .compin_sel (compin_sel_rden) + ); + + assign rx_cp_bond_testbus = {8'h00, + master_in_wren, + us_in_wren, + ds_in_wren, + ds_tap_wren, + us_tap_wren, + comp_out_wren_en, + master_in_rden, + us_in_rden, + ds_in_rden, + ds_tap_rden, + us_tap_rden, + comp_out_rden_en + }; + +assign comp_cnt_int = r_double_read ? r_comp_cnt << 1 : r_comp_cnt; + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_del_sm.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_del_sm.v new file mode 100644 index 0000000..1250e9b --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_del_sm.v @@ -0,0 +1,846 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_rx_datapath_del_sm + ( + input wire wr_rst_n, // Write Domain Active low Reset + input wire wr_clk, // Write Domain Clock + + input wire [39:0] aib_fabric_rx_data_in, // Write Data In + +// input wire [PCSCWIDTH-1:0] control_in, // Frame information +// input wire [PCSDWIDTH-1:0] data_in, // Write Data In (Contains CTRL+DATA) +// input wire data_valid_in, // Write Data In Valid +// input wire [77:0] data_in; + + input wire r_write_ctrl, + + input wire wr_pfull, // Write partial full + input wire wr_full, // Write full + + input wire wa_lock, // Word-align lock + input wire base_r_clkcomp_mode, + + output wire [19:0] deletion_sm_testbus, + output wire [39:0] data_out, + output wire block_lock, + output reg block_lock_lt, + output reg del_sm_wr_en, + output reg fifo_del // FIFO deletion + ); + +//******************************************************************** +// Define Parameters +//******************************************************************** +//`include "hd_pcs10g_params.v" + + localparam PCSDWIDTH = 'd64; // PCS data width + localparam PCSCWIDTH = 'd10; // PCS control width + + +// 10G, 40G & 100G Ethernet Parameters + // Spec Definitions + // MII Control Characters - Unencoded + localparam XGMII_IDLE = 8'h07; + localparam XGMII_START = 8'hfb; + localparam XGMII_TERM = 8'hfd; + localparam XGMII_ERROR = 8'hfe; + localparam XGMII_SEQOS = 8'h9c; + localparam XGMII_RES0 = 8'h1c; + localparam XGMII_RES1 = 8'h3c; + localparam XGMII_RES2 = 8'h7c; + localparam XGMII_RES3 = 8'hbc; + localparam XGMII_RES4 = 8'hdc; + localparam XGMII_RES5 = 8'hf7; + localparam XGMII_SIGOS = 8'h5c; + + // Local Fault OS and Error Block - Unencoded + localparam EBLOCK_R = {8{XGMII_ERROR}}; + localparam LBLOCK_R_10G = {8'h1,8'h0,8'h0,XGMII_SEQOS,8'h1,8'h0,8'h0,XGMII_SEQOS}; + +// Shared Parameters + // Control Bits + localparam CTL_DATA = 'd0; + localparam CTL_CTRL = 'd1; + localparam CTL_ERR = 'd8; + localparam CTL_BFL = 'd9; + + +// localparam PCSDWIDTH = 'd64, // PCS data width +// localparam PCSCWIDTH = 'd10 // PCS control width + + localparam WR_IDLE = 3'd0; + localparam WR_ADD_NXT_DAT = 3'd1; + localparam WR_ADD_STOR_DAT = 3'd2; + localparam WR_ADD_NULL_DAT = 3'd3; + localparam WR_ADD_NO_DEL = 3'd4; + + + localparam XGMII_IDLE_WORD = {4{XGMII_IDLE}}; + + localparam FIFO_DATA_DEFAULT = LBLOCK_R_10G; + localparam FIFO_CTRL_DEFAULT = 10'h11; + localparam FIFO_DEFAULT = {FIFO_CTRL_DEFAULT, FIFO_DATA_DEFAULT}; + + localparam FDWIDTH = PCSDWIDTH+PCSCWIDTH; + +//******************************************************************** +// Define variables +//******************************************************************** + + + wire [FDWIDTH-1:0] wr_data_in; + + // Define variables + // Regs + reg [FDWIDTH-1:0] nx1_data_in; + reg [FDWIDTH-1:0] nx0_data_in; + reg [FDWIDTH-1:0] cur_data_in; + reg nx1_data_valid_in; + reg nx0_data_valid_in; + reg cur_data_valid_in; + reg nx1_lsoctet_os; + reg nx1_lsoctet_idle; + reg nx1_lsoctet_term; + reg nx1_msoctet_os; + reg nx1_msoctet_idle; + reg nx1_msoctet_term; + reg nx0_lsoctet_os; + reg nx0_lsoctet_idle; + reg nx0_lsoctet_term; + reg nx0_msoctet_os; + reg nx0_msoctet_idle; + reg nx0_msoctet_term; + reg cur_lsoctet_os; + reg cur_lsoctet_idle; + reg cur_lsoctet_term; + reg cur_msoctet_os; + reg cur_msoctet_idle; + reg cur_msoctet_term; + reg cur_msoctet_del; + reg cur_lsoctet_del; + reg nx0_msoctet_del; + reg nx0_lsoctet_del; +// reg wr_en; + reg [FDWIDTH-3:0] wr_data; + reg [2:0] wr_del_sm; + reg [31:0] store_lsd; + reg [3:0] store_lsc; + + // Wires + wire [31:0] cur_data_in_lsd; + wire [31:0] cur_data_in_msd; + wire [3:0] cur_data_in_lsc; + wire [3:0] cur_data_in_msc; + wire [31:0] nx0_data_in_lsd; + wire [31:0] nx0_data_in_msd; + wire [3:0] nx0_data_in_lsc; + wire [3:0] nx0_data_in_msc; + + wire data_valid_in; + wire [63:0] data_in; + wire [9:0] control_in; +// wire block_lock; + wire block_lock_sync; +// reg block_lock_lt; + wire block_lock_int; + wire wr_srst_n; + reg keep_store; + reg wr_en; + +// Extract data, control, DV bits +//assign control_in = data_in[9:0]; +//assign data_valid_in = data_in[10]; +//assign data_in_int = data_in[77:14]; + + + wire [39:0] aib_in = aib_fabric_rx_data_in; + + reg [39:0] aib_in_reg; + reg [79:0] fifo_in_2x; + reg dv_2x_reg; + wire dv_2x; + + wire [79:0] data_out_del_sm_aib_2x; + reg [39:0] data_out_del_sm_aib; + +always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + aib_in_reg <= 'd0; + end + else begin + aib_in_reg <= aib_in; + end +end + + + always@(posedge wr_clk or negedge wr_rst_n) begin + if (!wr_rst_n) begin + fifo_in_2x <= 'd0; + end + else if (~dv_2x && wa_lock) begin + fifo_in_2x <= {aib_in, aib_in_reg}; + end + end + +//assign fifo_in_2x = {aib_in, aib_in_reg}; + +assign {data_valid_in, control_in, data_in} = aib_2_teng_map(fifo_in_2x); + +always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + dv_2x_reg <= 1'b0; + end + else begin + dv_2x_reg <= dv_2x; + end +end + +assign dv_2x = ~wa_lock ? 1'b0: ~dv_2x_reg; + + + +assign wr_data_in = {control_in, data_in}; + +// always @(negedge wr_rst_n or posedge wr_clk) begin +// if (wr_rst_n == 1'b0) begin +// nx1_data_valid_in <= 'd0; +// nx0_data_valid_in <= 'd0; +// cur_data_valid_in <= 'd0; +// end +// else if (dv_2x) begin +// nx1_data_valid_in <= data_valid_in; +// nx0_data_valid_in <= nx1_data_valid_in; +// cur_data_valid_in <= nx0_data_valid_in; +// end +// end + + always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + nx1_data_valid_in <= 'd0; + nx0_data_valid_in <= 'd0; + cur_data_valid_in <= 'd0; + nx1_data_in <= 'd0; + nx0_data_in <= 'd0; + cur_data_in <= 'd0; + end + else if (dv_2x_reg) begin + nx1_data_valid_in <= data_valid_in; + nx0_data_valid_in <= nx1_data_valid_in; + cur_data_valid_in <= nx0_data_valid_in; + nx1_data_in <= (data_valid_in) ? wr_data_in : nx1_data_in; + nx0_data_in <= (nx1_data_valid_in) ? nx1_data_in : nx0_data_in; + cur_data_in <= (nx0_data_valid_in) ? nx0_data_in : cur_data_in; + + end + end + + always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin +// nx1_data_in <= 'd0; +// nx0_data_in <= 'd0; +// cur_data_in <= 'd0; + + nx1_lsoctet_os <= 'd0; + nx1_lsoctet_idle <= 'd0; + nx1_lsoctet_term <= 'd0; + nx1_msoctet_os <= 'd0; + nx1_msoctet_idle <= 'd0; + nx1_msoctet_term <= 'd0; + + nx0_lsoctet_os <= 'd0; + nx0_lsoctet_idle <= 'd0; + nx0_lsoctet_term <= 'd0; + nx0_msoctet_os <= 'd0; + nx0_msoctet_idle <= 'd0; + nx0_msoctet_term <= 'd0; + + cur_lsoctet_os <= 'd0; + cur_lsoctet_idle <= 'd0; + cur_lsoctet_term <= 'd0; + cur_msoctet_os <= 'd0; + cur_msoctet_idle <= 'd0; + cur_msoctet_term <= 'd0; + + end + else if (dv_2x_reg) begin +// else begin +// nx1_data_in <= (data_valid_in) ? wr_data_in : nx1_data_in; +// nx0_data_in <= (nx1_data_valid_in) ? nx1_data_in : nx0_data_in; +// cur_data_in <= (nx0_data_valid_in) ? nx0_data_in : cur_data_in; + + nx0_lsoctet_os <= (nx1_data_valid_in) ? nx1_lsoctet_os : nx0_lsoctet_os; + nx0_lsoctet_idle <= (nx1_data_valid_in) ? nx1_lsoctet_idle : nx0_lsoctet_idle; + nx0_lsoctet_term <= (nx1_data_valid_in) ? nx1_lsoctet_term : nx0_lsoctet_term; + nx0_msoctet_os <= (nx1_data_valid_in) ? nx1_msoctet_os : nx0_msoctet_os; + nx0_msoctet_idle <= (nx1_data_valid_in) ? nx1_msoctet_idle : nx0_msoctet_idle; + nx0_msoctet_term <= (nx1_data_valid_in) ? nx1_msoctet_term : nx0_msoctet_term; + + cur_lsoctet_os <= (nx0_data_valid_in) ? nx0_lsoctet_os : cur_lsoctet_os; + cur_lsoctet_idle <= (nx0_data_valid_in) ? nx0_lsoctet_idle : cur_lsoctet_idle; + cur_lsoctet_term <= (nx0_data_valid_in) ? nx0_lsoctet_term : cur_lsoctet_term; + cur_msoctet_os <= (nx0_data_valid_in) ? nx0_msoctet_os : cur_msoctet_os; + cur_msoctet_idle <= (nx0_data_valid_in) ? nx0_msoctet_idle : cur_msoctet_idle; + cur_msoctet_term <= (nx0_data_valid_in) ? nx0_msoctet_term : cur_msoctet_term; + + + // Reset these before decoding + nx1_lsoctet_os <= 'd0; + nx1_lsoctet_idle <= 'd0; + nx1_lsoctet_term <= 'd0; + nx1_msoctet_os <= 'd0; + nx1_msoctet_idle <= 'd0; + nx1_msoctet_term <= 'd0; + + // Decode Next1 data + case(wr_data_in[71:64]) + 8'b1111_1111: begin + // 2nd row of Figure 49-7, BLOCK_TYPE_FIELD=8'h1e + // Check if all bits are control, then if true, convert from XGMII to 10GBASE-R + // C7,C6,C5,C4/C3,C2,C1,C0 + if (wr_data_in[63:32] == {4{XGMII_IDLE}}) begin + nx1_msoctet_idle <= 1'b1; + end + else begin + nx1_msoctet_idle <= 1'b0; + end + if (wr_data_in[31:0] == {4{XGMII_IDLE}}) begin + nx1_lsoctet_idle <= 1'b1; + end + else begin + nx1_lsoctet_idle <= 1'b0; + end + // 10th row of Figure 49-7, BLOCK_TYPE_FIELD=8'h87 + // C7,C6,C5,C4/C3,C2,C1,T0 + if (wr_data_in[7:0] == XGMII_TERM) begin + nx1_lsoctet_term <= 1'b1; + end + else begin + nx1_lsoctet_term <= 1'b0; + end + end + 8'b0001_1111: begin + // 3rd row of Figure 49-7, BLOCK_TYPE_FIELD=8'h2d + // Check if HIGH ORDERED SET and 1st_XGMII_transfer = all_control. + // D7,D6,D5,O4/C3,C2,C1,C0 + if (wr_data_in[39:32] == XGMII_SEQOS) begin + nx1_msoctet_os <= 1'b1; + end + else begin + nx1_msoctet_os <= 1'b0; + end + if (wr_data_in[31:0] == {4{XGMII_IDLE}}) begin + nx1_lsoctet_idle <= 1'b1; + end + else begin + nx1_lsoctet_idle <= 1'b0; + end + end + 8'b0001_0001: begin + // 6th row of Figure 49-7, BLOCK_TYPE_FIELD=8'h66 + // D7,D6,D5,O4/D3,D2,D1,O0 + if (wr_data_in[39:32] == XGMII_SEQOS) begin + nx1_msoctet_os <= 1'b1; + end + else begin + nx1_msoctet_os <= 1'b0; + end + if (wr_data_in[7:0] == XGMII_SEQOS) begin + nx1_lsoctet_os <= 1'b1; + end + else begin + nx1_lsoctet_os <= 1'b0; + end + end + 8'b1111_0001: begin + // 8th row of Figure 49-7, BLOCK_TYPE_FIELD=8'h4b + // C7,C6,C5,C4/D3,D2,D1,O0 + if (wr_data_in[63:32] == {4{XGMII_IDLE}}) begin + nx1_msoctet_idle <= 1'b1; + end + else begin + nx1_msoctet_idle <= 1'b0; + end + if (wr_data_in[7:0] == XGMII_SEQOS) begin + nx1_lsoctet_os <= 1'b1; + end + else begin + nx1_lsoctet_os <= 1'b0; + end + end + 8'b1111_1110: begin + // 10th row of Figure 49-7, BLOCK_TYPE_FIELD=8'h99 + // C7,C6,C5,C4/C3,C2,T1,D0 + if (wr_data_in[15:8] == XGMII_TERM) begin + nx1_lsoctet_term <= 1'b1; + end + else begin + nx1_lsoctet_term <= 1'b0; + end + end + 8'b1111_1100: begin + // 11th row of Figure 49-7, BLOCK_TYPE_FIELD=8'haa + // C7,C6,C5,C4/C3,T2,D1,D0 + if (wr_data_in[23:16] == XGMII_TERM) begin + nx1_lsoctet_term <= 1'b1; + end + else begin + nx1_lsoctet_term <= 1'b0; + end + end + 8'b1111_1000: begin + // 12th row of Figure 49-7, BLOCK_TYPE_FIELD=8'hb4 + // C7,C6,C5,C4/T3,D2,D1,D0 + if (wr_data_in[31:24] == XGMII_TERM) begin + nx1_lsoctet_term <= 1'b1; + end + else begin + nx1_lsoctet_term <= 1'b0; + end + end + 8'b1111_0000: begin + // 13th row of Figure 49-7, BLOCK_TYPE_FIELD=8'hcc + // C7,C6,C5,T4/D3,D2,D1,D0 + if (wr_data_in[39:32] == XGMII_TERM) begin + nx1_msoctet_term <= 1'b1; + end + else begin + nx1_msoctet_term <= 1'b0; + end + end + 8'b1110_0000: begin + // 14th row of Figure 49-7, BLOCK_TYPE_FIELD=8'hd2 + // C7,C6,T5,D4/D3,D2,D1,D0 + if (wr_data_in[47:40] == XGMII_TERM) begin + nx1_msoctet_term <= 1'b1; + end + else begin + nx1_msoctet_term <= 1'b0; + end + end + 8'b1100_0000: begin + // 15th row of Figure 49-7, BLOCK_TYPE_FIELD=8'he1 + // C7,T6,D5,D4/D3,D2,D1,D0 + if (wr_data_in[55:48] == XGMII_TERM) begin + nx1_msoctet_term <= 1'b1; + end + else begin + nx1_msoctet_term <= 1'b0; + end + end + 8'b1000_0000: begin + // 16th row of Figure 49-7, BLOCK_TYPE_FIELD=8'hff + // T7,D6,D5,D4/D3,D2,D1,D0 + if (wr_data_in[63:56] == XGMII_TERM) begin + nx1_msoctet_term <= 1'b1; + end + else begin + nx1_msoctet_term <= 1'b0; + end + end + default: begin + nx1_lsoctet_os <= 'd0; + nx1_lsoctet_idle <= 'd0; + nx1_lsoctet_term <= 'd0; + nx1_msoctet_os <= 'd0; + nx1_msoctet_idle <= 'd0; + nx1_msoctet_term <= 'd0; + end + endcase + end + end + + //******************************************************************** + // Delete the Current/Next0 LS OCTET if + // 1) Previous LS OCTET has T and Current LS OCTET is IDLE + // --> this will make sure that there is miminum of 5 IPG + // 2) Previous LS OCTET is not T & the Previous MS Octet is an OS + // and is same as the current LS OCTET which is an OS + // 2) Previous MS OCTET is not T & the current LS octet is IDLE + // + // Delete the Current/Next0 MS OCTET if + // 1) Previous MS OCTET has T and Current MS OCTET is IDLE + // --> this will make sure that there is a minimum 5 IPG + // 2) Previous LS OCTET is not T & the Previous MS Octet is an OS + // and is same as the current LS OCTET which is an OS + // 2) Previous LS OCTET is not T & the current LS octet is IDLE + //******************************************************************** + // Current OS is delete-able if previous word is an OS and it's not delete-able + + always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + nx0_lsoctet_del <= 1'b0; + nx0_msoctet_del <= 1'b0; + end + else begin + if (nx1_data_valid_in && dv_2x_reg) begin + // Decode for NEXT0 Data Decodes + if ((((nx0_msoctet_os & nx1_lsoctet_os & !nx0_msoctet_del) & (nx0_data_in[63:32] == nx1_data_in[31:0]))) | + (nx0_msoctet_term == 1'b0 & nx1_lsoctet_idle)) begin + nx0_lsoctet_del <= 1'b1; + end + else begin + nx0_lsoctet_del <= 1'b0; + end + + if ((((nx1_lsoctet_os & nx1_msoctet_os & !((nx0_msoctet_os & nx1_lsoctet_os & !nx0_msoctet_del) & (nx0_data_in[63:32] == nx1_data_in[31:0]))) & (nx1_data_in[31:0] == nx1_data_in[63:32]))) | + (nx1_lsoctet_term == 1'b0 & nx1_msoctet_idle)) begin + nx0_msoctet_del <= 1'b1; + end + else begin + nx0_msoctet_del <= 1'b0; + end + end + end + end + + always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + cur_lsoctet_del <= 1'b0; + cur_msoctet_del <= 1'b0; + end + else begin + if (nx0_data_valid_in && dv_2x_reg) begin + // Decode for Current Data Decodes + if ((((cur_msoctet_os & nx0_lsoctet_os & !cur_msoctet_del) & (cur_data_in[63:32] == nx0_data_in[31:0]))) | + (cur_msoctet_term == 1'b0 & nx0_lsoctet_idle)) begin + cur_lsoctet_del <= 1'b1; + end + else begin + cur_lsoctet_del <= 1'b0; + end + + if ((((nx0_lsoctet_os & nx0_msoctet_os & !((cur_msoctet_os & nx0_lsoctet_os & !cur_msoctet_del) & (cur_data_in[63:32] == nx0_data_in[31:0]))) & (nx0_data_in[31:0] == nx0_data_in[63:32]))) | + (nx0_lsoctet_term == 1'b0 & nx0_msoctet_idle)) begin + cur_msoctet_del <= 1'b1; + end + else begin + cur_msoctet_del <= 1'b0; + end + end + end + end + + + //******************************************************************** + // WRITE CLOCK DOMAIN: Delete 1 OCTET when PFULL. + // In order to stop the writing to the FOFO the following conditions has to be + // true + // 1) Check in the current received data if any octet can be deleted + // if it can be deleted, form a 64 it data by borrowing octet from next + // data + // 2) Before borrowing an octet from nex data, make sure the octet being + // borrowed is valid and not a ocetet that is to be deleted. + // 3) If no valid octet are present in the next data, store the current octet + // until a valid data is received to form a 64 bit data. + // + // The logic implemented below looks at the current 2 octet (MSB,LSB) and the next + // 2 octet (MSB,LSB). + // + // WR_IDLE: This is the default state. In this state are the 4 octets are looked + // at to decide how to form the 64 bit data. + // WR_ADD_NXT_DAT : In this state one VALID next data MSB/LSB octet is + // combined with the current data MSB/LSB octet. + // WR_ADD_STOR_DAT : In thei state the current data MSB/LSB is stored if the + // next data does not have a vaid data (MSB/LSB octet of next data to be + // deleted) + // WR_ADD_NULL_DAT: In this state, no data is formed and the fifo write enable + // is pulled low for a clock cycle. + //******************************************************************** + assign cur_data_in_lsd = cur_data_in[31:0]; + assign cur_data_in_msd = cur_data_in[63:32]; + assign cur_data_in_lsc = cur_data_in[67:64]; + assign cur_data_in_msc = cur_data_in[71:68]; + + assign nx0_data_in_lsd = nx0_data_in[31:0]; + assign nx0_data_in_msd = nx0_data_in[63:32]; + assign nx0_data_in_lsc = nx0_data_in[67:64]; + assign nx0_data_in_msc = nx0_data_in[71:68]; + +// assign block_lock = cur_data_in[PCSDWIDTH + CTL_BFL]; // Frame lock or Block lock status +// assign block_lock = ((phcomp_mode || basic_generic_mode) && wr_data_in[PCSDWIDTH + CTL_BFL] && (~r_bypass_blksync || r_fec_en)) || (base_r_clkcomp_mode && cur_data_in[PCSDWIDTH + CTL_BFL]); // Frame lock or Block lock status + assign block_lock = cur_data_in[PCSDWIDTH + CTL_BFL]; + + always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + block_lock_lt <= 1'b0; + end + else begin + block_lock_lt <= block_lock || (block_lock_lt && r_write_ctrl); + end + end + + assign block_lock_int = r_write_ctrl ? (block_lock_lt ||block_lock) : block_lock; + + // Sequintial Part of SM + always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + wr_en <= 1'b0; + wr_del_sm <= WR_IDLE; + wr_data <= FIFO_DEFAULT[FDWIDTH-3: 0]; + store_lsd <= 'd0; + store_lsc <= 'd0; + keep_store <= 1'b0; + end + else if (!block_lock_int) begin + wr_en <= 1'b0; + wr_del_sm <= WR_IDLE; + wr_data <= FIFO_DEFAULT[FDWIDTH-3: 0]; + store_lsd <= 'd0; + store_lsc <= 'd0; + keep_store <= 1'b0; + end + + else if (nx0_data_valid_in && dv_2x_reg) begin + keep_store <= 'd0; + + case(wr_del_sm) + WR_IDLE: begin + casez({wr_pfull, nx0_msoctet_del,nx0_lsoctet_del, cur_msoctet_del,cur_lsoctet_del}) + 5'b1_?0_01: begin + wr_del_sm <= WR_ADD_NXT_DAT; + wr_en <= 1'b1; + wr_data[PCSDWIDTH-1:0] <= {nx0_data_in_lsd , cur_data_in_msd}; // Data Bits + wr_data[FDWIDTH-3: PCSDWIDTH]<= {nx0_data_in_lsc , cur_data_in_msc}; // Control Bits + end + 5'b1_?0_10: begin + wr_del_sm <= WR_ADD_NXT_DAT; + wr_en <= 1'b1; + wr_data[PCSDWIDTH-1:0] <= {nx0_data_in_lsd , cur_data_in_lsd}; // Data Bits + wr_data[FDWIDTH-3: PCSDWIDTH]<= {nx0_data_in_lsc , cur_data_in_lsc}; // Control Bits + end + 5'b1_01_01: begin + wr_del_sm <= WR_ADD_NULL_DAT; + wr_en <= 1'b1; + wr_data[PCSDWIDTH-1:0] <= {nx0_data_in_msd , cur_data_in_msd}; // Data Bits + wr_data[FDWIDTH-3: PCSDWIDTH]<= {nx0_data_in_msc , cur_data_in_msc}; // Control Bits + end + 5'b1_01_10: begin + wr_del_sm <= WR_ADD_NULL_DAT; + wr_en <= 1'b1; + wr_data[PCSDWIDTH-1:0] <= {nx0_data_in_msd , cur_data_in_lsd}; // Data Bits + wr_data[FDWIDTH-3: PCSDWIDTH]<= {nx0_data_in_msc , cur_data_in_lsc}; // Control Bits + end + 5'b1_11_01: begin + wr_del_sm <= WR_ADD_STOR_DAT; + wr_en <= 1'b0; + store_lsd <= cur_data_in_msd; // Data Bits + store_lsc <= cur_data_in_msc; // Data Bits + keep_store <= 'd1; + end + 5'b1_11_10: begin + wr_del_sm <= WR_ADD_STOR_DAT; + wr_en <= 1'b0; + store_lsd <= cur_data_in_lsd; // Data Bits + store_lsc <= cur_data_in_lsc; // Control Bits + keep_store <= 'd1; + end + 5'b1_??_11: begin + wr_del_sm <= WR_IDLE; + wr_en <= 1'b0; + end + default: begin + wr_del_sm <= WR_IDLE; + wr_en <= 1'b1; + wr_data[PCSDWIDTH-1:0] <= {cur_data_in_msd , cur_data_in_lsd}; // Data Bits + wr_data[FDWIDTH-3: PCSDWIDTH]<= {cur_data_in_msc , cur_data_in_lsc}; // Control Bits + end + endcase + end + WR_ADD_NXT_DAT: begin + casez({wr_pfull,nx0_msoctet_del,nx0_lsoctet_del,cur_msoctet_del}) + 4'b1_?_01: begin + wr_del_sm <= WR_IDLE; + wr_en <= 1'b0; + end + 4'b1_0_10: begin + wr_del_sm <= WR_ADD_NULL_DAT; + wr_en <= 1'b1; + wr_data[PCSDWIDTH-1:0] <= {nx0_data_in_msd , cur_data_in_msd}; // Data Bits + wr_data[FDWIDTH-3: PCSDWIDTH]<= {nx0_data_in_msc , cur_data_in_msc}; // Control Bits + end + 4'b1_1_10: begin + wr_del_sm <= WR_ADD_STOR_DAT; + wr_en <= 1'b0; + store_lsd <= cur_data_in_msd; // Data Bits + store_lsc <= cur_data_in_msc; // Control Bits + keep_store <= 1'b1; + end + 4'b1_0_11: begin + wr_del_sm <= WR_ADD_STOR_DAT; + wr_en <= 1'b0; + store_lsd <= nx0_data_in_msd; // HN + store_lsc <= nx0_data_in_msc; // HN + keep_store <= 1'b1; + end + 4'b1_1_11: begin + wr_del_sm <= WR_ADD_NULL_DAT; + wr_en <= 1'b0; + end + default: begin + wr_del_sm <= WR_ADD_NXT_DAT; + wr_en <= 1'b1; + wr_data[PCSDWIDTH-1:0] <= {nx0_data_in_lsd , cur_data_in_msd}; // Data Bits + wr_data[FDWIDTH-3: PCSDWIDTH]<= {nx0_data_in_lsc , cur_data_in_msc}; // Control Bits + end + endcase + end + WR_ADD_STOR_DAT: begin + casez({wr_pfull,cur_msoctet_del,cur_lsoctet_del}) + 3'b1_01: begin + if (!keep_store) begin + wr_del_sm <= WR_IDLE; + wr_en <= 1'b1; + wr_data[PCSDWIDTH-1:0] <= {cur_data_in_msd , store_lsd}; // Data Bits + wr_data[FDWIDTH-3: PCSDWIDTH]<= {cur_data_in_msc , store_lsc}; // Control Bits + end + else begin + wr_del_sm <= WR_ADD_STOR_DAT; + wr_en <= 1'b0; + end + end + 3'b1_10: begin + wr_del_sm <= WR_IDLE; + wr_en <= 1'b1; + wr_data[PCSDWIDTH-1:0] <= {cur_data_in_lsd , store_lsd}; // Data Bits + wr_data[FDWIDTH-3: PCSDWIDTH]<= {cur_data_in_lsc , store_lsc}; // Control Bits + end + 3'b1_00: begin + wr_del_sm <= WR_ADD_STOR_DAT; + wr_en <= 1'b1; + wr_data[PCSDWIDTH-1:0] <= {cur_data_in_lsd , store_lsd}; // Data Bits + wr_data[FDWIDTH-3: PCSDWIDTH]<= {cur_data_in_lsc , store_lsc}; // Control Bits + store_lsd <= cur_data_in_msd; // Data Bits + store_lsc <= cur_data_in_msc; // Control Bits + end + 3'b1_11: begin + wr_del_sm <= WR_ADD_STOR_DAT; + wr_en <= 1'b0; + end + default: begin + wr_del_sm <= WR_ADD_STOR_DAT; + wr_en <= 1'b1; + wr_data[PCSDWIDTH-1:0] <= {cur_data_in_lsd , store_lsd}; // Data Bits + wr_data[FDWIDTH-3: PCSDWIDTH]<= {cur_data_in_lsc , store_lsc}; // Control Bits + store_lsd <= cur_data_in_msd; // Data Bits + store_lsc <= cur_data_in_msc; // Control Bits + end + + + + 3'b0_??: begin + if (keep_store) begin + wr_del_sm <= WR_ADD_STOR_DAT; + wr_en <= 1'b0; + end + else begin + wr_del_sm <= WR_ADD_STOR_DAT; + wr_en <= 1'b1; + wr_data[PCSDWIDTH-1:0] <= {cur_data_in_lsd , store_lsd}; // Data Bits + wr_data[FDWIDTH-3: PCSDWIDTH]<= {cur_data_in_lsc , store_lsc}; // Control Bits + store_lsd <= cur_data_in_msd; // Data Bits + store_lsc <= cur_data_in_msc; // Control Bits + end + end + + + + + endcase + end + WR_ADD_NULL_DAT: begin + wr_del_sm <= WR_IDLE; + wr_en <= 1'b0; + end + + default: begin + wr_del_sm <= WR_IDLE; + wr_en <= 1'b1; + wr_data[PCSDWIDTH-1:0] <= {cur_data_in_msd , cur_data_in_lsd}; // Data Bits + wr_data[FDWIDTH-3: PCSDWIDTH]<= {cur_data_in_msc , cur_data_in_lsc}; // Control Bits + end + + endcase + end + else if (dv_2x_reg) begin + wr_en <= 1'b0; + end + end + + + +// 10G BaseR Deletion Flag + always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + fifo_del <= 1'b0; + end +// else if (wr_en != cur_data_valid_in) begin +// fifo_del <= 1'b1; +// end +// else if (cur_data_valid_in) begin +// fifo_del <= 1'b0; +// end +// end +// Bug fix: de-assert fifo_del after it's has been written to FIFO on next word +// else if (block_lock_lt) begin +// fifo_del <= (wr_en != cur_data_valid_in); +// end +// end + else if (block_lock_lt && dv_2x_reg) begin + if (fifo_del && !wr_en) begin + fifo_del <= 1'b1; + end + else if (wr_en != cur_data_valid_in || (wr_en & wr_full) ) begin + fifo_del <= 1'b1; + end + else begin + fifo_del <= 1'b0; + end + end + end + + // Attach block lock and deletion flag to write data +// assign {control_out, data_out} = {block_lock_lt, fifo_del, wr_data[FDWIDTH-3:0]}; + + assign wr_srst_n = (block_lock || r_write_ctrl); + + +// assign data_out = {wr_data[PCSDWIDTH-1:0], 2'b00, wr_srst_n, wr_en, block_lock_lt, fifo_del, wr_data[FDWIDTH-3: FDWIDTH-10]}; + +assign data_out_del_sm_aib_2x = teng_2_aib_map({wr_en, block_lock_lt, fifo_del, wr_data[71:64], wr_data[63:0]}); + +always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + data_out_del_sm_aib <= 40'd0; + del_sm_wr_en <= 1'b0; + end + else begin + data_out_del_sm_aib <= dv_2x ? data_out_del_sm_aib_2x[39:0] : data_out_del_sm_aib_2x[79:40]; + del_sm_wr_en <= wr_en; + end +end + + +assign data_out = ~base_r_clkcomp_mode ? aib_fabric_rx_data_in : data_out_del_sm_aib; + +function [79:0] teng_2_aib_map; + input [74:0] teng_in; + begin +// MB, rsvd, 38-b data, MB, 2 rsvd, 10-b control dv, 26-b data --> New map: MB, 1b rsvd, ctrl[9:4], data[63:32], MB, 2-b rsvd, dv, ctrl[3:0], data[31:0] +// teng_2_aib_map = {1'b1, 1'b0, teng_in[63:26], 1'b0, 2'b00,teng_in[73:64], teng_in[74],teng_in[25:0]}; + teng_2_aib_map = {1'b1, 1'b0, teng_in[73:68], teng_in[63:32], 1'b0, 2'b00,teng_in[74], teng_in[67:64],teng_in[31:0]}; + end +endfunction + + +function [74:0] aib_2_teng_map; + input [79:0] aib_data; + begin +// aib_2_teng_map = {aib_data[26], aib_data[36:27], aib_data[77:40], aib_data[25:0]}; + aib_2_teng_map = {aib_data[36], aib_data[77:72], aib_data[35:32], aib_data[71:40], aib_data[31:0]}; + end +endfunction + +assign deletion_sm_testbus = {9'd0, cur_msoctet_term, cur_lsoctet_term, cur_msoctet_os, cur_lsoctet_os, cur_msoctet_del, cur_lsoctet_del, wr_full, wr_pfull , wr_del_sm[1:0], wr_en, fifo_del}; + + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_fifo.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_fifo.v new file mode 100644 index 0000000..dbfa361 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_fifo.v @@ -0,0 +1,986 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_rx_datapath_fifo + #( + parameter FDWIDTH = 'd40, // FIFO width + parameter FAWIDTH = 'd6 // FIFO Depth (address width) + ) + ( + input wire wr_rst_n, // Write Domain Active low Reset + input wire rd_rst_n, // Read Domain Active low Reset +// input wire wr_srst_n, // Write Domain Active low Reset +// input wire rd_srst_n, // Read Domain Active low Reset + input wire wr_clk, // Write Domain Clock + input wire q1_wr_clk, // Write Domain Clock + input wire q2_wr_clk, // Write Domain Clock + input wire q3_wr_clk, // Write Domain Clock + input wire q4_wr_clk, // Write Domain Clock + input wire q5_wr_clk, // Write Domain Clock + input wire q6_wr_clk, // Write Domain Clock + input wire rd_clk, // Read Domain Clock + input wire s_clk, // Latency Measure Sample Clock + input wire s_rst_n, // Latency Measure Sample Reset + + input wire [2:0] r_fifo_mode, // FIFO Mode: Phase-comp, BaseR RM, Interlaken, Register Mode + input wire [FAWIDTH-1:0] r_pempty, // FIFO partially empty threshold + input wire [FAWIDTH-1:0] r_pfull, // FIFO partially full threshold + input wire [FAWIDTH-1:0] r_empty, // FIFO empty threshold + input wire [FAWIDTH-1:0] r_full, // FIFO full threshold + input wire r_indv, // Individual Mode + input wire [2:0] r_phcomp_rd_delay, // Programmable read and write pointer gap in phase comp mode + + input wire r_pempty_type, // FIFO partially empty flag type + input wire r_pfull_type, // FIFO partially full flag type + input wire r_empty_type, // FIFO empty flag type + input wire r_full_type, // FIFO full flag type + input wire r_stop_read, // Disable/enable reading when FIFO is empty + input wire r_stop_write, // Disable/enable writing when FIFO is full + input wire r_double_read, // FIFO double write option + input wire r_gb_dv_en, // GB data valid enable + input wire r_truebac2bac, + input wire r_wa_en, + input wire [2:0] r_fifo_power_mode, + input wire r_wr_adj_en, + input wire r_rd_adj_en, + input wire r_pipe_en, + input wire r_write_ctrl, + input wire fifo_latency_adj, + + input wire [FDWIDTH-1:0] aib_fabric_rx_data_in, // Write Data In +// input wire data_valid_in, // Write Data In Valid + input wire rd_en, // Core read enable + input wire rd_align_clr, + + input wire comp_wren_en, // CP Bonding Write Enable + input wire comp_rden_en, // CP Bonding Read Enable + input wire compin_sel_wren, + input wire compin_sel_rden, + output wire phcomp_wren, // Wr Enable to CP Bonding + output wire phcomp_rden, // Rd Enable to CP Bonding + + input wire wr_pfull_stretch, // Write partial full stretch + input wire wr_empty_stretch, // Write empty stretch + input wire wr_pempty_stretch, // Write partial empty stretch + input wire wr_full_stretch, // Write full stretch + input wire wa_lock, // From word-align + + input wire [9:0] insert_sm_control_out, + input wire [63:0] insert_sm_data_out, + input wire insert_sm_rd_en, + input wire insert_sm_rd_en_lt, + + input wire block_lock, + input wire block_lock_lt, + input wire del_sm_wr_en, + + input wire asn_fifo_hold, // ASN hold value on FIFO output reg + input wire asn_fifo_srst, // sync reset + input wire asn_gen3_sel, // Switch between single/double mode + + output wire [73:0] baser_fifo_data, + output wire [73:0] baser_fifo_data2, + output wire baser_data_valid, + +// output reg [FDWIDTH-1:0] control_out, // Frame information + output wire [2*FDWIDTH-1:0] pld_rx_fabric_data_out, // Read Data Out +// output reg data_valid_out, // Read Data Out Valid + output wire rd_pfull, // Read partial full + output wire rd_empty, // Read empty + output wire rd_pempty, // Read partial empty + output wire rd_full, // Read full + output wire wr_full_comb, // Write full + output wire wr_pfull_comb, // Write partial full + output wire wr_full, // Write full + output wire wr_pfull, // Write partial full + output wire fifo_empty, // FIFO empty + output wire fifo_pempty, // FIFO partial empty + output wire fifo_pfull, // FIFO partial full + output wire fifo_full, // FIFO full + +// output wire wr_addr_msb, // Write address MSB +// output wire rd_addr_msb, // Read address MSB + output wire latency_pulse, + output wire align_done, + output wire wa_error, // To status reg + output reg [3:0] wa_error_cnt, // Go to status reg + + + output wire double_read_int, // Go to CP bonding + output wire fifo_srst_n_wr_clk, // Go to CP bonding + output wire fifo_srst_n_rd_clk, // Go to CP bonding + output wire wa_srst_n_wr_clk, // Go to WA + + output wire base_r_clkcomp_mode, // Go to del_sm + output reg rd_align_clr_reg, + output reg fifo_ready, + + output wire[19:0] testbus1, // Test Bus 1 + output wire[19:0] testbus2 // Test Bus 2 + + ); + +//******************************************************************** +// Define Parameters +//******************************************************************** +//`include "hd_pcs10g_params.v" + + +localparam FIFO_DATA_DEFAULT = {80{1'h0}}; + +//******************************************************************** +// Define variables +//******************************************************************** + +wire [FAWIDTH-1:0] rd_numdata; +wire [FAWIDTH-1:0] wr_numdata; + +wire wr_en_int; +wire [FDWIDTH-1:0] wr_data_in_int; + +//reg first_read; + +wire [FDWIDTH-1:0] data_in; +wire [FDWIDTH-1:0] wr_data_in; +wire [FDWIDTH-1:0] wr_data_in2; +wire [FDWIDTH-1:0] fifo_out; +wire [FDWIDTH-1:0] fifo_out_next; +wire [FDWIDTH-1:0] fifo_out2; +wire [FDWIDTH-1:0] fifo_out2_next; + +wire rd_en_int; + + +wire phcomp_rden_int; +wire comp_rden_en_int; + + + + +reg phcomp_wren_d0; +reg phcomp_wren_d1; + + +wire comp_dv_en_sync; +wire phcomp_wren_sync; + +reg dv_en_d0; +reg dv_en_d1; +reg dv_en_d2; +reg dv_en_d3; +reg dv_en_d4; + +wire wr_empty; +wire wr_pempty; +//wire wr_pfull; +//wire wr_full; + +wire phcomp_wren_sync2; +reg phcomp_wren_sync3; +reg phcomp_wren_sync4; +reg phcomp_wren_sync5; +reg phcomp_wren_sync6; + +wire wr_fifo_en; + +reg [79:0] data_out; +//wire [73:0] baser_fifo_data; +//wire [73:0] baser_fifo2_data; +wire data_valid_in; +reg data_valid_out; +wire [79:0] baser_insert_sm_data; + + +// FIFO mode decode +wire intl_generic_mode = (r_fifo_mode == 3'b001); +wire basic_generic_mode = (r_fifo_mode == 3'b101); +wire register_mode = (r_fifo_mode[1:0] == 2'b11); +wire phcomp_mode = (r_fifo_mode[1:0] == 2'b00); +//wire base_r_clkcomp_mode = (r_fifo_mode == 3'b010); +assign base_r_clkcomp_mode = (r_fifo_mode == 3'b010); + +wire generic_mode = intl_generic_mode || basic_generic_mode; + +//reg wm_bit; +//reg wm_bit_d1; +//reg wm_bit_d2; +//reg wm_bit_d3; +//reg wm_bit_d4; +//reg wm_bit_d5; +//wire wm_found; +//reg wm_found_lt; + +reg rd_en_lt; + +//wire [63:0] insert_sm_data_out; +//wire [9:0] insert_sm_control_out; +//wire insert_sm_rd_en; +//wire rd_en_lt0; +wire phcomp_wren_int; + +//assign rx_fifo_rd_en = rd_en_int; + +wire asn_gen3_sel_sync; +wire asn_fifo_hold_sync; + +wire dv_bit; +reg dv_bit_reg; + +reg fifo_latency_adj_wr_sync_d0; +reg fifo_latency_adj_wr_sync_d1; +wire fifo_latency_adj_wr_sync; +wire fifo_latency_adj_wr_pulse; +reg fifo_latency_adj_rd_sync_d0; +wire fifo_latency_adj_rd_sync; +wire fifo_latency_adj_rd_pulse; +wire wr_en_int2; +wire rd_en_int2; + +wire ps_rd_addr_msb; +wire ps_wr_addr_msb; + +reg phystatus_fall; +reg phystatus_delay; +wire phystatus; + +wire ps_dw_wr_addr_msb; +wire ps_dw_rd_addr_msb; + +reg phcomp_wren_d2; +wire asn_fifo_srst_n_rd_clk; +wire asn_fifo_srst_n_wr_clk; + +wire wr_srst_n_int; +wire rd_srst_n_int; + +wire block_lock_sync; +wire wr_align_clr; +wire comp_wren_en_int; +wire fifo_ready_int; + +reg compin_sel_wren_reg; +reg compin_sel_wren_reg2; +wire compin_sel_wren_neg_edge; + +reg compin_sel_rden_reg; +reg compin_sel_rden_reg2; +wire compin_sel_rden_neg_edge; +reg rd_addr_msb_reg; +reg ps_rd_addr_msb_reg; +reg ps_dw_rd_addr_msb_reg; + +// Bit mapping +// phcomp mode or elastic: data valid +// clock comp: 10G baseR wr_en +//assign dv_or_wren = data_in[38]; +//assign frame_lock = data_in[37]; +//assign control_bit = data_in[29]; + +assign data_in = aib_fabric_rx_data_in; + +//assign pld_rx_fabric_data_out = data_out; + +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) + rd_align_clr_reg <= 1'b0; + else + rd_align_clr_reg <= rd_align_clr; +end + + +//******************************************************************** +// Instantiate the Async FIFO +// (parameter FDWIDTH,parameter FAWIDTH,parameter FIFO_ALMFULL,parameter FIFO_ALMEMPTY) +//******************************************************************** +hdpldadapt_rx_datapath_async_fifo +#( +.DWIDTH (FDWIDTH), // FIFO Input data width +.AWIDTH (FAWIDTH) // FIFO Depth (address width) +) +hdpldadapt_rx_datapath_async_fifo +( +.wr_rst_n (wr_rst_n), // Write Domain Active low Reset +.wr_srst_n (fifo_srst_n_wr_clk), // Write Domain Active low Reset Synchronous +.wr_clk (wr_clk), // Write Domain Clock +.q1_wr_clk (q1_wr_clk), // Write Domain Clock +.q2_wr_clk (q2_wr_clk), // Write Domain Clock +.q3_wr_clk (q3_wr_clk), // Write Domain Clock +.q4_wr_clk (q4_wr_clk), // Write Domain Clock +.q5_wr_clk (q5_wr_clk), // Write Domain Clock +.q6_wr_clk (q6_wr_clk), // Write Domain Clock +.wr_en (wr_en_int2), // Write Data Enable +.wr_data (wr_data_in), // Write Data In +.rd_rst_n (rd_rst_n), // Read Domain Active low Reset +.rd_srst_n (fifo_srst_n_rd_clk), // Read Domain Active low Reset Synchronous +.rd_clk (rd_clk), // Read Domain Clock +.rd_en (rd_en_int2), // Read Data Enable +.rd_data (fifo_out), // Read Data Out +.rd_data_next (fifo_out_next),// Read Data Out +.rd_data2 (fifo_out2), // Read Data Out +.rd_data2_next (fifo_out2_next),// Read Data Out +.rd_numdata (rd_numdata), // Number of Data available in Read clock +.wr_numdata (wr_numdata), // Number of Data available in Write clock +.r_pempty (r_pempty), // FIFO partially empty threshold +.r_pfull (r_pfull), // FIFO partially full threshold +.r_empty (r_empty), // FIFO empty threshold +.r_full (r_full), // FIFO full threshold +.r_stop_write (r_stop_write), // FIFO write option +.r_stop_read (r_stop_read), // FIFO read option +.r_double_read (r_double_read), // FIFO read option +.r_fifo_power_mode (r_fifo_power_mode), +.wr_empty (wr_empty), // FIFO Empty +.wr_pempty (wr_pempty), // FIFO Partial Empty +.wr_full (wr_full), // FIFO Full +.wr_pfull (wr_pfull), // FIFO Parial Full +.wr_full_comb (wr_full_comb), // FIFO Full +.wr_pfull_comb (wr_pfull_comb), // FIFO Parial Full +.rd_empty (rd_empty), // FIFO Empty +.rd_pempty (rd_pempty), // FIFO Partial Empty +.rd_full (rd_full), // FIFO Full +.rd_pfull (rd_pfull), // FIFO Partial Full +.wr_addr_msb (wr_addr_msb), +.rd_addr_msb (rd_addr_msb), +.ps_dw_wr_addr_msb (ps_dw_wr_addr_msb), // Write address MSB for latency measure +.ps_dw_rd_addr_msb (ps_dw_rd_addr_msb), // Read address MSB for latency measure +.ps_wr_addr_msb (ps_wr_addr_msb), // Write address MSB for latency measure +.ps_rd_addr_msb (ps_rd_addr_msb) // Read address MSB for latency measure +); + +//******************************************************************** +// Instantiate latency measuring logic +//******************************************************************** + +hdpldadapt_cmn_latency_measure hdpldadapt_cmn_latency_measure ( +.s_clk (s_clk), +.s_rst_n (s_rst_n), +.r_fifo_power_mode (r_fifo_power_mode), +.wr_addr_msb (wr_addr_msb), // Write address MSB for latency measure +.rd_addr_msb (rd_addr_msb_reg), // Read address MSB for latency measure +.ps_dw_wr_addr_msb (ps_dw_wr_addr_msb), // Write address MSB for latency measure +.ps_dw_rd_addr_msb (ps_dw_rd_addr_msb_reg), // Read address MSB for latency measure +.ps_wr_addr_msb (ps_wr_addr_msb), // Write address MSB for latency measure +.ps_rd_addr_msb (ps_rd_addr_msb_reg), // Read address MSB for latency measure +.latency_pulse (latency_pulse) +); + +//assign del_sm_wr_data = {del_sm_control_out, del_sm__out}; + +// Insert data valid to control bit[7] +// assign wr_data_in_phcomp = same_clk_phcomp_mode ? {wr_data_in[FDWIDTH-1: FDWIDTH-2], data_valid_in_pre, wr_data_in[FDWIDTH-4: 0]} : wr_data_in; + +// Data & Write/Read selection for different modes +//assign wr_data_in_int = generic_mode ? wr_data_in : // Generic +// phcomp_mode ? wr_data_in : // Phase Comp mode +// del_sm_wr_data; // BaseR Clock Comp + +assign wr_data_in = data_in; + + +assign wr_en_int = (phcomp_mode && r_indv) ? phcomp_wren_int: // Phase Comp Indiviual mode + (phcomp_mode && ~r_indv) ? comp_wren_en_int: // Phase Comp Bonding mode + (base_r_clkcomp_mode) ? del_sm_wr_en: // BaseR mode + data_valid_in; // Interlaken mode or generic mode + + +assign rd_en_int = (phcomp_mode && r_indv) ? phcomp_rden : // Phase Comp Indiviual mode + (phcomp_mode && ~r_indv) ? comp_rden_en_int: // Phase Comp Bonding mode + generic_mode ? rd_en : // Interlaken or Generic mode + insert_sm_rd_en; // BaseR + +// FIFO sync reset +// Interlaken Generic: reset with rd_align_clr +// Clock comp: reset by block lock or not (depends on r_write_ctrl) +// Phase-comp: reset by rd_align_clr (depends on r_write_ctrl) +assign wr_srst_n_int = intl_generic_mode ? ~wr_align_clr : base_r_clkcomp_mode ? (block_lock || r_write_ctrl) : r_write_ctrl || ~wr_align_clr ; +assign rd_srst_n_int = intl_generic_mode ? ~rd_align_clr_reg : base_r_clkcomp_mode ? (block_lock_sync || r_write_ctrl) : r_write_ctrl || ~rd_align_clr_reg ; + +//******************************************************************** +// READ CLOCK DOMAIN: STOP reading when PEMPTY, +// empty, the FIFO read is stopped when the read data has a +// IDLE/TERM/SEQ_IDLE/IDLE_SEQ +//******************************************************************** + + +// Output Register and Bypass Logic +//always @(negedge rd_rst_n or posedge rd_clk) begin +// if (rd_rst_n == 1'b0) begin +// data_valid_out <= 1'b0; +// data_out <= FIFO_DATA_DEFAULT; +// end +// else if (fifo_srst_n_rd_clk == 1'b0) begin +// data_valid_out <= 1'b0; +// data_out <= FIFO_DATA_DEFAULT; +// end +//// PCI-e hold during switching +// else if (~asn_fifo_hold_sync) begin +// // PC mode: before reading from FIFO +// if (phcomp_mode && ~rd_en_int) begin +// data_valid_out <= 1'b0; +// data_out <= FIFO_DATA_DEFAULT; +// end +// // Non PC mode, when empty +// else if (rd_empty && ~phcomp_mode) begin +// data_valid_out <= 1'b0; +// data_out <= FIFO_DATA_DEFAULT; +// end +// else if (base_r_clkcomp_mode) begin +// data_valid_out <= 1'b1; +// data_out <= insert_sm_rd_en_lt? baser_insert_sm_data : data_out; +// end +// // Interlaken mode and Phase Comp mode +// // Use rd_en to gate data_out and generate data_valid_out +// else begin +// data_valid_out <= rd_en_int ? 1'b1: 1'b0; +// data_out <= rd_en_int ? {fifo_out_next, fifo_out}: data_out; +// end +// end +// +//end + +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + data_valid_out <= 1'b0; + data_out <= FIFO_DATA_DEFAULT; + end +// PCI-e hold during switching + else if (asn_fifo_hold_sync) begin + data_valid_out <= data_valid_out; + data_out <= data_out; + end + else if (fifo_srst_n_rd_clk == 1'b0) begin + data_valid_out <= 1'b0; + data_out <= FIFO_DATA_DEFAULT; + end + // Register mode + else if (register_mode) begin + data_valid_out <= 1'b1; + data_out <= {{FDWIDTH{1'b0}},data_in}; + end + // PC mode: before reading from FIFO + else if (phcomp_mode && ~rd_en_int2) begin + data_valid_out <= 1'b0; + data_out <= FIFO_DATA_DEFAULT; + end + // Non PC mode, when empty + else if (rd_empty && ~phcomp_mode) begin + data_valid_out <= 1'b0; + data_out <= FIFO_DATA_DEFAULT; + end + else if (base_r_clkcomp_mode) begin + data_valid_out <= 1'b1; + data_out <= insert_sm_rd_en_lt? baser_insert_sm_data : data_out; + end + // Interlaken mode and Phase Comp mode + // Use rd_en to gate data_out and generate data_valid_out + else begin + data_valid_out <= rd_en_int2 ? 1'b1: 1'b0; + data_out <= rd_en_int2 ? {fifo_out_next, fifo_out}: data_out; + end + +end + + +//******************************************************************** +// FIFO bonding logic +//******************************************************************** + +// Phase Comp FIFO mode Write/Read enable logic generation +// Write Enable +always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + phcomp_wren_d0 <= 1'b0; + phcomp_wren_d1 <= 1'b0; + phcomp_wren_d2 <= 1'b0; + end + else if (fifo_srst_n_wr_clk == 1'b0) begin + phcomp_wren_d0 <= 1'b0; + phcomp_wren_d1 <= 1'b0; + phcomp_wren_d2 <= 1'b0; + end + else begin +// phcomp_wren_d0 <= phcomp_wren_d0 || wa_lock && (data_valid_in || ~r_gb_dv_en); + phcomp_wren_d0 <= phcomp_wren_d0 || data_valid_in; + phcomp_wren_d1 <= phcomp_wren_d0; + phcomp_wren_d2 <= phcomp_wren_d1; + end +end + +assign phcomp_wren = phcomp_wren_d1; + +//assign phcomp_wren_int = phcomp_wren && (data_valid_in || ~r_gb_dv_en); +assign phcomp_wren_int = phcomp_wren && data_valid_in; + +//assign comp_wren_en_int = comp_wren_en && (data_valid_in || ~r_gb_dv_en); +assign comp_wren_en_int = comp_wren_en && data_valid_in; + +// phcomp_wren Synchronizer + cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (4), + .VID (1) + ) + cdclib_bitsync2_phcomp_wren + ( + .clk (rd_clk), + .rst_n (rd_rst_n), + .data_in (phcomp_wren), + .data_out (phcomp_wren_sync2) + ); + +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + phcomp_wren_sync3 <= 1'b0; + phcomp_wren_sync4 <= 1'b0; + phcomp_wren_sync5 <= 1'b0; + phcomp_wren_sync6 <= 1'b0; + end + else if (fifo_srst_n_rd_clk == 1'b0) begin + phcomp_wren_sync3 <= 1'b0; + phcomp_wren_sync4 <= 1'b0; + phcomp_wren_sync5 <= 1'b0; + phcomp_wren_sync6 <= 1'b0; + end + else begin + phcomp_wren_sync3 <= phcomp_wren_sync2; + phcomp_wren_sync4 <= phcomp_wren_sync3; + phcomp_wren_sync5 <= phcomp_wren_sync4; + phcomp_wren_sync6 <= phcomp_wren_sync5; + end +end + +// Read Enable +assign phcomp_wren_sync = (r_phcomp_rd_delay == 3'b110) ? phcomp_wren_sync6 : (r_phcomp_rd_delay == 3'b101) ? phcomp_wren_sync5 : (r_phcomp_rd_delay == 3'b100) ? phcomp_wren_sync4 : (r_phcomp_rd_delay == 3'b011) ? phcomp_wren_sync3 : phcomp_wren_sync2; +assign phcomp_rden = phcomp_wren_sync; + + +assign comp_rden_en_int = comp_rden_en; + + + + +// Testbus +assign testbus1 = {5'd0, fifo_srst_n_wr_clk, ps_dw_wr_addr_msb, ps_wr_addr_msb, wr_addr_msb, wr_pempty, wr_empty, phcomp_wren, comp_wren_en, wr_numdata[5:0], wr_en_int2}; +assign testbus2 = {2'd0, fifo_srst_n_rd_clk, fifo_ready, ps_dw_rd_addr_msb, ps_rd_addr_msb, rd_addr_msb, rd_empty, rd_pempty, data_valid_in, rd_numdata[5:0], rd_en_int2, comp_rden_en, phcomp_rden, data_valid_out}; + + +// Output flag +assign fifo_pempty = r_pempty_type ? wr_pempty_stretch : rd_pempty; +assign fifo_pfull = r_pfull_type ? wr_pfull_stretch : rd_pfull; +assign fifo_empty = r_empty_type ? wr_empty_stretch : rd_empty; +assign fifo_full = r_full_type ? wr_full_stretch : rd_full; + + +// Need to extract wr_en/DV bit from LW bit 26, bit[38] is Interlaken write_en +// Mapping update: wr_en/DV bit = bit 36, bit[38] is Interlaken write_en +//assign dv_bit = wa_lock && (intl_generic_mode ? data_in[38] && ~data_in[39] && data_in[26] : ~data_in[39] && data_in[26]); +//assign dv_bit = wa_lock && (intl_generic_mode ? data_in[38] && data_in[36] : data_in[36]); +//assign dv_bit = wa_lock && ~data_in[39] && (intl_generic_mode ? data_in[38] && data_in[36] : data_in[36]); + assign dv_kill = data_in[36] & r_gb_dv_en; + assign dv_bit = wa_lock && ~data_in[39] && (intl_generic_mode ? data_in[38] && dv_kill : dv_kill ); + +always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + dv_bit_reg <= 1'b0; + end +// Only logic used in PIPE/PCI-e mode uses sync reset +// else if (fifo_srst_n_wr_clk == 1'b0) begin +// dv_bit_reg <= 1'b0; +// end + else begin + dv_bit_reg <= dv_bit; + end +end + +//assign data_valid_in = dv_bit || dv_bit_reg || ~r_gb_dv_en; +assign data_valid_in = r_gb_dv_en ? (dv_bit || dv_bit_reg) : wa_lock; + + +//Word-align +//always @(negedge wr_rst_n or posedge wr_clk) begin +// if (wr_rst_n == 1'b0) begin +// wm_bit <= 1'b0; +// wm_bit_d1 <= 1'b0; +// wm_bit_d2 <= 1'b0; +// wm_bit_d3 <= 1'b0; +// wm_bit_d4 <= 1'b0; +// wm_bit_d5 <= 1'b0; +// wa_lock_lt <= 1'b0; +// end +// else begin +// wm_bit <= data_in[39]; +// wm_bit_d1 <= wm_bit; +// wm_bit_d2 <= wm_bit_d1; +// wm_bit_d3 <= wm_bit_d2; +// wm_bit_d4 <= wm_bit_d3; +// wm_bit_d5 <= wm_bit_d4; +// wm_found_lt <= wm_found_lt || wm_found; +// end +//end +// +//assign wm_found = wm_bit && ~wm_bit_d1 && wm_bit_d2 && ~wm_bit_d3 && wm_bit_d4 && ~wm_bit_d5 || ~r_wa_en; + +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + rd_en_lt <= 1'b0; + end + else if (~fifo_srst_n_rd_clk) + rd_en_lt <= 1'b0; + else begin + rd_en_lt <= rd_en_int2 || rd_en_lt; + end +end + + +assign align_done = r_wa_en && rd_en_lt; + + +//******************************************************************** +// 10G BaseR deletion/insertion logic +//******************************************************************** +//hdpldadapt_rx_datapath_del_sm +// #( +// .PCSDWIDTH (PCSDWIDTH), // PCS data width +// .PCSCWIDTH (PCSCWIDTH, // PCS control width +// .FAWIDTH (FAWIDTH), // FIFO Depth (address width) +// ) hdpldadapt_rx_datapath_del_sm +// ( +//.wr_rst_n (wr_rst_n), +//.wr_srst_n (wr_srst_n), +//.wr_clk (wr_clk), +//.control_in (control_in), +//.data_in (data_in), +//.data_valid_in (data_valid_in), +//.block_lock (block_lock), +//.r_write_ctrl (r_write_ctrl), +//.wr_pfull (wr_pfull), +//.wr_full (wr_full), +//.control_out (del_sm_control_out), +//.data_out (del_sm_data_out), +//.fifo_del (fifo_del), +//.wr_en (del_sm_wr_en) +// ); + +//hdpldadapt_rx_datapath_insert_sm +// #( +// .PCSDWIDTH (64), // PCS data width +// .PCSCWIDTH (10) // PCS control width +// ) hdpldadapt_rx_datapath_insert_sm +// ( +//.rd_rst_n (rd_rst_n), +//.rd_srst_n (rd_srst_n), +//.rd_clk (rd_clk), +//.fifo_out (baseR_fifo_data), +//.fifo_out_next (baseR_fifo_data2), +//.rd_pempty (rd_pempty), +//.rd_empty (rd_empty), +//.data_valid_out (data_valid_out), +//.r_truebac2bac (r_truebac2bac), +//.control_out (insert_sm_control_out), +//.data_out (insert_sm_data_out), +//.rd_en_10g (insert_sm_rd_en), +//.rd_en_lt0 (rd_en_lt0) +// ); + +// Remap +// assign baser_fifo_data = {fifo_out[36:27], fifo_out_next[37:0], fifo_out[25:0]}; +// assign baser_fifo_data2 = {fifo_out2[36:27], fifo_out2_next[37:0], fifo_out2[25:0]}; +assign baser_fifo_data = {fifo_out_next[37:32], fifo_out[35:32], fifo_out_next[31:0], fifo_out[31:0]}; +assign baser_fifo_data2 = {fifo_out2_next[37:32], fifo_out2[35:32], fifo_out2_next[31:0], fifo_out2[31:0]}; + + +// Map data from insert SM to 80-bit +// Remap: assign baser_insert_sm_data = {1'b1, 1'b0, insert_sm_data_out[63:26], 1'b0, 2'b00,insert_sm_control_out, data_valid_out,insert_sm_data_out[25:0]}; +assign baser_insert_sm_data = {1'b1, 1'b0, insert_sm_control_out[9:4], insert_sm_data_out[63:32], 1'b0, 2'b00, data_valid_out,insert_sm_control_out[3:0], insert_sm_data_out[31:0]}; + +assign baser_data_valid = data_valid_out; + +//Word-align error detect + +assign wa_error = (data_out[39] || ~data_out[79]) && r_wa_en && data_valid_out; + +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + wa_error_cnt <= 4'b0000; + end + else if (fifo_srst_n_rd_clk == 1'b0) begin + wa_error_cnt <= 4'b0000; + end + else if (wa_error_cnt < 4'b1111 && wa_error) begin + wa_error_cnt <= wa_error_cnt + 1'b1; + end +end + +// G3 switching/reset logic + +// Sync to write/read clock domain + cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (4), + .VID (1) + ) + cdclib_bitsync2_asn_srst_n_wr_clk + ( + .clk (wr_clk), + .rst_n (wr_rst_n), + .data_in (asn_fifo_srst_n), + .data_out (asn_fifo_srst_n_wr_clk) + ); + + cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (4), + .VID (1) + ) + cdclib_bitsync2_asn_srst_n_rd_clk + ( + .clk (rd_clk), + .rst_n (rd_rst_n), + .data_in (asn_fifo_srst_n), + .data_out (asn_fifo_srst_n_rd_clk) + ); + +// cdclib_bitsync2 +// #( +// .DWIDTH (1), // Sync Data input +// .RESET_VAL (0) // Reset Value +// ) +// cdclib_bitsync2_asn_gen3_sel +// ( +// .clk (rd_clk), +// .rst_n (rd_rst_n), +// .data_in (asn_gen3_sel), +// .data_out (asn_gen3_sel_sync) +// ); + + cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (4), + .VID (1) + ) + cdclib_bitsync2_asn_fifo_hold + ( + .clk (rd_clk), + .rst_n (rd_rst_n), + .data_in (asn_fifo_hold), + .data_out (asn_fifo_hold_sync) + ); + + cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (4), + .VID (1) + ) + cdclib_bitsync2_align_clr + ( + .clk (wr_clk), + .rst_n (wr_rst_n), + .data_in (rd_align_clr_reg), + .data_out (wr_align_clr) + ); + + cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (4), + .VID (1) + ) + hd_dpcmn_bitsync2_block_lock + ( + .clk (rd_clk), + .rst_n (rd_rst_n), + .data_in (block_lock_lt), + .data_out (block_lock_sync) + ); + +assign asn_fifo_srst_n = ~asn_fifo_srst; + +// Combine with legacy 10G sync reset +// Combine with bond signal neg edge detect +assign fifo_srst_n_rd_clk = asn_fifo_srst_n_rd_clk && rd_srst_n_int && ~compin_sel_rden_neg_edge; +assign fifo_srst_n_wr_clk = asn_fifo_srst_n_wr_clk && wr_srst_n_int && ~compin_sel_wren_neg_edge; +// HN func ECO assign wa_srst_n_wr_clk = asn_fifo_srst_n_wr_clk && ~compin_sel_wren_neg_edge; +assign wa_srst_n_wr_clk = asn_fifo_srst_n_wr_clk && ~compin_sel_wren_neg_edge && ~wr_align_clr; +//assign double_read_int = asn_gen3_sel_sync || r_double_read ? 1'b1: 1'b0; +assign double_read_int = r_double_read; + +// Latency adjust + cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (4), + .VID (1) + ) + cdclib_bitsync2_wr_adj + ( + .clk (wr_clk), + .rst_n (wr_rst_n), + .data_in (fifo_latency_adj), + .data_out (fifo_latency_adj_wr_sync) + ); + + cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (4), + .VID (1) + ) + cdclib_bitsync2_rd_adj + ( + .clk (rd_clk), + .rst_n (rd_rst_n), + .data_in (fifo_latency_adj), + .data_out (fifo_latency_adj_rd_sync) + ); + +always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + fifo_latency_adj_wr_sync_d0 <= 1'b0; + fifo_latency_adj_wr_sync_d1 <= 1'b0; + end + else if (fifo_srst_n_wr_clk == 1'b0) begin + fifo_latency_adj_wr_sync_d0 <= 1'b0; + fifo_latency_adj_wr_sync_d1 <= 1'b0; + end + else begin + fifo_latency_adj_wr_sync_d0 <= fifo_latency_adj_wr_sync; + fifo_latency_adj_wr_sync_d1 <= fifo_latency_adj_wr_sync_d0; + end +end + +assign fifo_latency_adj_wr_pulse = r_wr_adj_en && (r_double_read ? fifo_latency_adj_wr_sync && (~fifo_latency_adj_wr_sync_d0 || ~fifo_latency_adj_wr_sync_d1) : fifo_latency_adj_wr_sync && ~fifo_latency_adj_wr_sync_d0); + +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + fifo_latency_adj_rd_sync_d0 <= 1'b0; + end + else if (fifo_srst_n_rd_clk == 1'b0) begin + fifo_latency_adj_rd_sync_d0 <= 1'b0; + end + else begin + fifo_latency_adj_rd_sync_d0 <= fifo_latency_adj_rd_sync; + end +end + +assign fifo_latency_adj_rd_pulse = r_rd_adj_en && (fifo_latency_adj_rd_sync && ~fifo_latency_adj_rd_sync_d0); + +assign wr_en_int2 = wr_en_int && ~ fifo_latency_adj_wr_pulse; +assign rd_en_int2 = rd_en_int && ~ fifo_latency_adj_rd_pulse; + +// Gate phystatus to 1 during reset +assign phystatus = data_out[32]; + +always @ (posedge rd_clk or negedge rd_rst_n) begin + if (~rd_rst_n) begin + phystatus_fall <= 1'b0; + phystatus_delay <= 1'b0; + end +// else if (~fifo_srst_n_rd_clk) begin +// phystatus_fall <= 1'b0; +// phystatus_delay <= 1'b0; +// end + else begin + phystatus_fall <= phystatus_fall || (~phystatus && phystatus_delay); + phystatus_delay <= phystatus; + end +end + +// In PIPE mode, after reset release and before seeing phystatus first rising edge, gate phystatus to 1; +assign pld_rx_fabric_data_out[32] = (r_pipe_en && ~phystatus_fall) ? 1'b1 : data_out[32]; +//assign pld_rx_fabric_data_out[31:0] = data_out[31:0]; +//assign pld_rx_fabric_data_out[25:0] = data_out[25:0]; +//assign pld_rx_fabric_data_out[31:27] = data_out[31:27]; +assign pld_rx_fabric_data_out[31:0] = data_out[31:0]; +//assign pld_rx_fabric_data_out[79:33] = data_out[79:33]; +assign pld_rx_fabric_data_out[35:33] = data_out[35:33]; +assign pld_rx_fabric_data_out[36] = data_out[36]; +assign pld_rx_fabric_data_out[78:37] = data_out[78:37]; + + +// When GB data valid is enabled, map pld_rx_fabric_data_out[26] to FIFO data valid out +// Remap: assign pld_rx_fabric_data_out[26] = r_gb_dv_en ? data_valid_out: data_out[26]; +// assign data_valid_out to bit 79. This bit is needed for Interlaken, Elastic and regsiter mode with GB. Optional for PC and CC mode +//assign pld_rx_fabric_data_out[36] = r_gb_dv_en ? data_valid_out: data_out[36]; +assign pld_rx_fabric_data_out[79] = data_valid_out; + +assign fifo_ready_int = comp_rden_en_int || r_indv || ~phcomp_mode; + +always @ (posedge rd_clk or negedge rd_rst_n) begin + if (~rd_rst_n) begin + fifo_ready <= 1'b0; + end + else begin + fifo_ready <= fifo_ready_int; + end +end + +// Bonding signal falling edge detect for PIPE/HIP speed change reset + +always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) + begin + compin_sel_wren_reg <= 1'b0; + compin_sel_wren_reg2 <= 1'b0; + end + else + begin + compin_sel_wren_reg <= compin_sel_wren; + compin_sel_wren_reg2 <= compin_sel_wren_reg; + end + end // always @ (negedge rst_n or posedge clk) + +//assign compin_sel_wren_neg_edge = ~compin_sel_wren && compin_sel_wren_reg; +// Register cause compin_sel is timing-critical +assign compin_sel_wren_neg_edge = ~compin_sel_wren_reg && compin_sel_wren_reg2 && ~r_indv; + +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) + begin + compin_sel_rden_reg <= 1'b0; + compin_sel_rden_reg2 <= 1'b0; + end + else + begin + compin_sel_rden_reg <= compin_sel_rden; + compin_sel_rden_reg2 <= compin_sel_rden_reg; + end + end // always @ (negedge rst_n or posedge clk) + +assign compin_sel_rden_neg_edge = ~compin_sel_rden_reg && compin_sel_rden_reg2 && ~r_indv; + +// Delay rd_ptr_msb to account for FIFO ouput being registered +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) + begin + rd_addr_msb_reg <= 1'b0; + ps_rd_addr_msb_reg <= 1'b0; + ps_dw_rd_addr_msb_reg <= 1'b0; + end + else + begin + rd_addr_msb_reg <= rd_addr_msb; + ps_rd_addr_msb_reg <= ps_rd_addr_msb; + ps_dw_rd_addr_msb_reg <= ps_dw_rd_addr_msb; + end + end // always @ (negedge rst_n or posedge clk) + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_fifo_pointers.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_fifo_pointers.v new file mode 100644 index 0000000..9434bc6 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_fifo_pointers.v @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_rx_datapath_fifo_pointers + #( + parameter AWIDTH = 'd4, // Address width + parameter PS_AWIDTH = 'd3, // PS Address width + parameter DEPTH = 'd16, // FIFO Depth + parameter PS_DEPTH = 'd8 + ) +( + input wire wr_clk, // Write Domain Clock + input wire wr_rst_n, // Write Domain Reset + input wire wr_srst_n, // Write Domain Active low Reset Synchronous + input wire rd_clk, // Read Domain Clock + input wire rd_rst_n, // Read Domain Reset + input wire rd_srst_n, // Read Domain Active low Reset Synchronous + input wire wr_en, // Write Data Enable + input wire rd_en, // Read Data Enable + input wire rd_empty, + input wire wr_full, + input wire r_stop_read, // Disable/enable reading when FIFO is empty + input wire r_stop_write, // Disable/enable writing when FIFO is full + input wire r_double_read, // FIFO double read mode + input wire [2:0] r_fifo_power_mode, // FIFO double write mode + + + output wire [DEPTH-1:0] wr_ptr_one_hot, // Write Pointer + output wire [DEPTH-1:0] rd_ptr_one_hot, // Read Pointer + output wire [AWIDTH-1:0] wr_ptr_bin, // Write Pointer + output wire [AWIDTH-1:0] rd_ptr_bin, // Read Pointer + + output wire wr_addr_msb, // Write address MSB + output wire rd_addr_msb, // Read address MSB + output wire ps_wr_addr_msb, // PS Write address MSB + output wire ps_rd_addr_msb, // PS Read address MSB + output wire ps_dw_wr_addr_msb, // PS Write address MSB + output wire ps_dw_rd_addr_msb, // PS Read address MSB + + + output wire [AWIDTH-1:0] wr_numdata, + output wire [AWIDTH-1:0] rd_numdata + +); + //******************************************************************** + // Define Parameters + //******************************************************************** + + //******************************************************************** + // Define variables + //******************************************************************** + reg [AWIDTH:0] wr_addr_bin; + reg [AWIDTH:0] rd_addr_bin; + + reg [AWIDTH:0] wr_addr_gry; + reg [AWIDTH:0] rd_addr_gry; + + // Wires + wire [AWIDTH-1:0] wr_addr_mem; + wire [AWIDTH-1:0] rd_addr_mem; + + wire [AWIDTH:0] wr_addr_bin_nxt; + wire [AWIDTH:0] rd_addr_bin_nxt; + wire [AWIDTH:0] wr_addr_gry_nxt; + wire [AWIDTH:0] rd_addr_gry_nxt; + wire [AWIDTH:0] wr_addr_bin_sync; + wire [AWIDTH:0] rd_addr_bin_sync; + wire [AWIDTH:0] wr_addr_gry_sync; + wire [AWIDTH:0] rd_addr_gry_sync; + wire [AWIDTH:0] rd_addr_gry_nxt_dw; + + + // Convert pointer to onehot +// assign rd_ptr_one_hot = ~r_fifo_power_mode[1] ? {{DEPTH-PS_DEPTH{1'b0}}, bin_to_onehot_ps(rd_addr_mem[PS_AWIDTH-1:0])} : bin_to_onehot(rd_addr_mem); +// assign wr_ptr_one_hot = ~r_fifo_power_mode[1] ? {{DEPTH-PS_DEPTH{1'b0}}, bin_to_onehot_ps(wr_addr_mem[PS_AWIDTH-1:0])} : bin_to_onehot(wr_addr_mem); + + assign rd_ptr_one_hot = ~r_fifo_power_mode[1] ? {{DEPTH-PS_DEPTH{1'b0}}, bin_to_onehot_ps(rd_addr_mem[PS_AWIDTH-1:0])} : + ~r_fifo_power_mode[2] ? {{DEPTH-2*PS_DEPTH{1'b0}}, bin_to_onehot_2ps(rd_addr_mem[PS_AWIDTH:0])} : + bin_to_onehot(rd_addr_mem); + assign wr_ptr_one_hot = ~r_fifo_power_mode[1] ? {{DEPTH-PS_DEPTH{1'b0}}, bin_to_onehot_ps(wr_addr_mem[PS_AWIDTH-1:0])} : + ~r_fifo_power_mode[2] ? {{DEPTH-2*PS_DEPTH{1'b0}}, bin_to_onehot_2ps(wr_addr_mem[PS_AWIDTH:0])} : + bin_to_onehot(wr_addr_mem); + + assign wr_addr_msb = wr_addr_bin[AWIDTH]; + assign rd_addr_msb = rd_addr_bin[AWIDTH]; + + assign ps_wr_addr_msb = wr_addr_bin[PS_AWIDTH]; + assign ps_rd_addr_msb = rd_addr_bin[PS_AWIDTH]; + + assign ps_dw_wr_addr_msb = wr_addr_bin[PS_AWIDTH+1]; + assign ps_dw_rd_addr_msb = rd_addr_bin[PS_AWIDTH+1]; + + assign rd_ptr_bin = rd_addr_bin[AWIDTH-1:0]; + assign wr_ptr_bin = wr_addr_bin[AWIDTH-1:0]; + + //******************************************************************** + // WRITE CLOCK DOMAIN: Generate WRITE Address & WRITE Address GREY + //******************************************************************** + // Memory write-address pointer + assign wr_addr_mem = wr_addr_bin[AWIDTH-1:0]; + always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + wr_addr_bin <= 'd0; + wr_addr_gry <= 'd0; + end + else if (wr_srst_n == 1'b0) begin + wr_addr_bin <= 'd0; + wr_addr_gry <= 'd0; + end + else begin + wr_addr_bin <= wr_addr_bin_nxt; + wr_addr_gry <= wr_addr_gry_nxt; + end + end + // Binary Next Write Address + assign wr_addr_bin_nxt = wr_addr_bin + (r_stop_write ? (wr_en & ~wr_full) : wr_en); + + // Grey Next Write Address + assign wr_addr_gry_nxt = ((wr_addr_bin_nxt>>1'b1) ^ wr_addr_bin_nxt); + + //******************************************************************** + // WRITE CLOCK DOMAIN: Synchronize Read Address to Write Clock + //******************************************************************** + cdclib_bitsync2 + #( + .DWIDTH (AWIDTH+1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (1), + .VID (1) + ) + cdclib_bitsync2_wr + ( + .clk (wr_clk), + .rst_n (wr_rst_n), + .data_in (rd_addr_gry), + .data_out (rd_addr_gry_sync) + ); + + + assign rd_addr_bin_sync = !r_double_read ? greytobin(rd_addr_gry_sync) : greytobin_dw(rd_addr_gry_sync); + assign wr_numdata = (wr_addr_bin_nxt - rd_addr_bin_sync); + + //******************************************************************** + // READ CLOCK DOMAIN: Generate READ Address & READ Address GREY + //******************************************************************** + // Memory read-address pointer + assign rd_addr_mem = rd_addr_bin[AWIDTH-1:0]; + + always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + rd_addr_bin <= 'd0; + rd_addr_gry <= 'd0; + end + else if (rd_srst_n == 1'b0) begin + rd_addr_bin <= 'd0; + rd_addr_gry <= 'd0; + end + else begin + rd_addr_bin <= rd_addr_bin_nxt; + rd_addr_gry <= !r_double_read ? rd_addr_gry_nxt : rd_addr_gry_nxt_dw; + end + end + // Binary Next Read Address + + assign rd_addr_bin_nxt = rd_addr_bin + (!r_double_read ? (r_stop_read ? (rd_en & ~rd_empty) : rd_en) : + (r_stop_read ? 2*(rd_en & ~rd_empty) : 2*rd_en)); + + // Grey Next Read Address + assign rd_addr_gry_nxt = ((rd_addr_bin_nxt>>1'b1) ^ rd_addr_bin_nxt); + assign rd_addr_gry_nxt_dw = {((rd_addr_bin_nxt[AWIDTH:1]>>1'b1) ^ rd_addr_bin_nxt[AWIDTH:1]),1'b0}; + + //******************************************************************** + // READ CLOCK DOMAIN: Synchronize Write Address to Read Clock + //******************************************************************** + cdclib_bitsync2 + #( + .DWIDTH (AWIDTH+1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (1), + .VID (1) + ) + cdclib_bitsync2_rd + ( + .clk (rd_clk), + .rst_n (rd_rst_n), + .data_in (wr_addr_gry), + .data_out (wr_addr_gry_sync) + ); + + assign wr_addr_bin_sync = greytobin(wr_addr_gry_sync); + assign rd_numdata = (wr_addr_bin_sync - rd_addr_bin_nxt); + + //******************************************************************** + // Function to convert Grey to Binary + //******************************************************************** + function [AWIDTH:0] greytobin; + input [AWIDTH:0] data_in; // Gray pointers + integer i; + begin + for (i='d0; i<=AWIDTH; i=i+1'b1) begin + greytobin[i] = ^(data_in>> i); + end + end + endfunction + + function [AWIDTH:0] greytobin_dw; + input [AWIDTH:0] data_in; // Gray pointers + integer i; + begin + greytobin_dw[0] = 1'b0; + for (i='d1; i<=AWIDTH; i=i+1'b1) begin + greytobin_dw[i] = ^(data_in>> i); + end + end + endfunction + + function [(1< input of FIFO +assign fifo_data_in = wm_data_out; +assign wm_data_in = pld_tx_fabric_data_in; +assign fifo_wr_en = pld_tx_fabric_data_in[79]; + +assign pld_tx_fabric_fifo_full_int = fifo_full; +assign pld_tx_fabric_fifo_empty_int = fifo_empty; +assign pld_tx_fabric_fifo_pfull_int = fifo_pfull; +assign pld_tx_fabric_fifo_pempty_int = fifo_pempty; + +assign pld_tx_fabric_fifo_latency_pulse_int = latency_pulse; + +assign pld_10g_krfec_tx_frame_int = tx_frame; // Mux with krfec_frame??? + +assign pld_10g_tx_burst_en_exe_int = tx_burst_en_exe; +assign pld_10g_tx_wordslip_exe_int = tx_wordslip_exe; + +hdpldadapt_tx_datapath_fifo hdpldadapt_tx_datapath_fifo(/*AUTOINST*/ + // Outputs + .aib_fabric_tx_data_out(tx_data_out), // Rename port + .fifo_out_comb (fifo_out_comb), + .data_valid_out (data_valid_out), + .rd_pfull (rd_pfull), + .rd_full (rd_full), + .rd_empty_comb (rd_empty_raw), + .rd_pempty_comb (rd_pempty_raw), + .fifo_empty (fifo_empty), + .fifo_pempty (fifo_pempty), + .fifo_pfull (fifo_pfull), + .fifo_full (fifo_full), + .phcomp_wren (phcomp_wren), + .phcomp_rden (phcomp_rden), + .dv_en (dv_en), + .comp_dv_en_reg (comp_dv_en_reg), + .latency_pulse (latency_pulse), + .double_write_int(double_write_int), + .fifo_srst_n_wr_clk(fifo_srst_n_wr_clk), + .fifo_srst_n_rd_clk(fifo_srst_n_rd_clk), + .fifo_ready (tx_fifo_ready), + .testbus1 (tx_fifo_testbus1[19:0]), + .testbus2 (tx_fifo_testbus2[19:0]), + // Inputs + .wr_rst_n (wr_rst_n), + .rd_rst_n (rd_rst_n), + .wr_srst_n (wr_srst_n), + .rd_srst_n (rd_srst_n), + .wr_clk (wr_clk), + .q1_wr_clk (q1_wr_clk), + .q2_wr_clk (q2_wr_clk), + .q3_wr_clk (q3_wr_clk), + .q4_wr_clk (q4_wr_clk), + .q5_wr_clk (q5_wr_clk), + .q6_wr_clk (q6_wr_clk), + .rd_clk (rd_clk), + .s_clk (s_clk), + .s_rst_n (s_rst_n), + .r_fifo_mode (r_fifo_mode[2:0]), + .r_pempty (r_pempty[4:0]), + .r_pfull (r_pfull[4:0]), + .r_empty (r_empty[4:0]), + .r_full (r_full[4:0]), + .r_indv (r_indv), + .r_phcomp_rd_delay(r_phcomp_rd_delay[2:0]), + .r_pempty_type (r_pempty_type), + .r_pfull_type (r_pfull_type), + .r_empty_type (r_empty_type), + .r_full_type (r_full_type), + .r_stop_read (r_stop_read), + .r_stop_write (r_stop_write), + .r_double_write (r_double_write), + .r_dv_indv (r_dv_indv), + .r_gb_dv_en (r_gb_dv_en), + .r_fifo_power_mode (r_tx_fifo_power_mode), + .r_wr_adj_en (r_tx_wr_adj_en), + .r_rd_adj_en (r_tx_rd_adj_en), + .fifo_latency_adj (pld_tx_fifo_latency_adj_en), + .start_dv (start_dv), + .fifo_wr_en (fifo_wr_en), + .pld_tx_fabric_data_in(fifo_data_in), // Rename port + .frm_gen_rd_en (frm_gen_rd_en), + .data_valid_raw (data_valid_raw), + .data_valid_2x (dv_gen_data_valid_2x), + .comp_dv_en (comp_dv_en), + .comp_wren_en (comp_wren_en), + .comp_rden_en (comp_rden_en), + .compin_sel_wren (compin_sel_wren), + .compin_sel_rden (compin_sel_rden), + .asn_fifo_srst (asn_fifo_srst), + .asn_gen3_sel (asn_gen3_sel), + .asn_fifo_hold (tx_asn_fifo_hold), + .rd_pfull_stretch(rd_pfull_stretch), + .rd_empty_stretch(rd_empty_stretch), + .rd_pempty_stretch(rd_pempty_stretch), + .rd_full_stretch(rd_full_stretch)); +hdpldadapt_tx_datapath_word_mark hdpldadapt_tx_datapath_word_mark(/*AUTOINST*/ + // Outputs + .data_out (wm_data_out[79:0]), + // Inputs + .data_in (wm_data_in[79:0]), + .r_wm_en (r_wm_en)); +hdpldadapt_tx_datapath_cp_bond hdpldadapt_tx_datapath_cp_bond(/*AUTOINST*/ + // Outputs + .us_out_dv (us_out_dv), + .ds_out_dv (ds_out_dv), + .us_out_wren (us_out_wren), + .ds_out_wren (ds_out_wren), + .us_out_rden (us_out_rden), + .ds_out_rden (ds_out_rden), + .comp_out_dv_en (comp_out_dv_en), + .comp_out_wren_en (comp_out_wren_en), + .comp_out_rden_en (comp_out_rden_en), + .compin_sel_wren (compin_sel_wren), + .compin_sel_rden (compin_sel_rden), + .tx_cp_bond_testbus(tx_cp_bond_testbus[19:0]), + // Inputs + .tx_wrfifo_clk (tx_wrfifo_clk), + .tx_rdfifo_clk (tx_rdfifo_clk), + .tx_rdfifo_clk_rst_n(tx_rdfifo_clk_rst_n), + .tx_wrfifo_clk_rst_n(tx_wrfifo_clk_rst_n), + .wr_srst_n (fifo_srst_n_wr_clk), + .rd_srst_n (fifo_srst_n_rd_clk), + .data_valid_in_raw(data_valid_in_raw), + .r_us_master (r_us_master), + .r_ds_master (r_ds_master), + .r_us_bypass_pipeln(r_us_bypass_pipeln), + .r_ds_bypass_pipeln(r_ds_bypass_pipeln), + .r_compin_sel (r_compin_sel[1:0]), + .r_comp_cnt (r_comp_cnt), + .r_bonding_dft_in_en(r_bonding_dft_in_en), + .r_bonding_dft_in_value(r_bonding_dft_in_value), + .double_write_int (double_write_int), + .master_in_dv (master_in_dv), + .us_in_dv (us_in_dv), + .ds_in_dv (ds_in_dv), + .master_in_wren (master_in_wren), + .us_in_wren (us_in_wren), + .ds_in_wren (ds_in_wren), + .master_in_rden (master_in_rden), + .us_in_rden (us_in_rden), + .ds_in_rden (ds_in_rden)); +hdpldadapt_tx_datapath_dv_gen hdpldadapt_tx_datapath_dv_gen(/*AUTOINST*/ + // Outputs + .data_valid_2x (dv_gen_data_valid_2x), + .data_valid_out (dv_gen_data_valid_out), + .start_dv (start_dv), + .dv_gen_testbus (dv_gen_testbus), + // Inputs + .rst_n (rst_n), + .clk (clk), + .r_double_write (r_double_write), + .r_dv_indv (r_dv_indv), + .r_gb_idwidth (r_gb_idwidth[2:0]), + .r_gb_odwidth (r_gb_odwidth[1:0]), + .r_fifo_mode (r_fifo_mode[2:0]), + .r_gb_dv_en (r_gb_dv_en), + .rd_pempty (rd_pempty), +// .data_valid_in (data_valid_in), + .phcomp_rden (phcomp_rden), + .comp_dv_en_reg (comp_dv_en_reg)); +hdpldadapt_tx_datapath_frame_gen hdpldadapt_tx_datapath_frame_gen(/*AUTOINST*/ + // Outputs + .aib_fabric_tx_data_out(aib_fabric_tx_data_out[39:0]), + .rd_en (frm_gen_rd_en), + .tx_frame (tx_frame_raw), + .burst_en_exe (burst_en_exe_raw), + .wordslip_exe (wordslip_exe_raw), + .frame_gen_testbus1 (frame_gen_testbus1[19:0]), + .frame_gen_testbus2 (frame_gen_testbus2[19:0]), + // Inputs + .clk (tx_clock_fifo_rd_clk_frm_gen), + .rst_n (rst_n), + .r_bypass_frmgen (r_bypass_frmgen), + .r_pipeln_frmgen (r_pipeln_frmgen), + .r_mfrm_length (r_mfrm_length[15:0]), + .r_pyld_ins (r_pyld_ins), + .r_sh_err (r_sh_err), + .r_burst_en (r_burst_en), + .r_wordslip (r_wordslip), + .r_indv (r_indv), + .data_valid_in_raw (data_valid_in_raw), + .data_valid_2x (dv_gen_data_valid_2x), + .start_dv (start_dv), + .diag_status (diag_status[1:0]), + .burst_en (burst_en), + .wordslip (wordslip), + .rd_pfull (rd_pfull), + .tx_fifo_data (tx_data_out[39:0]), + .fifo_out_comb (fifo_out_comb[39:0])); + +hdpldadapt_tx_datapath_pulse_stretch hdpldadapt_tx_datapath_pulse_stretch ( + .clk (rd_clk), + .rst_n (rd_rst_n), + .rd_pempty_raw (rd_pempty_raw), + .rd_empty_raw (rd_empty_raw), + .burst_en_exe_raw (burst_en_exe_raw), + .wordslip_exe_raw (wordslip_exe_raw), + .tx_frame_raw (tx_frame_raw), + + .r_stretch_num_stages (r_tx_stretch_num_stages), + .rd_pempty_stretch (rd_pempty_stretch), + .rd_empty_stretch (rd_empty_stretch), + .tx_burst_en_exe (tx_burst_en_exe), + .tx_wordslip_exe (tx_wordslip_exe), + .tx_frame (tx_frame)); + + +// Pipeline hssi_latency_pulse +always @(negedge tx_reset_fifo_sclk_rst_n or posedge tx_clock_fifo_sclk) begin + if (tx_reset_fifo_sclk_rst_n == 1'b0) begin + pld_tx_hssi_fifo_latency_pulse_int <= 1'b0; + end + else begin + pld_tx_hssi_fifo_latency_pulse_int <= aib_fabric_pld_tx_hssi_fifo_latency_pulse; + end +end + +// Freeze outputs to PLD +assign nfrz_output_2one = nfrzdrv_in & pr_channel_freeze_n; + +assign pld_tx_fabric_fifo_empty = nfrz_output_2one ? pld_tx_fabric_fifo_empty_int : 1'b1; +assign pld_tx_fabric_fifo_full = nfrz_output_2one ? pld_tx_fabric_fifo_full_int : 1'b1; +assign pld_tx_fabric_fifo_pempty = nfrz_output_2one ? pld_tx_fabric_fifo_pempty_int : 1'b1; +assign pld_tx_fabric_fifo_pfull = nfrz_output_2one ? pld_tx_fabric_fifo_pfull_int : 1'b1; +assign pld_tx_fabric_fifo_latency_pulse = nfrz_output_2one ? pld_tx_fabric_fifo_latency_pulse_int : 1'b1; +assign pld_10g_tx_burst_en_exe = nfrz_output_2one ? pld_10g_tx_burst_en_exe_int : 1'b1; +assign pld_10g_tx_wordslip_exe = nfrz_output_2one ? pld_10g_tx_wordslip_exe_int : 1'b1; +assign pld_10g_krfec_tx_frame = nfrz_output_2one ? pld_10g_krfec_tx_frame_int : 1'b1; +assign pld_tx_hssi_fifo_latency_pulse = nfrz_output_2one ? (r_tx_usertest_sel ? pld_tx_hssi_fifo_latency_pulse_int : aib_fabric_pld_tx_hssi_fifo_latency_pulse ): 1'b1; +assign pld_tx_fifo_ready = nfrz_output_2one ? tx_fifo_ready : 1'b1; + + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_async_fifo.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_async_fifo.v new file mode 100644 index 0000000..c95f1e2 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_async_fifo.v @@ -0,0 +1,561 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// (C) 2009 Altera Corporation. All rights reserved. +// +//------------------------------------------------------------------------ +// File: $RCSfile: hdpldadapt_tx_chnl_async_fifo.v.rca $ +// Revision: $Revision: #8 $ +// Date: $Date: 2014/12/04 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ + + +module hdpldadapt_tx_datapath_async_fifo + #( + parameter DWIDTH = 'd40, // FIFO Input data width + parameter AWIDTH = 'd5 // FIFO Depth (address width) + ) + ( + input wire wr_rst_n, // Write Domain Active low Reset + input wire wr_srst_n, // Write Domain Active low Reset Synchronous + input wire wr_clk, // Write Domain Clock + input wire q1_wr_clk, // Write Domain Clock + input wire q2_wr_clk, // Write Domain Clock + input wire q3_wr_clk, // Write Domain Clock + input wire q4_wr_clk, // Write Domain Clock + input wire q5_wr_clk, // Write Domain Clock + input wire q6_wr_clk, // Write Domain Clock + input wire wr_en, // Write Data Enable + input wire [DWIDTH-1:0] wr_data, // Write Data In + input wire [DWIDTH-1:0] wr_data2, // Write Data In + input wire rd_rst_n, // Read Domain Active low Reset + input wire rd_srst_n, // Read Domain Active low Reset Synchronous + input wire rd_clk, // Read Domain Clock + input wire rd_en, // Read Data Enable + input wire [AWIDTH-1:0] r_pempty, // FIFO partially empty threshold + input wire [AWIDTH-1:0] r_pfull, // FIFO partially full threshold + input wire [AWIDTH-1:0] r_empty, // FIFO empty threshold + input wire [AWIDTH-1:0] r_full, // FIFO full threshold + input wire r_double_write, // FIFO double write mode + input wire [2:0] r_fifo_power_mode, // FIFO double write mode + +// input wire r_pempty_type, // FIFO partially empty flag type +// input wire r_pfull_type, // FIFO partially full flag type +// input wire r_empty_type, // FIFO empty flag type +// input wire r_full_type, // FIFO full flag type + input wire r_stop_read, // Disable/enable reading when FIFO is empty + input wire r_stop_write, // Disable/enable writing when FIFO is full + + output wire [DWIDTH-1:0] rd_data, // Read Data Out + output wire [AWIDTH-1:0] rd_numdata, // Number of Data available in Read clock + output wire [AWIDTH-1:0] wr_numdata, // Number of Data available in Write clock + output wire wr_addr_msb, // Write address MSB + output wire rd_addr_msb, // Write address MSB + output wire ps_wr_addr_msb, // Power-saving Write address MSB + output wire ps_rd_addr_msb, // Power-saving Write address MSB + output wire ps_dw_wr_addr_msb, // Power-saving Write address MSB + output wire ps_dw_rd_addr_msb, // Power-saving Write address MSB + + + output reg wr_empty, // FIFO Empty + output reg wr_pempty, // FIFO Partial Empty + output reg wr_full, // FIFO Full + output reg wr_pfull, // FIFO Parial Full + output reg rd_empty, // FIFO Empty + output reg rd_pempty, // FIFO Partial Empty + output reg rd_full, // FIFO Full + output reg rd_pfull, // FIFO Partial Full + output wire rd_empty_comb, // FIFO empty + output wire rd_pempty_comb // FIFO Parial empty + ); + + //******************************************************************** + // Define Parameters + //******************************************************************** + + localparam DEPTH = (1<= r_full) ? 1'b1 : 1'b0; + // Generate FIFO Almost Full + wr_pfull <= (wr_numdata >= r_pfull) ? 1'b1 : 1'b0; + + end + end + + + //******************************************************************** + // READ CLOCK DOMAIN: Generate Fifo Number of Data Present + // using Read Address and Synchronized Write Address + //******************************************************************** + always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + rd_empty <= 1'b1; + rd_pempty <= 1'b1; + rd_full <= 1'b0; + rd_pfull <= 1'b0; + end + else if (rd_srst_n == 1'b0) begin + rd_empty <= 1'b1; + rd_pempty <= 1'b1; + rd_full <= 1'b0; + rd_pfull <= 1'b0; + end + else begin + + // Generate FIFO Empty +// rd_empty <= (rd_numdata == r_empty) ? 1'b1 : 1'b0; + rd_empty <= rd_empty_comb; + // Generate FIFO Almost Empty +// rd_pempty <= (rd_numdata <= r_pempty) ? 1'b1 : 1'b0; + rd_pempty <= rd_pempty_comb; + // Generate FIFO Full + rd_full <= (rd_numdata >= r_full) ? 1'b1 : 1'b0; + // Generate FIFO Almost Full + rd_pfull <= (rd_numdata >= r_pfull) ? 1'b1 : 1'b0; + + end + end + +assign rd_empty_comb = (rd_numdata == r_empty) ? 1'b1 : 1'b0; +assign rd_pempty_comb = (rd_numdata <= r_pempty) ? 1'b1 : 1'b0; + + + + //******************************************************************** + // FIFO Mapping + //******************************************************************** +// assign q1_wr_en = r_fifo_power_mode[1] ? wr_en : |full_wr_ptr_one_hot[PS_DEPTH-1:0]; + assign q1_wr_en = wr_en; +// assign q1_wr_ptr = r_fifo_power_mode[1] ? top_wr_ptr_one_hot : full_wr_ptr_one_hot[PS_DEPTH-1:0]; +// assign q1_rd_ptr = r_fifo_power_mode[1] ? top_rd_ptr_one_hot : full_rd_ptr_one_hot[PS_DEPTH-1:0]; + assign q1_wr_ptr = full_wr_ptr_one_hot[PS_DEPTH-1:0]; + assign q1_rd_ptr = full_rd_ptr_one_hot[PS_DEPTH-1:0]; + assign q1_wr_data = wr_data[PS_DWIDTH-1:0]; + assign q1_wr_data2 = wr_data2[PS_DWIDTH-1:0]; + + assign q2_wr_en = q1_wr_en; + assign q2_wr_ptr = q1_wr_ptr; + assign q2_rd_ptr = q1_rd_ptr; + assign q2_wr_data = wr_data[DWIDTH-1:PS_DWIDTH]; + assign q2_wr_data2 = wr_data2[DWIDTH-1:PS_DWIDTH]; + +// assign q3_wr_en = |full_wr_ptr_one_hot[2*PS_DEPTH-1:PS_DEPTH]; + assign q3_wr_en = wr_en; + assign q3_wr_ptr = full_wr_ptr_one_hot[2*PS_DEPTH-1:PS_DEPTH]; + assign q3_rd_ptr = full_rd_ptr_one_hot[2*PS_DEPTH-1:PS_DEPTH]; + assign q3_wr_data = wr_data[PS_DWIDTH-1:0]; + assign q3_wr_data2 = wr_data2[PS_DWIDTH-1:0]; + + assign q4_wr_en = q3_wr_en; + assign q4_wr_ptr = q3_wr_ptr; + assign q4_rd_ptr = q3_rd_ptr; + assign q4_wr_data = wr_data[DWIDTH-1:PS_DWIDTH]; + assign q4_wr_data2 = wr_data2[DWIDTH-1:PS_DWIDTH]; + + assign q5_wr_en = wr_en; + assign q5_wr_ptr = full_wr_ptr_one_hot[DEPTH-1:2*PS_DEPTH]; + assign q5_rd_ptr = full_rd_ptr_one_hot[DEPTH-1:2*PS_DEPTH]; + assign q5_wr_data = wr_data[PS_DWIDTH-1:0]; + assign q5_wr_data2 = wr_data2[PS_DWIDTH-1:0]; + + assign q6_wr_en = q5_wr_en; + assign q6_wr_ptr = q5_wr_ptr; + assign q6_rd_ptr = q5_rd_ptr; + assign q6_wr_data = wr_data[DWIDTH-1:PS_DWIDTH]; + assign q6_wr_data2 = wr_data2[DWIDTH-1:PS_DWIDTH]; + + +// assign top_wr_clk = q1_wr_clk; +// assign top_rd_clk = q1_rd_clk; + assign top_wr_en = wr_en; + assign top_rd_en = rd_en; + assign top_rd_empty = rd_empty; + assign top_wr_full = wr_full; + +// assign full_wr_clk = q1_wr_clk; +// assign full_rd_clk = q1_rd_clk; + assign full_wr_en = wr_en; + assign full_rd_en = rd_en; + assign full_rd_empty = rd_empty; + assign full_wr_full = wr_full; + + + assign wr_numdata = ~r_fifo_power_mode[1] ? {{AWIDTH-PS_AWIDTH{1'b0}},full_wr_numdata[PS_AWIDTH-1:0]} : + ~r_fifo_power_mode[2] ? {{AWIDTH-PS_AWIDTH-1{1'b0}},full_wr_numdata[PS_AWIDTH:0]} : + full_wr_numdata; + + assign rd_numdata = ~r_fifo_power_mode[1] ? {{AWIDTH-PS_AWIDTH{1'b0}},full_rd_numdata[PS_AWIDTH-1:0]} : + ~r_fifo_power_mode[2] ? {{AWIDTH-PS_AWIDTH-1{1'b0}},full_rd_numdata[PS_AWIDTH:0]} : + full_rd_numdata; + + assign wr_addr_msb = full_wr_addr_msb; + assign rd_addr_msb = full_rd_addr_msb; + + assign top_rd_data = {q2_rd_data, q1_rd_data}; +// assign bot_rd_data = {q4_rd_data, q3_rd_data}; + + + +// Read data: concatenate data from multiple FIFOs + +integer i, j; + +always @ * begin + for (i='d0; i<= DEPTH-1; i=i+1'b1) begin + if (i<=PS_DEPTH-1) + mem_comb[i] = {q2_rd_data, q1_rd_data}; + else if (i<=2*PS_DEPTH-1) + mem_comb[i] = {q4_rd_data, q3_rd_data}; + else + mem_comb[i] = {q6_rd_data, q5_rd_data}; + end +end + +assign full_rd_data = mem_comb[full_rd_ptr_bin]; + +assign mid_rd_data = mem_comb[full_rd_ptr_bin[PS_AWIDTH:0]]; + + +assign rd_data = ~r_fifo_power_mode[1] ? top_rd_data : + ~r_fifo_power_mode[2] ? mid_rd_data : + full_rd_data; + +endmodule // hdpldadapt_tx_datapath_async_fifo diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_cp_bond.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_cp_bond.v new file mode 100644 index 0000000..5e353ef --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_cp_bond.v @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// (C) 2009 Altera Corporation. All rights reserved. +// +//------------------------------------------------------------------------ +// File: $RCSfile: hdpldiadapt_tx_datapath_cp_bond.v.rca $ +// Revision: $Revision: #8 $ +// Date: $Date: 2015/06/19 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ + + +module hdpldadapt_tx_datapath_cp_bond + #( + parameter CNTWIDTH = 'd8 + ) + ( + input wire tx_wrfifo_clk, // TX PCS clock clock + input wire tx_rdfifo_clk, // TX RD clock clock + input wire tx_rdfifo_clk_rst_n, // TX PCS rst output + input wire tx_wrfifo_clk_rst_n, // TX RD rst output + input wire wr_srst_n, // Write sync rst_n + input wire rd_srst_n, // Read sync rst_n + input wire data_valid_in_raw, // master data valid +// input wire double_write, // FIFO double write option + + input wire r_us_master, // CP up master sel + input wire r_ds_master, // CP dwn master sel + input wire r_us_bypass_pipeln, // CP up comb or seq sel + input wire r_ds_bypass_pipeln, // CP dwn comb or seq sel + input wire [1:0] r_compin_sel, // Comp input sel + input wire [CNTWIDTH-1:0] r_comp_cnt, // Comp timeout value + input wire r_bonding_dft_in_en, // Gate bonding signal during scan + input wire r_bonding_dft_in_value, // Gate bonding signal during scan + input wire double_write_int, // FIFO double write option + + input wire master_in_dv, // data valid master in + input wire us_in_dv, // data valid up in + input wire ds_in_dv, // data valid dwn in + input wire master_in_wren, // PC wren master in + input wire us_in_wren, // PC wren up in + input wire ds_in_wren, // PC wren dwn in + input wire master_in_rden, // PC rden master in + input wire us_in_rden, // PC rden up in + input wire ds_in_rden, // PC rden dwn in + + output wire us_out_dv, // data valid up out + output wire ds_out_dv, // data valid dwn out + output wire us_out_wren, // PC wren up out + output wire ds_out_wren, // PC wren dwn out + output wire us_out_rden, // PC rden up out + output wire ds_out_rden, // PC rden dwn out + output wire comp_out_dv_en, // data valid comp out + output wire comp_out_wren_en, // PC wren comp out + output wire comp_out_rden_en, // PC rden comp out + output wire compin_sel_rden, + output wire compin_sel_wren, + output wire [19:0] tx_cp_bond_testbus // testbus + ); + + + wire ds_tap_dv; + wire us_tap_dv; + wire ds_tap_wren; + wire us_tap_wren; + wire ds_tap_rden; + wire us_tap_rden; + + wire ds_in_dv_int; + wire us_in_dv_int; + wire ds_in_wren_int; + wire us_in_wren_int; + wire ds_in_rden_int; + wire us_in_rden_int; + + wire [CNTWIDTH-1:0] comp_cnt_int; +// wire double_write_int; + wire compin_sel_dv; + + + assign ds_in_dv_int = r_bonding_dft_in_en ? r_bonding_dft_in_value : ds_in_dv; + assign us_in_dv_int = r_bonding_dft_in_en ? r_bonding_dft_in_value : us_in_dv; + assign ds_in_wren_int = r_bonding_dft_in_en ? r_bonding_dft_in_value : ds_in_wren; + assign us_in_wren_int = r_bonding_dft_in_en ? r_bonding_dft_in_value : us_in_wren; + assign ds_in_rden_int = r_bonding_dft_in_en ? r_bonding_dft_in_value : ds_in_rden; + assign us_in_rden_int = r_bonding_dft_in_en ? r_bonding_dft_in_value : us_in_rden; + + hdpldadapt_cmn_cp_dist_pair + #( + .ASYNC_RESET_VAL (0), + .WIDTH (1) // Control width + ) + hdpldadapt_cmn_cp_dist_pair_dv + ( + .clk (tx_rdfifo_clk), + .rst_n (tx_rdfifo_clk_rst_n), + .srst_n (1'b1), + .data_enable (1'b1), + .master_in (master_in_dv), + .us_in (us_in_dv_int), + .ds_in (ds_in_dv_int), + .r_us_master (r_us_master), + .r_ds_master (r_ds_master), + .r_us_bypass_pipeln (1'b0), + .r_ds_bypass_pipeln (1'b0), + .us_out (us_out_dv), + .ds_out (ds_out_dv), + .ds_tap (ds_tap_dv), + .us_tap (us_tap_dv) + ); + + hdpldadapt_cmn_cp_comp_cntr + #( + .CNTWIDTH (8) + ) + hdpldadapt_cmn_cp_comp_cntr_dv + ( + .clk (tx_rdfifo_clk), + .rst_n (tx_rdfifo_clk_rst_n), + .srst_n (1'b1), + .data_enable (1'b1), + .master_in_en (master_in_dv), + .us_tap_en (us_tap_dv), + .ds_tap_en (ds_tap_dv), + .r_compin_sel (r_compin_sel), + .r_comp_cnt (r_comp_cnt), + .comp_cnt_match (comp_out_dv_en), + .compin_sel (compin_sel_dv) + ); + + hdpldadapt_cmn_cp_dist_pair + #( + .ASYNC_RESET_VAL (0), + .WIDTH (1) // Control width + ) + hdpldadapt_cmn_cp_dist_pair_dw_wren + ( + .clk (tx_wrfifo_clk), + .rst_n (tx_wrfifo_clk_rst_n), + .srst_n (wr_srst_n), + .data_enable (1'b1), + .master_in (master_in_wren), + .us_in (us_in_wren_int), + .ds_in (ds_in_wren_int), + .r_us_master (r_us_master), + .r_ds_master (r_ds_master), + .r_us_bypass_pipeln (1'b0), + .r_ds_bypass_pipeln (1'b0), + .us_out (us_out_wren), + .ds_out (ds_out_wren), + .ds_tap (ds_tap_wren), + .us_tap (us_tap_wren) + ); + + hdpldadapt_cmn_cp_comp_cntr + #( + .CNTWIDTH (8) + ) + hdpldadapt_cmn_cp_comp_cntr_wren + ( + .clk (tx_wrfifo_clk), + .rst_n (tx_wrfifo_clk_rst_n), + .srst_n (wr_srst_n), + .data_enable (1'b1), + .master_in_en (master_in_wren), + .us_tap_en (us_tap_wren), + .ds_tap_en (ds_tap_wren), + .r_compin_sel (r_compin_sel), + .r_comp_cnt (r_comp_cnt), + .comp_cnt_match (comp_out_wren_en), + .compin_sel (compin_sel_wren) + ); + + hdpldadapt_cmn_cp_dist_pair_dw + #( + .ASYNC_RESET_VAL (0), + .WIDTH (1) // Control width + ) + hdpldadapt_cmn_cp_dist_pair_dw_rden + ( + .clk (tx_rdfifo_clk), + .rst_n (tx_rdfifo_clk_rst_n), + .srst_n (rd_srst_n), + .data_enable (data_valid_in_raw), + .master_in (master_in_rden), + .us_in (us_in_rden_int), + .ds_in (ds_in_rden_int), + .r_us_master (r_us_master), + .r_ds_master (r_ds_master), + .r_us_bypass_pipeln (1'b0), + .r_ds_bypass_pipeln (1'b0), + .r_double_en (double_write_int), + .us_out (us_out_rden), + .ds_out (ds_out_rden), + .ds_tap (ds_tap_rden), + .us_tap (us_tap_rden) + ); + + hdpldadapt_cmn_cp_comp_cntr + #( + .CNTWIDTH (8) + ) + hdpldadapt_cmn_cp_comp_cntr_rden + ( + .clk (tx_rdfifo_clk), + .rst_n (tx_rdfifo_clk_rst_n), + .srst_n (rd_srst_n), + .data_enable (data_valid_in_raw), + .master_in_en (master_in_rden), + .us_tap_en (us_tap_rden), + .ds_tap_en (ds_tap_rden), + .r_compin_sel (r_compin_sel), + .r_comp_cnt (comp_cnt_int), + .comp_cnt_match (comp_out_rden_en), + .compin_sel (compin_sel_rden) + ); + + assign tx_cp_bond_testbus = {1'b0, + data_valid_in_raw, + master_in_dv, + us_in_dv, + ds_in_dv, + ds_tap_dv, + us_tap_dv, + comp_out_dv_en, + master_in_wren, + us_in_wren, + ds_in_wren, + ds_tap_wren, + us_tap_wren, + comp_out_wren_en, + master_in_rden, + us_in_rden, + ds_in_rden, + ds_tap_rden, + us_tap_rden, + comp_out_rden_en + }; + +assign comp_cnt_int = double_write_int ? r_comp_cnt << 1 : r_comp_cnt; + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_dv_gen.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_dv_gen.v new file mode 100644 index 0000000..3c25063 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_dv_gen.v @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// (C) 2009 Altera Corporation. All rights reserved. +// +//------------------------------------------------------------------------ +// File: $RCSfile: hdpldadapt_tx_datapath_dv_gen.v.rca $ +// Revision: $Revision: #8 $ +// Date: $Date: 2015/04/15 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ +module hdpldadapt_tx_datapath_dv_gen + #( + parameter ISWIDTH = 'd7 // Gearbox Selector width + ) + ( + input wire rst_n, // Active low Reset + input wire clk, // Clock + + input wire r_double_write, // FIFO double write option + input wire r_dv_indv, // Data valid Individual Mode + input wire [2:0] r_gb_idwidth, // Gearbox Input Width + input wire [1:0] r_gb_odwidth, // Gearbox Output Width + input wire [2:0] r_fifo_mode, // FIFO Mode: Phase-comp, Interlaken, Elastic, Register Mode + input wire r_gb_dv_en, // DV gen bypass + + input wire rd_pempty, +// input wire data_valid_in, + input wire phcomp_rden, + input wire comp_dv_en_reg, + + output wire [19:0] dv_gen_testbus, + output wire start_dv, + output wire data_valid_2x, // Toggling DV from DV gen + output wire data_valid_out // Data Valid Enable to CP Bonding + ); + +//******************************************************************** +// Define Parameters +//******************************************************************** + +//******************************************************************** +// Define variables +//******************************************************************** +reg [ISWIDTH-1:0] sel_cnt; +reg [2:0] gap_cnt; +wire rd_val; +wire [ISWIDTH:0] m_selcnt; +reg first_read; +reg dv_2x; + +// FIFO mode decode +wire intl_generic_mode = (r_fifo_mode == 3'b001); +wire basic_generic_mode = (r_fifo_mode == 3'b101); +wire register_mode = (r_fifo_mode[1:0] == 2'b11); +wire phcomp_mode = (r_fifo_mode[1:0] == 2'b00); + + +wire [6:0] gb_idwidth; +wire [6:0] gb_odwidth; + +wire [6:0] threshold; + +reg [6:0] dv_seq_cnt; + +wire gap_cnt_en; + +//wire start_dv; + +assign gb_idwidth = (r_gb_idwidth == 'd5) ? 'd64 : (r_gb_idwidth == 'd4) ? 'd32 : (r_gb_idwidth == 'd3) ? 'd40 : (r_gb_idwidth == 'd2) ? 'd50 : (r_gb_idwidth == 'd1) ? 'd67 : 'd66; +assign gb_odwidth = (r_gb_odwidth == 'd2) ? 'd64 : (r_gb_odwidth == 'd1) ? 'd40 : 'd32; + +assign threshold = (gb_idwidth == 'd50) ? 'd24 : (gb_idwidth == 'd67) ? 'd66 : (gb_idwidth == 'd64) ? 'd31 : 'd32; + +wire [6:0] diff_gb_iodwidth = gb_idwidth - gb_odwidth; +assign data_valid_2x = dv_2x; + +//******************************************************************** +// Instantiated modules +//******************************************************************** + +always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + dv_2x <= 1'b0; + end + else if (gap_cnt_en) begin +// dv_2x <= r_double_write ? ~dv_2x : 1'b1; + dv_2x <= r_gb_dv_en ? ~dv_2x : 1'b1; + end +end + + +always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + dv_seq_cnt <= 'd0; + end + else if (gap_cnt_en && dv_2x) begin + if (dv_seq_cnt < threshold) + dv_seq_cnt <= dv_seq_cnt + 1'b1; + else + dv_seq_cnt <= 'd0; + end +end + +assign start_dv = (dv_seq_cnt == 'd0) && gap_cnt_en; + +always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + first_read <= 1'b1; + end + else if (~rd_pempty && first_read) begin + first_read <= 1'b0; + end +end + + +assign gap_cnt_en = phcomp_rden && phcomp_mode && r_dv_indv || // Non bonding phase-comp + ~first_read && r_dv_indv && ~phcomp_mode || // Non bonding not phase-comp + (comp_dv_en_reg && ~r_dv_indv); // DV bonding + +assign rd_val = ~gap_cnt_en ? 1'b0 : (gap_cnt == 'd0) ? 1'b1 : 1'b0; + +assign m_selcnt = (gb_idwidth+sel_cnt); + +always @(negedge rst_n or posedge clk) begin + if (rst_n == 1'b0) begin + sel_cnt <= 'd0; + gap_cnt <= 'd0; + end + else begin +// rd_val Generation +// Phase Comp non-bonding: wait until first_read deasserts +// Phase Comp bonding: doesn't wait for first_read (Need data_valid to be available before write/read enable) +// Interlaken Generic: doesn't wait for first_read (Interlaken needs data_valid for Frame Generator) +// Basic Generic: wait until first_read deasserts + + if (gap_cnt_en && dv_2x) begin + if (gap_cnt == 'd0) begin + // calculate next MUX selection + if (m_selcnt >= gb_odwidth * 'd5) begin + sel_cnt <= (m_selcnt-gb_odwidth * 'd5); + gap_cnt <= 'd4; + end + else if (m_selcnt >= gb_odwidth * 'd4) begin + sel_cnt <= (m_selcnt-gb_odwidth * 'd4); + gap_cnt <= 'd3; + end + else if (m_selcnt >= gb_odwidth * 'd3) begin + sel_cnt <= (m_selcnt-gb_odwidth * 'd3); + gap_cnt <= 'd2; + end + else if (m_selcnt >= gb_odwidth * 'd2) begin + sel_cnt <= (m_selcnt-gb_odwidth * 'd2); + gap_cnt <= 'd1; + end + else begin + sel_cnt <= (m_selcnt-gb_odwidth); + gap_cnt <= 'd0; + end + end + else begin + gap_cnt <= gap_cnt-1'b1; + end + + end + + end +end + + +//assign data_valid_out = r_gb_dv_en ? data_valid_in : rd_val; +assign data_valid_out = rd_val; + +assign dv_gen_testbus = {6'd0, gap_cnt, sel_cnt, start_dv, gap_cnt_en, dv_2x, data_valid_out}; + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_fifo.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_fifo.v new file mode 100644 index 0000000..51264ec --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_fifo.v @@ -0,0 +1,894 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// (C) 2009 Altera Corporation. All rights reserved. +// +//------------------------------------------------------------------------ +// File: $RCSfile: hdpldadapt_tx_datapath_fifo.v.rca $ +// Revision: $Revision: #38 $ +// Date: $Date: 2015/07/24 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ + +module hdpldadapt_tx_datapath_fifo + #( + parameter FDWIDTH = 'd40, // FIFO width + parameter FAWIDTH = 'd5 // FIFO Depth (address width) + ) + ( + input wire wr_rst_n, // Write Domain Active low Reset + input wire rd_rst_n, // Read Domain Active low Reset + input wire wr_srst_n, // Write Domain Active low Reset + input wire rd_srst_n, // Read Domain Active low Reset + input wire wr_clk, // Write Domain Clock + input wire q1_wr_clk, // Write Domain Clock + input wire q2_wr_clk, // Write Domain Clock + input wire q3_wr_clk, // Write Domain Clock + input wire q4_wr_clk, // Write Domain Clock + input wire q5_wr_clk, // Write Domain Clock + input wire q6_wr_clk, // Write Domain Clock + input wire rd_clk, // Read Domain Clock + input wire s_clk, // Latency Measure Sample Clock + input wire s_rst_n, // Latency Measure Sample Reset + + input wire [2:0] r_fifo_mode, // FIFO Mode: Phase-comp, BaseR RM, Interlaken, Register Mode + input wire [4:0] r_pempty, // FIFO partially empty threshold + input wire [4:0] r_pfull, // FIFO partially full threshold + input wire [4:0] r_empty, // FIFO empty threshold + input wire [4:0] r_full, // FIFO full threshold + input wire r_indv, // Individual Mode + input wire [2:0] r_phcomp_rd_delay, // Programmable read and write pointer gap in phase comp mode + + input wire r_pempty_type, // FIFO partially empty flag type + input wire r_pfull_type, // FIFO partially full flag type + input wire r_empty_type, // FIFO empty flag type + input wire r_full_type, // FIFO full flag type + input wire r_stop_read, // Disable/enable reading when FIFO is empty + input wire r_stop_write, // Disable/enable writing when FIFO is full + input wire r_double_write, // FIFO double write option + input wire r_dv_indv, // Data valid Individual Mode + input wire r_gb_dv_en, // Gearbox data valid is enabled + input wire [2:0] r_fifo_power_mode, + input wire r_wr_adj_en, + input wire r_rd_adj_en, + + input wire fifo_latency_adj, + input wire start_dv, + input wire [2*FDWIDTH-1:0] pld_tx_fabric_data_in, // Write Data In + input wire frm_gen_rd_en, // Read Enable from 10G Frame Gen + input wire data_valid_raw, // Raw Data Valid from DV gen + input wire data_valid_2x, // From DV gen + input wire fifo_wr_en, + + input wire comp_dv_en, // CP Bonding Data Valid Enable + input wire comp_wren_en, // CP Bonding Write Enable + input wire comp_rden_en, // CP Bonding Read Enable + input wire compin_sel_wren, + input wire compin_sel_rden, + + input wire asn_fifo_hold, // ASN hold value on FIFO output reg + input wire asn_fifo_srst, // sync reset + input wire asn_gen3_sel, // Switch between single/double mode + + + input wire rd_pfull_stretch, // Read partial full stretch + input wire rd_empty_stretch, // Read empty stretch + input wire rd_pempty_stretch, // Read partial empty stretch + input wire rd_full_stretch, // Read full stretch + + output wire [FDWIDTH-1:0] aib_fabric_tx_data_out, // Read Data Out (Contains CTRL+DATA) + output wire [FDWIDTH-1:0] fifo_out_comb, // Read Data Out (Contains CTRL+DATA) + output reg data_valid_out, // Read Data Out Valid to Frame Gen + output wire rd_pfull, // Read partial full --> to Frame-gen + output wire rd_full, // Read full + output wire rd_empty_comb, // Read empty + output wire rd_pempty_comb, // Read partial empty + output wire fifo_empty, // FIFO empty + output wire fifo_pempty, // FIFO partial empty + output wire fifo_pfull, // FIFO partial full + output wire fifo_full, // FIFO full + output wire phcomp_wren, // Wr Enable to CP Bonding + output wire phcomp_rden, // Rd Enable to CP Bonding + output wire dv_en, // Data Valid Enable to CP Bonding + output reg comp_dv_en_reg, // To DV generator + + output wire latency_pulse, + output wire double_write_int, // To CP bonding + output wire fifo_srst_n_wr_clk, // Go to CP bonding + output wire fifo_srst_n_rd_clk, // Go to CP bonding + + output reg fifo_ready, + + output wire[19:0] testbus1, // Test Bus 1 + output wire[19:0] testbus2 // Test Bus 2 + + ); + +//******************************************************************** +// Define Parameters +//******************************************************************** +//`include "hd_pcs10g_params.v" + + +localparam FIFO_DATA_DEFAULT = {40{1'b0}}; + +//******************************************************************** +// Define variables +//******************************************************************** + +wire [FAWIDTH-1:0] rd_numdata; +wire [FAWIDTH-1:0] wr_numdata; + +wire wr_en_int; +wire [FDWIDTH-1:0] wr_data_in_int; + +//reg first_read; + +wire [FDWIDTH-1:0] wr_data_in; +wire [FDWIDTH-1:0] wr_data_in2; +wire [FDWIDTH-1:0] fifo_out; +wire [FDWIDTH-1:0] fifo_out_next; + +wire rd_en_int; +wire data_valid_in; + +// To be removed +//assign phcomp_wren = 1'b0; +//assign phcomp_rden = 1'b0; + + + + +wire phcomp_rden_int; +wire comp_rden_en_int; + + + +wire rd_en_generic; + +reg phcomp_wren_d0; + +wire comp_dv_en_sync; +wire phcomp_wren_sync; + +reg dv_en_d0; +reg dv_en_d1; +reg dv_en_d2; +reg dv_en_d3; +reg dv_en_d4; + +wire wr_empty; +wire wr_pempty; +wire wr_pfull; +wire wr_full; + +//reg comp_dv_en_reg; +wire phcomp_wren_sync2; +reg phcomp_wren_sync3; +reg phcomp_wren_sync4; +reg phcomp_wren_sync5; +reg phcomp_wren_sync6; +reg phcomp_wren_sync7; +reg phcomp_wren_sync8; +reg phcomp_wren_sync9; + +reg [FDWIDTH-1:0] data_out; +//reg data_valid_out; +wire [FDWIDTH -1:0] data_out_int; +wire wr_addr_msb; +wire rd_addr_msb; + +reg fifo_latency_adj_wr_sync_d0; +wire fifo_latency_adj_wr_sync; +wire fifo_latency_adj_wr_pulse; +reg fifo_latency_adj_rd_sync_d0; +reg fifo_latency_adj_rd_sync_d1; +wire fifo_latency_adj_rd_sync; +wire fifo_latency_adj_rd_pulse; +wire wr_en_int2; +wire rd_en_int2; + +wire ps_rd_addr_msb; +wire ps_wr_addr_msb; +wire ps_dw_rd_addr_msb; +wire ps_dw_wr_addr_msb; + +reg phcomp_wren_d1; +reg phcomp_wren_d2; + +wire asn_fifo_srst_n_rd_clk; +wire asn_fifo_srst_n_wr_clk; +wire [FDWIDTH-1:0] data_out_wm; +wire asn_fifo_hold_sync; + +reg first_write; +//wire first_write_uw; +reg insert_wm; +reg start_read; + + +//reg [3:0] wait_count; +reg phcomp_rden_reg; +wire phcomp_rden_gb_bond; + +reg wm_bit; +reg wm_bit_d1; +reg wm_bit_d2; +reg wm_bit_d3; +reg wm_bit_d4; +reg wm_bit_d5; +reg wm_found_lt; +wire wm_found_int; +wire wm_found; +wire fifo_ready_int; +reg compin_sel_wren_reg; +reg compin_sel_wren_reg2; +wire compin_sel_wren_neg_edge; + +reg compin_sel_rden_reg; +reg compin_sel_rden_reg2; +wire compin_sel_rden_neg_edge; +reg rd_addr_msb_reg; +reg ps_rd_addr_msb_reg; +reg ps_dw_rd_addr_msb_reg; +reg ps_dw_rd_addr_msb_reg2; + + +// FIFO mode decode +wire intl_generic_mode = (r_fifo_mode == 3'b001); +wire basic_generic_mode = (r_fifo_mode == 3'b101); +wire register_mode = (r_fifo_mode[1:0] == 2'b11); +wire phcomp_mode = (r_fifo_mode[1:0] == 2'b00); + +wire generic_mode = intl_generic_mode || basic_generic_mode; + +assign wr_data_in = pld_tx_fabric_data_in[FDWIDTH -1:0]; +assign wr_data_in2 = pld_tx_fabric_data_in[2*FDWIDTH -1:FDWIDTH]; + +assign aib_fabric_tx_data_out = data_out_int; +// Remap: assign data_valid_in = pld_tx_fabric_data_in[26]; +//assign data_valid_in = pld_tx_fabric_data_in[36]; +// Use pld_tx_fabric_data_in[79] as write enable (NF data_valid_in) in Interlaken, and elastic mode +assign data_valid_in = fifo_wr_en; +//assign tx_fifo_rd_en = rd_en_int; + +//******************************************************************** +// Instantiate the Async FIFO +// (parameter FDWIDTH,parameter FAWIDTH,parameter FIFO_ALMFULL,parameter FIFO_ALMEMPTY) +//******************************************************************** +hdpldadapt_tx_datapath_async_fifo +#( +.DWIDTH (FDWIDTH), // FIFO Input data width +.AWIDTH (FAWIDTH) // FIFO Depth (address width) +) +hdpldadapt_tx_datapath_async_fifo +( +.wr_rst_n (wr_rst_n), // Write Domain Active low Reset +.wr_srst_n (fifo_srst_n_wr_clk), // Write Domain Active low Reset Synchronous +.wr_clk (wr_clk), // Write Domain Clock +.q1_wr_clk (q1_wr_clk), // Write Domain Clock +.q2_wr_clk (q2_wr_clk), // Write Domain Clock +.q3_wr_clk (q3_wr_clk), // Write Domain Clock +.q4_wr_clk (q4_wr_clk), // Write Domain Clock +.q5_wr_clk (q5_wr_clk), // Write Domain Clock +.q6_wr_clk (q6_wr_clk), // Write Domain Clock +.wr_en (wr_en_int2), // Write Data Enable +.wr_data (wr_data_in), // Write Data In +.wr_data2 (wr_data_in2), // Write Data In +.rd_rst_n (rd_rst_n), // Read Domain Active low Reset +.rd_srst_n (fifo_srst_n_rd_clk), // Read Domain Active low Reset Synchronous +.rd_clk (rd_clk), // Read Domain Clock +.rd_en (rd_en_int2), // Read Data Enable +.rd_data (fifo_out), // Read Data Out +//.rd_data_next (fifo_out_next),// Read Data Out +.rd_numdata (rd_numdata), // Number of Data available in Read clock +.wr_numdata (wr_numdata), // Number of Data available in Write clock +.r_pempty (r_pempty), // FIFO partially empty threshold +.r_pfull (r_pfull), // FIFO partially full threshold +.r_empty (r_empty), // FIFO empty threshold +.r_full (r_full), // FIFO full threshold +.r_stop_write (r_stop_write), // FIFO write option +.r_stop_read (r_stop_read), // FIFO read option +.r_double_write (double_write_int), // FIFO read option +.r_fifo_power_mode (r_fifo_power_mode), +.wr_empty (wr_empty), // FIFO Empty +.wr_pempty (wr_pempty), // FIFO Partial Empty +.wr_full (wr_full), // FIFO Full +.wr_pfull (wr_pfull), // FIFO Parial Full +.rd_empty (rd_empty), // FIFO Empty +.rd_pempty (rd_pempty), // FIFO Partial Empty +.rd_empty_comb (rd_empty_comb), +.rd_pempty_comb (rd_pempty_comb), +.rd_full (rd_full), // FIFO Full +.rd_pfull (rd_pfull), // FIFO Partial Full +.wr_addr_msb (wr_addr_msb), +.rd_addr_msb (rd_addr_msb), +.ps_dw_wr_addr_msb (ps_dw_wr_addr_msb), // Write address MSB for latency measure +.ps_dw_rd_addr_msb (ps_dw_rd_addr_msb), // Read address MSB for latency measure +.ps_wr_addr_msb (ps_wr_addr_msb), // Write address MSB for latency measure +.ps_rd_addr_msb (ps_rd_addr_msb) // Read address MSB for latency measure +); + + +//******************************************************************** +// Instantiate latency measuring logic +//******************************************************************** + +hdpldadapt_cmn_latency_measure hdpldadapt_cmn_latency_measure ( +.s_clk (s_clk), +.s_rst_n (s_rst_n), +.r_fifo_power_mode (r_fifo_power_mode), +.wr_addr_msb (wr_addr_msb), // Write address MSB for latency measure +.rd_addr_msb (rd_addr_msb_reg), // Read address MSB for latency measure +.ps_wr_addr_msb (ps_wr_addr_msb), // Write address MSB for latency measure +.ps_rd_addr_msb (ps_rd_addr_msb_reg), // Read address MSB for latency measure +.ps_dw_wr_addr_msb (ps_dw_wr_addr_msb), // Write address MSB for latency measure +.ps_dw_rd_addr_msb (ps_dw_rd_addr_msb_reg2), // Read address MSB for latency measure +.latency_pulse (latency_pulse) +); + + +// Data & Write/Read selection for different modes + +assign rd_en_generic = basic_generic_mode ? data_valid_raw : frm_gen_rd_en; + + +assign wr_data_in_int = wr_data_in; + + +assign wr_en_int = (phcomp_mode && r_indv) ? phcomp_wren: // Phase Comp Indiviual mode + (phcomp_mode && ~r_indv) ? comp_wren_en: // Phase Comp Bonding mode + data_valid_in; // Interlaken or Generic mode + + +assign rd_en_int = (phcomp_mode && r_indv) ? phcomp_rden_int: // Phase Comp Indiviual mode + (phcomp_mode && ~r_indv) ? comp_rden_en_int: // Phase Comp Bonding mode + rd_en_generic; // Interlaken or Generic mode + + + +//******************************************************************** +//******************************************************************** + + +// Output Register and Bypass Logic +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + data_valid_out <= 1'b0; + data_out <= FIFO_DATA_DEFAULT; + end +// else if (asn_fifo_hold_sync) begin +// data_valid_out <= data_valid_out; +// data_out <= data_out; +// end + else if (fifo_srst_n_rd_clk == 1'b0) begin + data_valid_out <= 1'b0; + data_out <= FIFO_DATA_DEFAULT; + end +// register mode + else if (register_mode) begin +// data_valid_out <= 1'b1; + data_valid_out <= data_valid_in; + data_out <= wr_data_in; + end +// PC mode: before reading from FIFO +// else if (phcomp_mode && ~phcomp_rden) begin + else if (phcomp_mode && ~((phcomp_rden && r_indv) || (comp_rden_en && ~r_indv))) begin + data_valid_out <= 1'b0; + data_out <= FIFO_DATA_DEFAULT; + end +// Non PC mode, when empty + else if (rd_empty && ~phcomp_mode) begin + data_valid_out <= 1'b0; + data_out <= FIFO_DATA_DEFAULT; + end +// Interlaken mode and Phase Comp mode +// Use rd_en to gate data_out and generate data_valid_out + else begin + data_valid_out <= rd_en_int2 ? 1'b1: 1'b0; +// data_out <= rd_en_int ? fifo_out: data_out; + data_out <= fifo_out_comb; + end +end + +assign fifo_out_comb = rd_en_int2 ? fifo_out: data_out; + +// When GB DV is used, attach to data LW, bit 26 + +// Insert word-marking bits when not reading from FIFO due to data valid +//assign data_out_wm = ~r_gb_dv_en || ~double_write_int || data_valid_out ? data_out : {~data_valid_2x,data_out[38:0]}; +//assign data_out_wm = ~r_gb_dv_en || data_valid_out ? data_out : {~data_valid_2x,data_out[38:0]}; +assign data_out_wm = ~r_gb_dv_en || data_valid_out ? data_out : {~insert_wm,data_out[38:0]}; + +//assign data_out_int = ~r_gb_dv_en || ~double_write_int || data_out[39] ? data_out : {data_out[39:27], data_valid_out, data_out[25:0]}; +// Insert DV start of sequence bit to avoid TX GB overflow when ratio is 67:x: bit 38 +// Remap start dv is bit 77 (was bit 38) +//assign data_out_int = ~r_gb_dv_en || ~double_write_int || data_out_wm[39] ? data_out_wm : {data_out_wm[39], start_dv, data_out_wm[37:27], data_valid_out, data_out_wm[25:0]}; +assign data_out_int = r_gb_dv_en && ~data_out_wm[39] ? {data_out_wm[39:37], data_valid_out, data_out_wm[35:0]} : + r_gb_dv_en && data_out_wm[39] ? {data_out_wm[39:38], start_dv, data_out_wm[36:0]} : + data_out_wm; + + +//******************************************************************** +// FIFO bonding logic +//******************************************************************** + + +// Data valid Enable to CP Bonding +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + dv_en_d0 <= 1'b0; + dv_en_d1 <= 1'b0; + dv_en_d2 <= 1'b0; + dv_en_d3 <= 1'b0; + dv_en_d4 <= 1'b0; + end + else if (fifo_srst_n_rd_clk == 1'b0) begin + dv_en_d0 <= 1'b0; + dv_en_d1 <= 1'b0; + dv_en_d2 <= 1'b0; + dv_en_d3 <= 1'b0; + dv_en_d4 <= 1'b0; + end + else begin + dv_en_d0 <= 1'b1; + dv_en_d1 <= dv_en_d0; + dv_en_d2 <= dv_en_d1; + dv_en_d3 <= dv_en_d2; + dv_en_d4 <= dv_en_d3; + end +end + +assign dv_en = dv_en_d4; + +// Register comp_dv_en before synchronizing because comp_dv_en is not directly from register. +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + comp_dv_en_reg <= 1'b0; + end + else if (fifo_srst_n_rd_clk == 1'b0) begin + comp_dv_en_reg <= 1'b0; + end + else begin + comp_dv_en_reg <= comp_dv_en; + end +end + +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + phcomp_rden_reg <= 1'b0; + end + else if (fifo_srst_n_rd_clk == 1'b0) begin + phcomp_rden_reg <= 1'b0; + end + else begin + phcomp_rden_reg <= phcomp_wren_sync; + end +end + +// Delay 1 cycle if phcomp_rden asserts when data_valid_2x = 1 to make sure first word read from FIFO is LW +assign phcomp_rden_gb_bond = ~data_valid_2x ? phcomp_wren_sync || phcomp_rden_reg : phcomp_rden_reg; + +// comp_dv_en Synchronizer + cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (4), + .VID (1) + ) + cdclib_bitsync2_comp_dv_en + ( + .clk (wr_clk), + .rst_n (wr_rst_n), + .data_in (comp_dv_en_reg), + .data_out (comp_dv_en_sync) + ); + + +// Phase Comp FIFO mode Write/Read enable logic generation +// Write Enable +always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + phcomp_wren_d0 <= 1'b0; + phcomp_wren_d1 <= 1'b0; +// phcomp_wren_d2 <= 1'b0; + end + else if (~fifo_srst_n_wr_clk) begin + phcomp_wren_d0 <= 1'b0; + phcomp_wren_d1 <= 1'b0; +// phcomp_wren_d2 <= 1'b0; + end + else begin +// phcomp_wren_d0 <= (r_indv || comp_dv_en_sync || ~r_gb_dv_en) || phcomp_wren_d0; // Indv: 1, Bonding: goes high and stays high when comp_dv_en goes high +// phcomp_wren_d0 <= (~r_gb_dv_en || r_double_write || data_valid_in) && (r_indv || comp_dv_en_sync) || phcomp_wren_d0; // Indv: 1, Bonding: goes high and stays high when comp_dv_en goes high + phcomp_wren_d0 <= (~r_gb_dv_en || r_double_write || wm_found) && (r_indv || comp_dv_en_sync) || phcomp_wren_d0; // Indv: 1, Bonding: goes high and stays high when comp_dv_en goes high + phcomp_wren_d1 <= phcomp_wren_d0; +// phcomp_wren_d2 <= phcomp_wren_d1; + end +end + +// In 2x1x with GB mode, use pld_tx_fabric_data_in[79] as kick-start signal on LW +//assign phcomp_wren = phcomp_wren_d2; +//assign phcomp_wren = phcomp_wren_d2 && (~r_gb_dv_en || ~r_double_write || data_valid_in); +assign phcomp_wren = phcomp_wren_d1; + +// phcomp_wren Synchronizer + cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (4), + .VID (1) + ) + cdclib_bitsync2_phcomp_wren + ( + .clk (rd_clk), + .rst_n (rd_rst_n), + .data_in (phcomp_wren), + .data_out (phcomp_wren_sync2) + ); + +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + phcomp_wren_sync3 <= 1'b0; + phcomp_wren_sync4 <= 1'b0; + phcomp_wren_sync5 <= 1'b0; + phcomp_wren_sync6 <= 1'b0; + phcomp_wren_sync7 <= 1'b0; + phcomp_wren_sync8 <= 1'b0; + phcomp_wren_sync9 <= 1'b0; + end + else if (fifo_srst_n_rd_clk == 1'b0) begin + phcomp_wren_sync3 <= 1'b0; + phcomp_wren_sync4 <= 1'b0; + phcomp_wren_sync5 <= 1'b0; + phcomp_wren_sync6 <= 1'b0; + phcomp_wren_sync7 <= 1'b0; + phcomp_wren_sync8 <= 1'b0; + phcomp_wren_sync9 <= 1'b0; + end + else begin + phcomp_wren_sync3 <= phcomp_wren_sync2; + phcomp_wren_sync4 <= phcomp_wren_sync3; + phcomp_wren_sync5 <= phcomp_wren_sync4; + phcomp_wren_sync6 <= phcomp_wren_sync5; + phcomp_wren_sync7 <= phcomp_wren_sync6; + phcomp_wren_sync8 <= phcomp_wren_sync7; + phcomp_wren_sync9 <= phcomp_wren_sync8; + end +end + +// Read Enable +///* Temp hack for simulation debug +assign phcomp_wren_sync = (r_phcomp_rd_delay == 3'b010) ? phcomp_wren_sync2 : + (r_phcomp_rd_delay == 3'b011) ? phcomp_wren_sync3 : + (r_phcomp_rd_delay == 3'b100) ? phcomp_wren_sync4 : + (r_phcomp_rd_delay == 3'b101) ? phcomp_wren_sync5 : + (r_phcomp_rd_delay == 3'b110) ? phcomp_wren_sync6 : + (r_phcomp_rd_delay == 3'b111) ? phcomp_wren_sync7 : + (r_phcomp_rd_delay == 3'b000) ? phcomp_wren_sync8 : phcomp_wren_sync9; + +//assign phcomp_wren_sync = phcomp_wren_sync3; // To be removed + +// assign phcomp_rden = phcomp_wren_sync; +assign phcomp_rden = (r_gb_dv_en && ~r_indv) ? phcomp_rden_gb_bond : phcomp_wren_sync; + +// Phase comp mode, FIFO read enable signal asserts when data_valid_raw is high +assign phcomp_rden_int = phcomp_rden & (data_valid_raw || ~r_gb_dv_en); + +assign comp_rden_en_int = comp_rden_en & (data_valid_raw || ~r_gb_dv_en); + +//******************************************************************** +// READ Valid generation +//******************************************************************** + +// Testbus +assign testbus1 = {9'd0, fifo_srst_n_wr_clk, wr_addr_msb, wr_pempty, wr_empty, phcomp_wren, comp_wren_en, wr_numdata[3:0], wr_en_int2}; +assign testbus2 = {4'd0, fifo_srst_n_rd_clk, fifo_ready, rd_addr_msb, rd_empty, rd_pempty, rd_full, data_valid_raw, rd_numdata[3:0], rd_en_int2, comp_dv_en, comp_rden_en, phcomp_rden, data_valid_out}; + + +// Output flag +assign fifo_pempty = r_pempty_type ? wr_pempty : rd_pempty_stretch; +assign fifo_pfull = r_pfull_type ? wr_pfull : rd_pfull_stretch; +assign fifo_empty = r_empty_type ? wr_empty : rd_empty_stretch; +assign fifo_full = r_full_type ? wr_full : rd_full_stretch; + +// G3 switching/reset logic + +// Sync to write/read clock domain + cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (4), + .VID (1) + ) + cdclib_bitsync2_asn_srst_n_wr_clk + ( + .clk (wr_clk), + .rst_n (wr_rst_n), + .data_in (asn_fifo_srst_n), + .data_out (asn_fifo_srst_n_wr_clk) + ); + + cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (4), + .VID (1) + ) + cdclib_bitsync2_asn_srst_n_rd_clk + ( + .clk (rd_clk), + .rst_n (rd_rst_n), + .data_in (asn_fifo_srst_n), + .data_out (asn_fifo_srst_n_rd_clk) + ); + + cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (4), + .VID (1) + ) + cdclib_bitsync2_asn_fifo_hold + ( + .clk (rd_clk), + .rst_n (rd_rst_n), + .data_in (asn_fifo_hold), + .data_out (asn_fifo_hold_sync) + ); + +assign asn_fifo_srst_n = ~asn_fifo_srst; + +// Combine with bond signal neg edge detect +assign fifo_srst_n_rd_clk = asn_fifo_srst_n_rd_clk && ~compin_sel_rden_neg_edge; +assign fifo_srst_n_wr_clk = asn_fifo_srst_n_wr_clk && ~compin_sel_wren_neg_edge; + +//assign double_write_int = asn_gen3_sel || r_double_write ? 1'b1: 1'b0; +assign double_write_int = r_double_write; + +// Latency adjust + cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (5), + .VID (1) + ) + cdclib_bitsync2_wr_adj + ( + .clk (wr_clk), + .rst_n (wr_rst_n), + .data_in (fifo_latency_adj), + .data_out (fifo_latency_adj_wr_sync) + ); + + cdclib_bitsync2 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (5), + .VID (1) + ) + cdclib_bitsync2_rd_adj + ( + .clk (rd_clk), + .rst_n (rd_rst_n), + .data_in (fifo_latency_adj), + .data_out (fifo_latency_adj_rd_sync) + ); + +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + fifo_latency_adj_rd_sync_d0 <= 1'b0; + fifo_latency_adj_rd_sync_d1 <= 1'b0; + end + else if (fifo_srst_n_rd_clk == 1'b0) begin + fifo_latency_adj_rd_sync_d0 <= 1'b0; + fifo_latency_adj_rd_sync_d1 <= 1'b0; + end + else begin + fifo_latency_adj_rd_sync_d0 <= fifo_latency_adj_rd_sync; + fifo_latency_adj_rd_sync_d1 <= fifo_latency_adj_rd_sync_d0; + end +end + +assign fifo_latency_adj_rd_pulse = r_rd_adj_en && (r_double_write ? fifo_latency_adj_rd_sync && (~fifo_latency_adj_rd_sync_d0 || ~fifo_latency_adj_rd_sync_d1) : fifo_latency_adj_rd_sync && ~fifo_latency_adj_rd_sync_d0); + +always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + fifo_latency_adj_wr_sync_d0 <= 1'b0; + end + else if (fifo_srst_n_wr_clk == 1'b0) begin + fifo_latency_adj_wr_sync_d0 <= 1'b0; + end + else begin + fifo_latency_adj_wr_sync_d0 <= fifo_latency_adj_wr_sync; + end +end + +assign fifo_latency_adj_wr_pulse = r_wr_adj_en && (fifo_latency_adj_wr_sync && ~fifo_latency_adj_wr_sync_d0); + +assign wr_en_int2 = wr_en_int && ~ fifo_latency_adj_wr_pulse; +//assign wr_en_int2 = wr_en_int && ~ fifo_latency_adj_wr_pulse && ~first_write_uw; +assign rd_en_int2 = rd_en_int && ~ fifo_latency_adj_rd_pulse; + + +always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + first_write <= 1'b1; + end + else if (wr_en_int) begin + first_write <= 1'b0; + end +end + +// To be removed +//always @(negedge wr_rst_n or posedge wr_clk) begin +// if (wr_rst_n == 1'b0) begin +// wait_count <= 'd0; +// end +// else begin +// wait_count <= wait_count + 'd1; +// end +//end + +// Drop first word if it is UW for 2x1x mode +// assign first_write_uw = wr_en_int & first_write & r_gb_dv_en & ~r_double_write & pld_tx_fabric_data_in[39]; + +// Store last WM bit, so WM can be inseted correctly during DV = 0 for non 1-1 GB mode +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + insert_wm <= 1'b0; + end + else if (~start_read) begin + insert_wm <= 1'b0; + end + else if (data_valid_out) begin + insert_wm <= data_out[39]; + end + else begin + insert_wm <= ~insert_wm; + end +end + +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + start_read <= 1'b0; + end + else if (fifo_srst_n_rd_clk == 1'b0) begin + start_read <= 1'b0; + end + else if (rd_en_int) begin + start_read <= 1'b1; + end +end + +//assign fifo_ready = (comp_rden_en_int && (~r_gb_dv_en || r_double_write)) || (comp_dv_en_reg && (r_gb_dv_en && ~r_double_write)) || r_indv || ~phcomp_mode; +//assign fifo_ready_int = comp_rden_en_int || r_indv || ~phcomp_mode; +//assign fifo_ready_int = comp_rden_en || r_indv || ~phcomp_mode; +assign fifo_ready_int = start_read || ~phcomp_mode; + +always @ (posedge rd_clk or negedge rd_rst_n) begin + if (~rd_rst_n) begin + fifo_ready <= 1'b0; + end + else begin + fifo_ready <= fifo_ready_int; + end +end + +//WM bit detect +always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + wm_bit <= 1'b0; + wm_bit_d1 <= 1'b0; + wm_bit_d2 <= 1'b0; + wm_bit_d3 <= 1'b0; + wm_bit_d4 <= 1'b0; + wm_bit_d5 <= 1'b0; + end + else if (wr_srst_n == 1'b0) begin + wm_bit <= 1'b0; + wm_bit_d1 <= 1'b0; + wm_bit_d2 <= 1'b0; + wm_bit_d3 <= 1'b0; + wm_bit_d4 <= 1'b0; + wm_bit_d5 <= 1'b0; + end + else begin +// wm_bit <= pld_tx_fabric_data_in[39]; +// Detect after DV is up and running in bonding mode +// wm_bit <= pld_tx_fabric_data_in[39] && comp_dv_en_sync; + wm_bit <= pld_tx_fabric_data_in[39] && (comp_dv_en_sync || r_indv); + wm_bit_d1 <= wm_bit; + wm_bit_d2 <= wm_bit_d1; + wm_bit_d3 <= wm_bit_d2; + wm_bit_d4 <= wm_bit_d3; + wm_bit_d5 <= wm_bit_d4; + end +end + +always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + wm_found_lt <= 1'b0; + end + else if (wr_srst_n == 1'b0) begin + wm_found_lt <= 1'b0; + end + else begin + wm_found_lt <= wm_found_int || wm_found_lt; + end +end + +assign wm_found_int = wm_bit && ~wm_bit_d1 && wm_bit_d2 && ~wm_bit_d3 && wm_bit_d4 && ~wm_bit_d5; + +assign wm_found = wm_found_int || wm_found_lt; + +// Bonding signal falling edge detect for PIPE/HIP speed change reset + +always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) + begin + compin_sel_wren_reg <= 1'b0; + compin_sel_wren_reg2 <= 1'b0; + end + else + begin + compin_sel_wren_reg <= compin_sel_wren; + compin_sel_wren_reg2 <= compin_sel_wren_reg; + end + end // always @ (negedge rst_n or posedge clk) + +//assign compin_sel_wren_neg_edge = ~compin_sel_wren && compin_sel_wren_reg; +// Register cause compin_sel is timing-critical +assign compin_sel_wren_neg_edge = ~compin_sel_wren_reg && compin_sel_wren_reg2 && ~r_indv; + +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) + begin + compin_sel_rden_reg <= 1'b0; + compin_sel_rden_reg2 <= 1'b0; + end + else + begin + compin_sel_rden_reg <= compin_sel_rden; + compin_sel_rden_reg2 <= compin_sel_rden_reg; + end + end // always @ (negedge rst_n or posedge clk) + +assign compin_sel_rden_neg_edge = ~compin_sel_rden_reg && compin_sel_rden_reg2 && ~r_indv; + +// Delay rd_ptr_msb to account for FIFO ouput being registered +always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) + begin + rd_addr_msb_reg <= 1'b0; + ps_rd_addr_msb_reg <= 1'b0; + ps_dw_rd_addr_msb_reg <= 1'b0; + ps_dw_rd_addr_msb_reg2 <= 1'b0; + end + else + begin + rd_addr_msb_reg <= rd_addr_msb; + ps_rd_addr_msb_reg <= ps_rd_addr_msb; + ps_dw_rd_addr_msb_reg <= ps_dw_rd_addr_msb; + ps_dw_rd_addr_msb_reg2 <= ps_dw_rd_addr_msb_reg; + end + end // always @ (negedge rst_n or posedge clk) + + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_fifo_pointers.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_fifo_pointers.v new file mode 100644 index 0000000..86d319e --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_fifo_pointers.v @@ -0,0 +1,257 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_tx_datapath_fifo_pointers + #( + parameter AWIDTH = 'd4, // Address width + parameter PS_AWIDTH = 'd3, // PS Address width + parameter DEPTH = 'd16, // FIFO Depth + parameter PS_DEPTH = 'd8 + ) +( + input wire wr_clk, // Write Domain Clock + input wire wr_rst_n, // Write Domain Reset + input wire wr_srst_n, // Write Domain Active low Reset Synchronous + input wire rd_clk, // Read Domain Clock + input wire rd_rst_n, // Read Domain Reset + input wire rd_srst_n, // Read Domain Active low Reset Synchronous + input wire wr_en, // Write Data Enable + input wire rd_en, // Read Data Enable + input wire rd_empty, + input wire wr_full, + input wire r_stop_read, // Disable/enable reading when FIFO is empty + input wire r_stop_write, // Disable/enable writing when FIFO is full + input wire r_double_write, // FIFO double read mode + input wire [2:0] r_fifo_power_mode, // FIFO double write mode + + + output wire [DEPTH-1:0] wr_ptr_one_hot, // Write Pointer + output wire [DEPTH-1:0] rd_ptr_one_hot, // Read Pointer + output wire [AWIDTH-1:0] wr_ptr_bin, // Write Pointer + output wire [AWIDTH-1:0] rd_ptr_bin, // Read Pointer + + output wire wr_addr_msb, // Write address MSB + output wire rd_addr_msb, // Read address MSB + output wire ps_wr_addr_msb, // PS Write address MSB + output wire ps_rd_addr_msb, // PS Read address MSB + output wire ps_dw_wr_addr_msb, // PS Write address MSB + output wire ps_dw_rd_addr_msb, // PS Read address MSB + + output wire [AWIDTH-1:0] wr_numdata, + output wire [AWIDTH-1:0] rd_numdata + +); + //******************************************************************** + // Define Parameters + //******************************************************************** + + //******************************************************************** + // Define variables + //******************************************************************** + reg [AWIDTH:0] wr_addr_bin; + reg [AWIDTH:0] rd_addr_bin; + + reg [AWIDTH:0] wr_addr_gry; + reg [AWIDTH:0] rd_addr_gry; + + // Wires + wire [AWIDTH-1:0] wr_addr_mem; + wire [AWIDTH-1:0] rd_addr_mem; + + wire [AWIDTH:0] wr_addr_bin_nxt; + wire [AWIDTH:0] rd_addr_bin_nxt; + wire [AWIDTH:0] wr_addr_gry_nxt; + wire [AWIDTH:0] wr_addr_gry_nxt_dw; + wire [AWIDTH:0] rd_addr_gry_nxt; + wire [AWIDTH:0] wr_addr_bin_sync; + wire [AWIDTH:0] rd_addr_bin_sync; + wire [AWIDTH:0] wr_addr_gry_sync; + wire [AWIDTH:0] rd_addr_gry_sync; + + + // Convert pointer to onehot + assign rd_ptr_one_hot = ~r_fifo_power_mode[1] ? {{DEPTH-PS_DEPTH{1'b0}}, bin_to_onehot_ps(rd_addr_mem[PS_AWIDTH-1:0])} : + ~r_fifo_power_mode[2] ? {{DEPTH-2*PS_DEPTH{1'b0}}, bin_to_onehot_2ps(rd_addr_mem[PS_AWIDTH:0])} : + bin_to_onehot(rd_addr_mem); + assign wr_ptr_one_hot = ~r_fifo_power_mode[1] ? {{DEPTH-PS_DEPTH{1'b0}}, bin_to_onehot_ps(wr_addr_mem[PS_AWIDTH-1:0])} : + ~r_fifo_power_mode[2] ? {{DEPTH-2*PS_DEPTH{1'b0}}, bin_to_onehot_2ps(wr_addr_mem[PS_AWIDTH:0])} : + bin_to_onehot(wr_addr_mem); + + assign wr_addr_msb = wr_addr_bin[AWIDTH]; + assign rd_addr_msb = rd_addr_bin[AWIDTH]; + + assign ps_wr_addr_msb = wr_addr_bin[PS_AWIDTH]; + assign ps_rd_addr_msb = rd_addr_bin[PS_AWIDTH]; + + assign ps_dw_wr_addr_msb = wr_addr_bin[PS_AWIDTH+1]; + assign ps_dw_rd_addr_msb = rd_addr_bin[PS_AWIDTH+1]; + + assign rd_ptr_bin = rd_addr_bin[AWIDTH-1:0]; + assign wr_ptr_bin = wr_addr_bin[AWIDTH-1:0]; + + //******************************************************************** + // WRITE CLOCK DOMAIN: Generate WRITE Address & WRITE Address GREY + //******************************************************************** + // Memory write-address pointer + assign wr_addr_mem = wr_addr_bin[AWIDTH-1:0]; + always @(negedge wr_rst_n or posedge wr_clk) begin + if (wr_rst_n == 1'b0) begin + wr_addr_bin <= 'd0; + wr_addr_gry <= 'd0; + end + else if (wr_srst_n == 1'b0) begin + wr_addr_bin <= 'd0; + wr_addr_gry <= 'd0; + end + else begin + wr_addr_bin <= wr_addr_bin_nxt; + wr_addr_gry <= !r_double_write ? wr_addr_gry_nxt : wr_addr_gry_nxt_dw; + end + end + // Binary Next Write Address + // Add option to allow write when full +// assign wr_addr_bin_nxt = wr_addr_bin + (wr_en & ~wr_full); + assign wr_addr_bin_nxt = wr_addr_bin + (!r_double_write ? (r_stop_write ? (wr_en & ~wr_full) : wr_en) : + (r_stop_write ? 2*(wr_en & ~wr_full) : 2*wr_en)); + + // Grey Next Write Address + assign wr_addr_gry_nxt = ((wr_addr_bin_nxt>>1'b1) ^ wr_addr_bin_nxt); + assign wr_addr_gry_nxt_dw = {((wr_addr_bin_nxt[AWIDTH:1]>>1'b1) ^ wr_addr_bin_nxt[AWIDTH:1]),1'b0}; + + //******************************************************************** + // WRITE CLOCK DOMAIN: Synchronize Read Address to Write Clock + //******************************************************************** + cdclib_bitsync2 + #( + .DWIDTH (AWIDTH+1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (1), + .VID (1) + ) + cdclib_bitsync2_wr + ( + .clk (wr_clk), + .rst_n (wr_rst_n), + .data_in (rd_addr_gry), + .data_out (rd_addr_gry_sync) + ); + + + assign rd_addr_bin_sync = greytobin(rd_addr_gry_sync); + assign wr_numdata = (wr_addr_bin_nxt - rd_addr_bin_sync); + + //******************************************************************** + // READ CLOCK DOMAIN: Generate READ Address & READ Address GREY + //******************************************************************** + // Memory read-address pointer + assign rd_addr_mem = rd_addr_bin[AWIDTH-1:0]; + + always @(negedge rd_rst_n or posedge rd_clk) begin + if (rd_rst_n == 1'b0) begin + rd_addr_bin <= 'd0; + rd_addr_gry <= 'd0; + end + else if (rd_srst_n == 1'b0) begin + rd_addr_bin <= 'd0; + rd_addr_gry <= 'd0; + end + else begin + rd_addr_bin <= rd_addr_bin_nxt; + rd_addr_gry <= rd_addr_gry_nxt; + end + end + // Binary Next Read Address + // Add option to allow read when empty +// assign rd_addr_bin_nxt = rd_addr_bin + (rd_en & ~rd_empty); + assign rd_addr_bin_nxt = rd_addr_bin + (r_stop_read ? (rd_en & ~rd_empty) : rd_en); + + // Grey Next Read Address + assign rd_addr_gry_nxt = ((rd_addr_bin_nxt>>1'b1) ^ rd_addr_bin_nxt); + + //******************************************************************** + // READ CLOCK DOMAIN: Synchronize Write Address to Read Clock + //******************************************************************** + cdclib_bitsync2 + #( + .DWIDTH (AWIDTH+1), // Sync Data input + .RESET_VAL (0), // Reset Value + .CLK_FREQ_MHZ(1000), + .TOGGLE_TYPE (1), + .VID (1) + ) + cdclib_bitsync2_rd + ( + .clk (rd_clk), + .rst_n (rd_rst_n), + .data_in (wr_addr_gry), + .data_out (wr_addr_gry_sync) + ); + + assign wr_addr_bin_sync = !r_double_write ? greytobin(wr_addr_gry_sync) : greytobin_dw(wr_addr_gry_sync); + assign rd_numdata = (wr_addr_bin_sync - rd_addr_bin_nxt); + + //******************************************************************** + // Function to convert Grey to Binary + //******************************************************************** + function [AWIDTH:0] greytobin; + input [AWIDTH:0] data_in; // Gray pointers + integer i; + begin + for (i='d0; i<=AWIDTH; i=i+1'b1) begin + greytobin[i] = ^(data_in>> i); + end + end + endfunction + + function [AWIDTH:0] greytobin_dw; + input [AWIDTH:0] data_in; // Gray pointers + integer i; + begin + greytobin_dw[0] = 1'b0; + for (i='d1; i<=AWIDTH; i=i+1'b1) begin + greytobin_dw[i] = ^(data_in>> i); + end + end + endfunction + + function [(1< MB, 1b rsvd, start_dv, ctrl[8:4], data[63:32], MB, 2-b rsvd, dv, ctrl[3:0], data[31:0] +// teng_2_aib_map = {1'b1, 1'b0, teng_in[63:26], 1'b0, teng_in[74], 2'b00,teng_in[72:64], teng_in[73],teng_in[25:0]}; + teng_2_aib_map = {1'b1, 1'b0, teng_in[74], teng_in[72:68], teng_in[63:32], 1'b0, 2'b00,teng_in[73], teng_in[67:64],teng_in[31:0]}; + end +endfunction + + +function [73:0] aib_2_teng_map; + input [79:0] aib_in; + begin +// aib_2_teng_map = {aib_in[26], aib_in[35:27], aib_in[77:40], aib_in[25:0]}; + aib_2_teng_map = {aib_in[36], aib_in[76:72], aib_in[35:32], aib_in[71:40], aib_in[31:0]}; + end +endfunction + + +// Data serializer +//always@(posedge clk or negedge rst_n) begin +// if (!rst_n) begin +// aib_fabric_tx_data_out <= 'd0; +// end // if (!rst_n) +// else begin +// aib_fabric_tx_data_out <= ~data_valid_2x ? aib_tx_data_2x[39:0] : aib_tx_data_2x[79:40]; +// end // else: !if(!rst_n) +//end // always@ (posedge clk or negedge rst_n) + +always @* begin + aib_fabric_tx_data_out = r_bypass_frmgen? tx_fifo_data : (~data_valid_2x ? aib_tx_data_2x[39:0] : aib_tx_data_2x[79:40]); +end + +endmodule // hd_pcs10g_frame_gen + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_pulse_stretch.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_pulse_stretch.v new file mode 100644 index 0000000..e5c3d3a --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_pulse_stretch.v @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// (C) 2009 Altera Corporation. All rights reserved. +// +//------------------------------------------------------------------------ +// File: $RCSfile: hdpldadapt_tx_datapath_pulse_stretch.v.rca $ +// Revision: $Revision: #1 $ +// Date: $Date: 2014/09/23 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ + +module hdpldadapt_tx_datapath_pulse_stretch + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire tx_frame_raw, // input to stretch + input wire burst_en_exe_raw, // input to stretch + input wire wordslip_exe_raw, // input to stretch + input wire rd_empty_raw, // input to stretch + input wire rd_pempty_raw, // input to stretch + + input wire [2:0] r_stretch_num_stages, // # stages sel + output wire tx_frame, // stretched output + output wire tx_burst_en_exe, // stretched output + output wire tx_wordslip_exe, // stretched output + output wire rd_empty_stretch, // stretched output + output wire rd_pempty_stretch // stretched output + + ); + + wire [2:0] num_stages; + + assign num_stages = r_stretch_num_stages; + + hdpldadapt_cmn_pulse_stretch + #( + .RESET_VAL (0) // Reset Value + ) hdpldadapt_cmn_pulse_stretch_tx_wordslip_exe + ( + .clk (clk), + .rst_n (rst_n), + .num_stages (num_stages), + .data_in (wordslip_exe_raw), + .data_out (tx_wordslip_exe) + ); + + hdpldadapt_cmn_pulse_stretch + #( + .RESET_VAL (0) // Reset Value + ) hdpldadapt_cmn_pulse_stretch_tx_burst_en_exe + ( + .clk (clk), + .rst_n (rst_n), + .num_stages (num_stages), + .data_in (burst_en_exe_raw), + .data_out (tx_burst_en_exe) + ); + + hdpldadapt_cmn_pulse_stretch + #( + .RESET_VAL (0) // Reset Value + ) hdpldadapt_cmn_pulse_stretch_tx_frame_raw + ( + .clk (clk), + .rst_n (rst_n), + .num_stages (num_stages), + .data_in (tx_frame_raw), + .data_out (tx_frame) + ); + +// Flag pulse-stretch + hdpldadapt_cmn_pulse_stretch + #( + .RESET_VAL (1) // Reset Value + ) hdpldadapt_cmn_pulse_stretch_rd_empty + ( + .clk (clk), + .rst_n (rst_n), + .num_stages (num_stages), + .data_in (rd_empty_raw), + .data_out (rd_empty_stretch) + ); + + hdpldadapt_cmn_pulse_stretch + #( + .RESET_VAL (1) // Reset Value + ) hdpldadapt_cmn_pulse_stretch_rd_pempty + ( + .clk (clk), + .rst_n (rst_n), + .num_stages (num_stages), + .data_in (rd_pempty_raw), + .data_out (rd_pempty_stretch) + ); + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_word_mark.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_word_mark.v new file mode 100644 index 0000000..be82adf --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_word_mark.v @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// (C) 2009 Altera Corporation. All rights reserved. +// +//------------------------------------------------------------------------ +// File: $RCSfile: hdpldiadapt_tx_datapath_cp_bond.v.rca $ +// Revision: $Revision: #2 $ +// Date: $Date: 2014/08/29 $ +//------------------------------------------------------------------------ +// Description: +// +//------------------------------------------------------------------------ + +module hdpldadapt_tx_datapath_word_mark + ( + input wire [79:0] data_in, // Data In + input wire r_wm_en, // Word mark enable + output wire [79:0] data_out // Data Out + ); + +//******************************************************************** +// Define Parameters +//******************************************************************** + + +//******************************************************************** +// Define variables +//******************************************************************** + + +//******************************************************************** +// Main logic +//******************************************************************** + +assign data_out = r_wm_en ? {1'b1, data_in[78:40], 1'b0, data_in[38:0]} : data_in; + + +endmodule diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_txclk_ctl.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_txclk_ctl.v new file mode 100644 index 0000000..7a49b02 --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_txclk_ctl.v @@ -0,0 +1,731 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_txclk_ctl +( + input wire aib_fabric_pld_pcs_tx_clk_out, + input wire aib_fabric_pma_aib_tx_clk, + input wire aib_fabric_pld_pma_clkdiv_tx_user, + //input wire aib_fabric_pld_pma_fpll_fbclkout_lc_lvpecl_to_coreclk, + //input wire [3:0] aib_fabric_pld_pma_fpll_pllcout, + input wire [3:0] aib_fabric_fpll_shared_direct_async_in, + input wire rx_clock_pld_sclk, + input wire aib_fabric_rx_sr_clk_in, + input wire aib_fabric_tx_sr_clk_in, + //input wire pld_fpll_coreclkin_rowclk, + //input wire pld_fpll_coreclkin_dcm, + //input wire pld_fpll_fbclkin_rowclk, + //input wire pld_fpll_fbclkin_dcm, + input wire pld_fpll_shared_direct_async_in_rowclk, + input wire pld_fpll_shared_direct_async_in_dcm, + input wire pld_tx_clk1_rowclk, + input wire pld_tx_clk1_dcm, + input wire pld_tx_clk2_rowclk, + input wire pld_tx_clk2_dcm, + input wire nfrzdrv_in, + input wire pr_channel_freeze_n, + input wire pld_clk_dft_sel, + //input wire r_tx_fpll_coreclkin_sel, + //input wire r_tx_fpll_fbclkin_sel, + input wire r_tx_fpll_shared_direct_async_in_sel, + input wire [1:0] r_tx_aib_clk1_sel, + input wire [1:0] r_tx_aib_clk2_sel, + input wire [1:0] r_tx_fifo_rd_clk_sel, + //input wire r_tx_fifo_wr_clk_sel, + input wire r_tx_pld_clk1_sel, + input wire r_tx_pld_clk2_sel, + input wire r_tx_fifo_rd_clk_frm_gen_scg_en, + input wire r_tx_fifo_rd_clk_scg_en, + input wire r_tx_fifo_wr_clk_scg_en, + input wire r_tx_osc_clk_scg_en, + input wire r_tx_hrdrst_rx_osc_clk_scg_en, + input wire r_tx_hip_osc_clk_scg_en, + input wire [2:0] r_tx_fifo_power_mode, + input wire r_tx_pld_clk1_delay_en, + input wire [3:0] r_tx_pld_clk1_delay_sel, + input wire r_tx_pld_clk1_inv_en, + input wire dft_adpt_aibiobsr_fastclkn, + input wire adapter_scan_mode_n, + input wire adapter_scan_shift_n, + input wire adapter_scan_shift_clk, + input wire adapter_scan_user_clk0, // 125MHz + input wire adapter_scan_user_clk1, // 250MHz + input wire adapter_scan_user_clk2, // 500MHz + input wire adapter_scan_user_clk3, // 1GHz + input wire adapter_clk_sel_n, + input wire adapter_occ_enable, + //output wire aib_fabric_pld_fpll_coreclkin, + //output wire aib_fabric_pld_fpll_fbclkin, + output wire [0:0] aib_fabric_fpll_shared_direct_async_out, + output wire aib_fabric_tx_transfer_clk, + output wire pld_pcs_tx_clk_out1_hioint, + output wire pld_pcs_tx_clk_out1_dcm, + output wire pld_pcs_tx_clk_out2_hioint, + output wire pld_pcs_tx_clk_out2_dcm, + //output wire pld_pma_fpll_fbclkout_lc_lvpecl_to_coreclk_hioint, + //output wire pld_pma_fpll_fbclkout_lc_lvpecl_to_coreclk_dcm, + //output wire [3:0] pld_pma_fpll_pllcout_hioint, + //output wire [3:0] pld_pma_fpll_pllcout_dcm, + output wire [3:0] pld_fpll_shared_direct_async_out_hioint, + output wire [3:0] pld_fpll_shared_direct_async_out_dcm, + output wire tx_clock_reset_hrdrst_rx_osc_clk, + output wire tx_clock_reset_fifo_wr_clk, + output wire tx_clock_reset_fifo_rd_clk, + output wire tx_clock_fifo_sclk, + output wire tx_clock_reset_async_rx_osc_clk, + output wire tx_clock_reset_async_tx_osc_clk, + output wire tx_clock_fifo_wr_clk, // Static clock gated + output wire q1_tx_clock_fifo_wr_clk, // Static clock gated + output wire q2_tx_clock_fifo_wr_clk, // Static clock gated + output wire q3_tx_clock_fifo_wr_clk, // Static clock gated + output wire q4_tx_clock_fifo_wr_clk, // Static clock gated + output wire q5_tx_clock_fifo_wr_clk, // Static clock gated + output wire q6_tx_clock_fifo_wr_clk, // Static clock gated + output wire tx_clock_fifo_rd_clk_frm_gen, // Static clock gated + output wire tx_clock_fifo_rd_clk, // Static clock gated + output wire tx_clock_hrdrst_rx_osc_clk, // Static clock gated + output wire tx_clock_async_rx_osc_clk, // Static clock gated + output wire tx_clock_async_tx_osc_clk, // Static clock gated + output wire tx_clock_hip_async_rx_osc_clk, // Static clock gated + output wire tx_clock_hip_async_tx_osc_clk // Static clock gated +); + + //wire adapter_scan_mode; + wire adapter_scan_shift; + wire tx_clock_dft_scg_bypass; + wire tx_clock_dft_clk_sel_n; + wire tx_clock_dft_occ_atpg_mode; + + wire frz_2one_by_nfrzdrv_or_pr_channel_freeze_n; + wire frz_2one_by_nfrzdrv; + + wire tx_clock_fpll_shared_direct_async_in_mux1; + + wire [3:0] pld_fpll_shared_direct_async_out; + wire pld_fpll_shared_direct_async_out_dcm_bit3_mux1; + wire pld_fpll_shared_direct_async_out_dcm_bit2_mux1; + wire pld_fpll_shared_direct_async_out_dcm_bit1_mux1; + wire pld_fpll_shared_direct_async_out_dcm_bit0_mux1; + + wire tx_clock_aib_clk1_hioint_dft_mux1; + wire tx_clock_aib_clk1_hioint_dft_mux2; + wire tx_clock_aib_clk1_dcm_dft_mux1; + wire tx_clock_aib_clk1_mux1; + wire tx_clock_aib_clk1_mux2; + wire tx_aib_clk1_sel1; + wire tx_aib_clk1_sel2; + + wire tx_clock_aib_clk2_hioint_dft_mux1; + wire tx_clock_aib_clk2_hioint_dft_mux2; + wire tx_clock_aib_clk2_dcm_dft_mux1; + wire tx_clock_aib_clk2_mux1; + wire tx_clock_aib_clk2_mux2; + wire tx_aib_clk2_sel1; + wire tx_aib_clk2_sel2; + + wire tx_clock_fifo_rd_clk_mux1; + wire tx_clock_fifo_rd_clk_mux2; + wire tx_clock_fifo_rd_clk_mux3; + wire tx_clock_fifo_rd_clk_occ; + wire tx_fifo_rd_clk_frm_gen_clk_en; + wire tx_fifo_rd_clk_en; + wire tx_fifo_rd_clk_sel1; + wire tx_fifo_rd_clk_sel2; + wire tx_fifo_rd_clk_sel3; + + wire tx_clock_fifo_wr_clk_mux1; + wire tx_clock_fifo_wr_clk_occ; + wire q1_tx_fifo_wr_clk_en; + wire q2_tx_fifo_wr_clk_en; + wire q3_tx_fifo_wr_clk_en; + wire q4_tx_fifo_wr_clk_en; + wire q5_tx_fifo_wr_clk_en; + wire q6_tx_fifo_wr_clk_en; + + wire tx_clock_pld_clk1_delay_mux1; + wire tx_clock_pld_clk1_delay; + wire tx_clock_pld_clk1_inv_mux1; + wire tx_clock_pld_clk1_inv; + wire tx_clock_pld_clk1_mux1; + wire tx_clock_pld_clk2_mux1; + + wire tx_clock_fifo_sclk_mux1; + wire tx_clock_fifo_sclk_occ; + + wire tx_clock_rx_osc_clk_mux1; + wire tx_clock_rx_osc_clk_occ; + wire tx_hrdrst_rx_osc_clk_en; + wire tx_hip_osc_clk_en; + wire tx_osc_clk_en; + + wire tx_clock_tx_osc_clk_mux1; + wire tx_clock_tx_osc_clk_occ; + + // DFX + //assign adapter_scan_mode = ~adapter_scan_mode_n; + assign adapter_scan_shift = ~adapter_scan_shift_n; + assign tx_clock_dft_scg_bypass = ~dft_adpt_aibiobsr_fastclkn | ~adapter_scan_mode_n; + assign tx_clock_dft_clk_sel_n = dft_adpt_aibiobsr_fastclkn & adapter_scan_mode_n; + + assign tx_clock_dft_occ_atpg_mode = ~adapter_scan_mode_n; + +////////////////// +// Clock muxing // +////////////////// + +assign frz_2one_by_nfrzdrv_or_pr_channel_freeze_n = ~(nfrzdrv_in & pr_channel_freeze_n); +assign frz_2one_by_nfrzdrv = ~(nfrzdrv_in); + +assign aib_fabric_fpll_shared_direct_async_out[0:0] = tx_clock_fpll_shared_direct_async_in_mux1; + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_fpll_shared_direct_async_in_mux1 + ( + .clk_o(tx_clock_fpll_shared_direct_async_in_mux1), + .clk_0(pld_fpll_shared_direct_async_in_rowclk), + .clk_1(pld_fpll_shared_direct_async_in_dcm), + .clk_sel(r_tx_fpll_shared_direct_async_in_sel) + ); + +assign pld_fpll_shared_direct_async_out_hioint[3:0] = pld_fpll_shared_direct_async_out[3:0]; +// ECO assign pld_fpll_shared_direct_async_out_dcm[3:0] = pld_fpll_shared_direct_async_out[3:0]; + +hdpldadapt_cmn_clkor2 hdpldadapt_cmn_clkor2_pld_fpll_shared_direct_async_out_bit3_frz + ( + .clkout(pld_fpll_shared_direct_async_out[3]), + .clk(aib_fabric_fpll_shared_direct_async_in[3]), + .en(frz_2one_by_nfrzdrv) + ); + +hdpldadapt_cmn_clkor2 hdpldadapt_cmn_clkor2_pld_fpll_shared_direct_async_out_bit2_frz + ( + .clkout(pld_fpll_shared_direct_async_out[2]), + .clk(aib_fabric_fpll_shared_direct_async_in[2]), + .en(frz_2one_by_nfrzdrv) + ); + +hdpldadapt_cmn_clkor2 hdpldadapt_cmn_clkor2_pld_fpll_shared_direct_async_out_bit1_frz + ( + .clkout(pld_fpll_shared_direct_async_out[1]), + .clk(aib_fabric_fpll_shared_direct_async_in[1]), + .en(frz_2one_by_nfrzdrv) + ); + +hdpldadapt_cmn_clkor2 hdpldadapt_cmn_clkor2_pld_fpll_shared_direct_async_out_bit0_frz + ( + .clkout(pld_fpll_shared_direct_async_out[0]), + .clk(aib_fabric_fpll_shared_direct_async_in[0]), + .en(frz_2one_by_nfrzdrv) + ); + +// ECO Start // + +hdpldadapt_cmn_clkor2 hdpldadapt_cmn_clkor2_pld_fpll_shared_direct_async_out_dcm_bit3_frz + ( + .clkout(pld_fpll_shared_direct_async_out_dcm[3]), + .clk(pld_fpll_shared_direct_async_out_dcm_bit3_mux1), + .en(frz_2one_by_nfrzdrv) + ); + +hdpldadapt_cmn_clkor2 hdpldadapt_cmn_clkor2_pld_fpll_shared_direct_async_out_dcm_bit2_frz + ( + .clkout(pld_fpll_shared_direct_async_out_dcm[2]), + .clk(pld_fpll_shared_direct_async_out_dcm_bit2_mux1), + .en(frz_2one_by_nfrzdrv) + ); + +hdpldadapt_cmn_clkor2 hdpldadapt_cmn_clkor2_pld_fpll_shared_direct_async_out_dcm_bit1_frz + ( + .clkout(pld_fpll_shared_direct_async_out_dcm[1]), + .clk(pld_fpll_shared_direct_async_out_dcm_bit1_mux1), + .en(frz_2one_by_nfrzdrv) + ); + +hdpldadapt_cmn_clkor2 hdpldadapt_cmn_clkor2_pld_fpll_shared_direct_async_out_dcm_bit0_frz + ( + .clkout(pld_fpll_shared_direct_async_out_dcm[0]), + .clk(pld_fpll_shared_direct_async_out_dcm_bit0_mux1), + .en(frz_2one_by_nfrzdrv) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_pld_fpll_shared_direct_async_out_dcm_bit3_mux1 + ( + .clk_o(pld_fpll_shared_direct_async_out_dcm_bit3_mux1), + .clk_0(adapter_scan_shift_clk), + .clk_1(aib_fabric_fpll_shared_direct_async_in[3]), + .clk_sel(adapter_scan_mode_n) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_pld_fpll_shared_direct_async_out_dcm_bit2_mux1 + ( + .clk_o(pld_fpll_shared_direct_async_out_dcm_bit2_mux1), + .clk_0(adapter_scan_shift_clk), + .clk_1(aib_fabric_fpll_shared_direct_async_in[2]), + .clk_sel(adapter_scan_mode_n) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_pld_fpll_shared_direct_async_out_dcm_bit1_mux1 + ( + .clk_o(pld_fpll_shared_direct_async_out_dcm_bit1_mux1), + .clk_0(adapter_scan_shift_clk), + .clk_1(aib_fabric_fpll_shared_direct_async_in[1]), + .clk_sel(adapter_scan_mode_n) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_pld_fpll_shared_direct_async_out_dcm_bit0_mux1 + ( + .clk_o(pld_fpll_shared_direct_async_out_dcm_bit0_mux1), + .clk_0(adapter_scan_shift_clk), + .clk_1(aib_fabric_fpll_shared_direct_async_in[0]), + .clk_sel(adapter_scan_mode_n) + ); + +// ECO End // + +/* +hdpldadapt_cmn_clkor2 hdpldadapt_cmn_clkor2_pld_fpll_shared_direct_async_out_hioint_bit3_frz + ( + .clkout(pld_fpll_shared_direct_async_out_hioint[3]), + .clk(aib_fabric_fpll_shared_direct_async_in[3]), + .en(frz_2one_by_nfrzdrv_or_pr_channel_freeze_n) + ); + +hdpldadapt_cmn_clkor2 hdpldadapt_cmn_clkor2_pld_fpll_shared_direct_async_out_dcm_bit3_frz + ( + .clkout(pld_fpll_shared_direct_async_out_dcm[3]), + .clk(aib_fabric_fpll_shared_direct_async_in[3]), + .en(frz_2one_by_nfrzdrv) + ); +*/ + +hdpldadapt_cmn_clkor2 hdpldadapt_cmn_clkor2_pld_pcs_tx_clk_out1_hioint_frz + ( + .clkout(pld_pcs_tx_clk_out1_hioint), + .clk(tx_clock_aib_clk1_hioint_dft_mux1), + .en(frz_2one_by_nfrzdrv_or_pr_channel_freeze_n) + ); + +hdpldadapt_cmn_clkor2 hdpldadapt_cmn_clkor2_pld_pcs_tx_clk_out1_dcm_frz + ( + .clkout(pld_pcs_tx_clk_out1_dcm), + .clk(tx_clock_aib_clk1_dcm_dft_mux1), + .en(frz_2one_by_nfrzdrv) + ); + +hdpldadapt_cmn_clkor2 hdpldadapt_cmn_clkor2_pld_pcs_tx_clk_out2_hioint_frz + ( + .clkout(pld_pcs_tx_clk_out2_hioint), + .clk(tx_clock_aib_clk2_hioint_dft_mux1), + .en(frz_2one_by_nfrzdrv_or_pr_channel_freeze_n) + ); + +hdpldadapt_cmn_clkor2 hdpldadapt_cmn_clkor2_pld_pcs_tx_clk_out2_dcm_frz + ( + .clkout(pld_pcs_tx_clk_out2_dcm), + .clk(tx_clock_aib_clk2_dcm_dft_mux1), + .en(frz_2one_by_nfrzdrv) + ); + +// ECO Start // + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_clock_aib_clk1_hioint_dft_mux1 + ( + .clk_o(tx_clock_aib_clk1_hioint_dft_mux1), + .clk_0(tx_clock_aib_clk1_hioint_dft_mux2), + .clk_1(tx_clock_aib_clk1_mux1), + .clk_sel(adapter_scan_mode_n) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_clock_aib_clk1_hioint_dft_mux2 + ( + .clk_o(tx_clock_aib_clk1_hioint_dft_mux2), + .clk_0(tx_clock_pld_clk1_delay_mux1), + .clk_1(tx_clock_aib_clk1_mux1), + .clk_sel(pld_clk_dft_sel) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_clock_aib_clk1_dcm_dft_mux1 + ( + .clk_o(tx_clock_aib_clk1_dcm_dft_mux1), + .clk_0(adapter_scan_shift_clk), + .clk_1(tx_clock_aib_clk1_mux1), + .clk_sel(adapter_scan_mode_n) + ); + +// ECO End // + +assign tx_aib_clk1_sel1 = (r_tx_aib_clk1_sel == 2'b10); +assign tx_aib_clk1_sel2 = (r_tx_aib_clk1_sel == 2'b01); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_aib_clk1_mux1 + ( + .clk_o(tx_clock_aib_clk1_mux1), + .clk_0(tx_clock_aib_clk1_mux2), + .clk_1(aib_fabric_pld_pma_clkdiv_tx_user), + .clk_sel(tx_aib_clk1_sel1) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_aib_clk1_mux2 + ( + .clk_o(tx_clock_aib_clk1_mux2), + .clk_0(aib_fabric_pld_pcs_tx_clk_out), + .clk_1(aib_fabric_pma_aib_tx_clk), + .clk_sel(tx_aib_clk1_sel2) + ); + +// ECO Start // + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_clock_aib_clk2_hioint_dft_mux1 + ( + .clk_o(tx_clock_aib_clk2_hioint_dft_mux1), + .clk_0(tx_clock_aib_clk2_hioint_dft_mux2), + .clk_1(tx_clock_aib_clk2_mux1), + .clk_sel(adapter_scan_mode_n) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_clock_aib_clk2_hioint_dft_mux2 + ( + .clk_o(tx_clock_aib_clk2_hioint_dft_mux2), + .clk_0(tx_clock_pld_clk2_mux1), + .clk_1(tx_clock_aib_clk2_mux1), + .clk_sel(pld_clk_dft_sel) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_clock_aib_clk2_dcm_dft_mux1 + ( + .clk_o(tx_clock_aib_clk2_dcm_dft_mux1), + .clk_0(adapter_scan_shift_clk), + .clk_1(tx_clock_aib_clk2_mux1), + .clk_sel(adapter_scan_mode_n) + ); + +// ECO End // + +assign tx_aib_clk2_sel1 = (r_tx_aib_clk2_sel == 2'b10); +assign tx_aib_clk2_sel2 = (r_tx_aib_clk2_sel == 2'b01); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_aib_clk2_mux1 + ( + .clk_o(tx_clock_aib_clk2_mux1), + .clk_0(tx_clock_aib_clk2_mux2), + .clk_1(aib_fabric_pld_pma_clkdiv_tx_user), + .clk_sel(tx_aib_clk2_sel1) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_aib_clk2_mux2 + ( + .clk_o(tx_clock_aib_clk2_mux2), + .clk_0(aib_fabric_pld_pcs_tx_clk_out), + .clk_1(aib_fabric_pma_aib_tx_clk), + .clk_sel(tx_aib_clk2_sel2) + ); + +////////// FIFO Read Clock ////////// + +assign aib_fabric_tx_transfer_clk = tx_clock_fifo_rd_clk_mux1; // Should this be on separate clock source? + +assign tx_clock_reset_fifo_rd_clk = tx_clock_fifo_rd_clk_mux1; + +assign tx_fifo_rd_clk_frm_gen_clk_en = tx_clock_dft_scg_bypass | ~r_tx_fifo_rd_clk_frm_gen_scg_en; +assign tx_fifo_rd_clk_en = tx_clock_dft_scg_bypass | ~r_tx_fifo_rd_clk_scg_en; + +hdpldadapt_cmn_clkand2 hdpldadapt_cmn_clkand2_tx_fifo_rd_clk_frm_gen_scg + ( + .clkout(tx_clock_fifo_rd_clk_frm_gen), + .clk(tx_clock_fifo_rd_clk_mux1), + .en(tx_fifo_rd_clk_frm_gen_clk_en) + ); + +hdpldadapt_cmn_clkand2 hdpldadapt_cmn_clkand2_tx_fifo_rd_clk_scg + ( + .clkout(tx_clock_fifo_rd_clk), + .clk(tx_clock_fifo_rd_clk_mux1), + .en(tx_fifo_rd_clk_en) + ); + +assign tx_fifo_rd_clk_sel1 = tx_clock_dft_clk_sel_n && (r_tx_fifo_rd_clk_sel == 2'b00); +assign tx_fifo_rd_clk_sel2 = tx_clock_dft_clk_sel_n && (r_tx_fifo_rd_clk_sel == 2'b01); +assign tx_fifo_rd_clk_sel3 = tx_clock_dft_clk_sel_n && (r_tx_fifo_rd_clk_sel == 2'b10); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_fifo_rd_clk_mux1 + ( + .clk_o(tx_clock_fifo_rd_clk_mux1), + .clk_0(tx_clock_fifo_rd_clk_mux2), + .clk_1(aib_fabric_pma_aib_tx_clk), + .clk_sel(tx_fifo_rd_clk_sel1) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_fifo_rd_clk_mux2 + ( + .clk_o(tx_clock_fifo_rd_clk_mux2), + .clk_0(tx_clock_fifo_rd_clk_mux3), + .clk_1(tx_clock_pld_clk1_delay_mux1), + .clk_sel(tx_fifo_rd_clk_sel2) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_fifo_rd_clk_mux3 + ( + .clk_o(tx_clock_fifo_rd_clk_mux3), + .clk_0(tx_clock_fifo_rd_clk_occ), + .clk_1(tx_clock_pld_clk2_mux1), + .clk_sel(tx_fifo_rd_clk_sel3) + ); + +hdpldadapt_cmn_dft_clock_controller + #( + .CONTROL_REGISTER_PRESENT(1) + ) hdpldadapt_cmn_dft_clock_controller_tx_fifo_rd_clk_occ1 + ( + .user_clk(adapter_scan_user_clk3), //User clock + .test_clk(adapter_scan_shift_clk), //Test clock + .rst_n(1'b0), //Reset (active low) + .clk_sel_n(adapter_clk_sel_n), //Mux sel between user or test clock, Active low + .scan_enable(adapter_scan_shift), //Scan enable control signal, Active high in IP, Active low in top level + .occ_enable(adapter_occ_enable), //Control signal to enable OCC, Active high in IP, Active low in top level + .atpg_mode(tx_clock_dft_occ_atpg_mode), //Control signal for test mode, Active high in IP, Active low in top level + .out_clk(tx_clock_fifo_rd_clk_occ) //Output clock + ); + + +////////// FIFO Write Clock ////////// + +assign tx_clock_fifo_wr_clk = q1_tx_clock_fifo_wr_clk; // Should this be on separate clock source? +assign tx_clock_reset_fifo_wr_clk = tx_clock_fifo_wr_clk_mux1; + +assign q1_tx_fifo_wr_clk_en = tx_clock_dft_scg_bypass | ~r_tx_fifo_wr_clk_scg_en; +assign q2_tx_fifo_wr_clk_en = tx_clock_dft_scg_bypass | (~r_tx_fifo_wr_clk_scg_en & r_tx_fifo_power_mode[0]); +assign q3_tx_fifo_wr_clk_en = tx_clock_dft_scg_bypass | (~r_tx_fifo_wr_clk_scg_en & r_tx_fifo_power_mode[1]); +assign q4_tx_fifo_wr_clk_en = tx_clock_dft_scg_bypass | (~r_tx_fifo_wr_clk_scg_en & r_tx_fifo_power_mode[1] & r_tx_fifo_power_mode[0]); +assign q5_tx_fifo_wr_clk_en = tx_clock_dft_scg_bypass | (~r_tx_fifo_wr_clk_scg_en & r_tx_fifo_power_mode[2] & r_tx_fifo_power_mode[1]); +assign q6_tx_fifo_wr_clk_en = tx_clock_dft_scg_bypass | (~r_tx_fifo_wr_clk_scg_en & r_tx_fifo_power_mode[2] & r_tx_fifo_power_mode[1] & r_tx_fifo_power_mode[0]); + +hdpldadapt_cmn_clkand2 hdpldadapt_cmn_clkand2_q1_tx_fifo_wr_clk_scg + ( + .clkout(q1_tx_clock_fifo_wr_clk), + .clk(tx_clock_fifo_wr_clk_mux1), + .en(q1_tx_fifo_wr_clk_en) + ); + +hdpldadapt_cmn_clkand2 hdpldadapt_cmn_clkand2_q2_tx_fifo_wr_clk_scg + ( + .clkout(q2_tx_clock_fifo_wr_clk), + .clk(tx_clock_fifo_wr_clk_mux1), + .en(q2_tx_fifo_wr_clk_en) + ); + +hdpldadapt_cmn_clkand2 hdpldadapt_cmn_clkand2_q3_tx_fifo_wr_clk_scg + ( + .clkout(q3_tx_clock_fifo_wr_clk), + .clk(tx_clock_fifo_wr_clk_mux1), + .en(q3_tx_fifo_wr_clk_en) + ); + +hdpldadapt_cmn_clkand2 hdpldadapt_cmn_clkand2_q4_tx_fifo_wr_clk_scg + ( + .clkout(q4_tx_clock_fifo_wr_clk), + .clk(tx_clock_fifo_wr_clk_mux1), + .en(q4_tx_fifo_wr_clk_en) + ); + +hdpldadapt_cmn_clkand2 hdpldadapt_cmn_clkand2_q5_tx_fifo_wr_clk_scg + ( + .clkout(q5_tx_clock_fifo_wr_clk), + .clk(tx_clock_fifo_wr_clk_mux1), + .en(q5_tx_fifo_wr_clk_en) + ); + +hdpldadapt_cmn_clkand2 hdpldadapt_cmn_clkand2_q6_tx_fifo_wr_clk_scg + ( + .clkout(q6_tx_clock_fifo_wr_clk), + .clk(tx_clock_fifo_wr_clk_mux1), + .en(q6_tx_fifo_wr_clk_en) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_fifo_wr_clk_mux1 + ( + .clk_o(tx_clock_fifo_wr_clk_mux1), + .clk_0(tx_clock_fifo_wr_clk_occ), + .clk_1(tx_clock_pld_clk1_delay_mux1), + .clk_sel(tx_clock_dft_clk_sel_n) + ); + +hdpldadapt_cmn_dft_clock_controller + #( + .CONTROL_REGISTER_PRESENT(1) + ) hdpldadapt_cmn_dft_clock_controller_tx_fifo_wr_clk_occ2 + ( + .user_clk(adapter_scan_user_clk3), //User clock + .test_clk(adapter_scan_shift_clk), //Test clock + .rst_n(1'b0), //Reset (active low) + .clk_sel_n(adapter_clk_sel_n), //Mux sel between user or test clock, Active low + .scan_enable(adapter_scan_shift), //Scan enable control signal, Active high in IP, Active low in top level + .occ_enable(adapter_occ_enable), //Control signal to enable OCC, Active high in IP, Active low in top level + .atpg_mode(tx_clock_dft_occ_atpg_mode), //Control signal for test mode, Active high in IP, Active low in top level + .out_clk(tx_clock_fifo_wr_clk_occ) //Output clock + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_pld_clk1_delay_mux1 + ( + .clk_o(tx_clock_pld_clk1_delay_mux1), + .clk_0(tx_clock_pld_clk1_inv_mux1), + .clk_1(tx_clock_pld_clk1_delay), + .clk_sel(r_tx_pld_clk1_delay_en) + ); + +hdpldadapt_cmn_clkdelay_map hdpldadapt_cmn_clkdelay_tx_pld_clk1 + ( + .clkout(tx_clock_pld_clk1_delay), + .r_clk_delay_sel(r_tx_pld_clk1_delay_sel), + .clk(tx_clock_pld_clk1_inv_mux1) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_pld_clk1_inv_mux1 + ( + .clk_o(tx_clock_pld_clk1_inv_mux1), + .clk_0(tx_clock_pld_clk1_mux1), + .clk_1(tx_clock_pld_clk1_inv), + .clk_sel(r_tx_pld_clk1_inv_en) + ); + +hdpldadapt_cmn_clkinv hdpldadapt_cmn_clkinv_tx_pld_clk1_inv + ( + .clkout(tx_clock_pld_clk1_inv), + .clk(tx_clock_pld_clk1_mux1) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_pld_clk1_mux1 + ( + .clk_o(tx_clock_pld_clk1_mux1), + .clk_0(pld_tx_clk1_rowclk), + .clk_1(pld_tx_clk1_dcm), + .clk_sel(r_tx_pld_clk1_sel) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_pld_clk2_mux1 + ( + .clk_o(tx_clock_pld_clk2_mux1), + .clk_0(pld_tx_clk2_rowclk), + .clk_1(pld_tx_clk2_dcm), + .clk_sel(r_tx_pld_clk2_sel) + ); + +////////// Sample Clock ////////// + +assign tx_clock_fifo_sclk = tx_clock_fifo_sclk_mux1; + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_fifo_sclk_mux1 + ( + .clk_o(tx_clock_fifo_sclk_mux1), + .clk_0(tx_clock_fifo_sclk_occ), + .clk_1(rx_clock_pld_sclk), + .clk_sel(tx_clock_dft_clk_sel_n) + ); + +hdpldadapt_cmn_dft_clock_controller + #( + .CONTROL_REGISTER_PRESENT(1) + ) hdpldadapt_cmn_dft_clock_controller_tx_fifo_sclk_occ3 + ( + .user_clk(adapter_scan_user_clk1), //User clock + .test_clk(adapter_scan_shift_clk), //Test clock + .rst_n(1'b0), //Reset (active low) + .clk_sel_n(adapter_clk_sel_n), //Mux sel between user or test clock, Active low + .scan_enable(adapter_scan_shift), //Scan enable control signal, Active high in IP, Active low in top level + .occ_enable(adapter_occ_enable), //Control signal to enable OCC, Active high in IP, Active low in top level + .atpg_mode(tx_clock_dft_occ_atpg_mode), //Control signal for test mode, Active high in IP, Active low in top level + .out_clk(tx_clock_fifo_sclk_occ) //Output clock + ); + +////////// Rx Oscillator Clock ////////// + +assign tx_clock_reset_hrdrst_rx_osc_clk = tx_clock_rx_osc_clk_mux1; +assign tx_clock_reset_async_rx_osc_clk = tx_clock_rx_osc_clk_mux1; + +assign tx_hrdrst_rx_osc_clk_en = tx_clock_dft_scg_bypass | ~r_tx_hrdrst_rx_osc_clk_scg_en; +assign tx_hip_osc_clk_en = tx_clock_dft_scg_bypass | ~r_tx_hip_osc_clk_scg_en; +assign tx_osc_clk_en = tx_clock_dft_scg_bypass | ~r_tx_osc_clk_scg_en; + +hdpldadapt_cmn_clkand2 hdpldadapt_cmn_clkand2_tx_hrdrst_rx_osc_clk_scg + ( + .clkout(tx_clock_hrdrst_rx_osc_clk), + .clk(tx_clock_rx_osc_clk_mux1), + .en(tx_hrdrst_rx_osc_clk_en) + ); + +hdpldadapt_cmn_clkand2 hdpldadapt_cmn_clkand2_tx_hip_async_rx_osc_clk_scg + ( + .clkout(tx_clock_hip_async_rx_osc_clk), + .clk(tx_clock_rx_osc_clk_mux1), + .en(tx_hip_osc_clk_en) + ); + +hdpldadapt_cmn_clkand2 hdpldadapt_cmn_clkand2_tx_async_rx_osc_clk_scg + ( + .clkout(tx_clock_async_rx_osc_clk), + .clk(tx_clock_rx_osc_clk_mux1), + .en(tx_osc_clk_en) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_rx_osc_clk_mux1 + ( + .clk_o(tx_clock_rx_osc_clk_mux1), + .clk_0(tx_clock_rx_osc_clk_occ), + .clk_1(aib_fabric_rx_sr_clk_in), + .clk_sel(tx_clock_dft_clk_sel_n) + ); + +hdpldadapt_cmn_dft_clock_controller + #( + .CONTROL_REGISTER_PRESENT(1) + ) hdpldadapt_cmn_dft_clock_controller_tx_rx_osc_clk_occ4 + ( + .user_clk(adapter_scan_user_clk3), //User clock + .test_clk(adapter_scan_shift_clk), //Test clock + .rst_n(1'b0), //Reset (active low) + .clk_sel_n(adapter_clk_sel_n), //Mux sel between user or test clock, Active low + .scan_enable(adapter_scan_shift), //Scan enable control signal, Active high in IP, Active low in top level + .occ_enable(adapter_occ_enable), //Control signal to enable OCC, Active high in IP, Active low in top level + .atpg_mode(tx_clock_dft_occ_atpg_mode), //Control signal for test mode, Active high in IP, Active low in top level + .out_clk(tx_clock_rx_osc_clk_occ) //Output clock + ); + +////////// Tx Oscillator Clock ////////// + +assign tx_clock_reset_async_tx_osc_clk = tx_clock_tx_osc_clk_mux1; + +hdpldadapt_cmn_clkand2 hdpldadapt_cmn_clkand2_tx_hip_async_tx_osc_clk_scg + ( + .clkout(tx_clock_hip_async_tx_osc_clk), + .clk(tx_clock_tx_osc_clk_mux1), + .en(tx_hip_osc_clk_en) + ); + +hdpldadapt_cmn_clkand2 hdpldadapt_cmn_clkand2_tx_async_tx_osc_clk_scg + ( + .clkout(tx_clock_async_tx_osc_clk), + .clk(tx_clock_tx_osc_clk_mux1), + .en(tx_osc_clk_en) + ); + +hdpldadapt_cmn_clkmux2 hdpldadapt_cmn_clkmux2_tx_tx_osc_clk_mux1 + ( + .clk_o(tx_clock_tx_osc_clk_mux1), + .clk_0(tx_clock_tx_osc_clk_occ), + .clk_1(aib_fabric_tx_sr_clk_in), + .clk_sel(tx_clock_dft_clk_sel_n) + ); + +hdpldadapt_cmn_dft_clock_controller + #( + .CONTROL_REGISTER_PRESENT(1) + ) hdpldadapt_cmn_dft_clock_controller_tx_tx_osc_clk_occ5 + ( + .user_clk(adapter_scan_user_clk3), //User clock + .test_clk(adapter_scan_shift_clk), //Test clock + .rst_n(1'b0), //Reset (active low) + .clk_sel_n(adapter_clk_sel_n), //Mux sel between user or test clock, Active low + .scan_enable(adapter_scan_shift), //Scan enable control signal, Active high in IP, Active low in top level + .occ_enable(adapter_occ_enable), //Control signal to enable OCC, Active high in IP, Active low in top level + .atpg_mode(tx_clock_dft_occ_atpg_mode), //Control signal for test mode, Active high in IP, Active low in top level + .out_clk(tx_clock_tx_osc_clk_occ) //Output clock + ); + +endmodule // hdpldadapt_txclk_ctl diff --git a/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_txrst_ctl.v b/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_txrst_ctl.v new file mode 100644 index 0000000..8a79c7c --- /dev/null +++ b/maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_txrst_ctl.v @@ -0,0 +1,586 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module hdpldadapt_txrst_ctl +( + input wire csr_rdy_dly_in, + input wire nfrzdrv_in, + input wire pr_channel_freeze_n, + input wire usermode_in, + input wire pld_pcs_tx_pld_rst_n, + input wire pld_adapter_tx_pld_rst_n, + //input wire pld_pma_fpll_dps_rst_n_lc_tx_bonding_rstb, + //input wire pld_pma_fpll_phase_en_lc_master_cgb_rstn, + //input wire pld_pma_fpll_lc_rstb, + input wire [1:0] pld_fpll_shared_direct_async_in, + input wire pld_pma_txpma_rstb, + input wire pld_aib_fabric_tx_dcd_cal_req, + input wire pld_fabric_tx_fifo_srst, + //input wire pld_partial_reconfig, + //input wire [4:0] aib_fabric_fpll_shared_direct_async_in, + input wire aib_fabric_tx_dcd_cal_done, + input wire bond_tx_hrdrst_ds_in_fabric_tx_dcd_cal_done, + input wire bond_tx_hrdrst_us_in_fabric_tx_dcd_cal_done, + input wire bond_tx_hrdrst_ds_in_fabric_tx_dcd_cal_req, + input wire bond_tx_hrdrst_us_in_fabric_tx_dcd_cal_req, + input wire avmm_hrdrst_fabric_osc_transfer_en, + input wire sr_hssi_tx_dcd_cal_done, + input wire sr_hssi_tx_dll_lock, + input wire sr_hssi_tx_transfer_en, + input wire rx_asn_rate_change_in_progress, + input wire rx_asn_dll_lock_en, + input wire rx_asn_fifo_hold, + input wire tx_fifo_ready, + input wire tx_clock_reset_hrdrst_rx_osc_clk, + input wire tx_clock_reset_fifo_wr_clk, + input wire tx_clock_reset_fifo_rd_clk, + input wire tx_clock_fifo_sclk, + input wire tx_clock_reset_async_rx_osc_clk, + input wire tx_clock_reset_async_tx_osc_clk, + input wire tx_clock_hrdrst_rx_osc_clk, // Static clock gated + input wire r_tx_hrdrst_rst_sm_dis, + input wire r_tx_hrdrst_dcd_cal_done_bypass, + input wire r_tx_hrdrst_user_ctl_en, + input wire [1:0] r_tx_master_sel, + input wire r_tx_dist_master_sel, + input wire r_tx_ds_last_chnl, + input wire r_tx_us_last_chnl, + input wire r_tx_bonding_dft_in_en, + input wire r_tx_bonding_dft_in_value, + input wire adapter_scan_rst_n, + input wire adapter_scan_mode_n, + //output wire [4:0] pld_fpll_shared_direct_async_out, + output wire aib_fabric_pcs_tx_pld_rst_n, + output wire aib_fabric_adapter_tx_pld_rst_n, + //output wire aib_fabric_pld_pma_fpll_dps_rst_n_lc_tx_bonding_rstb, + //output wire aib_fabric_pld_pma_fpll_phase_en_lc_master_cgb_rstn, + //output wire aib_fabric_pld_pma_fpll_lc_rstb, + output wire pld_fabric_tx_transfer_en, + output wire pld_aib_fabric_tx_dcd_cal_done, + output wire [2:1] aib_fabric_fpll_shared_direct_async_out, + output wire aib_fabric_pld_pma_txpma_rstb, + output wire aib_fabric_tx_dcd_cal_req, + output wire bond_tx_hrdrst_ds_out_fabric_tx_dcd_cal_done, + output wire bond_tx_hrdrst_us_out_fabric_tx_dcd_cal_done, + output wire bond_tx_hrdrst_ds_out_fabric_tx_dcd_cal_req, + output wire bond_tx_hrdrst_us_out_fabric_tx_dcd_cal_req, + output wire tx_hrdrst_tx_fifo_srst, + output reg tx_hrdrst_fabric_tx_dcd_cal_done, + output reg tx_hrdrst_fabric_tx_transfer_en, + output wire [19:0] tx_hrdrst_testbus, + output wire tx_reset_fifo_wr_rst_n, + output wire tx_reset_fifo_rd_rst_n, + output wire tx_reset_fifo_sclk_rst_n, + output wire tx_reset_async_rx_osc_clk_rst_n, + output wire tx_reset_async_tx_osc_clk_rst_n +); + +//******************************************************************** +// Define Parameters +//******************************************************************** + + localparam WAIT_TX_TRANSFER_REQ = 3'b000; + localparam SEND_TX_DCD_CAL_REQ = 3'b001; + localparam WAIT_REMOTE_TX_DLL_LOCK = 3'b010; + localparam WAIT_REMOTE_TX_ALIGN_DONE = 3'b011; + localparam TX_TRANSFER_EN = 3'b100; + +//******************************************************************** +//******************************************************************** + + wire frz_2one_by_nfrzdrv_or_pr_channel_freeze_n; + + wire int_pld_pcs_tx_pld_rst_n; + wire int_pld_adapter_tx_pld_rst_n; + wire int_pld_pma_txpma_rstb; + wire int_pld_aib_fabric_tx_dcd_cal_req; + + wire int_tx_rst_n; + //wire int_tx_datapath_rst_n; + wire int_tx_hrd_rst_n; + wire tx_reset_hrdrst_rx_osc_clk_rst_n; + + reg [2:0] tx_rst_sm_cs; + reg [2:0] tx_rst_sm_ns; + + reg tx_hrdrst_fabric_tx_dcd_cal_req; + wire tx_hrdrst_fabric_tx_dcd_cal_req_pre; + reg tx_hrdrst_fabric_tx_dcd_cal_req_comb; + + //reg tx_hrdrst_fabric_tx_async_rst; + //wire tx_hrdrst_fabric_tx_async_rst_pre; + wire tx_hrdrst_fabric_tx_fifo_srst_final; + reg tx_hrdrst_fabric_tx_fifo_srst; + wire tx_hrdrst_fabric_tx_fifo_srst_pre; + reg tx_hrdrst_fabric_tx_rst_comb; + + wire tx_hrdrst_fabric_tx_dcd_cal_done_pre; + reg tx_hrdrst_fabric_tx_dcd_cal_done_comb; + + wire tx_hrdrst_fabric_tx_transfer_en_pre; + reg tx_hrdrst_fabric_tx_transfer_en_comb; + + wire sync_rx_asn_rate_change_in_progress; + wire sync_rx_asn_dll_lock_en; + wire sync_rx_asn_fifo_hold; + reg sync_rx_asn_fifo_hold_reg; + reg [5:0] tx_hrdrst_speed_chg_srst_cnt; + reg tx_hrdrst_speed_chg_srst_dly; + reg tx_hrdrst_speed_chg_srst; + + wire aib_fabric_tx_dcd_cal_req_int; + wire aib_fabric_tx_dcd_cal_done_int; + wire sync_aib_fabric_tx_dcd_cal_done; + wire sync_tx_fifo_ready; + + wire bond_tx_hrdrst_ds_in_fabric_tx_dcd_cal_done_int; + wire bond_tx_hrdrst_us_in_fabric_tx_dcd_cal_done_int; + wire bond_tx_hrdrst_ds_in_fabric_tx_dcd_cal_req_int; + wire bond_tx_hrdrst_us_in_fabric_tx_dcd_cal_req_int; + + wire tx_hrdrst_fabric_tx_dcd_cal_done_chnl_down; + wire tx_hrdrst_fabric_tx_dcd_cal_done_chnl_up; + wire tx_hrdrst_fabric_tx_dcd_cal_req_final; + wire tx_hrdrst_fabric_tx_dcd_cal_req_chnl_down; + wire tx_hrdrst_fabric_tx_dcd_cal_req_chnl_up; + +//******************************************************************** +// Gate with User Mode +//******************************************************************** + assign int_pld_pcs_tx_pld_rst_n = usermode_in & pld_pcs_tx_pld_rst_n; + assign int_pld_adapter_tx_pld_rst_n = usermode_in & pld_adapter_tx_pld_rst_n; + assign int_pld_pma_txpma_rstb = usermode_in & pld_pma_txpma_rstb; + + assign int_pld_aib_fabric_tx_dcd_cal_req = usermode_in & pld_aib_fabric_tx_dcd_cal_req; + +//******************************************************************** +// Feedthrough from PLD to AIB +//******************************************************************** + assign aib_fabric_pcs_tx_pld_rst_n = int_pld_pcs_tx_pld_rst_n; + assign aib_fabric_adapter_tx_pld_rst_n = int_pld_adapter_tx_pld_rst_n; + //assign aib_fabric_pld_pma_fpll_dps_rst_n_lc_tx_bonding_rstb = pld_pma_fpll_dps_rst_n_lc_tx_bonding_rstb; + //assign aib_fabric_pld_pma_fpll_phase_en_lc_master_cgb_rstn = pld_pma_fpll_phase_en_lc_master_cgb_rstn; + //assign aib_fabric_pld_pma_fpll_lc_rstb = pld_pma_fpll_lc_rstb; + assign aib_fabric_pld_pma_txpma_rstb = int_pld_pma_txpma_rstb; + assign aib_fabric_fpll_shared_direct_async_out[2:1] = pld_fpll_shared_direct_async_in[1:0]; + +//******************************************************************** +// Feedthrough from AIB to PLD +//******************************************************************** + // Freeze Control Logic + //assign nfrz_output_2one = nfrzdrv_in & pld_partial_reconfig; + //assign pld_fpll_shared_direct_async_out[4:0] = nfrz_output_2one ? aib_fabric_fpll_shared_direct_async_in[4:0] : 5'b11111; + +//******************************************************************** +// PLD +//******************************************************************** + assign frz_2one_by_nfrzdrv_or_pr_channel_freeze_n = ~(nfrzdrv_in & pr_channel_freeze_n); + + assign pld_fabric_tx_transfer_en = frz_2one_by_nfrzdrv_or_pr_channel_freeze_n | tx_hrdrst_fabric_tx_transfer_en; + assign pld_aib_fabric_tx_dcd_cal_done = frz_2one_by_nfrzdrv_or_pr_channel_freeze_n | aib_fabric_tx_dcd_cal_done; + + //assign pld_fabric_tx_transfer_en = nfrzdrv_in ? tx_hrdrst_fabric_tx_transfer_en : 1'b1; + //assign pld_aib_fabric_tx_dcd_cal_done = nfrzdrv_in ? aib_fabric_tx_dcd_cal_done : 1'b1; + +//******************************************************************** +// Reset Synchronizers +//******************************************************************** + + assign int_tx_rst_n = (adapter_scan_mode_n & csr_rdy_dly_in & int_pld_adapter_tx_pld_rst_n) | (~adapter_scan_mode_n & adapter_scan_rst_n); + +cdclib_rst_n_sync cdclib_rst_n_sync_tx_hrdrst_rx_osc_clk + ( + .rst_n(int_tx_rst_n), + .rst_n_bypass(adapter_scan_rst_n), + .clk (tx_clock_reset_hrdrst_rx_osc_clk), + .scan_mode_n(adapter_scan_mode_n), + .rst_n_sync(tx_reset_hrdrst_rx_osc_clk_rst_n) + ); + +//******************************************************************** + + //assign int_tx_datapath_rst_n = (adapter_scan_mode_n & csr_rdy_dly_in & int_pld_adapter_tx_pld_rst_n & ~tx_hrdrst_fabric_tx_async_rst) | (~adapter_scan_mode_n & adapter_scan_rst_n); + +cdclib_rst_n_sync cdclib_rst_n_sync_fifo_wr_clk + ( + //.rst_n(int_tx_datapath_rst_n), + .rst_n(int_tx_rst_n), + .rst_n_bypass(adapter_scan_rst_n), + .clk (tx_clock_reset_fifo_wr_clk), + .scan_mode_n(adapter_scan_mode_n), + .rst_n_sync(tx_reset_fifo_wr_rst_n) + ); + +cdclib_rst_n_sync cdclib_rst_n_sync_fifo_rd_clk + ( + //.rst_n(int_tx_datapath_rst_n), + .rst_n(int_tx_rst_n), + .rst_n_bypass(adapter_scan_rst_n), + .clk (tx_clock_reset_fifo_rd_clk), + .scan_mode_n(adapter_scan_mode_n), + .rst_n_sync(tx_reset_fifo_rd_rst_n) + ); + +cdclib_rst_n_sync cdclib_rst_n_sync_fifo_sclk + ( + //.rst_n(int_tx_datapath_rst_n), + .rst_n(int_tx_rst_n), + .rst_n_bypass(adapter_scan_rst_n), + .clk (tx_clock_fifo_sclk), + .scan_mode_n(adapter_scan_mode_n), + .rst_n_sync(tx_reset_fifo_sclk_rst_n) + ); + +//******************************************************************** + + assign int_tx_hrd_rst_n = (adapter_scan_mode_n & csr_rdy_dly_in) | (~adapter_scan_mode_n & adapter_scan_rst_n); + +cdclib_rst_n_sync cdclib_rst_n_sync_rx_osc_clk + ( + .rst_n(int_tx_hrd_rst_n), + .rst_n_bypass(adapter_scan_rst_n), + .clk (tx_clock_reset_async_rx_osc_clk), + .scan_mode_n(adapter_scan_mode_n), + .rst_n_sync(tx_reset_async_rx_osc_clk_rst_n) + ); + +cdclib_rst_n_sync cdclib_rst_n_sync_tx_osc_clk + ( + .rst_n(int_tx_hrd_rst_n), + .rst_n_bypass(adapter_scan_rst_n), + .clk (tx_clock_reset_async_tx_osc_clk), + .scan_mode_n(adapter_scan_mode_n), + .rst_n_sync(tx_reset_async_tx_osc_clk_rst_n) + ); + +//******************************************************************** +// Double Synchronizers +//******************************************************************** + +cdclib_bitsync4 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset value + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (2), + .VID (1) + ) cdclib_bitsync4_rx_asn_rate_change_in_progress + ( + .clk (tx_clock_hrdrst_rx_osc_clk), + .rst_n (tx_reset_hrdrst_rx_osc_clk_rst_n), + .data_in (rx_asn_rate_change_in_progress), + .data_out (sync_rx_asn_rate_change_in_progress) + ); + +cdclib_bitsync4 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (1), // Reset value + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (2), + .VID (1) + ) cdclib_bitsync4_rx_asn_dll_lock_en + ( + .clk (tx_clock_hrdrst_rx_osc_clk), + .rst_n (tx_reset_hrdrst_rx_osc_clk_rst_n), + .data_in (rx_asn_dll_lock_en), + .data_out (sync_rx_asn_dll_lock_en) + ); + +cdclib_bitsync4 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset value + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (2), + .VID (1) + ) cdclib_bitsync4_rx_asn_fifo_hold + ( + .clk (tx_clock_hrdrst_rx_osc_clk), + .rst_n (tx_reset_hrdrst_rx_osc_clk_rst_n), + .data_in (rx_asn_fifo_hold), + .data_out (sync_rx_asn_fifo_hold) + ); + +cdclib_bitsync4 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset value + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (2), + .VID (1) + ) cdclib_bitsync4_aib_fabric_tx_dcd_cal_req + ( + .clk (tx_clock_hrdrst_rx_osc_clk), + .rst_n (tx_reset_hrdrst_rx_osc_clk_rst_n), + .data_in (aib_fabric_tx_dcd_cal_req_int), + .data_out (aib_fabric_tx_dcd_cal_req) + ); + +cdclib_bitsync4 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset value + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (2), + .VID (1) + ) cdclib_bitsync4_aib_fabric_tx_dcd_cal_done_int + ( + .clk (tx_clock_hrdrst_rx_osc_clk), + .rst_n (tx_reset_hrdrst_rx_osc_clk_rst_n), + .data_in (aib_fabric_tx_dcd_cal_done_int), + .data_out (sync_aib_fabric_tx_dcd_cal_done) + ); + +cdclib_bitsync4 + #( + .DWIDTH (1), // Sync Data input + .RESET_VAL (0), // Reset value + .CLK_FREQ_MHZ(1200), + .TOGGLE_TYPE (2), + .VID (1) + ) cdclib_bitsync4_tx_fifo_ready + ( + .clk (tx_clock_hrdrst_rx_osc_clk), + .rst_n (tx_reset_hrdrst_rx_osc_clk_rst_n), + .data_in (tx_fifo_ready), + .data_out (sync_tx_fifo_ready) + ); + +//******************************************************************** +// Test bus +//******************************************************************** +assign tx_hrdrst_testbus[19:0] = {3'b000,aib_fabric_tx_dcd_cal_done,aib_fabric_tx_dcd_cal_req, + tx_hrdrst_fabric_tx_transfer_en,tx_hrdrst_fabric_tx_dcd_cal_done,tx_hrdrst_fabric_tx_fifo_srst,tx_hrdrst_speed_chg_srst,sync_rx_asn_fifo_hold,tx_hrdrst_fabric_tx_dcd_cal_req, + sr_hssi_tx_transfer_en,sr_hssi_tx_dll_lock,sync_aib_fabric_tx_dcd_cal_done,sr_hssi_tx_dcd_cal_done,sync_rx_asn_dll_lock_en, + sync_rx_asn_rate_change_in_progress,tx_rst_sm_cs[2:0]}; + +//******************************************************************** +// ASN +//******************************************************************** +always @ (negedge tx_reset_hrdrst_rx_osc_clk_rst_n or posedge tx_clock_hrdrst_rx_osc_clk) +begin + if (~tx_reset_hrdrst_rx_osc_clk_rst_n) + begin + sync_rx_asn_fifo_hold_reg <= 1'b0; + tx_hrdrst_speed_chg_srst_dly <= 1'b0; + tx_hrdrst_speed_chg_srst <= 1'b0; + end + else + begin + sync_rx_asn_fifo_hold_reg <= sync_rx_asn_fifo_hold; + tx_hrdrst_speed_chg_srst_dly <= (sync_rx_asn_fifo_hold && ~sync_rx_asn_fifo_hold_reg) || tx_hrdrst_speed_chg_srst_dly && (tx_hrdrst_speed_chg_srst_cnt[5:0] != 6'b111111); + //tx_hrdrst_speed_chg_srst <= (sync_rx_asn_fifo_hold && ~sync_rx_asn_fifo_hold_reg) || (tx_hrdrst_speed_chg_srst && (tx_hrdrst_speed_chg_srst_cnt[4:0] != 5'b11111)); + tx_hrdrst_speed_chg_srst <= (tx_hrdrst_speed_chg_srst_dly && (tx_hrdrst_speed_chg_srst_cnt[5:0] == 6'b111111)) || (tx_hrdrst_speed_chg_srst && (tx_hrdrst_speed_chg_srst_cnt[5:0] != 6'b111111)); + end + end + + +// The tx_hrdrst_speed_chg_srst pulse must be long enough to be sampled by FIFO clock domain during PIPE mode, i.e. slowest is 125MHz. +always @ (negedge tx_reset_hrdrst_rx_osc_clk_rst_n or posedge tx_clock_hrdrst_rx_osc_clk) +begin + if (~tx_reset_hrdrst_rx_osc_clk_rst_n) + begin + tx_hrdrst_speed_chg_srst_cnt[5:0] <= 6'b000000; + end + else + begin + //if (tx_hrdrst_speed_chg_srst) + if (tx_hrdrst_speed_chg_srst_dly || tx_hrdrst_speed_chg_srst) + begin + tx_hrdrst_speed_chg_srst_cnt[5:0] <= tx_hrdrst_speed_chg_srst_cnt[5:0] + 6'b000001; + end + else + begin + tx_hrdrst_speed_chg_srst_cnt[5:0] <= 6'b000000; + end + end + end + +//******************************************************************** +// FIFO Reset +//******************************************************************** +assign tx_hrdrst_tx_fifo_srst = r_tx_hrdrst_user_ctl_en ? pld_fabric_tx_fifo_srst : tx_hrdrst_fabric_tx_fifo_srst_final; +// FIFO Reset when Reset SM is enabled +// From master Reset SM when current channel is master channel +// From master ASN SM when current channel is slave channel +assign tx_hrdrst_fabric_tx_fifo_srst_final = (r_tx_master_sel == 2'b00) ? tx_hrdrst_fabric_tx_fifo_srst : tx_hrdrst_speed_chg_srst; + +//******************************************************************** +// Tx Reset State Machine Bonding Input Output +//******************************************************************** +assign bond_tx_hrdrst_ds_in_fabric_tx_dcd_cal_done_int = r_tx_bonding_dft_in_en ? r_tx_bonding_dft_in_value : bond_tx_hrdrst_ds_in_fabric_tx_dcd_cal_done; +assign bond_tx_hrdrst_us_in_fabric_tx_dcd_cal_done_int = r_tx_bonding_dft_in_en ? r_tx_bonding_dft_in_value : bond_tx_hrdrst_us_in_fabric_tx_dcd_cal_done; +assign bond_tx_hrdrst_ds_in_fabric_tx_dcd_cal_req_int = r_tx_bonding_dft_in_en ? r_tx_bonding_dft_in_value : bond_tx_hrdrst_ds_in_fabric_tx_dcd_cal_req; +assign bond_tx_hrdrst_us_in_fabric_tx_dcd_cal_req_int = r_tx_bonding_dft_in_en ? r_tx_bonding_dft_in_value : bond_tx_hrdrst_us_in_fabric_tx_dcd_cal_req; + +hdpldadapt_cmn_cp_dist_pair + #( + .ASYNC_RESET_VAL(0), + .WIDTH(1) // Control width + ) hdpldadapt_cmn_cp_dist_pair_fabric_tx_dcd_cal_req + ( + .clk(1'b0), // clock + .rst_n(1'b1), // async reset + .srst_n(1'b1), // sync reset + .data_enable(1'b1), // data enable / data valid + .master_in(tx_hrdrst_fabric_tx_dcd_cal_req), // master control signal + .us_in(bond_tx_hrdrst_us_in_fabric_tx_dcd_cal_req_int), // CP distributed signal in up + .ds_in(bond_tx_hrdrst_ds_in_fabric_tx_dcd_cal_req_int), // CP distributed signal in dwn + .r_us_master(r_tx_dist_master_sel), // CRAM to control master or distributed up + .r_ds_master(r_tx_dist_master_sel), // CRAM to control master or distributed dwn + .r_us_bypass_pipeln(1'b1), // CRAM combo or registered up + .r_ds_bypass_pipeln(1'b1), // CRAM combo or registered dwn + .us_out(bond_tx_hrdrst_us_out_fabric_tx_dcd_cal_req), // CP distributed signal out up + .ds_out(bond_tx_hrdrst_ds_out_fabric_tx_dcd_cal_req), // CP distributed signal out dwn + .ds_tap(tx_hrdrst_fabric_tx_dcd_cal_req_chnl_down), // CP output for this channel dwn + .us_tap(tx_hrdrst_fabric_tx_dcd_cal_req_chnl_up) // CP output for this channel up + ); + + //assign aib_fabric_tx_dcd_cal_req = r_tx_hrdrst_rst_sm_dis ? int_pld_aib_fabric_tx_dcd_cal_req : tx_hrdrst_fabric_tx_dcd_cal_req_final; + assign aib_fabric_tx_dcd_cal_req_int = r_tx_hrdrst_user_ctl_en ? int_pld_aib_fabric_tx_dcd_cal_req : tx_hrdrst_fabric_tx_dcd_cal_req_final; + assign tx_hrdrst_fabric_tx_dcd_cal_req_final = (r_tx_master_sel == 2'b00) ? tx_hrdrst_fabric_tx_dcd_cal_req : + (r_tx_master_sel == 2'b01) ? tx_hrdrst_fabric_tx_dcd_cal_req_chnl_up : + (r_tx_master_sel == 2'b10) ? tx_hrdrst_fabric_tx_dcd_cal_req_chnl_down : + tx_hrdrst_fabric_tx_dcd_cal_req ; + + assign tx_hrdrst_fabric_tx_dcd_cal_done_chnl_down = r_tx_ds_last_chnl ? 1'b1 : bond_tx_hrdrst_ds_in_fabric_tx_dcd_cal_done_int; + assign tx_hrdrst_fabric_tx_dcd_cal_done_chnl_up = r_tx_us_last_chnl ? 1'b1 : bond_tx_hrdrst_us_in_fabric_tx_dcd_cal_done_int; + assign aib_fabric_tx_dcd_cal_done_int = (aib_fabric_tx_dcd_cal_done & tx_hrdrst_fabric_tx_dcd_cal_done_chnl_up & tx_hrdrst_fabric_tx_dcd_cal_done_chnl_down); + assign bond_tx_hrdrst_us_out_fabric_tx_dcd_cal_done = aib_fabric_tx_dcd_cal_done & tx_hrdrst_fabric_tx_dcd_cal_done_chnl_down; + assign bond_tx_hrdrst_ds_out_fabric_tx_dcd_cal_done = aib_fabric_tx_dcd_cal_done & tx_hrdrst_fabric_tx_dcd_cal_done_chnl_up; + +//******************************************************************** +// Tx Reset State Machine Output +//******************************************************************** + +assign tx_hrdrst_fabric_tx_dcd_cal_req_pre = tx_hrdrst_fabric_tx_dcd_cal_req_comb; + +// Generate asynchronous reset during non PCIe rate change. +// Bypass Tx Reset State Machine if Reset State Machine is diabled. +//assign tx_hrdrst_fabric_tx_async_rst_pre = r_tx_hrdrst_rst_sm_dis ? (~sync_rx_asn_rate_change_in_progress & ~sr_hssi_tx_dll_lock) : +// (~sync_rx_asn_rate_change_in_progress & tx_hrdrst_fabric_tx_rst_comb); + +// Generate synchronous reset to FIFO during PCIe rate change. +// Bypass Tx Reset State Machine if Reset State Machine is diabled. +//assign tx_hrdrst_fabric_tx_fifo_srst_pre = r_tx_hrdrst_rst_sm_dis ? (sync_rx_asn_rate_change_in_progress & ~sr_hssi_tx_dll_lock) : +// (sync_rx_asn_rate_change_in_progress & tx_hrdrst_fabric_tx_rst_comb); +//assign tx_hrdrst_fabric_tx_fifo_srst_pre = r_tx_hrdrst_user_ctl_en ? (~sr_hssi_tx_dll_lock) : tx_hrdrst_fabric_tx_rst_comb; +assign tx_hrdrst_fabric_tx_fifo_srst_pre = tx_hrdrst_fabric_tx_rst_comb; + +assign tx_hrdrst_fabric_tx_dcd_cal_done_pre = tx_hrdrst_fabric_tx_dcd_cal_done_comb; + +// Bypass Tx Reset State Machine if Reset State Machine is diabled. +//assign tx_hrdrst_fabric_tx_transfer_en_pre = r_tx_hrdrst_rst_sm_dis ? sr_hssi_tx_transfer_en : tx_hrdrst_fabric_tx_transfer_en_comb; +//assign tx_hrdrst_fabric_tx_transfer_en_pre = r_tx_hrdrst_user_ctl_en ? sr_hssi_tx_transfer_en : tx_hrdrst_fabric_tx_transfer_en_comb; +assign tx_hrdrst_fabric_tx_transfer_en_pre = tx_hrdrst_fabric_tx_transfer_en_comb; + +always @ (negedge tx_reset_hrdrst_rx_osc_clk_rst_n or posedge tx_clock_hrdrst_rx_osc_clk) +begin + if (~tx_reset_hrdrst_rx_osc_clk_rst_n) + begin + tx_hrdrst_fabric_tx_dcd_cal_req <= 1'b0; + //tx_hrdrst_fabric_tx_async_rst <= 1'b1; + //tx_hrdrst_fabric_tx_fifo_srst <= 1'b0; + tx_hrdrst_fabric_tx_fifo_srst <= 1'b1; + tx_hrdrst_fabric_tx_dcd_cal_done <= 1'b0; + tx_hrdrst_fabric_tx_transfer_en <= 1'b0; + end + else + begin + tx_hrdrst_fabric_tx_dcd_cal_req <= tx_hrdrst_fabric_tx_dcd_cal_req_pre; + //tx_hrdrst_fabric_tx_async_rst <= tx_hrdrst_fabric_tx_async_rst_pre; + tx_hrdrst_fabric_tx_fifo_srst <= tx_hrdrst_fabric_tx_fifo_srst_pre; + tx_hrdrst_fabric_tx_dcd_cal_done <= tx_hrdrst_fabric_tx_dcd_cal_done_pre; + tx_hrdrst_fabric_tx_transfer_en <= tx_hrdrst_fabric_tx_transfer_en_pre; + end + end + +//******************************************************************** +// Tx Reset State Machine +//******************************************************************** +always @(negedge tx_reset_hrdrst_rx_osc_clk_rst_n or posedge tx_clock_hrdrst_rx_osc_clk) +begin + if (~tx_reset_hrdrst_rx_osc_clk_rst_n) + begin + tx_rst_sm_cs <= WAIT_TX_TRANSFER_REQ; + end + else if ( ~avmm_hrdrst_fabric_osc_transfer_en || r_tx_hrdrst_rst_sm_dis || r_tx_hrdrst_user_ctl_en) + begin + tx_rst_sm_cs <= WAIT_TX_TRANSFER_REQ; + end + else + begin + tx_rst_sm_cs <= tx_rst_sm_ns; + end +end + + +always @ (*) +begin + tx_rst_sm_ns = tx_rst_sm_cs; + tx_hrdrst_fabric_tx_dcd_cal_req_comb = 1'b0; + tx_hrdrst_fabric_tx_rst_comb = 1'b1; + tx_hrdrst_fabric_tx_dcd_cal_done_comb = 1'b0; + tx_hrdrst_fabric_tx_transfer_en_comb = 1'b0; + + case(tx_rst_sm_cs) + WAIT_TX_TRANSFER_REQ: + begin + if(sr_hssi_tx_dcd_cal_done && sync_rx_asn_dll_lock_en && ~sync_aib_fabric_tx_dcd_cal_done) + begin + tx_rst_sm_ns = SEND_TX_DCD_CAL_REQ; + end + end + + SEND_TX_DCD_CAL_REQ: + begin + tx_hrdrst_fabric_tx_dcd_cal_req_comb = 1'b1; + if(sync_aib_fabric_tx_dcd_cal_done || r_tx_hrdrst_dcd_cal_done_bypass) + begin + tx_rst_sm_ns = WAIT_REMOTE_TX_DLL_LOCK; + end + end + + WAIT_REMOTE_TX_DLL_LOCK: + begin + tx_hrdrst_fabric_tx_dcd_cal_req_comb = 1'b1; + tx_hrdrst_fabric_tx_dcd_cal_done_comb = 1'b1; + if (sr_hssi_tx_dll_lock) + begin + tx_rst_sm_ns = WAIT_REMOTE_TX_ALIGN_DONE; + end + end + + WAIT_REMOTE_TX_ALIGN_DONE: + begin + tx_hrdrst_fabric_tx_dcd_cal_req_comb = 1'b1; + tx_hrdrst_fabric_tx_rst_comb = 1'b0; + if (sr_hssi_tx_transfer_en && sync_tx_fifo_ready) + begin + tx_rst_sm_ns = TX_TRANSFER_EN; + end + end + TX_TRANSFER_EN: + begin + tx_hrdrst_fabric_tx_dcd_cal_req_comb = 1'b1; + tx_hrdrst_fabric_tx_rst_comb = 1'b0; + tx_hrdrst_fabric_tx_transfer_en_comb = 1'b1; + if (~sr_hssi_tx_transfer_en || ~sync_rx_asn_dll_lock_en) + begin + tx_rst_sm_ns = WAIT_TX_TRANSFER_REQ; + end + end + + default: + begin + tx_rst_sm_ns = WAIT_TX_TRANSFER_REQ; + tx_hrdrst_fabric_tx_dcd_cal_req_comb = 1'b0; + tx_hrdrst_fabric_tx_dcd_cal_done_comb = 1'b0; + tx_hrdrst_fabric_tx_rst_comb = 1'b1; + tx_hrdrst_fabric_tx_transfer_en_comb = 1'b0; + end + endcase + end + + +endmodule // hdpldadapt_txrst_ctl diff --git a/maib_rtl/io_common_custom/rtl/block_function/block_function b/maib_rtl/io_common_custom/rtl/block_function/block_function new file mode 100644 index 0000000..e69de29 diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_8phs_calibrate_x48.v b/maib_rtl/io_common_custom/rtl/block_function/io_8phs_calibrate_x48.v new file mode 100644 index 0000000..dd57b14 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_8phs_calibrate_x48.v @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module io_8phs_calibrate_x48 ( +input [7:0] phs_in, +input [3:0] phy_clk_phs_ctrl, +input cenable, +input [5:0] f_gray_pair0, +input [5:0] f_gray_pair1, +input [5:0] f_gray_pair2, +input [5:0] f_gray_pair3, +input [5:0] r_gray_pair0, +input [5:0] r_gray_pair1, +input [5:0] r_gray_pair2, +input [5:0] r_gray_pair3, +input rst_n, +input sample_clk, +output [7:0] phs_calibrate, +output [7:0] phs_and_sample, +output [3:0] phs_sample +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +wire spc; +wire snc; +wire [7:0] adjusted_phase; + +assign spc = ~cenable; +assign snc = cenable; + +`ifdef TEST_DUTY_CYCLE_CORRECTION + assign #40 adjusted_phase[0] = phs_in[0]; + assign #30 adjusted_phase[1] = phs_in[1]; + assign #1 adjusted_phase[2] = phs_in[2]; + assign #10 adjusted_phase[3] = phs_in[3]; + assign #10 adjusted_phase[4] = phs_in[4]; + assign #40 adjusted_phase[5] = phs_in[5]; + assign #20 adjusted_phase[6] = phs_in[6]; + assign #50 adjusted_phase[7] = phs_in[7]; +`else + assign adjusted_phase[0] = phs_in[0]; + assign adjusted_phase[1] = phs_in[1]; + assign adjusted_phase[2] = phs_in[2]; + assign adjusted_phase[3] = phs_in[3]; + assign adjusted_phase[4] = phs_in[4]; + assign adjusted_phase[5] = phs_in[5]; + assign adjusted_phase[6] = phs_in[6]; + assign adjusted_phase[7] = phs_in[7]; +`endif + +io_phs_check xphs_check ( +.rst_n ( rst_n ), +.sample_clk ( sample_clk ), +.ph_in ( phs_calibrate[7:0] ), +.ph_and_sample ( phs_and_sample[7:0] ), +.ph_sample ( phs_sample[3:0] ) +); + +io_phs_pair_couple_x48 xpair0 ( +.c_in_p ( adjusted_phase[0] ), +.c_in_n ( adjusted_phase[4] ), +.phy_clk_phs_ctrl( phy_clk_phs_ctrl[0] ), +.snc ( snc ), +.spc ( spc ), +.r_gray ( r_gray_pair0[5:0] ), +.f_gray ( f_gray_pair0[5:0] ), +.c_out_p ( phs_calibrate[0] ), +.c_out_n ( phs_calibrate[4] ) +); + +io_phs_pair_couple_x48 xpair1 ( +.c_in_p ( adjusted_phase[1] ), +.c_in_n ( adjusted_phase[5] ), +.phy_clk_phs_ctrl( phy_clk_phs_ctrl[1] ), +.snc ( snc ), +.spc ( spc ), +.r_gray ( r_gray_pair1[5:0] ), +.f_gray ( f_gray_pair1[5:0] ), +.c_out_p ( phs_calibrate[1] ), +.c_out_n ( phs_calibrate[5] ) +); + +io_phs_pair_couple_x48 xpair2 ( +.c_in_p ( adjusted_phase[2] ), +.c_in_n ( adjusted_phase[6] ), +.phy_clk_phs_ctrl( phy_clk_phs_ctrl[2] ), +.snc ( snc ), +.spc ( spc ), +.r_gray ( r_gray_pair2[5:0] ), +.f_gray ( f_gray_pair2[5:0] ), +.c_out_p ( phs_calibrate[2] ), +.c_out_n ( phs_calibrate[6] ) +); + +io_phs_pair_couple_x48 xpair3 ( +.c_in_p ( adjusted_phase[3] ), +.c_in_n ( adjusted_phase[7] ), +.phy_clk_phs_ctrl( phy_clk_phs_ctrl[3] ), +.snc ( snc ), +.spc ( spc ), +.r_gray ( r_gray_pair3[5:0] ), +.f_gray ( f_gray_pair3[5:0] ), +.c_out_p ( phs_calibrate[3] ), +.c_out_n ( phs_calibrate[7] ) +); + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_clk_wkup.v b/maib_rtl/io_common_custom/rtl/block_function/io_clk_wkup.v new file mode 100644 index 0000000..abcd668 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_clk_wkup.v @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #1 $ +// Date: $DateTime: 2014/11/15 16:17:29 $ +//------------------------------------------------------------------------ +// Description: smaller size dq/dqs driver +// +//------------------------------------------------------------------------ + +module io_clk_wkup ( +input enb, // +output drain_out // +); + +assign drain_out = enb ? 1'bz : 1'b1; + +endmodule + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_cmos_16ph_decode.v b/maib_rtl/io_common_custom/rtl/block_function/io_cmos_16ph_decode.v new file mode 100644 index 0000000..1a72d0f --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_cmos_16ph_decode.v @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #3 $ +// Date: $DateTime: 2015/05/27 18:53:02 $ +//------------------------------------------------------------------------ +// Description: 16 phase interpolator gray code decode +// +//------------------------------------------------------------------------ + +module io_cmos_16ph_decode ( +input enable, // Active high enable 0 = Force interpolator_clk[1:0] to 2'b10 +input test_enable_buf, // Active high test enable +input test_enable_n, // Active low test enable +input dft_mux_sel_p, // mux selection during test +input dft_mux_sel_n, // complimentary mux selection during test +input clk_p_0, // clock for sync gray code - 1st latch +input clk_n_0, // clock for sync gray code - 1st latch +input clk_p_2, // clock for sync gray code - 2nd latch +input clk_n_2, // clock for sync gray code - 2nd latch +input [3:0] gray_sel_a, // The gray code output to control the interpolator (even) +input [3:0] gray_sel_b, // The gray code output to control the interpolator (odd ) +input [1:0] filter_code, // 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz +output [7:0] sp, // thermal code for 8 phase interpolator +output [7:0] sn, // complimentary thermal code for 8 phase interpolator +output [6:0] selp, // code for 2 phase interpolator (including decode for test) +output [6:0] seln, // complimentary code for 2 phase interpolator (including decode for test) +output [3:1] scp, // filter capacitance selection +output reg [3:1] scn // complimentary filter capacitance selection +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter INV_DELAY = 15; // 15ps +parameter LATCH_DELAY = 50; // 50ps +parameter BUF_DELAY = 25; // 25ps +parameter MUX_DELAY = 50; // 50ps + +reg [3:0] gray_sel_ax; +reg [3:0] gray_sel_bx; +reg [3:0] out_gray_az; +reg [3:0] out_gray_bz; +reg [7:0] sp_a; +reg [7:0] sp_b; +wire [7:0] sn_a; +wire [7:0] sn_b; +reg [6:0] seln_a; +reg [6:0] seln_b; +wire [6:0] selp_a; +wire [6:0] selp_b; +wire clk_p_0_buf; +wire clk_n_0_buf; +wire clk_p_2_buf; +wire clk_n_2_buf; + +assign #BUF_DELAY clk_p_0_buf = clk_p_0; +assign #BUF_DELAY clk_n_0_buf = clk_n_0; +assign #BUF_DELAY clk_p_2_buf = clk_p_2; +assign #BUF_DELAY clk_n_2_buf = clk_n_2; + +//filter code decode +always @(*) + case (filter_code[1:0]) + 2'b00 : scn[3:1] = 3'b000; + 2'b01 : scn[3:1] = 3'b001; + 2'b10 : scn[3:1] = 3'b011; + 2'b11 : scn[3:1] = 3'b111; + endcase +assign #INV_DELAY scp[3:1] = ~scn[3:1]; + +//gray code sync +always @(*) + if (~enable) gray_sel_ax[3:0] <= #LATCH_DELAY 4'h0; + else if (clk_p_0_buf) gray_sel_ax[3:0] <= #LATCH_DELAY gray_sel_a[3:0]; + +always @(*) + if (~enable) gray_sel_bx[3:0] <= #LATCH_DELAY 4'h0; + else if (clk_n_0_buf) gray_sel_bx[3:0] <= #LATCH_DELAY gray_sel_b[3:0]; + +always @(*) + if (~enable) out_gray_az[3:0] <= #LATCH_DELAY 4'h0; + else if (clk_p_2_buf) out_gray_az[3:0] <= #LATCH_DELAY gray_sel_ax[3:0]; + +always @(*) + if (~enable) out_gray_bz[3:0] <= #LATCH_DELAY 4'h0; + else if (clk_n_2_buf) out_gray_bz[3:0] <= #LATCH_DELAY gray_sel_bx[3:0]; + +//gray code decode +always @(*) + case (out_gray_az[3:0]) + 4'b0000 : sp_a[7:0] = 8'b0000_0000; + 4'b0001 : sp_a[7:0] = 8'b0000_0001; + 4'b0011 : sp_a[7:0] = 8'b0000_0011; + 4'b0010 : sp_a[7:0] = 8'b0000_0111; + 4'b0110 : sp_a[7:0] = 8'b0000_1111; + 4'b0111 : sp_a[7:0] = 8'b0001_1111; + 4'b0101 : sp_a[7:0] = 8'b0011_1111; + 4'b0100 : sp_a[7:0] = 8'b0111_1111; + 4'b1100 : sp_a[7:0] = 8'b1111_1111; + 4'b1101 : sp_a[7:0] = 8'b0111_1111; + 4'b1111 : sp_a[7:0] = 8'b0011_1111; + 4'b1110 : sp_a[7:0] = 8'b0001_1111; + 4'b1010 : sp_a[7:0] = 8'b0000_1111; + 4'b1011 : sp_a[7:0] = 8'b0000_0111; + 4'b1001 : sp_a[7:0] = 8'b0000_0011; + 4'b1000 : sp_a[7:0] = 8'b0000_0001; + endcase + +always @(*) + case (out_gray_bz[3:0]) + 4'b0000 : sp_b[7:0] = 8'b0000_0000; + 4'b0001 : sp_b[7:0] = 8'b0000_0001; + 4'b0011 : sp_b[7:0] = 8'b0000_0011; + 4'b0010 : sp_b[7:0] = 8'b0000_0111; + 4'b0110 : sp_b[7:0] = 8'b0000_1111; + 4'b0111 : sp_b[7:0] = 8'b0001_1111; + 4'b0101 : sp_b[7:0] = 8'b0011_1111; + 4'b0100 : sp_b[7:0] = 8'b0111_1111; + 4'b1100 : sp_b[7:0] = 8'b1111_1111; + 4'b1101 : sp_b[7:0] = 8'b0111_1111; + 4'b1111 : sp_b[7:0] = 8'b0011_1111; + 4'b1110 : sp_b[7:0] = 8'b0001_1111; + 4'b1010 : sp_b[7:0] = 8'b0000_1111; + 4'b1011 : sp_b[7:0] = 8'b0000_0111; + 4'b1001 : sp_b[7:0] = 8'b0000_0011; + 4'b1000 : sp_b[7:0] = 8'b0000_0001; + endcase + +//assign sp_a[7] = out_gray_az[3]; +//assign sp_b[7] = out_gray_bz[3]; +assign sn_a[7:0] = ~sp_a[7:0]; +assign sn_b[7:0] = ~sp_b[7:0]; + +//gray code decode for 2 phase interpolator including special decoding during test +//for int_a clk_in_a clk_in_c clk_in_b +//greay3 gray2 test s0_n s1_n s2_n s3_n s4_n s4_n +// 0 * 0 1 1 0 0 1 1 interpolate clk_in_a and clk_in_b +// 1 * 0 0 1 0 1 1 1 clk_in_b +// 0 0 1 1 1 0 0 0 0 clk_in_a +// 1 1 1 0 0 0 0 1 1 clk_in_b +// 0 1 1 0 0 0 0 1 1 clk_in_b +// 1 0 1 0 0 1 1 0 0 clk_in_c +//for int_c clk_in_a clk_in_c clk_in_b +//greay3 gray2 test s0_n s5_n s6_n s3_n s4_n s4_n (s5_n connects to s1_n of xip2c; s6_n connects to s2_n of xip2c) +// 0 * 0 1 0 1 0 1 1 clk_in_b +// 1 * 0 0 0 1 1 1 1 interpolate clk_in_b and clk_in_c +// 0 0 1 1 1 0 0 0 0 clk_in_a +// 1 1 1 0 0 0 0 1 1 clk_in_b +// 0 1 1 0 0 0 0 1 1 clk_in_b +// 1 0 1 0 0 1 1 0 0 clk_in_c + +always @(*) + casez ({out_gray_az[3:2],test_enable_buf}) + 3'b0?0 : seln_a[6:0] = 7'b101_0011; //int_a=(clk_in_a+clk_in_b)/2; int_c=clk_in_b; + 3'b1?0 : seln_a[6:0] = 7'b101_1010; //int_c=clk_in_b; int_a=(clk_in_b+clk_in_c)/2; + 3'b001 : seln_a[6:0] = 7'b000_0011; //int_a=int_c=clk_in_a; + 3'b111 : seln_a[6:0] = 7'b001_0000; //int_a=int_c=clk_in_b; + 3'b011 : seln_a[6:0] = 7'b001_0000; //int_a=int_c=clk_in_b; + 3'b101 : seln_a[6:0] = 7'b100_1000; //int_a=int_c=clk_in_c; + endcase + +always @(*) + casez ({out_gray_bz[3:2],test_enable_buf}) + 3'b0?0 : seln_b[6:0] = 7'b101_0011; //int_a=(clk_in_a+clk_in_b)/2; int_c=clk_in_b; + 3'b1?0 : seln_b[6:0] = 7'b101_1010; //int_a=clk_in_b; int_c=(clk_in_b+clk_in_c)/2; + 3'b001 : seln_b[6:0] = 7'b000_0011; //int_a=int_c=clk_in_a; + 3'b111 : seln_b[6:0] = 7'b001_0000; //int_a=int_c=clk_in_b; + 3'b011 : seln_b[6:0] = 7'b001_0000; //int_a=int_c=clk_in_b; + 3'b101 : seln_b[6:0] = 7'b100_1000; //int_a=int_c=clk_in_c; + endcase + +assign selp_a[6:0] = ~seln_a[6:0]; +assign selp_b[6:0] = ~seln_b[6:0]; + +//gray code mux +//assign #MUX_DELAY sp[7:0] = ({8{clk_n_2}} & {out_gray_az[3],sp_a[6:0]}) | ({8{clk_p_2}} & {out_gray_bz[3],sp_b[6:0]}); +//assign #INV_DELAY sn[7:0] = ~sp[7:0]; +assign clk_p_2_buf2 = ~(dft_mux_sel_p & ~(clk_p_2 & test_enable_n )); +assign clk_n_2_buf2 = ~(dft_mux_sel_n & ~(clk_n_2 & test_enable_n )); +assign #MUX_DELAY sp[7:0] = clk_p_2_buf2? sp_b[7:0] : sp_a[7:0]; +assign #MUX_DELAY sn[7:0] = clk_n_2_buf2? sn_a[7:0] : sn_b[7:0]; +assign #MUX_DELAY selp[6:0] = clk_p_2_buf2? selp_b[6:0] : selp_a[6:0]; +assign #MUX_DELAY seln[6:0] = clk_n_2_buf2? seln_a[6:0] : seln_b[6:0]; + +//========================================================================================================================================================================= +// Waveforms +//========================================================================================================================================================================= +// +// ___________________ ___________________ ________________________: ___________________ +// clk_p_0 ___/ \________________________/ \___________________/ \___________________/ \__ +// ___________________ ___________________ ________________________ _________________ +// clk_p_1 ________/ \________________________/ \___________________/ \___________________/ +// ___________________ ___________________ ________________________ ____________ +// clk_p_2 _____________/ \________________________/ \___________________/ \___________________/ +// +// ________ ______________________________ _________________________ ______________________________ +// out_gray_az[3:0] ________XXXXXXXXXXXXXXX_____________________2________XXXXXXXXXXXXXXX________________C________XXXXXXXXXXXXXXX_____________________6________XXXXXXXXXXXX +// ____________________________ ______________________________ ______________________________ _________________ +// out_gray_bz[3:0] ___________________D________XXXXXXXXXXXXXXX_____________________7________XXXXXXXXXXXXXXX_____________________1________XXXXXXXXXXXXXXX_______________B_ +// __________ ___________________ ________________________ ___________________ ___________________ ________________________ ___________________ _____________ +// sn[7:0] __________X_________D_________X_____________2__________X__________7________X__________C________X_____________1__________X__________6________X__________B__ +// +//=========================================================================================================================================================================== + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x1.v b/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x1.v new file mode 100644 index 0000000..15e4f92 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x1.v @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// io_cmos_nand_x1 +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module io_cmos_nand_x1 ( +input in_p, +input in_n, +input bk, +input ci_p, +input ci_n, +output out_p, +output out_n, +output co_p, +output co_n +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter NAND_DELAY = 20; + +reg tp; +reg tn; + +assign #NAND_DELAY co_p = ~(in_p & bk); + +always @(*) + if (~in_p) tp <= #NAND_DELAY 1'b1; + else if (~bk) tp <= #NAND_DELAY 1'b0; + +assign #NAND_DELAY out_p = ~(tp & ci_p); + +assign #NAND_DELAY co_n = ~(in_n & bk); + +always @(*) + if (~in_n) tn <= #NAND_DELAY 1'b1; + else if (~bk) tn <= #NAND_DELAY 1'b0; + +assign #NAND_DELAY out_n = ~(tn & ci_n); + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x128.v b/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x128.v new file mode 100644 index 0000000..cffbe46 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x128.v @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// io_cmos_nand_x128 +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module io_cmos_nand_x128 ( +input in_p, +input in_n, +input [6:0] gray, +output out_p, +output out_n +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter NAND_DELAY = 20; + +wire [127:0] bk; +wire [125:0] a; +wire [124:0] b; +wire [125:0] c; +wire [124:0] d; + +io_cmos_nand_x128_decode xdec ( +.gray ( gray[6:0] ), +.bk ( bk[127:0] ) +); + +io_cmos_nand_x6 xnand_x6 [20:0] ( +.in_p ( {a[119],a[113],a[107],a[101],a[95],a[89],a[83],a[77],a[71],a[65],a[59],a[53],a[47],a[41],a[35],a[29],a[23],a[17],a[11],a[5],in_p} ), +.in_n ( {c[119],c[113],c[107],c[101],c[95],c[89],c[83],c[77],c[71],c[65],c[59],c[53],c[47],c[41],c[35],c[29],c[23],c[17],c[11],c[5],in_n} ), +.bk5 ( {1'b0,bk[119],bk[113],bk[107],bk[101],bk[95],bk[89],bk[83],bk[77],bk[71],bk[65],bk[59],bk[53],bk[47],bk[41],bk[35],bk[29],bk[23],bk[17],bk[11],bk[5]} ), +.bk4 ( {bk[124],bk[118],bk[112],bk[106],bk[100],bk[94],bk[88],bk[82],bk[76],bk[70],bk[64],bk[58],bk[52],bk[46],bk[40],bk[34],bk[28],bk[22],bk[16],bk[10],bk[4]} ), +.bk3 ( {bk[123],bk[117],bk[111],bk[105],bk[99],bk[93],bk[87],bk[81],bk[75],bk[69],bk[63],bk[57],bk[51],bk[45],bk[39],bk[33],bk[27],bk[21],bk[15],bk[9],bk[3]} ), +.bk2 ( {bk[122],bk[116],bk[110],bk[104],bk[98],bk[92],bk[86],bk[80],bk[74],bk[68],bk[62],bk[56],bk[50],bk[44],bk[38],bk[32],bk[26],bk[20],bk[14],bk[8],bk[2]} ), +.bk1 ( {bk[121],bk[115],bk[109],bk[103],bk[97],bk[91],bk[85],bk[79],bk[73],bk[67],bk[61],bk[55],bk[49],bk[43],bk[37],bk[31],bk[25],bk[19],bk[13],bk[7],bk[1]} ), +.bk0 ( {bk[120],bk[114],bk[108],bk[102],bk[96],bk[90],bk[84],bk[78],bk[72],bk[66],bk[60],bk[54],bk[48],bk[42],bk[36],bk[30],bk[24],bk[18],bk[12],bk[6],bk[0]} ), +.ci_p ( {1'b1,b[119],b[113],b[107],b[101],b[95],b[89],b[83],b[77],b[71],b[65],b[59],b[53],b[47],b[41],b[35],b[29],b[23],b[17],b[11],b[5]} ), +.ci_n ( {1'b1,d[119],d[113],d[107],d[101],d[95],d[89],d[83],d[77],d[71],d[65],d[59],d[53],d[47],d[41],d[35],d[29],d[23],d[17],d[11],d[5]} ), +.out_p ( {b[119],b[113],b[107],b[101],b[95],b[89],b[83],b[77],b[71],b[65],b[59],b[53],b[47],b[41],b[35],b[29],b[23],b[17],b[11],b[5],out_p} ), +.out_n ( {d[119],d[113],d[107],d[101],d[95],d[89],d[83],d[77],d[71],d[65],d[59],d[53],d[47],d[41],d[35],d[29],d[23],d[17],d[11],d[5],out_n} ), +.co_p ( {a[125],a[119],a[113],a[107],a[101],a[95],a[89],a[83],a[77],a[71],a[65],a[59],a[53],a[47],a[41],a[35],a[29],a[23],a[17],a[11],a[5]} ), +.co_n ( {c[125],c[119],c[113],c[107],c[101],c[95],c[89],c[83],c[77],c[71],c[65],c[59],c[53],c[47],c[41],c[35],c[29],c[23],c[17],c[11],c[5]} ) +); + +endmodule + + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x128_decode.v b/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x128_decode.v new file mode 100644 index 0000000..6022e14 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x128_decode.v @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// io_cmos_nand_x128_decode +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module io_cmos_nand_x128_decode ( +input [6:0] gray, +output [127:0] bk +); + +wire [5:0] b_gray; + +assign b_gray[5] = ~gray[5] & gray[6]; +assign b_gray[4:0] = gray[4:0] & {5{gray[6]}}; + +io_cmos_nand_x64_decode xdec_0 ( +.gray ( gray[6:0] ), +.bk ( bk[63:0] ) +); + +io_cmos_nand_x64_decode xdec_1 ( +.gray ( {1'b0, b_gray[5:0]} ), +.bk ( bk[127:64] ) +); + +endmodule + + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x4.v b/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x4.v new file mode 100644 index 0000000..3b3d098 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x4.v @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// io_cmos_nand_x4 +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module io_cmos_nand_x4 ( +input ci_p, +input ci_n, +input in_p, +input in_n, +input bk3, +input bk2, +input bk1, +input bk0, +output co_p, +output co_n, +output out_p, +output out_n +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +wire [2:0] a; +wire [2:0] b; +wire [2:0] c; +wire [2:0] d; + +parameter NAND_DELAY = 20; + +io_cmos_nand_x1 UD00 [3:0] ( +.in_p ( {a[2:0],in_p} ), +.in_n ( {c[2:0],in_n} ), +.bk ( {bk3,bk2,bk1,bk0} ), +.ci_p ( {ci_p,b[2:0]} ), +.ci_n ( {ci_n,d[2:0]} ), +.out_p ( {b[2:0],out_p} ), +.out_n ( {d[2:0],out_n} ), +.co_p ( {co_p,a[2:0]} ), +.co_n ( {co_n,c[2:0]} ) +); + +endmodule + + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x6.v b/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x6.v new file mode 100644 index 0000000..cb8d186 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x6.v @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// io_cmos_nand_x6 +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module io_cmos_nand_x6 ( +input ci_p, +input ci_n, +input in_p, +input in_n, +input bk5, +input bk4, +input bk3, +input bk2, +input bk1, +input bk0, +output co_p, +output co_n, +output out_p, +output out_n +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +wire [4:0] a; +wire [4:0] b; +wire [4:0] c; +wire [4:0] d; + +parameter NAND_DELAY = 20; + +io_cmos_nand_x1 UD00 [5:0] ( +.in_p ( {a[4:0],in_p} ), +.in_n ( {c[4:0],in_n} ), +.bk ( {bk5,bk4,bk3,bk2,bk1,bk0} ), +.ci_p ( {ci_p,b[4:0]} ), +.ci_n ( {ci_n,d[4:0]} ), +.out_p ( {b[4:0],out_p} ), +.out_n ( {d[4:0],out_n} ), +.co_p ( {co_p,a[4:0]} ), +.co_n ( {co_n,c[4:0]} ) +); + +endmodule + + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x64.v b/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x64.v new file mode 100644 index 0000000..3ea6277 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x64.v @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// io_cmos_nand_x64 +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module io_cmos_nand_x64 ( +input b63, +input d63, +input in_p, +input in_n, +input [6:0] gray, +output a63, +output c63, +output out_p, +output out_n +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter NAND_DELAY = 20; + +wire [63:0] bk; +wire [62:0] a; +wire [62:0] b; +wire [62:0] c; +wire [62:0] d; + +io_cmos_nand_x64_decode xdec ( +.gray ( gray[6:0] ), +.bk ( bk[63:0] ) +); + +io_cmos_nand_x6 xnand_x6 [9:0] ( +.in_p ( {a[53],a[47],a[41],a[35],a[29],a[23],a[17],a[11],a[5],in_p} ), +.in_n ( {c[53],c[47],c[41],c[35],c[29],c[23],c[17],c[11],c[5],in_n} ), +.bk5 ( {bk[59],bk[53],bk[47],bk[41],bk[35],bk[29],bk[23],bk[17],bk[11],bk[5]} ), +.bk4 ( {bk[58],bk[52],bk[46],bk[40],bk[34],bk[28],bk[22],bk[16],bk[10],bk[4]} ), +.bk3 ( {bk[57],bk[51],bk[45],bk[39],bk[33],bk[27],bk[21],bk[15],bk[9],bk[3]} ), +.bk2 ( {bk[56],bk[50],bk[44],bk[38],bk[32],bk[26],bk[20],bk[14],bk[8],bk[2]} ), +.bk1 ( {bk[55],bk[49],bk[43],bk[37],bk[31],bk[25],bk[19],bk[13],bk[7],bk[1]} ), +.bk0 ( {bk[54],bk[48],bk[42],bk[36],bk[30],bk[24],bk[18],bk[12],bk[6],bk[0]} ), +.ci_p ( {b[59],b[53],b[47],b[41],b[35],b[29],b[23],b[17],b[11],b[5]} ), +.ci_n ( {d[59],d[53],d[47],d[41],d[35],d[29],d[23],d[17],d[11],d[5]} ), +.out_p ( {b[53],b[47],b[41],b[35],b[29],b[23],b[17],b[11],b[5],out_p} ), +.out_n ( {d[53],d[47],d[41],d[35],d[29],d[23],d[17],d[11],d[5],out_n} ), +.co_p ( {a[59],a[53],a[47],a[41],a[35],a[29],a[23],a[17],a[11],a[5]} ), +.co_n ( {c[59],c[53],c[47],c[41],c[35],c[29],c[23],c[17],c[11],c[5]} ) +); + +io_cmos_nand_x4 xnand_x4 ( +.in_p ( a[59] ), +.in_n ( c[59] ), +.bk3 ( bk[63] ), +.bk2 ( bk[62] ), +.bk1 ( bk[61] ), +.bk0 ( bk[60] ), +.ci_p ( b63 ), +.ci_n ( d63 ), +.out_p ( b[59] ), +.out_n ( d[59] ), +.co_p ( a63 ), +.co_n ( c63 ) +); + +endmodule + + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x64_decode.v b/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x64_decode.v new file mode 100644 index 0000000..d86f452 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x64_decode.v @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// io_cmos_nand_x64_decode +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module io_cmos_nand_x64_decode ( +input [6:0] gray, +output [63:0] bk +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter NAND_DELAY = 20; + +wire [6:0] col; +wire [6:0] row; +wire [6:0] newcol; + +assign col[0] = gray[5] | gray[4] | gray[3]; +assign col[1] = gray[5] | gray[4]; +assign col[2] = gray[5] | ~(~gray[4] | gray[3]); +assign col[3] = gray[5]; +assign col[4] = ~gray[5] | ~(~gray[4] | gray[3]); +assign col[5] = ~gray[5] | gray[4]; +assign col[6] = ~gray[5] | gray[4] | gray[3]; + +assign row[0] = ~gray[2] & ~gray[1] & ~gray[0]; +assign row[1] = ~gray[2] & ~gray[1]; +assign row[2] = ~gray[2] & ~(gray[1] & ~gray[0]); +assign row[3] = ~gray[2]; +assign row[4] = ~(gray[2] & ~(gray[1] & ~gray[0])); +assign row[5] = ~(gray[2] & ~gray[1]); +assign row[6] = ~(gray[2] & ~gray[1] & ~gray[0]); + +assign newcol[0] = ~(col[0] | gray[6]); +assign newcol[1] = ~(col[1] | gray[6]); +assign newcol[2] = ~(col[2] | gray[6]); +assign newcol[3] = ~(col[3] | gray[6]); +assign newcol[4] = ~(~col[4] | gray[6]); +assign newcol[5] = ~(~col[5] | gray[6]); +assign newcol[6] = ~(~col[6] | gray[6]); + +assign bk[0] = ~(newcol[0] & row[0]); +assign bk[1] = ~(newcol[0] & row[1]); +assign bk[2] = ~(newcol[0] & row[2]); +assign bk[3] = ~(newcol[0] & row[3]); +assign bk[4] = ~(newcol[0] & row[4]); +assign bk[5] = ~(newcol[0] & row[5]); +assign bk[6] = ~(newcol[0] & row[6]); +assign bk[7] = ~newcol[0]; +assign bk[8] = ~(newcol[1] & ~(col[0] & row[6])); +assign bk[9] = ~(newcol[1] & ~(col[0] & row[5])); +assign bk[10] = ~(newcol[1] & ~(col[0] & row[4])); +assign bk[11] = ~(newcol[1] & ~(col[0] & row[3])); +assign bk[12] = ~(newcol[1] & ~(col[0] & row[2])); +assign bk[13] = ~(newcol[1] & ~(col[0] & row[1])); +assign bk[14] = ~(newcol[1] & ~(col[0] & row[0])); +assign bk[15] = ~newcol[1]; +assign bk[16] = ~(newcol[2] & (~col[1] | row[0])); +assign bk[17] = ~(newcol[2] & (~col[1] | row[1])); +assign bk[18] = ~(newcol[2] & (~col[1] | row[2])); +assign bk[19] = ~(newcol[2] & (~col[1] | row[3])); +assign bk[20] = ~(newcol[2] & (~col[1] | row[4])); +assign bk[21] = ~(newcol[2] & (~col[1] | row[5])); +assign bk[22] = ~(newcol[2] & (~col[1] | row[6])); +assign bk[23] = ~newcol[2]; +assign bk[24] = ~(newcol[3] & ~(col[2] & row[6])); +assign bk[25] = ~(newcol[3] & ~(col[2] & row[5])); +assign bk[26] = ~(newcol[3] & ~(col[2] & row[4])); +assign bk[27] = ~(newcol[3] & ~(col[2] & row[3])); +assign bk[28] = ~(newcol[3] & ~(col[2] & row[2])); +assign bk[29] = ~(newcol[3] & ~(col[2] & row[1])); +assign bk[30] = ~(newcol[3] & ~(col[2] & row[0])); +assign bk[31] = ~newcol[3]; +assign bk[32] = ~(newcol[4] & (~col[3] | row[0])); +assign bk[33] = ~(newcol[4] & (~col[3] | row[1])); +assign bk[34] = ~(newcol[4] & (~col[3] | row[2])); +assign bk[35] = ~(newcol[4] & (~col[3] | row[3])); +assign bk[36] = ~(newcol[4] & (~col[3] | row[4])); +assign bk[37] = ~(newcol[4] & (~col[3] | row[5])); +assign bk[38] = ~(newcol[4] & (~col[3] | row[6])); +assign bk[39] = ~newcol[4]; +assign bk[40] = ~(newcol[5] & ~(~col[4] & row[6])); +assign bk[41] = ~(newcol[5] & ~(~col[4] & row[5])); +assign bk[42] = ~(newcol[5] & ~(~col[4] & row[4])); +assign bk[43] = ~(newcol[5] & ~(~col[4] & row[3])); +assign bk[44] = ~(newcol[5] & ~(~col[4] & row[2])); +assign bk[45] = ~(newcol[5] & ~(~col[4] & row[1])); +assign bk[46] = ~(newcol[5] & ~(~col[4] & row[0])); +assign bk[47] = ~newcol[5]; +assign bk[48] = ~(newcol[6] & ( col[5] | row[0])); +assign bk[49] = ~(newcol[6] & ( col[5] | row[1])); +assign bk[50] = ~(newcol[6] & ( col[5] | row[2])); +assign bk[51] = ~(newcol[6] & ( col[5] | row[3])); +assign bk[52] = ~(newcol[6] & ( col[5] | row[4])); +assign bk[53] = ~(newcol[6] & ( col[5] | row[5])); +assign bk[54] = ~(newcol[6] & ( col[5] | row[6])); +assign bk[55] = ~newcol[6]; +assign bk[56] = gray[6] | (~col[6] & row[6]); +assign bk[57] = gray[6] | (~col[6] & row[5]); +assign bk[58] = gray[6] | (~col[6] & row[4]); +assign bk[59] = gray[6] | (~col[6] & row[3]); +assign bk[60] = gray[6] | (~col[6] & row[2]); +assign bk[61] = gray[6] | (~col[6] & row[1]); +assign bk[62] = gray[6] | (~col[6] & row[0]); +assign bk[63] = gray[6]; + +endmodule + + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_delay_line_dcc.v b/maib_rtl/io_common_custom/rtl/block_function/io_delay_line_dcc.v new file mode 100644 index 0000000..f730694 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_delay_line_dcc.v @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module io_delay_line_dcc ( +input c_in_p, +input c_in_n, +input [3:0] r_gray, +input [3:0] f_gray, +output c_out_p, +output c_out_n +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter STEP_DELAY = 40; + +reg c_in_del; + +wire [15:0] c_in_p_f; +wire [15:0] c_in_p_r; + +assign #63 c_in_p_f[0] = c_in_p; +assign #67 c_in_p_f[1] = c_in_p; +assign #71 c_in_p_f[2] = c_in_p; +assign #75 c_in_p_f[3] = c_in_p; +assign #79 c_in_p_f[4] = c_in_p; +assign #83 c_in_p_f[5] = c_in_p; +assign #87 c_in_p_f[6] = c_in_p; +assign #91 c_in_p_f[7] = c_in_p; +assign #95 c_in_p_f[8] = c_in_p; +assign #99 c_in_p_f[9] = c_in_p; +assign #103 c_in_p_f[10] = c_in_p; +assign #107 c_in_p_f[11] = c_in_p; +assign #111 c_in_p_f[12] = c_in_p; +assign #115 c_in_p_f[13] = c_in_p; +assign #119 c_in_p_f[14] = c_in_p; +assign #123 c_in_p_f[15] = c_in_p; + +assign #63 c_in_p_r[0] = c_in_p; +assign #67 c_in_p_r[1] = c_in_p; +assign #71 c_in_p_r[2] = c_in_p; +assign #75 c_in_p_r[3] = c_in_p; +assign #79 c_in_p_r[4] = c_in_p; +assign #83 c_in_p_r[5] = c_in_p; +assign #87 c_in_p_r[6] = c_in_p; +assign #91 c_in_p_r[7] = c_in_p; +assign #95 c_in_p_r[8] = c_in_p; +assign #99 c_in_p_r[9] = c_in_p; +assign #103 c_in_p_r[10] = c_in_p; +assign #107 c_in_p_r[11] = c_in_p; +assign #111 c_in_p_r[12] = c_in_p; +assign #115 c_in_p_r[13] = c_in_p; +assign #119 c_in_p_r[14] = c_in_p; +assign #123 c_in_p_r[15] = c_in_p; + +always @(*) + if (c_in_p == 1'b0) + begin + case (f_gray[3:0]) + 4'b0000 : c_in_del = c_in_p_f[0]; + 4'b0001 : c_in_del = c_in_p_f[1]; + 4'b0011 : c_in_del = c_in_p_f[2]; + 4'b0010 : c_in_del = c_in_p_f[3]; + 4'b0110 : c_in_del = c_in_p_f[4]; + 4'b0111 : c_in_del = c_in_p_f[5]; + 4'b0101 : c_in_del = c_in_p_f[6]; + 4'b0100 : c_in_del = c_in_p_f[7]; + 4'b1100 : c_in_del = c_in_p_f[8]; + 4'b1101 : c_in_del = c_in_p_f[9]; + 4'b1111 : c_in_del = c_in_p_f[10]; + 4'b1110 : c_in_del = c_in_p_f[11]; + 4'b1010 : c_in_del = c_in_p_f[12]; + 4'b1011 : c_in_del = c_in_p_f[13]; + 4'b1001 : c_in_del = c_in_p_f[14]; + 4'b1000 : c_in_del = c_in_p_f[15]; + default : c_in_del = c_in_p_f[0]; + endcase + end + else if (c_in_p == 1'b1) + begin + case (r_gray[3:0]) + 4'b0000 : c_in_del = c_in_p_r[0]; + 4'b0001 : c_in_del = c_in_p_r[1]; + 4'b0011 : c_in_del = c_in_p_r[2]; + 4'b0010 : c_in_del = c_in_p_r[3]; + 4'b0110 : c_in_del = c_in_p_r[4]; + 4'b0111 : c_in_del = c_in_p_r[5]; + 4'b0101 : c_in_del = c_in_p_r[6]; + 4'b0100 : c_in_del = c_in_p_r[7]; + 4'b1100 : c_in_del = c_in_p_r[8]; + 4'b1101 : c_in_del = c_in_p_r[9]; + 4'b1111 : c_in_del = c_in_p_r[10]; + 4'b1110 : c_in_del = c_in_p_r[11]; + 4'b1010 : c_in_del = c_in_p_r[12]; + 4'b1011 : c_in_del = c_in_p_r[13]; + 4'b1001 : c_in_del = c_in_p_r[14]; + 4'b1000 : c_in_del = c_in_p_r[15]; + default : c_in_del = c_in_p_r[0]; + endcase + end + +assign c_out_p = c_in_del; +assign c_out_n = ~c_in_del; + +endmodule + +//====================================================================== +// r_dly(f_gray=4'b0) f_dly(r_gray=4'b0) +// wc tt bc wc tt bc +//0 8.95E-11 5.99E-11 4.78E-11 9.34E-11 6.25E-11 5.04E-11 +//1 9.17E-11 6.20E-11 5.03E-11 9.55E-11 6.45E-11 5.25E-11 +//2 9.60E-11 6.53E-11 5.35E-11 9.75E-11 6.67E-11 5.51E-11 +//3 9.86E-11 6.81E-11 5.70E-11 1.00E-10 6.93E-11 5.83E-11 +//4 1.03E-10 7.21E-11 6.13E-11 1.03E-10 7.22E-11 6.22E-11 +//5 1.06E-10 7.58E-11 6.66E-11 1.06E-10 7.57E-11 6.74E-11 +//6 1.11E-10 8.06E-11 7.26E-11 1.09E-10 7.98E-11 7.31E-11 +//7 1.15E-10 8.57E-11 8.19E-11 1.13E-10 8.49E-11 8.23E-11 +//8 1.20E-10 9.18E-11 9.16E-11 1.18E-10 9.06E-11 9.20E-11 +//9 1.23E-10 9.51E-11 9.89E-11 1.20E-10 9.39E-11 9.94E-11 +//10 1.25E-10 9.90E-11 1.06E-10 1.22E-10 9.73E-11 1.06E-10 +//11 1.28E-10 1.03E-10 1.18E-10 1.25E-10 1.01E-10 1.18E-10 +//12 1.31E-10 1.08E-10 1.29E-10 1.28E-10 1.06E-10 1.29E-10 +//13 1.34E-10 1.13E-10 1.51E-10 1.31E-10 1.11E-10 1.51E-10 +//14 1.37E-10 1.18E-10 1.73E-10 1.34E-10 1.16E-10 1.73E-10 +//15 1.41E-10 1.25E-10 2.74E-10 1.37E-10 1.23E-10 2.76E-10 +// diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_dll_custom.v b/maib_rtl/io_common_custom/rtl/block_function/io_dll_custom.v new file mode 100644 index 0000000..8968696 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_dll_custom.v @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #3 $ +// Date: $DateTime: 2015/06/30 10:09:02 $ +//------------------------------------------------------------------------ +// Description: IO DLL TOP +// +//------------------------------------------------------------------------ + + +module io_dll_custom +#( +//----------------------------------------------------------------------------------------------------------------------- +// delay chain parameters +//----------------------------------------------------------------------------------------------------------------------- +parameter NAND_DELAY = 20, +parameter FF_DELAY = 200 +) +( + input launch, // Decode from gate_shf, Used as the input to the delay line + input measure, // Decode from gate_shf, Used as the clock for the phase detector + input [6:0] f_gray, // gray code for nand delay chain + input [2:0] i_gray, // gray code for phase interpolator + input dll_reset_n, + input nfrzdrv, + input wire osc_mode, // Mux control for the x64 ring oscillator + input wire osc_in_p, // input for the x64 ring oscillator + input wire osc_in_n, // input for the x64 ring oscillator + output wire osc_out_p, // output for the x64 ring oscillator + output wire osc_out_n, // output for the x64 ring oscillator + output t_up, // output of phase detector + output t_down // output of phase detector +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +//---------------------------------------------------------------------------------------------------------------------------------------------------------------- +// wire & reg +//---------------------------------------------------------------------------------------------------------------------------------------------------------------- + + wire i_del_p; // delay chain output + wire i_del_n; // delay chain output + wire phase_clk; // clock for phase detector + wire phase_clkb; // complementary clock for phase detector + wire launch_p; // Decode from gate_shf, Used as the input to the delay line + wire launch_n; // Decode from gate_shf, Used as the complementary input to the delay line + wire measure_p; // Decode from gate_shf, Used as the clock for the phase detector + wire measure_n; // Decode from gate_shf, Used as the complementary clock for the phase detector + +//----------------------------------------------------------------------------------------------------------------------- +// custom design portion +//----------------------------------------------------------------------------------------------------------------------- + +//----------------------------------------------------------------------------------------------------------------------- +// split and align: +//----------------------------------------------------------------------------------------------------------------------- + +io_split_align xsplit_align_0 ( +.din ( launch ), // input +.dout_p ( launch_p ), // splitted output positive +.dout_n ( launch_n ) // splitted output negative +); + +io_split_align xsplit_align_1 ( +.din ( measure ), // input +.dout_p ( measure_p ), // splitted output positive +.dout_n ( measure_n ) // splitted output negative +); + +//----------------------------------------------------------------------------------------------------------------------- +// delay line: +//----------------------------------------------------------------------------------------------------------------------- + +io_nand_x128_delay_line xdelay_line ( + .nfrzdrv ( nfrzdrv ), + .in_p ( launch_p ), + .in_n ( launch_n ), + .osc_mode ( osc_mode ), + .osc_in_p ( osc_in_p ), + .osc_in_n ( osc_in_n ), + .osc_out_p ( osc_out_p ), + .osc_out_n ( osc_out_n ), + .f_gray ( f_gray[6:0] ), + .i_gray ( i_gray[2:0] ), + .out_p ( i_del_p ), + .out_n ( i_del_n ) +); + +io_nand_delay_line_min xdelay_line_match ( + .nfrzdrv ( nfrzdrv ), + .in_p ( measure_p ), + .in_n ( measure_n ), + .out_p ( phase_clk ), + .out_n ( phase_clkb ) +); + +//----------------------------------------------------------------------------------------------------------------------- +// phase_detector : +//----------------------------------------------------------------------------------------------------------------------- + +//assign #INTRINSIC_DELAY phase_clk = measure; +//assign #INTRINSIC_DELAY phase_clkb = measureb; + +io_dll_phdet xdll_phdet ( + .i_del_p ( i_del_p ), + .i_del_n ( i_del_n ), + .phase_clk ( phase_clk ), + .phase_clkb ( phase_clkb ), + .dll_reset_n ( dll_reset_n ), + .t_up ( t_up ), + .t_down ( t_down ) +); + +endmodule // io_dll_custom diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_dll_phdet.v b/maib_rtl/io_common_custom/rtl/block_function/io_dll_phdet.v new file mode 100644 index 0000000..18aeeb1 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_dll_phdet.v @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #4 $ +// Date: $DateTime: 2015/06/09 19:56:18 $ +//------------------------------------------------------------------------ +// Description: IO DLL PHASE DETECTOR +// +//------------------------------------------------------------------------ + + +module io_dll_phdet ( + input wire i_del_p, // phase detector input, from delay chain output + input wire i_del_n, // phase detector complementary input, from delay chain output + input wire phase_clk, // clock for phase detector + input wire phase_clkb, // complementary clock for phase detector + input wire dll_reset_n, + output wire t_up, // output of phase detector + output wire t_down // output of phase detector +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +/* +always @(posedge phase_clk or negedge dll_reset_n) + if (~dll_reset_n) {t_up,t_down} <= #FF_DELAY 2'b00; + else if ({i_del_p,i_del_n} == 2'b10) {t_up,t_down} <= #FF_DELAY 2'b10; + else if ({i_del_p,i_del_n} == 2'b01) {t_up,t_down} <= #FF_DELAY 2'b01; + else {t_up,t_down} <= #FF_DELAY 2'b00; +*/ + +an_io_phdet_ff_ln xsampling_up ( + .dp(i_del_p), + .dn(i_del_n), + .clk_p(phase_clk), + .rst_n(dll_reset_n), + .q(t_up) +); + +an_io_phdet_ff_ln xsampling_dn ( + .dp(phase_clkb), + .dn(phase_clk), + .clk_p(i_del_n), + .rst_n(dll_reset_n), + .q(t_down) +); + +endmodule // io_dll_phdet diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_dly_interpclk.v b/maib_rtl/io_common_custom/rtl/block_function/io_dly_interpclk.v new file mode 100644 index 0000000..a4f0a18 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_dly_interpclk.v @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// io_dly_interpclk +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module io_dly_interpclk ( +input nfrzdrv, +input fout_p, +input fout_n, +output a_in_p, +output b_in_p, +output c_in_p, +output a_in_n, +output b_in_n, +output c_in_n +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter NAND_DELAY = 20; + +assign #(0 * NAND_DELAY) a_in_p = nfrzdrv? fout_p : 1'b0; +assign #(2 * NAND_DELAY) b_in_p = nfrzdrv? fout_p : 1'b0; +assign #(4 * NAND_DELAY) c_in_p = nfrzdrv? fout_p : 1'b0; + +assign #(0 * NAND_DELAY) a_in_n = nfrzdrv? fout_n : 1'b1; +assign #(2 * NAND_DELAY) b_in_n = nfrzdrv? fout_n : 1'b1; +assign #(4 * NAND_DELAY) c_in_n = nfrzdrv? fout_n : 1'b1; + +/* +io_interp_basecap xxcapap ( +.cin (a_in_p ) +); + +io_interp_basecap xxcapbp ( +.cin (b_in_p ) +); + +io_interp_basecap xxcapcp ( +.cin (c_in_p ) +); + +io_interp_basecap xxcapan ( +.cin (a_in_n ) +); + +io_interp_basecap xxcapbn ( +.cin (b_in_n ) +); + +io_interp_basecap xxcapcn ( +.cin (c_in_n ) +); + +*/ + +endmodule + + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_dly_interpolator.v b/maib_rtl/io_common_custom/rtl/block_function/io_dly_interpolator.v new file mode 100644 index 0000000..b2b3547 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_dly_interpolator.v @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// io_dly_interpolator +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module io_dly_interpolator ( +input nfrzdrv, +input fout_p, +input fout_n, +input [2:0] gray, +output out_p, +output out_n, +output osc_out_p, +output osc_out_n +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter NAND_DELAY = 20; + +wire a_in_p; +wire b_in_p; +wire c_in_p; +wire a_in_n; +wire b_in_n; +wire c_in_n; +wire out_pb; +wire out_nb; +wire x_p; +wire x_n; +wire x_pb; +wire x_nb; +wire [6:0] sn; +reg [6:0] sp; + +io_dly_interpclk xio_dly_interpclk ( +.nfrzdrv (nfrzdrv ), +.fout_p (fout_p ), +.fout_n (fout_n ), +.a_in_p (a_in_p ), +.b_in_p (b_in_p ), +.c_in_p (c_in_p ), +.a_in_n (a_in_n ), +.b_in_n (b_in_n ), +.c_in_n (c_in_n ) +); + +always @(*) + case (gray[2:0]) + 3'b000 : sp[6:0] = 7'b000_0000; + 3'b001 : sp[6:0] = 7'b000_0001; + 3'b011 : sp[6:0] = 7'b000_0011; + 3'b010 : sp[6:0] = 7'b000_0111; + 3'b110 : sp[6:0] = 7'b000_1111; + 3'b111 : sp[6:0] = 7'b001_1111; + 3'b101 : sp[6:0] = 7'b011_1111; + 3'b100 : sp[6:0] = 7'b111_1111; + endcase + +assign sn[6:0] = ~sp[6:0]; + +io_ip8phs_3in xio_ip8phs_3in_n ( +.a_in ( a_in_n ), +.b_in ( b_in_n ), +.c_in ( c_in_n ), +.svcc ( 1'b1 ), +.sp ( sp[6:0] ), +.sn ( sn[6:0] ), +.clk_outb ( out_nb ) +); + +io_ip8phs_3in xio_ip8phs_3in_p ( +.a_in ( a_in_p ), +.b_in ( b_in_p ), +.c_in ( c_in_p ), +.svcc ( 1'b1 ), +.sp ( sp[6:0] ), +.sn ( sn[6:0] ), +.clk_outb ( out_pb ) +); + +assign x_p = ~out_pb; +assign x_n = ~out_nb; +//cross couple +assign x_pb = ~x_p; +assign x_nb = ~x_n; +assign out_p = ~x_pb; +assign out_n = ~x_nb; +assign osc_out_p = ~x_pb; +assign osc_out_n = ~x_nb; + +/* +`ifdef LEC +assign x_p = ~x_n; +assign x_n = ~x_p; +`endif +*/ + +endmodule + + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_dq_clkdrv.v b/maib_rtl/io_common_custom/rtl/block_function/io_dq_clkdrv.v new file mode 100644 index 0000000..40d86ce --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_dq_clkdrv.v @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #1 $ +// Date: $DateTime: 2014/11/15 16:17:29 $ +//------------------------------------------------------------------------ +// Description: smaller size dq/dqs driver +// +//------------------------------------------------------------------------ + +module io_dq_clkdrv ( +input din_p, // +input din_n, // +output dout_p, // +output dout_n // +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter INV_DELAY = 15; // 15ps + +assign #(4 * INV_DELAY) dout_p = din_p; +assign #(4 * INV_DELAY) dout_n = din_n; + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_dqs_clkdrv.v b/maib_rtl/io_common_custom/rtl/block_function/io_dqs_clkdrv.v new file mode 100644 index 0000000..bb1cf8d --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_dqs_clkdrv.v @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #1 $ +// Date: $DateTime: 2014/11/15 16:17:29 $ +//------------------------------------------------------------------------ +// Description: big size dqs driver +// +//------------------------------------------------------------------------ + +module io_dqs_clkdrv ( +input cin_p, // +input cin_n, // +output cout_p, // +output cout_n // +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter INV_DELAY = 15; // 15ps + +assign #(4 * INV_DELAY) cout_p = cin_p; +assign #(4 * INV_DELAY) cout_n = cin_n; + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_dqs_custom.v b/maib_rtl/io_common_custom/rtl/block_function/io_dqs_custom.v new file mode 100644 index 0000000..9224834 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_dqs_custom.v @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//==================================================================== +// Module : io_dqs_lgc_top +// Filename : io_dqs_lgc_top.v +// Description: DQS Logic Block +// Note : +// +//==================================================================== + +module io_dqs_custom ( + input [7:0] phy_clk_phs, // PLL : full rate 8 phase clock + input [1:0] dqs_clean_a, // DQS : DQS complimentary output after the clean up gate + input [1:0] dqs_clean_b, // DQS : DQS complimentary output after the clean up gate + input x128_osc_in_p, // DLL : input for the x64 ring oscillator + input x128_osc_in_n, // DLL : input for the x64 ring oscillator + output x128_osc_out_p, // IOEREG : output for the x64 ring oscillator + output x128_osc_out_n, // IOEREG : output for the x64 ring oscillator + output x128_osc_lca_p, // x128 ring oscillator A + output x128_osc_lca_n, // x128 ring oscillator A + input x128_osc_lcb_p, // x128 ring oscillator B + input x128_osc_lcb_n, // x128 ring oscillator B + input [6:0] dqs_f_gray_a, // delay control of "a" delay chain ( NAND chain ) + input [2:0] dqs_i_gray_a, // delay control of "a" delay chain ( Interpolator ) + input [3:0] dqs_rise_gray_a, // Delay : Gray code rising edge dcc setting + input [3:0] dqs_fall_gray_a, // Delay : Gray code falling edge dcc setting + input [6:0] dqs_f_gray_b, // delay control of "b" delay chain ( NAND chain ) + input [2:0] dqs_i_gray_b, // delay control of "b" delay chain ( Interpolator ) + input [3:0] dqs_rise_gray_b, // Delay : Gray code rising edge dcc setting + input [3:0] dqs_fall_gray_b, // Delay : Gray code falling edge dcc setting + input osc_mode, // Mux control for the x64 ring oscillator, 1 = osc test, 0 = normal + output [1:0] dqs_out_a, // DQS tree : DQS complimentary clock to the DQS clock tree -- dqs_clk_a[1] = dqs+, dqs_clk_a[0] = dqs- + output [1:0] dqs_out_b, // DQS tree : DQS complimentary clock to the DQS clock tree -- dqs_clk_a[1] = dqs+, dqs_clk_a[0] = dqs- + input nfrzdrv, + input reset_n, // Reset block : System reset active low + input [2:0] power_down_n, // 0 = power down, 1 = power up + input [1:0] rb_filter_code, // 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz ( Interpolator filter setting ) + input [2:0] mux_sel_a_a, // The gray code to control (even) of the 8 to 1 phase multiplexer + input [2:0] mux_sel_b_a, // The gray code to control (odd ) of the 8 to 1 phase multiplexer + input [3:0] interp_sel_a_a, // The gray code output to control the interpolator + input [3:0] interp_sel_b_a, // The gray code output to control the interpolator + input [1:0] dirty_clk_out_a, // pass through code is 2'b01, disable code is 2'b00, divider is dynamic + output int_clk_a, // Clocks from the output of the 3 (8 to 1 phase select multiplexers) clk_p[0] arrives first, clk_p[2] arrives last + output [1:0] interp_clk_out_a, // Complimentary Clock output + input [2:0] mux_sel_a_b, // The gray code to control (even) of the 8 to 1 phase multiplexer + input [2:0] mux_sel_b_b, // The gray code to control (odd ) of the 8 to 1 phase multiplexer + input [3:0] interp_sel_a_b, // The gray code output to control the interpolator + input [3:0] interp_sel_b_b, // The gray code output to control the interpolator + input [1:0] dirty_clk_out_b, // pass through code is 2'b01, disable code is 2'b00, divider is dynamic + output int_clk_b, // Clocks from the output of the 3 (8 to 1 phase select multiplexers) clk_p[0] arrives first, clk_p[2] arrives last + output [1:0] interp_clk_out_b, // Complimentary Clock output + input test_enable, // Active high test enable 1: avoid tristate on output of interp_mux during testing + input rb_couple_enable, // Active high cross couple enable + output [7:0] phy_clk_phs_lane_out, // domain crossed and buffered phy_clk_phs + output clk_ph_1_buf, // min-delayed phy_clk_phs[0], used by the io_dqs_en_path and ioereg write fifo for clock domain crossing + output clk_ph_3_buf // min-delayed phy_clk_phs[2], used by the io_dqs_en_path and ioereg write fifo for clock domain crossing +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +//================================================================================================================================================================ +// wire & reg +//================================================================================================================================================================ + + wire [1:0] dqs_out_a_int; // DQS tree before dcc: DQS complimentary clock to the DQS clock tree -- dqs_clk_a[1] = dqs+, dqs_clk_a[0] = dqs- + wire [1:0] dqs_out_b_int; // DQS tree before dcc: DQS complimentary clock to the DQS clock tree -- dqs_clk_a[1] = dqs+, dqs_clk_a[0] = dqs- + +//========================================================================================================================================================================= +// Delay chain +//========================================================================================================================================================================= + +io_nand_x128_delay_line xio_nand_x128_delay_line_a ( +.nfrzdrv ( nfrzdrv ), +.in_p ( dqs_clean_a[1] ), +.in_n ( dqs_clean_a[0] ), +.osc_mode ( osc_mode ), +.osc_in_p ( x128_osc_in_p ), +.osc_in_n ( x128_osc_in_n ), +.osc_out_p ( x128_osc_lca_p ), +.osc_out_n ( x128_osc_lca_n ), +.f_gray ( dqs_f_gray_a[6:0] ), +.i_gray ( dqs_i_gray_a[2:0] ), +.out_p ( dqs_out_a_int[0] ), // Swap, invert the output here +.out_n ( dqs_out_a_int[1] ) // Swap, invert the output here +); + +io_nand_x128_delay_line xio_nand_x128_delay_line_b ( +.nfrzdrv ( nfrzdrv ), +.in_p ( dqs_clean_b[1] ), +.in_n ( dqs_clean_b[0] ), +.osc_mode ( osc_mode ), +.osc_in_p ( x128_osc_lcb_p ), +.osc_in_n ( x128_osc_lcb_n ), +.osc_out_p ( x128_osc_out_p ), +.osc_out_n ( x128_osc_out_n ), +.f_gray ( dqs_f_gray_b[6:0] ), +.i_gray ( dqs_i_gray_b[2:0] ), +.out_p ( dqs_out_b_int[0] ), // Swap, invert the output here +.out_n ( dqs_out_b_int[1] ) // Swap, invert the output here +); + +//========================================================================================================================================================================= +// Phase interpolator +//========================================================================================================================================================================= + +io_phs_gated xio_phs_gated ( +.nfrzdrv ( nfrzdrv ), // active low +.phy_clk_phs ( phy_clk_phs[7:0] ), // 8 phase 1.6GHz local clock +.phy_clk_phs_gated ( phy_clk_phs_lane_out[7:0] ) // gated 8 phase 1.6GHz local clock +); + +io_interpolator xio_interpolator_a ( +.reset_n ( reset_n ), +.nfrzdrv ( nfrzdrv ), +.pdn ( power_down_n[0] ), // power down active low +.phy_clk_phs ( phy_clk_phs_lane_out[7:0]), // 8 phase 1.6GHz local clock +.rb_filter_code ( rb_filter_code[1:0] ), // LANE CSR : 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz ( Interpolator filter setting ) +.mux_sel_a ( mux_sel_a_a[2:0] ), // The gray code to control (even) of the 8 to 1 phase multiplexer +.mux_sel_b ( mux_sel_b_a[2:0] ), // The gray code to control (odd ) of the 8 to 1 phase multiplexer +.interp_sel_a ( interp_sel_a_a[3:0] ), // The gray code output to control the interpolator +.interp_sel_b ( interp_sel_b_a[3:0] ), // The gray code output to control the interpolator +.dirty_clk ( dirty_clk_out_a[1:0] ), // pass through code is 2'b01, disable code is 2'b00, divider is dynamic +.enable ( nfrzdrv ), // Active high enable 0 = Force interpolator_clk[1:0] to 2'b10 +.test_enable ( test_enable ), // +.rb_couple_enable ( rb_couple_enable ), // +.int_clk ( int_clk_a ), // Clock for the counter +.clk_out ( interp_clk_out_a[1:0] ), // Complimentary Clock output sent to the dqs_lgc_pnr +.interpolator_clk ( ) // Complimentary Clock output sent to the pstamble_reg, not used any more since pstabmle in pnr now +); + +io_interpolator xio_interpolator_b ( +.reset_n ( reset_n ), +.nfrzdrv ( nfrzdrv ), +.pdn ( power_down_n[1] ), // power down active low +.phy_clk_phs ( phy_clk_phs_lane_out[7:0]), // 8 phase 1.6GHz local clock +.rb_filter_code ( rb_filter_code[1:0] ), // LANE CSR : 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz ( Interpolator filter setting ) +.mux_sel_a ( mux_sel_a_b[2:0] ), // The gray code to control (even) of the 8 to 1 phase multiplexer +.mux_sel_b ( mux_sel_b_b[2:0] ), // The gray code to control (odd ) of the 8 to 1 phase multiplexer +.interp_sel_a ( interp_sel_a_b[3:0] ), // The gray code output to control the interpolator +.interp_sel_b ( interp_sel_b_b[3:0] ), // The gray code output to control the interpolator +.dirty_clk ( dirty_clk_out_b[1:0] ), // pass through code is 2'b01, disable code is 2'b00, divider is dynamic +.enable ( nfrzdrv ), // Active high enable 0 = Force interpolator_clk[1:0] to 2'b10 +.test_enable ( test_enable ), // +.rb_couple_enable ( rb_couple_enable ), // +.int_clk ( int_clk_b ), // Clock for the counter +.clk_out ( interp_clk_out_b[1:0] ), // Complimentary Clock output sent to the dqs_lgc_pnr +.interpolator_clk ( ) // Complimentary Clock output sent to the pstamble_reg, not used any more since pstabmle in pnr now +); + +io_min_inter xio_min_inter_1 ( +.phy_clk_phs ( phy_clk_phs_lane_out[7:0]), +.rb_filter_code ( rb_filter_code[1:0] ), +.test_enable ( test_enable ), +.rb_couple_enable ( rb_couple_enable ), +.nfrzdrv ( nfrzdrv ), +.pdn ( power_down_n[2] ), +.c_out ( clk_ph_1_buf ) +); + +io_min_inter xio_min_inter_3 ( +.phy_clk_phs ( {phy_clk_phs_lane_out[1:0], phy_clk_phs_lane_out[7:2]} ), +.rb_filter_code ( rb_filter_code[1:0] ), +.test_enable ( test_enable ), +.rb_couple_enable ( rb_couple_enable ), +.nfrzdrv ( nfrzdrv ), +.pdn ( power_down_n[2] ), +.c_out ( clk_ph_3_buf ) +); + +io_delay_line_dcc xio_delay_line_dcc_a ( +.c_in_p ( dqs_out_a_int[0] ), +.c_in_n ( dqs_out_a_int[1] ), +.f_gray ( dqs_fall_gray_a[3:0] ), +.r_gray ( dqs_rise_gray_a[3:0] ), +.c_out_p ( dqs_out_a[0] ), +.c_out_n ( dqs_out_a[1] ) +); + +io_delay_line_dcc xio_delay_line_dcc_b ( +.c_in_p ( dqs_out_b_int[0] ), +.c_in_n ( dqs_out_b_int[1] ), +.f_gray ( dqs_fall_gray_b[3:0] ), +.r_gray ( dqs_rise_gray_b[3:0] ), +.c_out_p ( dqs_out_b[0] ), +.c_out_n ( dqs_out_b[1] ) +); + +endmodule diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_filter_dec.v b/maib_rtl/io_common_custom/rtl/block_function/io_filter_dec.v new file mode 100644 index 0000000..0b0df8a --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_filter_dec.v @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #1 $ +// Date: $DateTime: 2014/09/20 12:06:43 $ +//------------------------------------------------------------------------ +// Description: 16 phase interpolator min +// +//------------------------------------------------------------------------ + +module io_filter_dec ( +input [1:0] filter_code, // 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz +output [3:1] scp, +output reg [3:1] scn +); + +//filter code decode + +always @(*) + case (filter_code[1:0]) + 2'b00 : scn[3:1] = 3'b000; + 2'b01 : scn[3:1] = 3'b001; + 2'b10 : scn[3:1] = 3'b011; + 2'b11 : scn[3:1] = 3'b111; + endcase +assign scp[3:1] = ~scn[3:1]; + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_interp_latch_in.v b/maib_rtl/io_common_custom/rtl/block_function/io_interp_latch_in.v new file mode 100644 index 0000000..5934849 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_interp_latch_in.v @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +// io_interp_latch_in : mux_sel latches +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +module io_interp_latch_in ( +input l_reset_n, // Active low reset +input clk, // clock for latch +input [2:0] mux_sel_in, // The gray code to control (even) of the 8 to 1 phase multiplexer +output reg [2:0] mux_sel_latch, // latched gray code to control (even) of the 8 to 1 phase multiplexer +output [2:0] mux_sel_buf, // buffered gray code to control (even) of the 8 to 1 phase multiplexer +output [2:0] mux_sel_inv // inverted gray code to control (even) of the 8 to 1 phase multiplexer +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter INV_DELAY = 15; // 15ps +parameter LATCH_DELAY = 50; // 50ps +parameter BUF_DELAY = 25; // 25ps +parameter MUX_DELAY = 50; // 50ps + +//========================================================================================================================================================================= +// io_interpolator_mux selects 3 of the 8 input clock phases (A complimentary set) +//========================================================================================================================================================================= + +always @(*) + if (~l_reset_n) mux_sel_latch[2:0] <= #LATCH_DELAY 3'h0; + else if (clk) mux_sel_latch[2:0] <= #LATCH_DELAY mux_sel_in[2:0]; + +assign mux_sel_buf = mux_sel_latch[2:0]; +assign mux_sel_inv = ~mux_sel_latch[2:0]; + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_interp_misc.v b/maib_rtl/io_common_custom/rtl/block_function/io_interp_misc.v new file mode 100644 index 0000000..81112f2 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_interp_misc.v @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +// io_interp_misc : misc block for interpolator +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +module io_interp_misc ( +input reset_n, // Active low reset +input test_enable, // Active high test enable 1: avoid tristate on output of interp_mux during testing +input nfrzdrv, // for power domain crossing protection +input couple_enable, // cross coupling enable +input filter_code, // borrowed from filter_code[0] for test +input clk_p_buf0, // Clock for pnr int_clk +input [1:0] int_clk_out, // interpolator clock for pnr/dpa +input [7:0] phy_clk_phs, // 8 phase 1.6GHz local clock +output [7:0] slow_clk_ph_p, // 8 phase 1.6GHz local clock +output [7:0] slow_clk_ph_n, // 8 phase 1.6GHz local clock +output test_enable_buf, // Active high test enable 1: avoid tristate on output of interp_mux during testing +output test_enable_frz, // Active high test enable 1: avoid tristate on output of interp_mux during testing +output test_enable_n, // Active low test enable 0: avoid tristate on output of interp_mux during testing +output l_reset_n, // Active low reset +output [1:0] clk_out, // interpolator clock for pnr/dpa +output dft_mux_sel_n, // for test +output dft_mux_sel_p, // for test +output pon, // cross couple control for p fingers +output non, // cross couple control for n fingers +output int_clk // Clock for the counter +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter INV_DELAY = 15; // 15ps +parameter LATCH_DELAY = 50; // 50ps +parameter BUF_DELAY = 25; // 25ps +parameter MUX_DELAY = 50; // 50ps + +wire test_rst_p; +wire test_rst_n; + +assign #(2 * INV_DELAY) clk_out[1:0] = int_clk_out[1:0] & {2{nfrzdrv}}; +assign #(2 * INV_DELAY) int_clk = clk_p_buf0 & nfrzdrv; +assign l_reset_n = reset_n; +assign test_enable_n = ~test_enable; +assign test_enable_buf = ~test_enable_n; +assign test_enable_frz = ~(test_enable_n & nfrzdrv); +assign test_rst_n = test_enable_n & reset_n; +assign test_rst_p = ~test_rst_n; +assign #(3 * INV_DELAY) slow_clk_ph_p[7:0] = phy_clk_phs[7:0] | {8{test_rst_p}} | {8{~nfrzdrv}}; +assign #(3 * INV_DELAY) slow_clk_ph_n[7:0] = phy_clk_phs[7:0] & {8{test_rst_n}} & {8{nfrzdrv}}; +assign dft_mux_sel_p = ~(~filter_code & test_enable_buf); +assign dft_mux_sel_n = ~(filter_code & test_enable_buf); +assign non = couple_enable & test_enable_n; +assign pon = ~non; + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_interp_mux.v b/maib_rtl/io_common_custom/rtl/block_function/io_interp_mux.v new file mode 100644 index 0000000..dea9a3f --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_interp_mux.v @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #2 $ +// Date: $DateTime: 2014/10/18 21:47:06 $ +//------------------------------------------------------------------------ +// Description: interpolator mux +// +//------------------------------------------------------------------------ + +module io_interp_mux ( + +input [7:0] phy_clk_phs, // 8 phase 1.6GHz clock +input [7:0] slow_clk_ph_p, // 8 phase 1.6GHz clock combined with reset +input [7:0] slow_clk_ph_n, // 8 phase 1.6GHz clock combined with reset +input [2:0] gray_a_buf, // Mux select A +input [2:0] gray_a_inv, // inverted Mux select A +input [2:0] gray_b_buf, // Mux select B +input [2:0] gray_b_inv, // inverted Mux select B +input test_enable_n, // active low test enable +input dft_mux_sel, // mux selection during test +output c_out, // 1 of the 3 output phases, sent to the interpolator +output mux_out_b // 1 of the 3 output phases, sent to other logic +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter NAND_DELAY = 17; // 17ps +parameter NOR_DELAY = 22; // 22ps +parameter INV_DELAY = 12; // 10ps +parameter MUX_DELAY = 40; // 35ps +parameter BUF_DELAY = 20; // 16ps +parameter FINGER_DELAY = 55; // 55ps + +//wire [7:0] slow_clk_ph; //move to io_interpolator +reg [7:0] dc_a,dc_b; +wire [7:0] amx; +wire [7:0] ap; +reg [7:0] en,ep; +wire [7:0] xn,sn,xp,sp; +wire c_out_n; +wire c_out_int_n; +wire c_out_p; +wire c_out_int_p; +wire c_out_n_mux; + +//----------------------------------------------------------------------------------------------------------------------------- +// This circuit is used to mux out 2 of the clock phases and not glitch during the transition to the next clock phase. +// The circuit must stretch the output and not glitch the output. +//----------------------------------------------------------------------------------------------------------------------------- +// ___________________ ___________________ ___________________ +// clk_ph[0] ________/ \___________________/ \___________________/ \___ +// ___________________ ___________________ __________________ +// clk_ph[1] _____________/ \___________________/ \___________________/ +// ___________________ ___________________ _____________ +// clk_ph[2] __________________/ \___________________/ \___________________/ +// ___ ___________________ ___________________ ________ +// clk_ph[3] \___________________/ \___________________/ \___________________/ +// ________ ___________________ ___________________ ___ +// clk_ph[4] \___________________/ \___________________/ \___________________/ +// __________ _____________________________ ___________ +// clk_out \_____________________________/ \_____________________________/ +// ______________________________ +// en[0] \_________________________________________________________________________________ +// ____________________________________________________________________________________________________ +// ep[0] ___________/ +// _____________________________ +// en[2] ___________/ \______________________________________________________________________ +// ___________________ _____________________________________________________ +// ep[2] *******\______________________________________/ +// _______________________________________ +// en[4] __________________________________________*******/ \______________________ +// _________________________________________ ________________________________________ +// ep[4] \_____________________________/ +// +//----------------------------------------------------------------------------------------------------------------------------- + +//-------------------------------------------------------------------------------------------------- +// clk_ph buffers +//-------------------------------------------------------------------------------------------------- + +//assign #(2 * INV_DELAY) slow_clk_ph[7:0] = phy_clk_phs[7:0]; //move to io_interpolator + +//-------------------------------------------------------------------------------------------------- +// Decoder of the gray_sel input +//-------------------------------------------------------------------------------------------------- + +always @(*) + case (gray_a_buf[2:0]) + 3'b000 : dc_a[7:0] = 8'b0000_0001; + 3'b001 : dc_a[7:0] = 8'b0000_0010; + 3'b011 : dc_a[7:0] = 8'b0000_0100; + 3'b010 : dc_a[7:0] = 8'b0000_1000; + 3'b110 : dc_a[7:0] = 8'b0001_0000; + 3'b111 : dc_a[7:0] = 8'b0010_0000; + 3'b101 : dc_a[7:0] = 8'b0100_0000; + 3'b100 : dc_a[7:0] = 8'b1000_0000; + endcase + +always @(*) + case (gray_b_buf[2:0]) + 3'b000 : dc_b[7:0] = 8'b0000_0001; + 3'b001 : dc_b[7:0] = 8'b0000_0010; + 3'b011 : dc_b[7:0] = 8'b0000_0100; + 3'b010 : dc_b[7:0] = 8'b0000_1000; + 3'b110 : dc_b[7:0] = 8'b0001_0000; + 3'b111 : dc_b[7:0] = 8'b0010_0000; + 3'b101 : dc_b[7:0] = 8'b0100_0000; + 3'b100 : dc_b[7:0] = 8'b1000_0000; + endcase + +assign #MUX_DELAY amx[7:0] = c_out_int_p ? dc_b[7:0] : dc_a[7:0]; + +assign #INV_DELAY ap[7:0] = ~amx[7:0]; +//assign #BUF_DELAY an[7:0] = amx[7:0]; + +//-------------------------------------------------------------------------------------------------- +// Finger enable for out[0] +//-------------------------------------------------------------------------------------------------- + +assign #NAND_DELAY xn[7:0] = ~({8{c_out_int_n}} & slow_clk_ph_n[7:0]); +assign #NAND_DELAY sn[7:0] = ~(amx[7:0] & xn[7:0]) ; + +always @(*) + if ( ~sn[0] ) en[0] <= #NAND_DELAY 1'b1; + else if ( ~slow_clk_ph_n[0] ) en[0] <= #NAND_DELAY 1'b0; + else if ( ~ap[7] ) en[0] <= #NAND_DELAY 1'b0; + +always @(*) + if ( ~sn[1] ) en[1] <= #NAND_DELAY 1'b1; + else if ( ~slow_clk_ph_n[1] ) en[1] <= #NAND_DELAY 1'b0; + else if ( ~ap[0] ) en[1] <= #NAND_DELAY 1'b0; + +always @(*) + if ( ~sn[2] ) en[2] <= #NAND_DELAY 1'b1; + else if ( ~slow_clk_ph_n[2] ) en[2] <= #NAND_DELAY 1'b0; + else if ( ~ap[1] ) en[2] <= #NAND_DELAY 1'b0; + +always @(*) + if ( ~sn[3] ) en[3] <= #NAND_DELAY 1'b1; + else if ( ~slow_clk_ph_n[3] ) en[3] <= #NAND_DELAY 1'b0; + else if ( ~ap[2] ) en[3] <= #NAND_DELAY 1'b0; + +always @(*) + if ( ~sn[4] ) en[4] <= #NAND_DELAY 1'b1; + else if ( ~slow_clk_ph_n[4] ) en[4] <= #NAND_DELAY 1'b0; + else if ( ~ap[3] ) en[4] <= #NAND_DELAY 1'b0; + +always @(*) + if ( ~sn[5] ) en[5] <= #NAND_DELAY 1'b1; + else if ( ~slow_clk_ph_n[5] ) en[5] <= #NAND_DELAY 1'b0; + else if ( ~ap[4] ) en[5] <= #NAND_DELAY 1'b0; + +always @(*) + if ( ~sn[6] ) en[6] <= #NAND_DELAY 1'b1; + else if ( ~slow_clk_ph_n[6] ) en[6] <= #NAND_DELAY 1'b0; + else if ( ~ap[5] ) en[6] <= #NAND_DELAY 1'b0; + +always @(*) + if ( ~sn[7] ) en[7] <= #NAND_DELAY 1'b1; + else if ( ~slow_clk_ph_n[7] ) en[7] <= #NAND_DELAY 1'b0; + else if ( ~ap[6] ) en[7] <= #NAND_DELAY 1'b0; + +assign #NOR_DELAY xp[7:0] = ~({8{c_out_int_n}} | slow_clk_ph_p[7:0]); +assign #NOR_DELAY sp[7:0] = ~(ap[7:0] | xp[7:0]) ; + +always @(*) + if ( sp[0] ) ep[0] <= #NAND_DELAY 1'b0; + else if ( slow_clk_ph_p[0] ) ep[0] <= #NAND_DELAY 1'b1; + else if ( amx[7] ) ep[0] <= #NAND_DELAY 1'b1; + +always @(*) + if ( sp[1] ) ep[1] <= #NAND_DELAY 1'b0; + else if ( slow_clk_ph_p[1] ) ep[1] <= #NAND_DELAY 1'b1; + else if ( amx[0] ) ep[1] <= #NAND_DELAY 1'b1; + +always @(*) + if ( sp[2] ) ep[2] <= #NAND_DELAY 1'b0; + else if ( slow_clk_ph_p[2] ) ep[2] <= #NAND_DELAY 1'b1; + else if ( amx[1] ) ep[2] <= #NAND_DELAY 1'b1; + +always @(*) + if ( sp[3] ) ep[3] <= #NAND_DELAY 1'b0; + else if ( slow_clk_ph_p[3] ) ep[3] <= #NAND_DELAY 1'b1; + else if ( amx[2] ) ep[3] <= #NAND_DELAY 1'b1; + +always @(*) + if ( sp[4] ) ep[4] <= #NAND_DELAY 1'b0; + else if ( slow_clk_ph_p[4] ) ep[4] <= #NAND_DELAY 1'b1; + else if ( amx[3] ) ep[4] <= #NAND_DELAY 1'b1; + +always @(*) + if ( sp[5] ) ep[5] <= #NAND_DELAY 1'b0; + else if ( slow_clk_ph_p[5] ) ep[5] <= #NAND_DELAY 1'b1; + else if ( amx[4] ) ep[5] <= #NAND_DELAY 1'b1; + +always @(*) + if ( sp[6] ) ep[6] <= #NAND_DELAY 1'b0; + else if ( slow_clk_ph_p[6] ) ep[6] <= #NAND_DELAY 1'b1; + else if ( amx[5] ) ep[6] <= #NAND_DELAY 1'b1; + +always @(*) + if ( sp[7] ) ep[7] <= #NAND_DELAY 1'b0; + else if ( slow_clk_ph_p[7] ) ep[7] <= #NAND_DELAY 1'b1; + else if ( amx[6] ) ep[7] <= #NAND_DELAY 1'b1; + +//-------------------------------------------------------------------------------------------------- +// Finger Mux for out[0] +//-------------------------------------------------------------------------------------------------- + +assign c_out_n_mux = ({ep[0],phy_clk_phs[0]}==2'b00)? 1'b1 : 1'bz; +assign c_out_n_mux = ({ep[1],phy_clk_phs[1]}==2'b00)? 1'b1 : 1'bz; +assign c_out_n_mux = ({ep[2],phy_clk_phs[2]}==2'b00)? 1'b1 : 1'bz; +assign c_out_n_mux = ({ep[3],phy_clk_phs[3]}==2'b00)? 1'b1 : 1'bz; +assign c_out_n_mux = ({ep[4],phy_clk_phs[4]}==2'b00)? 1'b1 : 1'bz; +assign c_out_n_mux = ({ep[5],phy_clk_phs[5]}==2'b00)? 1'b1 : 1'bz; +assign c_out_n_mux = ({ep[6],phy_clk_phs[6]}==2'b00)? 1'b1 : 1'bz; +assign c_out_n_mux = ({ep[7],phy_clk_phs[7]}==2'b00)? 1'b1 : 1'bz; +assign c_out_n_mux = ({en[0],phy_clk_phs[0]}==2'b11)? 1'b0 : 1'bz; +assign c_out_n_mux = ({en[1],phy_clk_phs[1]}==2'b11)? 1'b0 : 1'bz; +assign c_out_n_mux = ({en[2],phy_clk_phs[2]}==2'b11)? 1'b0 : 1'bz; +assign c_out_n_mux = ({en[3],phy_clk_phs[3]}==2'b11)? 1'b0 : 1'bz; +assign c_out_n_mux = ({en[4],phy_clk_phs[4]}==2'b11)? 1'b0 : 1'bz; +assign c_out_n_mux = ({en[5],phy_clk_phs[5]}==2'b11)? 1'b0 : 1'bz; +assign c_out_n_mux = ({en[6],phy_clk_phs[6]}==2'b11)? 1'b0 : 1'bz; +assign c_out_n_mux = ({en[7],phy_clk_phs[7]}==2'b11)? 1'b0 : 1'bz; + +assign #FINGER_DELAY c_out_n = c_out_n_mux; + +assign #INV_DELAY c_out = ~c_out_n; +assign #INV_DELAY mux_out_b = ~c_out_n; +assign #INV_DELAY c_out_p = ~c_out_n; +assign #INV_DELAY c_out_int_n = ~c_out_p; + +assign #(2 * NAND_DELAY) c_out_int_p = ~(dft_mux_sel & ~(test_enable_n & c_out_p)); + +endmodule + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_interp_mux_match.v b/maib_rtl/io_common_custom/rtl/block_function/io_interp_mux_match.v new file mode 100644 index 0000000..110586a --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_interp_mux_match.v @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #2 $ +// Date: $DateTime: 2014/10/18 21:47:06 $ +//------------------------------------------------------------------------ +// Description: interpolator mux match cell +// +//------------------------------------------------------------------------ + +module io_interp_mux_match ( + +input [7:0] phy_clk_phs, // 8 phase 1.6GHz clock +input [7:0] slow_clk_ph_p, // 8 phase 1.6GHz clock combined with reset +input [7:0] slow_clk_ph_n, // 8 phase 1.6GHz clock combined with reset +input [2:0] gray_a_buf, // Mux select A +input [2:0] gray_a_inv, // inverted Mux select A +input [2:0] gray_b_buf, // Mux select B +input [2:0] gray_b_inv, // inverted Mux select B +input nfrzdrv, // active low test enable +input test_enable_n, // active low test enable +input dft_mux_sel, // mux selection during test +output int_clk_out // 1 of the 3 output phases, sent to the counter +); + +wire int_clk_out_x; +wire mux_out_b; + +io_interp_mux xinterp_mux ( +.slow_clk_ph_p (slow_clk_ph_p[7:0] ), +.slow_clk_ph_n (slow_clk_ph_n[7:0] ), +.phy_clk_phs (phy_clk_phs[7:0] ), +.gray_a_buf (gray_a_buf[2:0] ), +.gray_b_buf (gray_b_buf[2:0] ), +.gray_a_inv (gray_a_inv[2:0] ), +.gray_b_inv (gray_b_inv[2:0] ), +.c_out ( ), +.mux_out_b (mux_out_b ), +.test_enable_n (test_enable_n ), +.dft_mux_sel (dft_mux_sel ) +); + +assign int_clk_out_x = ~nfrzdrv | mux_out_b; +assign int_clk_out = int_clk_out_x; + +endmodule + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_interp_mux_pair.v b/maib_rtl/io_common_custom/rtl/block_function/io_interp_mux_pair.v new file mode 100644 index 0000000..cf10598 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_interp_mux_pair.v @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +// io_interp_mux_pair : mux_sel latch and 8to1 mux +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +module io_interp_mux_pair ( +input [7:0] phy_clk_phs_gated, // 8 phase 1.6GHz local clock +input l_reset_n, // Active low reset +input [2:0] mux_sel_a, // The gray code to control (even) of the 8 to 1 phase multiplexer +input [2:0] mux_sel_b, // The gray code to control (odd ) of the 8 to 1 phase multiplexer +input [7:0] slow_clk_ph_p, +input [7:0] slow_clk_ph_n, +input test_enable_n, +input test_enable_frz, +input dft_mux_sel_p, +input dft_mux_sel_n, +output [2:0] mux_sel_x_a, // The latched gray code to control (even) of the 8 to 1 phase multiplexer +output [2:0] mux_sel_x_b, // The latched gray code to control (odd ) of the 8 to 1 phase multiplexer +output c_out_n, +output c_out_n_buf, +output c_out_p, +output c_out_p_buf +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter INV_DELAY = 12; // 10ps + +wire [2:0] mux_sel_x_a_buf; // The buffered gray code to control (even) of the 8 to 1 phase multiplexer +wire [2:0] mux_sel_x_a_inv; // The inverted gray code to control (even) of the 8 to 1 phase multiplexer +wire [2:0] mux_sel_x_b_buf; // The buffered gray code to control (even) of the 8 to 1 phase multiplexer +wire [2:0] mux_sel_x_b_inv; // The inverted gray code to control (even) of the 8 to 1 phase multiplexer +wire clk_p_buf2; +wire clk_n_buf2; + +io_interp_latch_in xlatch_in_x_a ( +.l_reset_n (l_reset_n ), // Active low reset +.clk (clk_p_buf2 ), // clock for latch +.mux_sel_in (mux_sel_a[2:0] ), // The gray code to control (even) of the 8 to 1 phase multiplexer +.mux_sel_latch (mux_sel_x_a[2:0] ), // latched gray code to control (even) of the 8 to 1 phase multiplexer +.mux_sel_buf (mux_sel_x_a_buf[2:0] ), // buffered gray code to control (even) of the 8 to 1 phase multiplexer +.mux_sel_inv (mux_sel_x_a_inv[2:0] ) +); + +io_interp_latch_in xlatch_in_x_b ( +.l_reset_n (l_reset_n ), // Active low reset +.clk (clk_n_buf2 ), // clock for latch +.mux_sel_in (mux_sel_b[2:0] ), // The gray code to control (even) of the 8 to 1 phase multiplexer +.mux_sel_latch (mux_sel_x_b[2:0] ), // latched gray code to control (even) of the 8 to 1 phase multiplexer +.mux_sel_buf (mux_sel_x_b_buf[2:0] ), // buffered gray code to control (even) of the 8 to 1 phase multiplexer +.mux_sel_inv (mux_sel_x_b_inv[2:0] ) +); + +io_interp_mux ximp0 ( +.slow_clk_ph_p (slow_clk_ph_p[7:0] ), +.slow_clk_ph_n (slow_clk_ph_n[7:0] ), +.phy_clk_phs (phy_clk_phs_gated[7:0] ), +.gray_a_buf (mux_sel_x_a_buf[2:0] ), +.gray_b_buf (mux_sel_x_b_buf[2:0] ), +.gray_a_inv (mux_sel_x_a_inv[2:0] ), +.gray_b_inv (mux_sel_x_b_inv[2:0] ), +.c_out (c_out_p ), +.mux_out_b (mux_out_b_p ), +.test_enable_n (test_enable_n ), +.dft_mux_sel (dft_mux_sel_p ) +); + +io_interp_mux ximn0 ( +.slow_clk_ph_p ({slow_clk_ph_p[3:0],slow_clk_ph_p[7:4]} ), +.slow_clk_ph_n ({slow_clk_ph_n[3:0],slow_clk_ph_n[7:4]} ), +.phy_clk_phs ({phy_clk_phs_gated[3:0],phy_clk_phs_gated[7:4]}), +.gray_a_buf (mux_sel_x_b_buf[2:0] ), +.gray_b_buf (mux_sel_x_a_buf[2:0] ), +.gray_a_inv (mux_sel_x_b_inv[2:0] ), +.gray_b_inv (mux_sel_x_a_inv[2:0] ), +.c_out (c_out_n ), +.mux_out_b (mux_out_b_n ), +.test_enable_n (test_enable_n ), +.dft_mux_sel (dft_mux_sel_n ) +); + +assign #(2 * INV_DELAY) c_out_p_buf = mux_out_b_p | test_enable_frz; +assign #(2 * INV_DELAY) clk_p_buf2 = mux_out_b_p | test_enable_frz; +assign #(2 * INV_DELAY) c_out_n_buf = mux_out_b_n | test_enable_frz; +assign #(2 * INV_DELAY) clk_n_buf2 = mux_out_b_n | test_enable_frz; + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_interp_output.v b/maib_rtl/io_common_custom/rtl/block_function/io_interp_output.v new file mode 100644 index 0000000..e8ef7c0 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_interp_output.v @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +// io_interp_output : Output Frequency = phy_clk_phs frequency +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +module io_interp_output ( +input clk_n_buf0, +input clk_n_buf2, +input clk_p_buf0, +input clk_p_buf2, +input [1:0] dirty_clk, // The divided clock outputs with a duty cycle that is not 50%, The Interpolator will modify this clock to 50% duty cycle +input enable, // Active high enable 0 = Force interpolator_clk[1:0] to 2'b10 +input [1:0] interp_clk_x, // interpolator clk after ip16phs +input reset_n, // Active low reset +input test_enable_n, // Active low test enable +input pon, // cross coupling enable p finger +input non, // cross coupling enable n finger +output [1:0] int_clk_out, // Complimentary Clock output sent to the dqs_lgc_pnr/ioereg_pnr +output [1:0] interpolator_clk // Complimentary Clock output sent to the ioereg +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter INV_DELAY = 15; // 15ps +parameter LATCH_DELAY = 50; // 50ps +parameter BUF_DELAY = 25; // 25ps +parameter MUX_DELAY = 50; // 50ps + +reg [1:0] dirty_clk_int; +reg [1:0] dirty_clk_out; +wire [1:0] interp_clk; + +//========================================================================================================================================================================= +// output merge, clock divider & interpolator +//========================================================================================================================================================================= + +always @(*) + if (~reset_n) dirty_clk_int[0] <= #LATCH_DELAY 1'b0; + else if (clk_n_buf0) dirty_clk_int[0] <= #LATCH_DELAY ~dirty_clk[0]; + +always @(*) + if (~reset_n) dirty_clk_int[1] <= #LATCH_DELAY 1'b0; + else if (clk_p_buf0) dirty_clk_int[1] <= #LATCH_DELAY dirty_clk[1]; + +always @(*) + if (~reset_n) dirty_clk_out[0] <= #LATCH_DELAY 1'b0; + else if (clk_n_buf2) dirty_clk_out[0] <= #LATCH_DELAY dirty_clk_int[0]; + +always @(*) + if (~reset_n) dirty_clk_out[1] <= #LATCH_DELAY 1'b0; + else if (clk_p_buf2) dirty_clk_out[1] <= #LATCH_DELAY dirty_clk_int[1]; + +assign interp_clk = interp_clk_x[1:0]; + +an_io_double_edge_ff xdouble_edge_ff ( +.clk_in ( interp_clk[1:0] ), +.reset_n ( enable ), +.test_enable_n ( test_enable_n ), +.data_in ( {dirty_clk_out[1],~dirty_clk_out[0]} ), +.data_out ( int_clk_out[1:0] ) +); + +assign interpolator_clk[1:0] = int_clk_out[1:0]; // needs a balanced buffer to keep the matched timing for clk_out[1:0] signals + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_interp_pdn.v b/maib_rtl/io_common_custom/rtl/block_function/io_interp_pdn.v new file mode 100644 index 0000000..5c8f8ba --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_interp_pdn.v @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #1 $ +// Date: $DateTime: 2014/09/20 12:06:43 $ +//------------------------------------------------------------------------ +// Description: gated 8 clock phases for powerdown and regulator power domain crossing +// +//------------------------------------------------------------------------ + +module io_interp_pdn ( +input pdn, // power down active low +input [7:0] phy_clk_phs, // 8 phase 1.6GHz local clock +output [7:0] phy_clk_phs_gated // gated 8 phase 1.6GHz local clock +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter INV_DELAY = 15; // 15ps + +assign #(2 * INV_DELAY) phy_clk_phs_gated[3:0] = phy_clk_phs[3:0] & {4{pdn}}; +assign #(2 * INV_DELAY) phy_clk_phs_gated[7:4] = phy_clk_phs[7:4] | {4{~pdn}}; + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_interpolator.v b/maib_rtl/io_common_custom/rtl/block_function/io_interpolator.v new file mode 100644 index 0000000..21896f8 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_interpolator.v @@ -0,0 +1,570 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +// io_interpolator : Output Frequency = phy_clk_phs frequency +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +module io_interpolator ( +input reset_n, // Active low reset +input pdn, // power down active low +input nfrzdrv, // for power domain crossing protection +input [7:0] phy_clk_phs, // 8 phase 1.6GHz local clock +input [1:0] rb_filter_code, // 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz +input [2:0] mux_sel_a, // The gray code to control (even) of the 8 to 1 phase multiplexer +input [2:0] mux_sel_b, // The gray code to control (odd ) of the 8 to 1 phase multiplexer +input [3:0] interp_sel_a, // The gray code output to control the interpolator (even) +input [3:0] interp_sel_b, // The gray code output to control the interpolator (odd ) +input [1:0] dirty_clk, // The divided clock outputs with a duty cycle that is not 50%, The Interpolator will modify this clock to 50% duty cycle +input enable, // Active high enable 0 = Force interpolator_clk[1:0] to 2'b10 +input test_enable, // Active high test enable 1: avoid tristate on output of interp_mux during testing +input rb_couple_enable, // Active high cross couple enable +output int_clk, // Clock for the counter +output [1:0] clk_out, // Complimentary Clock output sent to the dqs_lgc_pnr/ioereg_pnr +output [1:0] interpolator_clk // Complimentary Clock output sent to the ioereg +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter INV_DELAY = 15; // 15ps +parameter LATCH_DELAY = 50; // 50ps +parameter BUF_DELAY = 25; // 25ps +parameter FF_DELAY = 80; // 50ps +parameter MUX_DELAY = 50; // 50ps + +wire [2:0] mux_sel_x_a; +wire [2:0] mux_sel_y_a; +wire [2:0] mux_sel_z_a; +wire [2:0] mux_sel_x_b; +wire [2:0] mux_sel_y_b; +wire [2:0] mux_sel_z_b; +wire [2:0] clk_p_buf; +wire [2:0] clk_n_buf; +wire [2:0] clk_p; +wire [2:0] clk_n; + +wire [7:0] phy_clk_phs_gated; +wire [7:0] slow_clk_ph_p; +wire [7:0] slow_clk_ph_n; +wire test_enable_n; +wire test_enable_buf; +wire test_enable_frz; +wire dft_mux_sel_p; +wire dft_mux_sel_n; +wire pon; +wire non; + +wire [7:0] sp; +wire [7:0] sn; +wire [6:0] selp; // code for 2 phase interpolator (including decode for test) +wire [6:0] seln; // complimentary code for 2 phase interpolator (including decode for test) +wire [3:1] scp; +wire [3:1] scn; + +wire [1:0] interp_clk_x; +wire [1:0] int_clk_out; + +io_interp_pdn xphs_gated ( +.pdn ( pdn ), // power down active low +.phy_clk_phs ( phy_clk_phs[7:0] ), // 8 phase 1.6GHz local clock +.phy_clk_phs_gated ( phy_clk_phs_gated[7:0] ) // gated 8 phase 1.6GHz local clock +); + +// `define FAST_SIM +`ifdef FAST_SIM + +reg [3:0] ph_counter; +reg time_measured_event; +time a_time, b_time; +reg [2:0] mux_sel_t_a; +reg [2:0] mux_sel_t_b; +reg [3:0] interp_sel_t_a; +reg [3:0] interp_sel_t_b; +reg int_clk_local; +wire intrinsic_clk; +time calc_delay_a; +time del_2x_a; +time rem_2x_a; +time del_1x_a; +time del_0x_a; +time calc_delay_b; +time del_2x_b; +time rem_2x_b; +time del_1x_b; +time del_0x_b; +wire [4:0] c_sig; +reg pmx_2, pmx_1, pmx_0; +reg [1:0] dirty_clk_reg; +reg div_clk; + +initial ph_counter[3:0] = 4'h0; +initial time_measured_event = 1'b1; + +always @(posedge phy_clk_phs_gated[0]) + begin + ph_counter[3:0] <= #FF_DELAY ph_counter[3:0] + 1'b1; + if (ph_counter[3:0] == 4'h1) + begin + a_time = $time; + @(posedge phy_clk_phs_gated[1]) b_time = (($time - a_time) + 8) / 16; + time_measured_event <= #FF_DELAY ~time_measured_event; + end + end + +always @(negedge int_clk_local or negedge reset_n) + if (~reset_n) mux_sel_t_a[2:0] <= #FF_DELAY 3'h0; + else mux_sel_t_a[2:0] <= #FF_DELAY mux_sel_a[2:0]; + +always @(posedge int_clk_local or negedge reset_n) + if (~reset_n) mux_sel_t_b[2:0] <= #FF_DELAY 3'h0; + else mux_sel_t_b[2:0] <= #FF_DELAY mux_sel_b[2:0]; + +always @(negedge int_clk_local or negedge reset_n) + if (~reset_n) interp_sel_t_a[3:0] <= #FF_DELAY 4'h0; + else interp_sel_t_a[3:0] <= #FF_DELAY interp_sel_a[3:0]; + +always @(posedge int_clk_local or negedge reset_n) + if (~reset_n) interp_sel_t_b[3:0] <= #FF_DELAY 4'h0; + else interp_sel_t_b[3:0] <= #FF_DELAY interp_sel_b[3:0]; + +always @(posedge phy_clk_phs_gated[0]) if (mux_sel_t_a[2:0] == 3'b000) int_clk_local <= 1'b1; +always @(posedge phy_clk_phs_gated[1]) if (mux_sel_t_a[2:0] == 3'b001) int_clk_local <= 1'b1; +always @(posedge phy_clk_phs_gated[2]) if (mux_sel_t_a[2:0] == 3'b011) int_clk_local <= 1'b1; +always @(posedge phy_clk_phs_gated[3]) if (mux_sel_t_a[2:0] == 3'b010) int_clk_local <= 1'b1; +always @(posedge phy_clk_phs_gated[4]) if (mux_sel_t_a[2:0] == 3'b110) int_clk_local <= 1'b1; +always @(posedge phy_clk_phs_gated[5]) if (mux_sel_t_a[2:0] == 3'b111) int_clk_local <= 1'b1; +always @(posedge phy_clk_phs_gated[6]) if (mux_sel_t_a[2:0] == 3'b101) int_clk_local <= 1'b1; +always @(posedge phy_clk_phs_gated[7]) if (mux_sel_t_a[2:0] == 3'b100) int_clk_local <= 1'b1; + +always @(negedge phy_clk_phs_gated[0]) if (mux_sel_t_b[2:0] == 3'b000) int_clk_local <= 1'b0; +always @(negedge phy_clk_phs_gated[1]) if (mux_sel_t_b[2:0] == 3'b001) int_clk_local <= 1'b0; +always @(negedge phy_clk_phs_gated[2]) if (mux_sel_t_b[2:0] == 3'b011) int_clk_local <= 1'b0; +always @(negedge phy_clk_phs_gated[3]) if (mux_sel_t_b[2:0] == 3'b010) int_clk_local <= 1'b0; +always @(negedge phy_clk_phs_gated[4]) if (mux_sel_t_b[2:0] == 3'b110) int_clk_local <= 1'b0; +always @(negedge phy_clk_phs_gated[5]) if (mux_sel_t_b[2:0] == 3'b111) int_clk_local <= 1'b0; +always @(negedge phy_clk_phs_gated[6]) if (mux_sel_t_b[2:0] == 3'b101) int_clk_local <= 1'b0; +always @(negedge phy_clk_phs_gated[7]) if (mux_sel_t_b[2:0] == 3'b100) int_clk_local <= 1'b0; + +assign #116 int_clk = int_clk_local; +assign #150 intrinsic_clk = int_clk; + +always @(interp_sel_t_a or time_measured_event) + begin + case (interp_sel_t_a[3:0]) + 4'b0000 : calc_delay_a = 0 * b_time; + 4'b0001 : calc_delay_a = 1 * b_time; + 4'b0011 : calc_delay_a = 2 * b_time; + 4'b0010 : calc_delay_a = 3 * b_time; + 4'b0110 : calc_delay_a = 4 * b_time; + 4'b0111 : calc_delay_a = 5 * b_time; + 4'b0101 : calc_delay_a = 6 * b_time; + 4'b0100 : calc_delay_a = 7 * b_time; + 4'b1100 : calc_delay_a = 8 * b_time; + 4'b1101 : calc_delay_a = 9 * b_time; + 4'b1111 : calc_delay_a = 10 * b_time; + 4'b1110 : calc_delay_a = 11 * b_time; + 4'b1010 : calc_delay_a = 12 * b_time; + 4'b1011 : calc_delay_a = 13 * b_time; + 4'b1001 : calc_delay_a = 14 * b_time; + 4'b1000 : calc_delay_a = 15 * b_time; + default : calc_delay_a = 8 * b_time; + endcase + + del_2x_a = calc_delay_a / 100; // 100 ps + rem_2x_a = calc_delay_a - (del_2x_a * 100); + del_1x_a = rem_2x_a / 10; // 10 ps + del_0x_a = rem_2x_a - (del_1x_a * 10); // 1 ps + + end + +always @(interp_sel_t_b or time_measured_event) + begin + case (interp_sel_t_b[3:0]) + 4'b0000 : calc_delay_b = 0 * b_time; + 4'b0001 : calc_delay_b = 1 * b_time; + 4'b0011 : calc_delay_b = 2 * b_time; + 4'b0010 : calc_delay_b = 3 * b_time; + 4'b0110 : calc_delay_b = 4 * b_time; + 4'b0111 : calc_delay_b = 5 * b_time; + 4'b0101 : calc_delay_b = 6 * b_time; + 4'b0100 : calc_delay_b = 7 * b_time; + 4'b1100 : calc_delay_b = 8 * b_time; + 4'b1101 : calc_delay_b = 9 * b_time; + 4'b1111 : calc_delay_b = 10 * b_time; + 4'b1110 : calc_delay_b = 11 * b_time; + 4'b1010 : calc_delay_b = 12 * b_time; + 4'b1011 : calc_delay_b = 13 * b_time; + 4'b1001 : calc_delay_b = 14 * b_time; + 4'b1000 : calc_delay_b = 15 * b_time; + default : calc_delay_b = 8 * b_time; + endcase + + del_2x_b = calc_delay_b / 100; // 100 ps + rem_2x_b = calc_delay_b - (del_2x_b * 100); + del_1x_b = rem_2x_b / 10; // 10 ps + del_0x_b = rem_2x_b - (del_1x_b * 10); // 1 ps + + end + +assign #10 c_sig[0] = intrinsic_clk; +assign #100 c_sig[1] = c_sig[0]; +assign #100 c_sig[2] = c_sig[1]; +assign #100 c_sig[3] = c_sig[2]; +assign #100 c_sig[4] = c_sig[3]; + +always @(posedge c_sig[0]) if (del_2x_a == 0) pmx_2 <= 1'b1; +always @(posedge c_sig[1]) if (del_2x_a == 1) pmx_2 <= 1'b1; +always @(posedge c_sig[2]) if (del_2x_a == 2) pmx_2 <= 1'b1; +always @(posedge c_sig[3]) if (del_2x_a == 3) pmx_2 <= 1'b1; +always @(posedge c_sig[4]) if (del_2x_a >= 4) pmx_2 <= 1'b1; + +always @(posedge pmx_2) + case (del_1x_a) + 0 : pmx_1 <= #0 pmx_2; + 1 : pmx_1 <= #10 pmx_2; + 2 : pmx_1 <= #20 pmx_2; + 3 : pmx_1 <= #30 pmx_2; + 4 : pmx_1 <= #40 pmx_2; + 5 : pmx_1 <= #50 pmx_2; + 6 : pmx_1 <= #60 pmx_2; + 7 : pmx_1 <= #70 pmx_2; + 8 : pmx_1 <= #80 pmx_2; + 9 : pmx_1 <= #90 pmx_2; + default : pmx_1 <= #90 pmx_2; + endcase + +always @(posedge pmx_1) + case (del_0x_a) + 0 : pmx_0 <= #0 pmx_1; + 1 : pmx_0 <= #1 pmx_1; + 2 : pmx_0 <= #2 pmx_1; + 3 : pmx_0 <= #3 pmx_1; + 4 : pmx_0 <= #4 pmx_1; + 5 : pmx_0 <= #5 pmx_1; + 6 : pmx_0 <= #6 pmx_1; + 7 : pmx_0 <= #7 pmx_1; + 8 : pmx_0 <= #8 pmx_1; + 9 : pmx_0 <= #9 pmx_1; + default : pmx_0 <= #9 pmx_1; + endcase + +always @(negedge c_sig[0]) if (del_2x_b == 0) pmx_2 <= 1'b0; +always @(negedge c_sig[1]) if (del_2x_b == 1) pmx_2 <= 1'b0; +always @(negedge c_sig[2]) if (del_2x_b == 2) pmx_2 <= 1'b0; +always @(negedge c_sig[3]) if (del_2x_b == 3) pmx_2 <= 1'b0; +always @(negedge c_sig[4]) if (del_2x_b >= 4) pmx_2 <= 1'b0; + +always @(negedge pmx_2) + case (del_1x_b) + 0 : pmx_1 <= #0 pmx_2; + 1 : pmx_1 <= #10 pmx_2; + 2 : pmx_1 <= #20 pmx_2; + 3 : pmx_1 <= #30 pmx_2; + 4 : pmx_1 <= #40 pmx_2; + 5 : pmx_1 <= #50 pmx_2; + 6 : pmx_1 <= #60 pmx_2; + 7 : pmx_1 <= #70 pmx_2; + 8 : pmx_1 <= #80 pmx_2; + 9 : pmx_1 <= #90 pmx_2; + default : pmx_1 <= #90 pmx_2; + endcase + +always @(negedge pmx_1) + case (del_0x_b) + 0 : pmx_0 <= #0 pmx_1; + 1 : pmx_0 <= #1 pmx_1; + 2 : pmx_0 <= #2 pmx_1; + 3 : pmx_0 <= #3 pmx_1; + 4 : pmx_0 <= #4 pmx_1; + 5 : pmx_0 <= #5 pmx_1; + 6 : pmx_0 <= #6 pmx_1; + 7 : pmx_0 <= #7 pmx_1; + 8 : pmx_0 <= #8 pmx_1; + 9 : pmx_0 <= #9 pmx_1; + default : pmx_0 <= #9 pmx_1; + endcase + +always @(posedge int_clk_local or negedge reset_n) + if (~reset_n) dirty_clk_reg[0] <= #FF_DELAY 1'b1; + else dirty_clk_reg[0] <= #FF_DELAY dirty_clk[0]; + +always @(negedge int_clk_local or negedge reset_n) + if (~reset_n) dirty_clk_reg[1] <= #FF_DELAY 1'b0; + else dirty_clk_reg[1] <= #FF_DELAY dirty_clk[1]; + +always @(posedge pmx_0 or negedge enable) + if (~enable) div_clk <= #100 1'b0; + else div_clk <= #100 dirty_clk_reg[0]; +always @(negedge pmx_0 or negedge enable) + if (~enable) div_clk <= #100 1'b0; + else div_clk <= #100 dirty_clk_reg[1]; + +assign #150 clk_out[1:0] = {~div_clk,div_clk}; +assign #150 interpolator_clk[1:0] = {~div_clk,div_clk}; + +`else + +//==================================================================================================================================== +// io_interp_misc +//==================================================================================================================================== + +io_interp_misc xinterp_misc ( +.reset_n (reset_n ), // Active low reset +.test_enable (test_enable ), // Active high test enable 1: avoid tristate on output of interp_mux during testing +.nfrzdrv (nfrzdrv ), // for power domain crossing protection +.couple_enable (rb_couple_enable ), // cross coupling enable +.filter_code (rb_filter_code[0] ), // borrowed from filter_code[0] for test +.clk_p_buf0 (clk_p_buf[0] ), // Clock for pnr int_clk +.int_clk_out (int_clk_out[1:0] ), // interpolator clock for pnr/dpa +.phy_clk_phs (phy_clk_phs_gated[7:0] ), // 8 phase 1.6GHz local clock +.slow_clk_ph_p (slow_clk_ph_p[7:0] ), // 8 phase 1.6GHz local clock +.slow_clk_ph_n (slow_clk_ph_n[7:0] ), // 8 phase 1.6GHz local clock +.test_enable_buf (test_enable_buf ), // Active high test enable 1: avoid tristate on output of interp_mux during testing +.test_enable_frz (test_enable_frz ), // Active high test enable 1: avoid tristate on output of interp_mux during testing +.test_enable_n (test_enable_n ), // Active low test enable 0: avoid tristate on output of interp_mux during testing +.l_reset_n (l_reset_n ), // Active low reset +.clk_out (clk_out[1:0] ), // interpolator clock for pnr/dpa +.dft_mux_sel_n (dft_mux_sel_n ), // for test +.dft_mux_sel_p (dft_mux_sel_p ), // for test +.pon (pon ), // cross couple control for p fingers +.non (non ), // cross couple control for n fingers +.int_clk (int_clk ) // Clock for the counter +); + +//==================================================================================================================================== +// io_interpolator_mux selects 3 of the 8 input clock phases (A complimentary set) +//==================================================================================================================================== + + +io_interp_mux_pair xim0( +.phy_clk_phs_gated (phy_clk_phs_gated[7:0] ), // 8 phase 1.6GHz local clock +.l_reset_n (l_reset_n ), // Active low reset +.mux_sel_a (mux_sel_a[2:0] ), // The gray code to control (even) of the 8 to 1 phase multiplexer +.mux_sel_b (mux_sel_b[2:0] ), // The gray code to control (odd ) of the 8 to 1 phase multiplexer +.slow_clk_ph_p (slow_clk_ph_p[7:0] ), +.slow_clk_ph_n (slow_clk_ph_n[7:0] ), +.test_enable_n (test_enable_n ), +.test_enable_frz (test_enable_frz ), +.dft_mux_sel_p (dft_mux_sel_p ), +.dft_mux_sel_n (dft_mux_sel_n ), +.mux_sel_x_a (mux_sel_x_a[2:0] ), // The latched gray code to control (even) of the 8 to 1 phase multiplexer +.mux_sel_x_b (mux_sel_x_b[2:0] ), // The latched gray code to control (odd ) of the 8 to 1 phase multiplexer +.c_out_n (clk_n[0] ), +.c_out_n_buf (clk_n_buf[0] ), +.c_out_p (clk_p[0] ), +.c_out_p_buf (clk_p_buf[0] ) +); + +io_interp_mux_pair xim1( +.phy_clk_phs_gated ({phy_clk_phs_gated[0],phy_clk_phs_gated[7:1]} ), // 8 phase 1.6GHz local clock +.l_reset_n (l_reset_n ), // Active low reset +.mux_sel_a (mux_sel_x_a[2:0] ), // The gray code to control (even) of the 8 to 1 phase multiplexer +.mux_sel_b (mux_sel_x_b[2:0] ), // The gray code to control (odd ) of the 8 to 1 phase multiplexer +.slow_clk_ph_p ({slow_clk_ph_p[0],slow_clk_ph_p[7:1]} ), +.slow_clk_ph_n ({slow_clk_ph_n[0],slow_clk_ph_n[7:1]} ), +.test_enable_n (test_enable_n ), +.test_enable_frz (test_enable_frz ), +.dft_mux_sel_p (dft_mux_sel_p ), +.dft_mux_sel_n (dft_mux_sel_n ), +.mux_sel_x_a (mux_sel_y_a[2:0] ), // The latched gray code to control (even) of the 8 to 1 phase multiplexer +.mux_sel_x_b (mux_sel_y_b[2:0] ), // The latched gray code to control (odd ) of the 8 to 1 phase multiplexer +.c_out_n (clk_n[1] ), +.c_out_n_buf (clk_n_buf[1] ), +.c_out_p (clk_p[1] ), +.c_out_p_buf (clk_p_buf[1] ) +); + +io_interp_mux_pair xim2( +.phy_clk_phs_gated ({phy_clk_phs_gated[1:0],phy_clk_phs_gated[7:2]} ), // 8 phase 1.6GHz local clock +.l_reset_n (l_reset_n ), // Active low reset +.mux_sel_a (mux_sel_x_a[2:0] ), // The gray code to control (even) of the 8 to 1 phase multiplexer +.mux_sel_b (mux_sel_x_b[2:0] ), // The gray code to control (odd ) of the 8 to 1 phase multiplexer +.slow_clk_ph_p ({slow_clk_ph_p[1:0],slow_clk_ph_p[7:2]} ), +.slow_clk_ph_n ({slow_clk_ph_n[1:0],slow_clk_ph_n[7:2]} ), +.test_enable_n (test_enable_n ), +.test_enable_frz (test_enable_frz ), +.dft_mux_sel_p (dft_mux_sel_p ), +.dft_mux_sel_n (dft_mux_sel_n ), +.mux_sel_x_a (mux_sel_z_a[2:0] ), // The latched gray code to control (even) of the 8 to 1 phase multiplexer +.mux_sel_x_b (mux_sel_z_b[2:0] ), // The latched gray code to control (odd ) of the 8 to 1 phase multiplexer +.c_out_n (clk_n[2] ), +.c_out_n_buf (clk_n_buf[2] ), +.c_out_p (clk_p[2] ), +.c_out_p_buf (clk_p_buf[2] ) +); + +//==================================================================================================================================== +// io_cmos_16ph_decode decode interp_sel[3:0] for ip16phs +//==================================================================================================================================== + +io_cmos_16ph_decode xdec ( + .gray_sel_a ( interp_sel_a[3:0] ), + .gray_sel_b ( interp_sel_b[3:0] ), + .clk_p_0 ( clk_p_buf[0] ), + .clk_p_2 ( clk_p_buf[2] ), + .clk_n_0 ( clk_n_buf[0] ), + .clk_n_2 ( clk_n_buf[2] ), + .filter_code ( rb_filter_code[1:0] ), + .enable ( l_reset_n ), + .test_enable_buf ( test_enable_buf ), + .test_enable_n ( test_enable_n ), + .dft_mux_sel_p ( dft_mux_sel_p ), + .dft_mux_sel_n ( dft_mux_sel_n ), + .sp ( sp[7:0] ), + .sn ( sn[7:0] ), + .selp ( selp[6:0] ), + .seln ( seln[6:0] ), + .scp ( scp[3:1] ), + .scn ( scn[3:1] ) +); + +//========================================================================================================================================================================= +// io_ip16phs is the 16 phase interpolator +//========================================================================================================================================================================= + +io_ip16phs xip16p ( + .c_in ( clk_p[2:0] ), + .sp ( sp[7:0] ), + .sn ( sn[7:0] ), + .selp ( {selp[6],1'b1,selp[4:3],1'b1,selp[1:0]} ), + .seln ( {seln[6],1'b0,seln[4:3],1'b0,seln[1:0]} ), + .scp ( scp[3:1] ), + .scn ( scn[3:1] ), + .c_out ( interp_clk_x[0] ) +); + +io_ip16phs xip16n ( + .c_in ( clk_n[2:0] ), + .sp ( sp[7:0] ), + .sn ( sn[7:0] ), + .selp ( {selp[6],1'b1,selp[4:3],1'b1,selp[1:0]} ), + .seln ( {seln[6],1'b0,seln[4:3],1'b0,seln[1:0]} ), + .scp ( scp[3:1] ), + .scn ( scn[3:1] ), + .c_out ( interp_clk_x[1] ) +); + +//========================================================================================================================================================================= +// output merge, clock divider & interpolator +//========================================================================================================================================================================= + +io_interp_output xinterp_output ( +.clk_n_buf0 (clk_n_buf[0] ), +.clk_n_buf2 (clk_n_buf[2] ), +.clk_p_buf0 (clk_p_buf[0] ), +.clk_p_buf2 (clk_p_buf[2] ), +.dirty_clk (dirty_clk[1:0] ), // The divided clock outputs with a duty cycle that is not 50%, The Interpolator will modify this clock to 50% duty cycle +.enable (enable ), // Active high enable 0 = Force interpolator_clk[1:0] to 2'b10 +.interp_clk_x (interp_clk_x[1:0] ), // interpolator clk after ip16phs +.reset_n (l_reset_n ), // Active low reset +.test_enable_n (test_enable_n ), // Active low test enable +.pon (pon ), // cross coupling enable p finger +.non (non ), // cross coupling enable n finger +.int_clk_out (int_clk_out[1:0] ), // Complimentary Clock output sent to the dqs_lgc_pnr/ioereg_pnr +.interpolator_clk (interpolator_clk[1:0] ) // Complimentary Clock output sent to the ioereg +); + +//========================================================================================================================================================================= +// Waveforms +//========================================================================================================================================================================= +// +// _ ______________________________ _________________________ ______________________________ ____ +// mux_sel_x_a[2:0] _XXXXXXXXXXXXXXX_____________________0________XXXXXXXXXXXXXXX________________0________XXXXXXXXXXXXXXX_____________________1________XXXXXXXXXXXXXXX____ +// _____________________ ______________________________ ______________________________ ________________________ +// mux_sel_x_b[2:0] ____________7________XXXXXXXXXXXXXXX_____________________0________XXXXXXXXXXXXXXX_____________________1________XXXXXXXXXXXXXXX__________________1_____ +// _ ___________________ ________________________ ___________________ ___________________ ________________________ ___________________ ___________________ +// imp0.amx[7:0] _X_________7_________X_____________0__________X__________0________X__________0________X_____________1__________X__________1________X__________1________X_ +// +// ___________________ ___________________ ___________________ ___________________ +// clk_ph[0] ________/ \___________________/ \___________________/ \___________________/ \_______ +// ___________________ : ___________________ ___________________ ___________________ +// clk_ph[1] _____________/ \______________:____/ \___________________/ \___________________/ \__ +// ___________________ : ___________________ ______________:____ _________________ +// clk_ph[2] __________________/ \_________:_________/ \___________________/ : \___________________/ +// ___ ___________________ : ___________________ _________:_________ ____________ +// clk_ph[3] \___________________/ \____:______________/ \___________________/ : \___________________/ +// ________ ___________________: ___________________ ____:______________ _______ +// clk_ph[4] \___________________/ :___________________/ \___________________/ : \___________________/ +// _____________ ______________:____ ___________________ :___________________ __ +// clk_ph[5] \___________________/ : \___________________/ \___________________: \___________________/ +// __________________ _________:_________ ___________________ : ___________________ +// clk_ph[6] \___________________/ : \___________________/ \______________:____/ \_________________ +// ___________________ ____:______________ ___________________ : ___________________ +// clk_ph[7] ___/ \___________________/ : \___________________/ \_________:_________/ \____________ +// : : : : +// :___________________: :___________________ ________________________: ___________________ +// clk_p[0] ___/ \________________________/ \___________________/ \___________________/ \__ +// ___________________ ___________________ ________________________ _________________ +// clk_p[1] ________/ \________________________/ \___________________/ \___________________/ +// ___________________ ___________________ ________________________ ____________ +// clk_p[2] _____________/ \________________________/ \___________________/ \___________________/ +// +// ________ ______________________________ _________________________ ______________________________ +// out_interp_az[3:0] ________XXXXXXXXXXXXXXX_____________________2________XXXXXXXXXXXXXXX________________C________XXXXXXXXXXXXXXX_____________________6________XXXXXXXXXXXX +// ____________________________ ______________________________ ______________________________ _________________ +// out_interp_bz[3:0] ___________________D________XXXXXXXXXXXXXXX_____________________7________XXXXXXXXXXXXXXX_____________________1________XXXXXXXXXXXXXXX_______________B_ +// __________ ___________________ ________________________ ___________________ ___________________ ________________________ ___________________ _____________ +// therm_sel[7:0] __________X_________D_________X_____________2__________X__________7________X__________C________X_____________1__________X__________6________X__________B__ +// +// interp_clk ____________________ _____________________ _____________________ ____________________ +// ideal _____/ \_____________________/ \____________________/ \____________________/ +// ____________________ _____________________ _____________________ ____ +// interp_clk[0] \____________________/ \_____________________/ \____________________/ \____________________/ +// ____________________ _____________________ ____________________ ____________________ +// interp_clk[1] / \____________________/ \_____________________/ \_____________________/ \____ +// +//=========================================================================================================================================================================== +//===================================================================== divide 1 ============================================================================================ +// +// _________________________________________________________________________________________________________________________________________________________ +// dbl_edge.lat[0] 1 1 1 1 +// +// dbl_edge.lat[1] _______________0_________________________________________0___________________________________________0___________________________________________________ +// +// _____________________ _____________________ _____________________ __ +// clk_out[0] ________lat[1]______/ lat[0] \_______lat[1]________/ lat[0] \________lat[1]______/ lat[0] \________lat[1]______/ +// +// +//=========================================================================================================================================================================== +//===================================================================== divide 2 ============================================================================================ +// +// _________________________ ______________________________ +// dirty_clk_out[0] XXXXX 1 XXXXXXXXXXXXXXX______________0_______________XXXXXXXXXXXXXXX 1 XXXXXXXXXXXXXXX____________0____ +// ___________________________ ____________________________ +// dbl_edge.lat[0] _XXXXXXXXXXXXXXX 1 XXXXXXXXXXXXXXX______________0______________XXXXXXXXXXXXXXX 1 XXXXXXXXXXXXXXX________ +// +// ______________________________ ______________________________ +// dirty_clk_out[1] ___0______XXXXXXXXXXXXXXX 1 XXXXXXXXXXXXXXX____________0____________XXXXXXXXXXXXXXX 1 XXXXXXXXXXXX +// ____________________________ ____________________________ +// dbl_edge.lat[1] ________0_____________XXXXXXXXXXXXXXX 1 XXXXXXXXXXXXXXX______________0_____________XXXXXXXXXXXXXXX 1 XX +// +// _____________________ _____________________ _____________________ ____________________ +// clk_out[0] ________lat[1]______/ lat[0] | lat[1] \________lat[0]_______|________lat[1]______/ lat[0] - lat[1] \__ +// +// +//=========================================================================================================================================================================== +//===================================================================== divide 4 ============================================================================================ +// +// _________________________ ______________________________ +// dirty_clk_out[0] XXXXX 1 --------------- 1 XXXXXXXXXXXXXXX________________0_____________---------------______________0__ +// ___________________________ _____________________________ +// dbl_edge.lat[0] _XXXXXXXXXXXXXXX 1 --------------- 1 XXXXXXXXXXXXXXX______________0_____________---------------________ +// +// ______________________________ _________________________ +// dirty_clk_out[1] __0_______XXXXXXXXXXXXXXX 1 --------------- 1 XXXXXXXXXXXXXXX_______________0______________------------ +// ____________________________ ____________________________ +// dbl_edge.lat[1] __________0___________XXXXXXXXXXXXXXX 1 --------------- 1 XXXXXXXXXXXXXXX_______________0____________-- +// _____________________ _____________________ _____________________ ____________________ __ +// clk_out[0] ________lat[1]______/ lat[0] - lat[1] - lat[0] - lat[1] \________lat[0]_______-________lat[1]______/ +// +// +//=========================================================================================================================================================================== + +`endif + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_ioereg_custom.v b/maib_rtl/io_common_custom/rtl/block_function/io_ioereg_custom.v new file mode 100644 index 0000000..5f4a5cb --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_ioereg_custom.v @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +module io_ioereg_custom ( + input [1:0] data_dq_in, // I/O : DQ complimentary inputs from the I/O cell sent to delay chain -- dq_in[1] = dq+ + input [1:0] data_dqb_in, // I/O : DQ complimentary inputs from the I/O cell sent to delay chain -- dq_in[0] = dq- + input x64_osc_in_p, // input for the x64 ring oscillator + input x64_osc_in_n, // input for the x64 ring oscillator + output x64_osc_out_p, // output for the x64 ring oscillator + output x64_osc_out_n, // output for the x64 ring oscillator + input x64_osc_mode, // Mux control for the x64 ring oscillator, 1 = osc test, 0 = normal + input nfrzdrv, + input [11:0] dq_f_gray, // Delay : Gray code DQ delay setting used by the NAND delay line + input [5:0] dq_i_gray, // Delay : Gray code DQ delay setting used by the NAND delay line (interpolator) + input [7:0] dq_rise_gray, // Delay : Gray code rising edge dcc setting + input [7:0] dq_fall_gray, // Delay : Gray code falling edge dcc setting + output [3:0] dq_in_del, // dq input path, the output of the delay chain going to the DQ dummy tree, to match DQS tree delays + input [7:0] phy_clk_phs, // PLL : full rate 8 phase clock + input [1:0] rb_filter_code, // DQS LGC : 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz ( Interpolator filter setting ) + input test_enable, // Active high test enable 1: avoid tristate on output of interp_mux during testing + input rb_couple_enable, // Active high cross couple enable + input [1:0] power_down_n, // 0 = power down, 1 = power up + input [5:0] mux_sel_a, // The gray code to control (even) of the 8 to 1 phase multiplexer + input [5:0] mux_sel_b, // The gray code to control (odd ) of the 8 to 1 phase multiplexer + input [7:0] interp_sel_a, // The gray code output to control (even) the interpolator + input [7:0] interp_sel_b, // The gray code output to control (odd ) the interpolator + input [3:0] dirty_clk, // pass through code is 2'b01, disable code is 2'b00, divider is dynamic + input [1:0] interp_enable, // 0 = GPIO mode, 1 = DDR mode + output [1:0] int_clk, // Clocks from the output of the 3 (8 to 1 phase select multiplexers) clk_p[0] arrives first, clk_p[2] arrives last + output [3:0] interp_clk_out, // Complimentary Clock output sent to io_ioereg_pnr & DPA + output [3:0] interpolator_clk // Complimentary Clock output sent to io_ioereg_struct +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +//----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +// reg & wire +//----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + + wire [3:0] dq_in_del_int; // output of delay line before dcc + wire x64_osc_p; // input for the x64 ring oscillator + wire x64_osc_n; // input for the x64 ring oscillator + +//================================================================================================================================================================ +// Delay chain & phase interpolator +// assign dirty_clk[1:0] = phy_mode_out ? 2'b00 : 2'b01; +//================================================================================================================================================================ + +io_interpolator xio_interpolator_0 ( +.reset_n ( nfrzdrv ), +.pdn ( power_down_n[0] ), // power down active low +.nfrzdrv ( nfrzdrv ), // active low +.phy_clk_phs ( phy_clk_phs[7:0] ), // PLL : 8 phase 1.6GHz local clock +.rb_filter_code ( rb_filter_code[1:0] ), // LANE CSR : 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz ( Interpolator filter setting ) +.mux_sel_a ( mux_sel_a[2:0] ), // The gray code to control (even) of the 8 to 1 phase multiplexer +.mux_sel_b ( mux_sel_b[2:0] ), // The gray code to control (odd ) of the 8 to 1 phase multiplexer +.interp_sel_a ( interp_sel_a[3:0] ), // The gray code output to control (even) the interpolator +.interp_sel_b ( interp_sel_b[3:0] ), // The gray code output to control (odd ) the interpolator +.dirty_clk ( dirty_clk[1:0] ), // pass through code is 2'b01, disable code is 2'b00, divider is dynamic +.enable ( interp_enable[0] ), // Active high enable 0 = Force interpolator_clk[1:0] to 2'b10 +.test_enable ( test_enable ), // Active high test enable 1: avoid tristate on output of interp_mux during testing +.rb_couple_enable ( rb_couple_enable ), // Active high cross couple enable +.int_clk ( int_clk[0] ), // Clocks for the counter +.clk_out ( interp_clk_out[1:0] ), // Complimentary Clock output sent to io_ioereg_pnr +.interpolator_clk ( interpolator_clk[1:0] ) // Complimentary Clock output sent to io_ioereg_struct +); + +io_interpolator xio_interpolator_1 ( +.reset_n ( nfrzdrv ), +.pdn ( power_down_n[1] ), // power down active low +.nfrzdrv ( nfrzdrv ), // active low +.phy_clk_phs ( phy_clk_phs[7:0] ), // PLL : 8 phase 1.6GHz local clock +.rb_filter_code ( rb_filter_code[1:0] ), // LANE CSR : 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz ( Interpolator filter setting ) +.mux_sel_a ( mux_sel_a[5:3] ), // The gray code to control (even) of the 8 to 1 phase multiplexer +.mux_sel_b ( mux_sel_b[5:3] ), // The gray code to control (odd ) of the 8 to 1 phase multiplexer +.interp_sel_a ( interp_sel_a[7:4] ), // The gray code output to control (even) the interpolator +.interp_sel_b ( interp_sel_b[7:4] ), // The gray code output to control (odd ) the interpolator +.dirty_clk ( dirty_clk[3:2] ), // pass through code is 2'b01, disable code is 2'b00, divider is dynamic +.enable ( interp_enable[1] ), // Active high enable 0 = Force interpolator_clk[1:0] to 2'b10 +.test_enable ( test_enable ), // Active high test enable 1: avoid tristate on output of interp_mux during testing +.rb_couple_enable ( rb_couple_enable ), // Active high cross couple enable +.int_clk ( int_clk[1] ), // Clocks for the counter +.clk_out ( interp_clk_out[3:2] ), // Complimentary Clock output sent to io_ioereg_pnr +.interpolator_clk ( interpolator_clk[3:2] ) // Complimentary Clock output sent to io_ioereg_struct +); + +io_nand_x64_delay_line xio_nand_x64_delay_line_0 ( +.nfrzdrv ( nfrzdrv ), +.in_p ( data_dq_in[0] ), +.in_n ( data_dqb_in[0] ), +.osc_mode ( x64_osc_mode ), +.osc_in_p ( x64_osc_in_p ), +.osc_in_n ( x64_osc_in_n ), +.osc_out_p ( x64_osc_p ), +.osc_out_n ( x64_osc_n ), +.f_gray ( dq_f_gray[5:0] ), +.i_gray ( dq_i_gray[2:0] ), +.out_p ( dq_in_del_int[0] ), // Swap and invert the output here +.out_n ( dq_in_del_int[1] ) // Swap and invert the output here +); + +io_nand_x64_delay_line xio_nand_x64_delay_line_1 ( +.nfrzdrv ( nfrzdrv ), +.in_p ( data_dq_in[1] ), +.in_n ( data_dqb_in[1] ), +.osc_mode ( x64_osc_mode ), +.osc_in_p ( x64_osc_p ), +.osc_in_n ( x64_osc_n ), +.osc_out_p ( x64_osc_out_p ), +.osc_out_n ( x64_osc_out_n ), +.f_gray ( dq_f_gray[11:6] ), +.i_gray ( dq_i_gray[5:3] ), +.out_p ( dq_in_del_int[2] ), // Swap and invert the output here +.out_n ( dq_in_del_int[3] ) // Swap and invert the output here +); + + +io_delay_line_dcc xio_delay_line_dcc_0 ( +.c_in_p ( dq_in_del_int[0] ), +.c_in_n ( dq_in_del_int[1] ), +.f_gray ( dq_fall_gray[3:0] ), +.r_gray ( dq_rise_gray[3:0] ), +.c_out_p ( dq_in_del[0] ), +.c_out_n ( dq_in_del[1] ) +); + +io_delay_line_dcc xio_delay_line_dcc_1 ( +.c_in_p ( dq_in_del_int[2] ), +.c_in_n ( dq_in_del_int[3] ), +.f_gray ( dq_fall_gray[7:4] ), +.r_gray ( dq_rise_gray[7:4] ), +.c_out_p ( dq_in_del[2] ), +.c_out_n ( dq_in_del[3] ) +); + +endmodule + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_ioereg_struct.v b/maib_rtl/io_common_custom/rtl/block_function/io_ioereg_struct.v new file mode 100644 index 0000000..ed99467 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_ioereg_struct.v @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +module io_ioereg_struct ( +input [1:0] interpolator_clk, // Complimentary Clock output sent to io_ioereg_struct +input [1:0] d_out_p_mux, // I/O : Output P transistor before the final output mux +input [1:0] d_out_n_mux, // I/O : Output N transistor before the final output mux +output codin_p, // I/O : The high speed data output sent to the P type transistor + +output codin_pb, // I/O : The high speed data output sent to the P type transistor - +output codin_n, // I/O : The high speed data output sent to the N type transistor + +output codin_nb, // I/O : The high speed data output sent to the N type transistor - +input [2:0] rb_dq_select, // CSR : 000 = DQ input disabled, 1?? = Single ended DQ, 010 = loopback, 011 = xor loopback, 001 = differential DQ +input latch_open_n, // Static : 0 = force the latches open (GPIO & ATPG), 1 = clock the latches, Memory IF +input [1:0] dq_diff_in, // I/O : differential DQ input +input [1:0] dq_sstl_in, // I/O : single ended DQ input +input nfrzdrv, // freez signal +input loopback_p, // I/O : P-tran loopback +input loopback_n, // I/O : N-tran loopback +input loopback_en_n, // I/O : Active low loopback enable +output datovr, // I/O : DQ complimentary inputs from the I/O cell sent to gpio -- dq_in[1] = dq+ +output datovrb, // I/O : DQ complimentary inputs from the I/O cell sent to gpio -- dq_in[0] = dq- +output data_dq, // I/O : DQ complimentary inputs from the I/O cell sent to delay chain -- dq_in[1] = dq+ +output data_dqb, // I/O : DQ complimentary inputs from the I/O cell sent to delay chain -- dq_in[0] = dq- +output [1:0] dqs_loop_back, // +input scan_in, // ATPG : Scan in +input scan_shift_n, // ATPG : Scan shift enable +input test_clk, // ATPG : Scan clock +input sample_clk, // sampling clock for dcc +input [1:0] dcc_select, // dcc sampling point selection +input rb_gpio_or_ddr_sel, // used for ioereg_struct timing model generation only +input rb_mode_ddr, // used for ioereg_struct timing model generation only + +output dcc_sample, // dcc sample value +output reg scan_out // ATPG : Scan out +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter FF_DELAY = 80; +parameter LATCH_DELAY = 70; +parameter MUX_DELAY = 60; + +reg dcc_sample_b; +reg sample_value; +reg sample_value_reg_1; +reg sample_value_reg_2; +reg sample_value_reg_3; +wire sample_value_0; +wire sample_value_1; +wire sample_value_2; +wire sample_value_3; +reg [1:0] dq_in_mux; +reg [3:0] scan_chain; + +//----------------------------------------------------- +// Output Mux +//----------------------------------------------------- + +io_ioereg_struct_out xstruct_out ( +.interpolator_clk (interpolator_clk[1:0] ), +.d_out_p_mux (d_out_p_mux[1:0] ), +.d_out_n_mux (d_out_n_mux[1:0] ), +.codin_p (codin_p ), +.codin_pb (codin_pb ), +.codin_n (codin_n ), +.codin_nb (codin_nb ), +.latch_open_n (latch_open_n ), +.nfrzdrv (nfrzdrv ), +.loopback_p (loopback_p ), +.loopback_n (loopback_n ), +.loopback_en_n (loopback_en_n ) +); + +assign dqs_loop_back = (rb_dq_select[2:0]==3'b001)? 2'b01 : {~codin_pb,~codin_p}; + +//----------------------------------------------------- +// Input Mux +//----------------------------------------------------- + +always @(*) + casez (rb_dq_select[2:0]) + 3'b000 : dq_in_mux[1:0] = dq_sstl_in[1:0]; + 3'b001 : dq_in_mux[1:0] = dq_sstl_in[1:0]; + 3'b010 : dq_in_mux[1:0] = {codin_pb,codin_p}; + 3'b011 : dq_in_mux[1:0] = {(codin_pb ^ codin_n),(codin_p ~^ codin_nb)}; + 3'b1?? : dq_in_mux[1:0] = dq_diff_in[1:0]; + endcase + +assign {datovr,datovrb} = dq_in_mux[1:0]; + +assign {data_dq,data_dqb} = dq_in_mux[1:0]; + +//----------------------------------------------------- +// Scan Flops +//----------------------------------------------------- + +always @(posedge test_clk) + if (scan_shift_n) scan_chain[0] <= #FF_DELAY d_out_n_mux[0]; + else scan_chain[0] <= #FF_DELAY scan_in; + +always @(posedge test_clk) + if (scan_shift_n) scan_chain[1] <= #FF_DELAY d_out_n_mux[1]; + else scan_chain[1] <= #FF_DELAY scan_chain[0]; + +always @(posedge test_clk) + if (scan_shift_n) scan_chain[2] <= #FF_DELAY d_out_p_mux[0]; + else scan_chain[2] <= #FF_DELAY scan_chain[1]; + +always @(posedge test_clk) + if (scan_shift_n) scan_chain[3] <= #FF_DELAY d_out_p_mux[1]; + else scan_chain[3] <= #FF_DELAY scan_chain[2]; + +always @(*) + if (!test_clk) scan_out <= #LATCH_DELAY scan_chain[3]; + +//----------------------------------------------------- +// sampling for dcc +//----------------------------------------------------- + +an_io_phdet_ff_ln sample_reg_0 ( +.dp ( datovr ), +.dn ( datovrb ), +.clk_p ( sample_clk ), +.rst_n ( nfrzdrv ), +.q ( sample_value_0 ) +); + +an_io_phdet_ff_ln sample_reg_1 ( +.dp ( codin_n ), +.dn ( codin_nb ), +.clk_p ( sample_clk ), +.rst_n ( nfrzdrv ), +.q ( sample_value_1 ) +); + +an_io_phdet_ff_ln sample_reg_2 ( +.dp ( codin_p ), +.dn ( codin_pb ), +.clk_p ( sample_clk ), +.rst_n ( nfrzdrv ), +.q ( sample_value_2 ) +); + +an_io_phdet_ff_ln sample_reg_3 ( +.dp ( interpolator_clk[0] ), +.dn ( interpolator_clk[1] ), +.clk_p ( sample_clk ), +.rst_n ( nfrzdrv ), +.q ( sample_value_3 ) +); + +always @(*) + case (dcc_select[1:0]) + 2'b00 : sample_value = sample_value_0; + 2'b01 : sample_value = sample_value_1; + 2'b10 : sample_value = sample_value_2; + 2'b11 : sample_value = sample_value_3; + default : sample_value = sample_value_0; + endcase + +// synchronizer +/* +always @(posedge sample_clk or negedge nfrzdrv) + if (~nfrzdrv) sample_value_reg <= #FF_DELAY 1'b0; + else sample_value_reg <= #FF_DELAY sample_value; + +always @(posedge sample_clk or negedge nfrzdrv) + if (~nfrzdrv) dcc_sample <= #FF_DELAY 1'b0; + else dcc_sample <= #FF_DELAY sample_value_reg; +*/ + +always @(*) + if (~sample_clk) sample_value_reg_1 <= #LATCH_DELAY ~(sample_value & nfrzdrv); + +always @(*) + if (sample_clk) sample_value_reg_2 <= #LATCH_DELAY sample_value_reg_1; + +always @(*) + if (~sample_clk) sample_value_reg_3 <= #LATCH_DELAY ~sample_value_reg_2; + +always @(*) + if (sample_clk) dcc_sample_b <= #LATCH_DELAY ~sample_value_reg_3; + +assign dcc_sample = ~dcc_sample_b; + +endmodule diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_ioereg_struct_out.v b/maib_rtl/io_common_custom/rtl/block_function/io_ioereg_struct_out.v new file mode 100644 index 0000000..d04da26 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_ioereg_struct_out.v @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +module io_ioereg_struct_out ( +input [1:0] interpolator_clk, // Complimentary Clock output sent to io_ioereg_struct +input [1:0] d_out_p_mux, // I/O : Output P transistor before the final output mux +input [1:0] d_out_n_mux, // I/O : Output N transistor before the final output mux +output reg codin_p, // I/O : The high speed data output sent to the P type transistor + +output reg codin_pb, // I/O : The high speed data output sent to the P type transistor - +output reg codin_n, // I/O : The high speed data output sent to the N type transistor + +output reg codin_nb, // I/O : The high speed data output sent to the N type transistor - +input latch_open_n, // Static : 0 = force the latches open (GPIO & ATPG), 1 = clock the latches, Memory IF +input nfrzdrv, // freez signal +input loopback_p, // I/O : P-tran loopback +input loopback_n, // I/O : N-tran loopback +input loopback_en_n // I/O : Active low loopback enable +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter FF_DELAY = 80; +parameter LATCH_DELAY = 70; +parameter MUX_DELAY = 60; + +wire [1:0] clk_bf; +reg [1:0] latch_p; +reg [1:0] latch_n; + +//----------------------------------------------------- +// Output Mux +//----------------------------------------------------- +assign clk_bf[1:0] = nfrzdrv ? interpolator_clk[1:0] : 2'b10; + +//always @(*) +always @(*) + casez ({loopback_en_n,nfrzdrv,latch_open_n,clk_bf[1:0]}) + 5'b0_?_?_?? : {latch_p[1:0],latch_n[1:0]} <= #LATCH_DELAY {loopback_p,loopback_p,loopback_n,loopback_n}; + 5'b1_0_?_?? : {latch_p[1:0],latch_n[1:0]} <= #LATCH_DELAY {d_out_p_mux[1],d_out_p_mux[1],d_out_n_mux[1],d_out_n_mux[1]}; + 5'b1_1_0_?? : {latch_p[1:0],latch_n[1:0]} <= #LATCH_DELAY {d_out_p_mux[1],d_out_p_mux[0],d_out_n_mux[1],d_out_n_mux[0]}; + 5'b1_1_1_00 : {latch_p[1:0],latch_n[1:0]} <= #LATCH_DELAY {d_out_p_mux[1],d_out_p_mux[0],d_out_n_mux[1],d_out_n_mux[0]}; +// 5'b1_1_1_01 : {latch_p[1:0],latch_n[1:0]} <= #LATCH_DELAY {d_out_p_mux[1],latch_p[0],d_out_n_mux[1],latch_n[0]}; +// 5'b1_1_1_10 : {latch_p[1:0],latch_n[1:0]} <= #LATCH_DELAY {latch_p[1],d_out_p_mux[0],latch_n[1],d_out_n_mux[0]}; +// 5'b1_1_1_11 : {latch_p[1:0],latch_n[1:0]} <= #LATCH_DELAY {latch_p[1],latch_p[0],latch_n[1],latch_n[0]}; + 5'b1_1_1_01 : {latch_p[1],latch_n[1]} <= #LATCH_DELAY {d_out_p_mux[1],d_out_n_mux[1]}; + 5'b1_1_1_10 : {latch_p[0],latch_n[0]} <= #LATCH_DELAY {d_out_p_mux[0],d_out_n_mux[0]}; + 5'b1_1_1_11 : ; + endcase + +always @(*) + casez ({nfrzdrv,interpolator_clk[1:0]}) + 3'b0_?? : {codin_p,codin_pb,codin_n,codin_nb} = {latch_p[0],~latch_p[1],latch_n[0],~latch_n[1]}; + 3'b1_00 : {codin_p,codin_pb,codin_n,codin_nb} = {latch_p[0],~latch_p[0],latch_n[0],~latch_n[0]}; + 3'b1_01 : {codin_p,codin_pb,codin_n,codin_nb} = {latch_p[0],~latch_p[0],latch_n[0],~latch_n[0]}; + 3'b1_10 : {codin_p,codin_pb,codin_n,codin_nb} = {latch_p[1],~latch_p[1],latch_n[1],~latch_n[1]}; + 3'b1_11 : {codin_p,codin_pb,codin_n,codin_nb} = {latch_p[1],~latch_p[1],latch_n[1],~latch_n[1]}; + endcase + +endmodule diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_ip16phs.v b/maib_rtl/io_common_custom/rtl/block_function/io_ip16phs.v new file mode 100644 index 0000000..d0eec38 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_ip16phs.v @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// io_ip16phs +// The model supports a range from 1.6GHz to 0.8GHz for the phy's clock frequency +// The models intrinsic delay could be as large as 312 ps, the actual delay is smaller +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module io_ip16phs ( +input [2:0] c_in, // c_in[0] = First clock phase, c_in[1] = Second clock phase, c_in[2] = Third clock phase, +input [7:0] sp, // Thermometer code select +input [7:0] sn, // complimentary Thermometer code select +input [3:1] scp, // filter_cap selection: 111 = 1.6 GHz, 110 = 1.2 GHz, 100 = 1.0 GHz, 000 = 0.8 GHz +input [3:1] scn, // filter_cap selection: 000 = 1.6 GHz, 001 = 1.2 GHz, 011 = 1.0 GHz, 111 = 0.8 GHz +input [6:0] selp, // code for 2 phase interpolator (including decode for test) +input [6:0] seln, // complimentary code for 2 phase interpolator (including decode for test) +`ifndef SYN +output reg c_out // Clock out +`else +output c_out // Clock out +`endif +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +`ifndef SYN +integer message_flag; +time intrinsic; +time a_time, b_time; +time c_a_time, c_b_time; +time calc_delay; +time del_2x, rem_2x, del_1x, del_0x; +wire [4:0] c_sig; +reg pmx_2, pmx_1, pmx_0; + +//-------------------------------------------------------------------------------------------------------------------------------------------- +//--- Calculate the delay of the interpolator +//-------------------------------------------------------------------------------------------------------------------------------------------- + +initial message_flag = 1; + +always @(*) + case (scn[3:1]) + 3'b000 : intrinsic = 200; // Supports 0.95 GHz - 1.9 GHz + 3'b001 : intrinsic = 260; // Supports 0.75 GHz - 1.5 GHz + 3'b011 : intrinsic = 320; // Supports 0.60 GHz - 1.2 GHz + 3'b111 : intrinsic = 400; // Supports 0.50 GHz - 1.0 GHz + default : intrinsic = 400; // Supports 0.50 GHz - 1.0 GHz + endcase + +always @(c_in[0]) a_time = $time; +always @(c_in[1]) b_time = $time; +always @(c_in[2]) + begin + c_a_time = $time - a_time; + c_b_time = $time - b_time; + + if ((2 * intrinsic) < (c_a_time + c_b_time)) + begin + if (message_flag == 1) + begin + case (scn[3:1]) + 3'b000 : $display("Warning : The 8 phase phy clock frequency is lower than 0.95 GHz, measured phase period = %t and/or %t",(c_a_time / 2),c_b_time); + 3'b001 : $display("Warning : The 8 phase phy clock frequency is lower than 0.75 GHz, measured phase period = %t and/or %t",(c_a_time / 2),c_b_time); + 3'b011 : $display("Warning : The 8 phase phy clock frequency is lower than 0.60 GHz, measured phase period = %t and/or %t",(c_a_time / 2),c_b_time); + 3'b111 : $display("Warning : The 8 phase phy clock frequency is lower than 0.50 GHz, measured phase period = %t and/or %t",(c_a_time / 2),c_b_time); + endcase + $display("Warning : At time = %t\n %m",$time); + end + calc_delay = 0; + message_flag = 0; // Don't repeat the message + end + else + begin + case ({seln[3],sp[7:0]}) + 9'b0_0000_0000 : calc_delay = intrinsic - ((c_b_time + (16 * c_a_time)/16)/2); + 9'b0_0000_0001 : calc_delay = intrinsic - ((c_b_time + (15 * c_a_time)/16)/2); + 9'b0_0000_0011 : calc_delay = intrinsic - ((c_b_time + (14 * c_a_time)/16)/2); + 9'b0_0000_0111 : calc_delay = intrinsic - ((c_b_time + (13 * c_a_time)/16)/2); + 9'b0_0000_1111 : calc_delay = intrinsic - ((c_b_time + (12 * c_a_time)/16)/2); + 9'b0_0001_1111 : calc_delay = intrinsic - ((c_b_time + (11 * c_a_time)/16)/2); + 9'b0_0011_1111 : calc_delay = intrinsic - ((c_b_time + (10 * c_a_time)/16)/2); + 9'b0_0111_1111 : calc_delay = intrinsic - ((c_b_time + ( 9 * c_a_time)/16)/2); + 9'b1_1111_1111 : calc_delay = intrinsic - ((c_b_time + ( 8 * c_a_time)/16)/2); + 9'b1_0111_1111 : calc_delay = intrinsic - ((c_b_time + ( 7 * c_a_time)/16)/2); + 9'b1_0011_1111 : calc_delay = intrinsic - ((c_b_time + ( 6 * c_a_time)/16)/2); + 9'b1_0001_1111 : calc_delay = intrinsic - ((c_b_time + ( 5 * c_a_time)/16)/2); + 9'b1_0000_1111 : calc_delay = intrinsic - ((c_b_time + ( 4 * c_a_time)/16)/2); + 9'b1_0000_0111 : calc_delay = intrinsic - ((c_b_time + ( 3 * c_a_time)/16)/2); + 9'b1_0000_0011 : calc_delay = intrinsic - ((c_b_time + ( 2 * c_a_time)/16)/2); + 9'b1_0000_0001 : calc_delay = intrinsic - ((c_b_time + ( 1 * c_a_time)/16)/2); + default : calc_delay = intrinsic - ((c_b_time + ( 1 * c_a_time)/16)/2); + endcase + message_flag = 1; + end + + del_2x = calc_delay / 100; // 100 ps + rem_2x = calc_delay - (del_2x * 100); + del_1x = rem_2x / 10; // 10 ps + del_0x = rem_2x - (del_1x * 10); // 1 ps + + end + +//-------------------------------------------------------------------------------------------------------------------------------------------- +//--- Delay the signal +//-------------------------------------------------------------------------------------------------------------------------------------------- + +assign #10 c_sig[0] = c_in[2]; +assign #100 c_sig[1] = c_sig[0]; +assign #100 c_sig[2] = c_sig[1]; +assign #100 c_sig[3] = c_sig[2]; +assign #100 c_sig[4] = c_sig[3]; + +always @(*) + case (del_2x) + 0 : pmx_2 = c_sig[0]; + 1 : pmx_2 = c_sig[1]; + 2 : pmx_2 = c_sig[2]; + 3 : pmx_2 = c_sig[3]; + 4 : pmx_2 = c_sig[4]; + default : pmx_2 = c_sig[4]; + endcase + +always @(*) + case (del_1x) + 0 : pmx_1 <= #0 pmx_2; + 1 : pmx_1 <= #10 pmx_2; + 2 : pmx_1 <= #20 pmx_2; + 3 : pmx_1 <= #30 pmx_2; + 4 : pmx_1 <= #40 pmx_2; + 5 : pmx_1 <= #50 pmx_2; + 6 : pmx_1 <= #60 pmx_2; + 7 : pmx_1 <= #70 pmx_2; + 8 : pmx_1 <= #80 pmx_2; + 9 : pmx_1 <= #90 pmx_2; + default : pmx_1 <= #90 pmx_2; + endcase + +always @(*) + case (del_0x) + 0 : pmx_0 <= #0 pmx_1; + 1 : pmx_0 <= #1 pmx_1; + 2 : pmx_0 <= #2 pmx_1; + 3 : pmx_0 <= #3 pmx_1; + 4 : pmx_0 <= #4 pmx_1; + 5 : pmx_0 <= #5 pmx_1; + 6 : pmx_0 <= #6 pmx_1; + 7 : pmx_0 <= #7 pmx_1; + 8 : pmx_0 <= #8 pmx_1; + 9 : pmx_0 <= #9 pmx_1; + default : pmx_0 <= #9 pmx_1; + endcase + +//assign c_out = pmx_0; + +always @(*) + casez (seln[6:0]) + 7'b101_0011 : c_out = pmx_0; //int_a=(clk_in_a+clk_in_b)/2; int_c=clk_in_b; + 7'b101_1010 : c_out = pmx_0; //int_c=clk_in_b; int_a=(clk_in_b+clk_in_c)/2; + 7'b000_0011 : c_out = c_in[0]; //int_a=int_c=clk_in_a; + 7'b001_0000 : c_out = c_in[1]; //int_a=int_c=clk_in_b; + 7'b100_1000 : c_out = c_in[2]; //int_a=int_c=clk_in_c; + default : c_out = pmx_0; //default will not happen with io_cmos_16ph_decode + endcase + +`else +assign c_out = c_in[2]; +`endif + +endmodule diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_ip8phs_3in.v b/maib_rtl/io_common_custom/rtl/block_function/io_ip8phs_3in.v new file mode 100644 index 0000000..368c26c --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_ip8phs_3in.v @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// io_ip8phs_3in +// The model supports a NAND step size up to 60 ns +// The models intrinsic delay could be as large as 120 ps, the actual delay could be larger +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module io_ip8phs_3in ( +input a_in, // a_in = First clock phase +input b_in, // b_in = Second clock phase +input c_in, // c_in = Third clock phase, +input svcc, // +input [6:0] sp, // thermal code +input [6:0] sn, // inverted thermal code +output clk_outb // Clock out +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +`ifndef SYN +integer message_flag; +time intrinsic; +time a_time, b_time; +time c_a_time, c_b_time; +time calc_delay; +time del_2x, rem_2x, del_1x, del_0x; +wire [2:0] c_sig; +reg pmx_2, pmx_1, pmx_0; + +//-------------------------------------------------------------------------------------------------------------------------------------------- +//--- Calculate the delay of the interpolator +//-------------------------------------------------------------------------------------------------------------------------------------------- + +initial intrinsic = 120; // Supports 80 ps step size + +always @(a_in) a_time = $time; +always @(b_in) b_time = $time; +always @(c_in) + begin + c_a_time = $time - a_time; + c_b_time = $time - b_time; + + if ((2 * intrinsic) < (c_a_time + c_b_time)) + begin + if (message_flag == 1) + begin + $display("Warning : The Nand Delay chain step size is larger than 80 ps, measured step size = %t and/or %t",(c_a_time / 2),c_b_time); + $display("Warning : At time = %t\n %m",$time); + end + calc_delay = 0; + message_flag = 0; // Don't repeat the message + end + else + begin + case (sp[6:0]) + 7'b000_0000 : calc_delay = intrinsic - ((c_b_time + (16 * c_a_time)/16)/2); + 7'b000_0001 : calc_delay = intrinsic - ((c_b_time + (14 * c_a_time)/16)/2); + 7'b000_0011 : calc_delay = intrinsic - ((c_b_time + (12 * c_a_time)/16)/2); + 7'b000_0111 : calc_delay = intrinsic - ((c_b_time + (10 * c_a_time)/16)/2); + 7'b000_1111 : calc_delay = intrinsic - ((c_b_time + (8 * c_a_time)/16)/2); + 7'b001_1111 : calc_delay = intrinsic - ((c_b_time + (6 * c_a_time)/16)/2); + 7'b011_1111 : calc_delay = intrinsic - ((c_b_time + (4 * c_a_time)/16)/2); + 7'b111_1111 : calc_delay = intrinsic - ((c_b_time + (2 * c_a_time)/16)/2); + default : calc_delay = intrinsic - ((c_b_time + (2 * c_a_time)/16)/2); + endcase + message_flag = 1; + end + + del_2x = calc_delay / 100; // 100 ps + rem_2x = calc_delay - (del_2x * 100); + del_1x = rem_2x / 10; // 10 ps + del_0x = rem_2x - (del_1x * 10); // 1 ps + + end + +//-------------------------------------------------------------------------------------------------------------------------------------------- +//--- Delay the signal +//-------------------------------------------------------------------------------------------------------------------------------------------- + +assign #10 c_sig[0] = c_in; +assign #100 c_sig[1] = c_sig[0]; +assign #100 c_sig[2] = c_sig[1]; + +always @(*) + case (del_2x) + 0 : pmx_2 = c_sig[0]; + 1 : pmx_2 = c_sig[1]; + 2 : pmx_2 = c_sig[2]; + default : pmx_2 = c_sig[2]; + endcase + +always @(*) + case (del_1x) + 0 : pmx_1 <= #0 pmx_2; + 1 : pmx_1 <= #10 pmx_2; + 2 : pmx_1 <= #20 pmx_2; + 3 : pmx_1 <= #30 pmx_2; + 4 : pmx_1 <= #40 pmx_2; + 5 : pmx_1 <= #50 pmx_2; + 6 : pmx_1 <= #60 pmx_2; + 7 : pmx_1 <= #70 pmx_2; + 8 : pmx_1 <= #80 pmx_2; + 9 : pmx_1 <= #90 pmx_2; + default : pmx_1 <= #90 pmx_2; + endcase + +always @(*) + case (del_0x) + 0 : pmx_0 <= #0 pmx_1; + 1 : pmx_0 <= #1 pmx_1; + 2 : pmx_0 <= #2 pmx_1; + 3 : pmx_0 <= #3 pmx_1; + 4 : pmx_0 <= #4 pmx_1; + 5 : pmx_0 <= #5 pmx_1; + 6 : pmx_0 <= #6 pmx_1; + 7 : pmx_0 <= #7 pmx_1; + 8 : pmx_0 <= #8 pmx_1; + 9 : pmx_0 <= #9 pmx_1; + default : pmx_0 <= #9 pmx_1; + endcase + +assign clk_outb = ~pmx_0; +`else +assign clk_outb = ~c_in; +`endif + +endmodule + + + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_min_inter.v b/maib_rtl/io_common_custom/rtl/block_function/io_min_inter.v new file mode 100644 index 0000000..2072c2e --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_min_inter.v @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #2 $ +// Date: $DateTime: 2014/10/18 21:47:06 $ +//------------------------------------------------------------------------ +// Description: Delay cell used to match the delay of the interpolator +// +//------------------------------------------------------------------------ + +module io_min_inter ( +input [7:0] phy_clk_phs, // 8 phase 1.6GHz local clock +input [1:0] rb_filter_code, // 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz +input test_enable, // Active high test enable 1: avoid tristate on output of interp_mux during testing +input rb_couple_enable, // Active high cross couple enable +input nfrzdrv, // for power domain crossing protection +input pdn, // Active low power down +output c_out // +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +wire [7:0] phy_clk_phs_gated; // 8 phase 1.6GHz local clock +wire [1:0] interp_clk_x; +wire [1:0] c_out_x; +wire [3:1] scp; +wire [3:1] scn; +wire svcc; +wire c_out_nc; + +//================================================================================================================================================================================= +// +//================================================================================================================================================================================= + +io_min_pdn xphs_gated ( +.pdn ( pdn ), // power down active low +.phy_clk_phs ( phy_clk_phs[7:0] ), // 8 phase 1.6GHz local clock +.phy_clk_phs_gated ( phy_clk_phs_gated[7:0] ) // gated 8 phase 1.6GHz local clock +); + +io_min_interp_mux ximp ( .phy_clk_phs(phy_clk_phs_gated[3:0]), .c_out(clk_p), .svcc(svcc) ); +io_min_interp_mux ximn ( .phy_clk_phs(phy_clk_phs_gated[7:4]), .c_out(clk_n), .svcc(svcc) ); + +io_min_ip16phs xip16p ( + .c_in ( clk_p ), + .scp ( scp[3:1] ), + .scn ( scn[3:1] ), + .c_out ( interp_clk_x[0] ) +); + +io_min_ip16phs xip16n ( + .c_in ( clk_n ), + .scp ( scp[3:1] ), + .scn ( scn[3:1] ), + .c_out ( interp_clk_x[1] ) +); + +io_min_misc xminmisc ( +.filter_code (rb_filter_code[1:0] ), // 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz +.c_out_x (c_out_x[1:0] ), // interpolator clock for pnr/dpa +.couple_enable (rb_couple_enable ), // cross coupling enable +.nfrzdrv (nfrzdrv ), // for power domain crossing protection +.test_enable (test_enable ), // Active high test enable 1: avoid tristate on output of interp_mux during testing +.c_out ({c_out_nc,c_out} ), // interpolator clock for pnr/dpa +.pon (pon ), // cross couple control for p fingers +.non (non ), // cross couple control for n fingers +.scp (scp[3:1] ), // filter capacitance selection +.scn (scn[3:1] ), // filter capacitance selection +.svcc (svcc ), // for test +.test_enable_n (test_enable_n ) +); + +io_min_output xminoutput ( +.interp_clk_x (interp_clk_x[1:0] ), // clock generated from min_ip16phs +.test_enable_n (test_enable_n ), // Active low test enable +.pon (pon ), // cross coupling enable p finger +.non (non ), // cross coupling enable n finger +.enable (nfrzdrv ), // latch enable +.svcc (svcc ), // soft tie vcc +.int_clk_out (c_out_x[1:0] ) // +); + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_min_interp_mux.v b/maib_rtl/io_common_custom/rtl/block_function/io_min_interp_mux.v new file mode 100644 index 0000000..2810695 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_min_interp_mux.v @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +module io_min_interp_mux ( + +input [3:0] phy_clk_phs, // half of 8 phase 1.6GHz clock +input svcc, // for soft tie high +output c_out // 1 of the 3 output phases +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter INVERTER_DELAY = 15; +parameter FINGER_DELAY = 45; + +wire out_vl; + +//-------------------------------------------------------------------------------------------------- +// Finger Mux delay for phs[0] +//-------------------------------------------------------------------------------------------------- + +assign #FINGER_DELAY out_vl = phy_clk_phs[1]; +assign #(2 * INVERTER_DELAY) c_out = out_vl; + +endmodule + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_min_ip16phs.v b/maib_rtl/io_common_custom/rtl/block_function/io_min_ip16phs.v new file mode 100644 index 0000000..374e78f --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_min_ip16phs.v @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// io_min_ip16phs +// The model supports a range from 1.6GHz to 0.8GHz for the phy's clock frequency +// The models intrinsic delay could be as large as 312 ps, the actual delay is smaller +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module io_min_ip16phs ( +input c_in, // Clock in +input [3:1] scp, // filter_cap selection: 111 = 1.6 GHz, 110 = 1.2 GHz, 100 = 1.0 GHz, 000 = 0.8 GHz +input [3:1] scn, // filter_cap selection: 000 = 1.6 GHz, 001 = 1.2 GHz, 011 = 1.0 GHz, 111 = 0.8 GHz +output c_out // Clock out +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +`ifndef SYN +time intrinsic; +time c_time; +time c_c_time; +time calc_delay; +time del_2x, rem_2x, del_1x, del_0x; +wire [4:0] c_sig; +reg pmx_2, pmx_1, pmx_0; + +//-------------------------------------------------------------------------------------------------------------------------------------------- +//--- Calculate the delay of the interpolator +//-------------------------------------------------------------------------------------------------------------------------------------------- + +always @(*) + case (scn[3:1]) + 3'b000 : intrinsic = 200; // Supports 0.95 GHz - 1.9 GHz + 3'b001 : intrinsic = 260; // Supports 0.75 GHz - 1.5 GHz + 3'b011 : intrinsic = 320; // Supports 0.60 GHz - 1.2 GHz + 3'b111 : intrinsic = 400; // Supports 0.50 GHz - 1.0 GHz + default : intrinsic = 400; // Supports 0.50 GHz - 1.0 GHz + endcase + +always @(posedge c_in) c_time = $time; +always @(negedge c_in) + begin + #100 ; + c_c_time = $time - c_time ; + calc_delay = intrinsic - (c_c_time/4); + + del_2x = calc_delay / 100; // 100 ps + rem_2x = calc_delay - (del_2x * 100); + del_1x = rem_2x / 10; // 10 ps + del_0x = rem_2x - (del_1x * 10); // 1 ps + + end + +//-------------------------------------------------------------------------------------------------------------------------------------------- +//--- Delay the signal +//-------------------------------------------------------------------------------------------------------------------------------------------- + +assign #10 c_sig[0] = c_in; +assign #100 c_sig[1] = c_sig[0]; +assign #100 c_sig[2] = c_sig[1]; +assign #100 c_sig[3] = c_sig[2]; +assign #100 c_sig[4] = c_sig[3]; + +always @(*) + case (del_2x) + 0 : pmx_2 = c_sig[0]; + 1 : pmx_2 = c_sig[1]; + 2 : pmx_2 = c_sig[2]; + 3 : pmx_2 = c_sig[3]; + 4 : pmx_2 = c_sig[4]; + default : pmx_2 = c_sig[4]; + endcase + +always @(*) + case (del_1x) + 0 : pmx_1 = #0 pmx_2; + 1 : pmx_1 = #10 pmx_2; + 2 : pmx_1 = #20 pmx_2; + 3 : pmx_1 = #30 pmx_2; + 4 : pmx_1 = #40 pmx_2; + 5 : pmx_1 = #50 pmx_2; + 6 : pmx_1 = #60 pmx_2; + 7 : pmx_1 = #70 pmx_2; + 8 : pmx_1 = #80 pmx_2; + 9 : pmx_1 = #90 pmx_2; + default : pmx_1 = #90 pmx_2; + endcase + +always @(*) + case (del_0x) + 0 : pmx_0 = #0 pmx_1; + 1 : pmx_0 = #1 pmx_1; + 2 : pmx_0 = #2 pmx_1; + 3 : pmx_0 = #3 pmx_1; + 4 : pmx_0 = #4 pmx_1; + 5 : pmx_0 = #5 pmx_1; + 6 : pmx_0 = #6 pmx_1; + 7 : pmx_0 = #7 pmx_1; + 8 : pmx_0 = #8 pmx_1; + 9 : pmx_0 = #9 pmx_1; + default : pmx_0 = #9 pmx_1; + endcase + +assign c_out = pmx_0; + +`else +assign c_out = c_in; +`endif + +endmodule + + + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_min_misc.v b/maib_rtl/io_common_custom/rtl/block_function/io_min_misc.v new file mode 100644 index 0000000..51a3d3c --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_min_misc.v @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +// io_min_misc : misc block for interpolator +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +module io_min_misc ( +input [1:0] filter_code, // 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz +input [1:0] c_out_x, // interpolator clock for pnr/dpa +input couple_enable, // cross coupling enable +input nfrzdrv, // for power domain crossing protection +input test_enable, // Active high test enable 1: avoid tristate on output of interp_mux during testing +output [1:0] c_out, // interpolator clock for pnr/dpa +output pon, // cross couple control for p fingers +output non, // cross couple control for n fingers +output [3:1] scp, // filter capacitance selection +output reg [3:1] scn, // filter capacitance selection +output svcc, // for test +output test_enable_n // Active low test enable +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter INV_DELAY = 15; // 15ps +parameter LATCH_DELAY = 50; // 50ps +parameter BUF_DELAY = 25; // 25ps +parameter MUX_DELAY = 50; // 50ps + +assign svcc = 1'b1; +assign test_enable_n = ~test_enable; +assign #(2 * INV_DELAY) c_out[1:0] = c_out_x[1:0] & {2{nfrzdrv}}; +assign non = couple_enable & test_enable_n; +assign pon = ~non; + +//filter code decode +always @(*) + case (filter_code[1:0]) + 2'b00 : scn[3:1] = 3'b000; + 2'b01 : scn[3:1] = 3'b001; + 2'b10 : scn[3:1] = 3'b011; + 2'b11 : scn[3:1] = 3'b111; + endcase +assign #INV_DELAY scp[3:1] = ~scn[3:1]; + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_min_output.v b/maib_rtl/io_common_custom/rtl/block_function/io_min_output.v new file mode 100644 index 0000000..06f8180 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_min_output.v @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #2 $ +// Date: $DateTime: 2014/10/18 21:47:06 $ +//------------------------------------------------------------------------ +// Description: Delay cell used to match the delay of the interpolator +// +//------------------------------------------------------------------------ + +module io_min_output ( +input [1:0] interp_clk_x, // clock generated from min_ip16phs +input test_enable_n, // Active low test enable +input pon, // cross coupling enable p finger +input non, // cross coupling enable n finger +input enable, // latch enable +input svcc, // soft tie vcc +output [1:0] int_clk_out // +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +wire [1:0] interp_clk; + +//================================================================================================================================================================================= +// +//================================================================================================================================================================================= + +assign interp_clk = interp_clk_x[1:0]; + +an_io_double_edge_ff xdouble_edge_ff ( +.clk_in ( interp_clk[1:0] ), +.test_enable_n ( test_enable_n ), +.reset_n ( enable ), +.data_in ( 2'b01 ), // pass through +.data_out ( int_clk_out[1:0] ) +); + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_min_pdn.v b/maib_rtl/io_common_custom/rtl/block_function/io_min_pdn.v new file mode 100644 index 0000000..0fd11d3 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_min_pdn.v @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #1 $ +// Date: $DateTime: 2014/09/20 12:06:43 $ +//------------------------------------------------------------------------ +// Description: gated 8 clock phases for powerdown and regulator power domain crossing +// +//------------------------------------------------------------------------ + +module io_min_pdn ( +input pdn, // power down active low +input [7:0] phy_clk_phs, // 8 phase 1.6GHz local clock +output [7:0] phy_clk_phs_gated // gated 8 phase 1.6GHz local clock +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter INV_DELAY = 15; // 15ps + +assign #(2 * INV_DELAY) phy_clk_phs_gated[3:0] = phy_clk_phs[3:0] & {4{pdn}}; +assign #(2 * INV_DELAY) phy_clk_phs_gated[7:4] = phy_clk_phs[7:4] | {4{~pdn}}; + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_nand_delay_line_min.v b/maib_rtl/io_common_custom/rtl/block_function/io_nand_delay_line_min.v new file mode 100644 index 0000000..1cb9ba2 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_nand_delay_line_min.v @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// io_nand_delay_line_min +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module io_nand_delay_line_min( +input nfrzdrv, +input in_p, +input in_n, +output out_p, +output out_n +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter NAND_DELAY = 20; + +wire fout_p; +wire fout_n; +wire osc_out_p; +wire osc_out_n; + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// +//--------------------------------------------------------------------------------------------------------------------------------------------- + +io_cmos_nand_x1 xnandx1 ( +.in_p ( in_p ), +.in_n ( in_n ), +.bk ( 1'b0 ), +.ci_p ( 1'b1 ), +.ci_n ( 1'b1 ), +.out_p ( fout_p ), +.out_n ( fout_n ), +.co_p ( ), +.co_n ( ) +); + +io_dly_interpolator xinterp ( +.nfrzdrv ( nfrzdrv ), +.fout_p ( fout_p ), +.fout_n ( fout_n ), +.gray ( 3'b000 ), +.out_p ( out_p ), +.out_n ( out_n ), +.osc_out_p ( osc_out_p ), +.osc_out_n ( osc_out_n ) +); + +endmodule + + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_nand_x128_delay_line.v b/maib_rtl/io_common_custom/rtl/block_function/io_nand_x128_delay_line.v new file mode 100644 index 0000000..6b30ae6 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_nand_x128_delay_line.v @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// io_cmos_nand_delay_line +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module io_nand_x128_delay_line ( +input nfrzdrv, +input in_p, +input in_n, +input osc_mode, // Mux control for the x64 ring oscillator +input osc_in_p, // input for the x64 ring oscillator +input osc_in_n, // input for the x64 ring oscillator +output osc_out_p, // output for the x64 ring oscillator +output osc_out_n, // output for the x64 ring oscillator +input [6:0] f_gray, +input [2:0] i_gray, +output out_p, +output out_n +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter NAND_DELAY = 20; + +wire fout_p; +wire fout_n; +wire x128_in_p; +wire x128_in_n; + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// input mux +//--------------------------------------------------------------------------------------------------------------------------------------------- + +assign x128_in_p = osc_mode ? osc_in_p : in_p; +assign x128_in_n = osc_mode ? osc_in_n : in_n; + +io_cmos_nand_x128 xnand128 ( +.in_p ( x128_in_p ), +.in_n ( x128_in_n ), +.gray ( f_gray[6:0] ), +.out_p ( fout_p ), +.out_n ( fout_n ) +); + +io_dly_interpolator xinterp ( +.nfrzdrv ( nfrzdrv ), +.fout_p ( fout_p ), +.fout_n ( fout_n ), +.gray ( i_gray[2:0] ), +.out_p ( out_p ), +.out_n ( out_n ), +.osc_out_p ( osc_out_p ), +.osc_out_n ( osc_out_n ) + +); + +endmodule + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_nand_x64_delay_line.v b/maib_rtl/io_common_custom/rtl/block_function/io_nand_x64_delay_line.v new file mode 100644 index 0000000..a288c99 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_nand_x64_delay_line.v @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// io_nand_x64_delay_line +//--------------------------------------------------------------------------------------------------------------------------------------------- + +module io_nand_x64_delay_line ( +input nfrzdrv, +input in_p, +input in_n, +input osc_mode, // Mux control for the x64 ring oscillator +input osc_in_p, // input for the x64 ring oscillator +input osc_in_n, // input for the x64 ring oscillator +output osc_out_p, // output for the x64 ring oscillator +output osc_out_n, // output for the x64 ring oscillator +input [5:0] f_gray, +input [2:0] i_gray, +output out_p, +output out_n +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter NAND_DELAY = 20; + +wire x64_in_p; +wire x64_in_n; +wire fout_p; +wire fout_n; +wire a63; +wire c63; + + +//--------------------------------------------------------------------------------------------------------------------------------------------- +// +//--------------------------------------------------------------------------------------------------------------------------------------------- + +assign x64_in_p = osc_mode ? osc_in_p : in_p; +assign x64_in_n = osc_mode ? osc_in_n : in_n; + +io_cmos_nand_x64 xnand64 ( +.b63 ( 1'b1 ), +.d63 ( 1'b1 ), +.in_p ( x64_in_p ), +.in_n ( x64_in_n ), +.gray ( {1'b0, f_gray[5:0]} ), +.a63 ( a63 ), +.c63 ( c63 ), +.out_p ( fout_p ), +.out_n ( fout_n ) +); + +io_dly_interpolator xinterp ( +.nfrzdrv ( nfrzdrv ), +.fout_p ( fout_p ), +.fout_n ( fout_n ), +.gray ( i_gray[2:0] ), +.out_p ( out_p ), +.out_n ( out_n ), +.osc_out_p ( osc_out_p ), +.osc_out_n ( osc_out_n ) + +); + +endmodule + + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_pa_custom.v b/maib_rtl/io_common_custom/rtl/block_function/io_pa_custom.v new file mode 100644 index 0000000..d0ae427 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_pa_custom.v @@ -0,0 +1,243 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #4 $ +// Date: $DateTime: 2014/11/15 16:17:29 $ +//------------------------------------------------------------------------ +// Description: IO PHASE ALIGNMENT TOP +// +//------------------------------------------------------------------------ + + +module io_pa_custom #( +parameter NAND_DELAY = 15, +parameter FF_DELAY = 100 +) +( + input wire pa_reset_n, // reset for phase alignment, come from core + input wire nfrzdrv, // core control signal + input wire [7:0] phy_clk_phs, // 8 clock phase from PLL + input wire pdn, // Active low power down control from pnr for 8 phases + input wire test_enable, // Active high test enable 1: avoid tristate on output of interp_mux during testing + input wire [2:0] mux_sel_a_master_0, // The gray code to control the first of the 8 to 1 phase multiplexer + input wire [2:0] mux_sel_b_master_0, // The gray code to control the second of the 8 to 1 phase multiplexer + input wire [2:0] mux_sel_a_master_1, // The gray code to control the first of the 8 to 1 phase multiplexer + input wire [2:0] mux_sel_b_master_1, // The gray code to control the second of the 8 to 1 phase multiplexer + input wire [2:0] mux_sel_a_slave_0, // The gray code to control the first of the 8 to 1 phase multiplexer + input wire [2:0] mux_sel_b_slave_0, // The gray code to control the second of the 8 to 1 phase multiplexer + input wire [2:0] mux_sel_a_slave_1, // The gray code to control the first of the 8 to 1 phase multiplexer + input wire [2:0] mux_sel_b_slave_1, // The gray code to control the second of the 8 to 1 phase multiplexer + input wire [3:0] interp_sel_a_master_0, // The gray code output to control the interpolator + input wire [3:0] interp_sel_b_master_0, // The gray code output to control the interpolator + input wire [3:0] interp_sel_a_master_1, // The gray code output to control the interpolator + input wire [3:0] interp_sel_b_master_1, // The gray code output to control the interpolator + input wire [3:0] interp_sel_a_slave_0, // The gray code output to control the interpolator + input wire [3:0] interp_sel_b_slave_0, // The gray code output to control the interpolator + input wire [3:0] interp_sel_a_slave_1, // The gray code output to control the interpolator + input wire [3:0] interp_sel_b_slave_1, // The gray code output to control the interpolator + input wire [1:0] rbpa_filter_code, // 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz + input wire rbpa_couple_enable, // cross couple enable + input wire [1:0] dirty_clk_master_0, // The clock outputs with a duty cycle that is not 50%, The Interpolator will modify this clock to 50% duty cycle + input wire [1:0] dirty_clk_master_1, // The clock outputs with a duty cycle that is not 50%, The Interpolator will modify this clock to 50% duty cycle + input wire [1:0] dirty_clk_slave_0, // The clock outputs with a duty cycle that is not 50%, The Interpolator will modify this clock to 50% duty cycle + input wire [1:0] dirty_clk_slave_1, // The clock outputs with a duty cycle that is not 50%, The Interpolator will modify this clock to 50% duty cycle + input wire [2:0] phx_sel_master_0, // The gray code output to control the clk_accum phase from of the 8 to 1 phase multiplexer + input wire [2:0] phx_sel_master_1, // The gray code output to control the clk_accum phase from of the 8 to 1 phase multiplexer + + output wire clk_ph_0_buf, + output wire phx_clk_master_0, + output wire phx_clk_master_1, + output wire int_clk_master_0, // Clocks from the output of the 3 (8 to 1 phase select multiplexers) clk_p[0] arrives first, clk_p[2] arrives last + output wire int_clk_master_1, // Clocks from the output of the 3 (8 to 1 phase select multiplexers) clk_p[0] arrives first, clk_p[2] arrives last + output wire int_clk_slave_0, // Clocks from the output of the 3 (8 to 1 phase select multiplexers) clk_p[0] arrives first, clk_p[2] arrives last + output wire int_clk_slave_1, // Clocks from the output of the 3 (8 to 1 phase select multiplexers) clk_p[0] arrives first, clk_p[2] arrives last + output wire [1:0] clk_hps, // clock sent to the HPS + output wire [1:0] core_clk_out, // Clock output sent to the core + output wire [1:0] periphery_clk_out // Periphery Clock output sent to the phy_clk tree +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +//---------------------------------------------------------------------------------------------------------------------------------------------------------------- +// wire & reg +//---------------------------------------------------------------------------------------------------------------------------------------------------------------- + + wire [7:0] phy_clk_phs_gated; // gated 8 phases + wire [7:0] slow_clk_ph_p; // buffered 8 phase 1.6GHz local clock combined with reset + wire [7:0] slow_clk_ph_n; // buffered 8 phase 1.6GHz local clock combined with reset + wire [2:0] phx_master_0_buf; // buffered gray code for interp_mux + wire [2:0] phx_master_1_buf; // buffered gray code for interp_mux + wire [2:0] phx_slave_0_buf; // buffered gray code for interp_mux + wire [2:0] phx_slave_1_buf; // buffered gray code for interp_mux + wire [2:0] phx_master_0_inv; // Inverted gray code for interp_mux + wire [2:0] phx_master_1_inv; // Inverted gray code for interp_mux + wire [2:0] phx_slave_0_inv; // Inverted gray code for interp_mux + wire [2:0] phx_slave_1_inv; // Inverted gray code for interp_mux + wire test_enable_n; + wire dft_mux_sel; + wire [1:0] periphery_clk_x; // periphery_clk from io_interpolator + wire [1:0] core_clk_x; // core_clk from io_interpolator + wire [5:0] dummy; // ports not used + +//----------------------------------------------------------------------------------------------------------------------- +// custom design portion +//----------------------------------------------------------------------------------------------------------------------- + +//----------------------------------------------------------------------------------------------------------------------- +// phx clock io_interp_muxes : +//----------------------------------------------------------------------------------------------------------------------- + +io_pa_phs_gated xio_phs_gated ( +.nfrzdrv ( pdn ), // active low +.phy_clk_phs ( phy_clk_phs[7:0] ), // 8 phase 1.6GHz local clock +.phy_clk_phs_gated ( phy_clk_phs_gated[7:0] ) // gated 8 phase 1.6GHz local clock +); + +io_pa_phs_buf xio_pa_phs_buf( +.reset_n (pa_reset_n ), +.nfrzdrv (nfrzdrv ), +.test_enable (test_enable ), +.phy_clk_phs (phy_clk_phs_gated[7:0] ), +.phx_sel_master_0 (phx_sel_master_0[2:0] ), +.phx_sel_master_1 (phx_sel_master_1[2:0] ), +.periphery_clk_x (periphery_clk_x[1:0] ), // periphery_clk from io_interpolator +.core_clk_x (core_clk_x[1:0] ), // core_clk from io_interpolator +.periphery_clk_out (periphery_clk_out[1:0] ), // Clock feedback to the periphery +.core_clk_out (core_clk_out[1:0] ), // Clock feedback to the core +.phx_master_0_buf (phx_master_0_buf[2:0] ), +.phx_master_1_buf (phx_master_1_buf[2:0] ), +.phx_master_0_inv (phx_master_0_inv[2:0] ), +.phx_master_1_inv (phx_master_1_inv[2:0] ), +.slow_clk_ph_p (slow_clk_ph_p[7:0] ), +.slow_clk_ph_n (slow_clk_ph_n[7:0] ), +.test_enable_n (test_enable_n ), +.dft_mux_sel (dft_mux_sel ) +); + +io_interp_mux_match xinterp_mux_0 ( +.slow_clk_ph_p (slow_clk_ph_p[7:0] ), +.slow_clk_ph_n (slow_clk_ph_n[7:0] ), +.phy_clk_phs (phy_clk_phs_gated[7:0] ), +.gray_a_buf (3'b000 ), +.gray_b_buf (3'b000 ), +.gray_a_inv (3'b111 ), +.gray_b_inv (3'b111 ), +.int_clk_out (clk_ph_0_buf ), +.nfrzdrv (nfrzdrv ), +.test_enable_n (test_enable_n ), +.dft_mux_sel (dft_mux_sel ) +); + +io_interp_mux_match xinterp_mux_1 ( +.slow_clk_ph_p (slow_clk_ph_p[7:0] ), +.slow_clk_ph_n (slow_clk_ph_n[7:0] ), +.phy_clk_phs (phy_clk_phs_gated[7:0] ), +.gray_a_buf (phx_master_0_buf[2:0] ), +.gray_b_buf (phx_master_0_buf[2:0] ), +.gray_a_inv (phx_master_0_inv[2:0] ), +.gray_b_inv (phx_master_0_inv[2:0] ), +.int_clk_out (phx_clk_master_0 ), +.nfrzdrv (nfrzdrv ), +.test_enable_n (test_enable_n ), +.dft_mux_sel (dft_mux_sel ) +); + +io_interp_mux_match xinterp_mux_2 ( +.slow_clk_ph_p (slow_clk_ph_p[7:0] ), +.slow_clk_ph_n (slow_clk_ph_n[7:0] ), +.phy_clk_phs (phy_clk_phs_gated[7:0] ), +.gray_a_buf (phx_master_1_buf[2:0] ), +.gray_b_buf (phx_master_1_buf[2:0] ), +.gray_a_inv (phx_master_1_inv[2:0] ), +.gray_b_inv (phx_master_1_inv[2:0] ), +.int_clk_out (phx_clk_master_1 ), +.nfrzdrv (nfrzdrv ), +.test_enable_n (test_enable_n ), +.dft_mux_sel (dft_mux_sel ) +); + +//----------------------------------------------------------------------------------------------------------------------- +// phase alignment io_interpolator : +//----------------------------------------------------------------------------------------------------------------------- + +io_interpolator master_interpolator_0 ( +.reset_n ( pa_reset_n ), +.pdn ( pdn ), +.nfrzdrv ( nfrzdrv ), //local control signal +.phy_clk_phs ( phy_clk_phs_gated[7:0] ), // 8 phase 1.6GHz local clock +.rb_filter_code ( rbpa_filter_code[1:0] ), // 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz +.rb_couple_enable ( rbpa_couple_enable ), // cross couple enable +.mux_sel_a ( mux_sel_a_master_0[2:0] ), // The gray code output to control the first of the 8 to 1 phase multiplexer(3 MSB bits), and the interpolator (4 LSB bits) +.mux_sel_b ( mux_sel_b_master_0[2:0] ), // The gray code output to control the second of the 8 to 1 phase multiplexer(3 MSB bits), and the interpolator (4 LSB bits) +.interp_sel_a ( interp_sel_a_master_0[3:0] ), // The gray code output to control the interpolator (4 LSB bits) +.interp_sel_b ( interp_sel_b_master_0[3:0] ), // The gray code output to control the interpolator (4 LSB bits) +.dirty_clk ( dirty_clk_master_0[1:0] ), // The clock outputs with a duty cycle that is not 50%, The Interpolator will modify this clock to 50% duty cycle +.enable ( nfrzdrv ), // Active high enable 0 = Force interpolator_clk[1:0] to 2'b10 +.test_enable ( test_enable ), // Active high enable 1: avoid tristate on output of interp_mux during testing +.int_clk ( int_clk_master_0 ), // Clocks from the output of the 3 (8 to 1 phase select multiplexers) clk_p[0] arrives first, clk_p[2] arrives last +.clk_out ( ), // not used +.interpolator_clk ( {dummy[0],periphery_clk_x[0]} ) // Periphery Clock output sent to the phy_clk tree +); + +io_interpolator master_interpolator_1 ( +.reset_n ( pa_reset_n ), +.pdn ( pdn ), +.nfrzdrv ( nfrzdrv ), //local control signal +.phy_clk_phs ( phy_clk_phs_gated[7:0] ), // 8 phase 1.6GHz local clock +.rb_filter_code ( rbpa_filter_code[1:0] ), // 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz +.rb_couple_enable ( rbpa_couple_enable ), // cross couple enable +.mux_sel_a ( mux_sel_a_master_1[2:0] ), // The gray code output to control the first of the 8 to 1 phase multiplexer(3 MSB bits), and the interpolator (4 LSB bits) +.mux_sel_b ( mux_sel_b_master_1[2:0] ), // The gray code output to control the second of the 8 to 1 phase multiplexer(3 MSB bits), and the interpolator (4 LSB bits) +.interp_sel_a ( interp_sel_a_master_1[3:0] ), // The gray code output to control the interpolator (4 LSB bits) +.interp_sel_b ( interp_sel_b_master_1[3:0] ), // The gray code output to control the interpolator (4 LSB bits) +.dirty_clk ( dirty_clk_master_1[1:0] ), // The clock outputs with a duty cycle that is not 50%, The Interpolator will modify this clock to 50% duty cycle +.enable ( nfrzdrv ), // Active high enable 0 = Force interpolator_clk[1:0] to 2'b10 +.test_enable ( test_enable ), // Active high enable 1: avoid tristate on output of interp_mux during testing +.int_clk ( int_clk_master_1 ), // Clocks from the output of the 3 (8 to 1 phase select multiplexers) clk_p[0] arrives first, clk_p[2] arrives last +.clk_out ( ), // not used +.interpolator_clk ( {dummy[1],periphery_clk_x[1]} ) // Periphery Clock output sent to the phy_clk tree +); + +io_interpolator slave_interpolator_0 ( +.reset_n ( pa_reset_n ), +.pdn ( pdn ), +.nfrzdrv ( nfrzdrv ), //local control signal +.phy_clk_phs ( phy_clk_phs_gated[7:0] ), // 8 phase 1.6GHz local clock +.rb_filter_code ( rbpa_filter_code[1:0] ), // 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz +.rb_couple_enable ( rbpa_couple_enable ), // cross couple enable +.mux_sel_a ( mux_sel_a_slave_0[2:0] ), // The gray code output to control the first of the 8 to 1 phase multiplexer(3 MSB bits), and the interpolator (4 LSB bits) +.mux_sel_b ( mux_sel_b_slave_0[2:0] ), // The gray code output to control the second of the 8 to 1 phase multiplexer(3 MSB bits), and the interpolator (4 LSB bits) +.interp_sel_a ( interp_sel_a_slave_0[3:0] ), // The gray code output to control the interpolator (4 LSB bits) +.interp_sel_b ( interp_sel_b_slave_0[3:0] ), // The gray code output to control the interpolator (4 LSB bits) +.dirty_clk ( dirty_clk_slave_0[1:0] ), // The clock outputs with a duty cycle that is not 50%, The Interpolator will modify this clock to 50% duty cycle +.enable ( nfrzdrv ), // Active high enable 0 = Force interpolator_clk[1:0] to 2'b10 +.test_enable ( test_enable ), // Active high enable 1: avoid tristate on output of interp_mux during testing +.int_clk ( int_clk_slave_0 ), // Clocks from the output of the 3 (8 to 1 phase select multiplexers) clk_p[0] arrives first, clk_p[2] arrives last +.clk_out ( {dummy[4],clk_hps[0]} ), // sent to the hps +.interpolator_clk ( {dummy[2],core_clk_x[0]} ) // Clock output sent to the core +); + +io_interpolator slave_interpolator_1 ( +.reset_n ( pa_reset_n ), +.pdn ( pdn ), +.nfrzdrv ( nfrzdrv ), //local control signal +.phy_clk_phs ( phy_clk_phs_gated[7:0] ), // 8 phase 1.6GHz local clock +.rb_filter_code ( rbpa_filter_code[1:0] ), // 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz +.rb_couple_enable ( rbpa_couple_enable ), // cross couple enable +.mux_sel_a ( mux_sel_a_slave_1[2:0] ), // The gray code output to control the first of the 8 to 1 phase multiplexer(3 MSB bits), and the interpolator (4 LSB bits) +.mux_sel_b ( mux_sel_b_slave_1[2:0] ), // The gray code output to control the second of the 8 to 1 phase multiplexer(3 MSB bits), and the interpolator (4 LSB bits) +.interp_sel_b ( interp_sel_b_slave_1[3:0] ), // The gray code output to control the interpolator (4 LSB bits) +.interp_sel_a ( interp_sel_a_slave_1[3:0] ), // The gray code output to control the interpolator (4 LSB bits) +.dirty_clk ( dirty_clk_slave_1[1:0] ), // The clock outputs with a duty cycle that is not 50%, The Interpolator will modify this clock to 50% duty cycle +.enable ( nfrzdrv ), // Active high enable 0 = Force interpolator_clk[1:0] to 2'b10 +.test_enable ( test_enable ), // Active high enable 1: avoid tristate on output of interp_mux during testing +.int_clk ( int_clk_slave_1 ), // Clocks from the output of the 3 (8 to 1 phase select multiplexers) clk_p[0] arrives first, clk_p[2] arrives last +.clk_out ( {dummy[5],clk_hps[1]} ), // sent to the hps +.interpolator_clk ( {dummy[3],core_clk_x[1]} ) // Clock output sent to the core +); + +endmodule // io_pa_custom diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_pa_phs_buf.v b/maib_rtl/io_common_custom/rtl/block_function/io_pa_phs_buf.v new file mode 100644 index 0000000..b365511 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_pa_phs_buf.v @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved + +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +// io_pa_phs_buf : buffer for phy_clk_phs +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +module io_pa_phs_buf ( +input reset_n, // Active low reset +input nfrzdrv, // Active low reset +input [7:0] phy_clk_phs, // 8 phase 1.6GHz local clock +input test_enable, // Active high test enable 1: avoid tristate on output of interp_mux during testing +input [2:0] phx_sel_master_0, // The gray code to control the first of the 8 to 1 phase multiplexer +input [2:0] phx_sel_master_1, // The gray code to control the first of the 8 to 1 phase multiplexer +input [1:0] periphery_clk_x, // periphery_clk from io_interpolator +input [1:0] core_clk_x, // core_clk from io_interpolator +output [1:0] periphery_clk_out, // Clock feedback to the periphery +output [1:0] core_clk_out, // Clock feedback to the core +output [2:0] phx_master_0_buf, // buffered gray code for interp_mux +output [2:0] phx_master_1_buf, // buffered gray code for interp_mux +output [2:0] phx_master_0_inv, // Inverted gray code for interp_mux +output [2:0] phx_master_1_inv, // Inverted gray code for interp_mux +output [7:0] slow_clk_ph_p, // buffered 8 phase 1.6GHz local clock +output [7:0] slow_clk_ph_n, // buffered 8 phase 1.6GHz local clock +output test_enable_n, // active low test enable +output dft_mux_sel // mux control during test +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter INV_DELAY = 15; // 15ps + +wire test_rst_p; // reset control for io_interp_mux +wire test_rst_n; // reset control for io_interp_mux +wire test_enable_buf; // active high test enable + +assign test_enable_n = ~test_enable; +assign test_enable_buf = ~test_enable_n; +assign dft_mux_sel = ~(~phx_master_0_inv[0] & test_enable_buf); +assign test_rst_n = test_enable_n & reset_n; +assign test_rst_p = ~test_rst_n; +assign #(3 * INV_DELAY) slow_clk_ph_p[7:0] = phy_clk_phs[7:0] | {8{test_rst_p}}; +assign #(3 * INV_DELAY) slow_clk_ph_n[7:0] = phy_clk_phs[7:0] & {8{test_rst_n}}; +assign phx_master_0_buf = phx_sel_master_0[2:0]; +assign phx_master_1_buf = phx_sel_master_1[2:0]; +assign phx_master_0_inv = ~phx_sel_master_0[2:0]; +assign phx_master_1_inv = ~phx_sel_master_1[2:0]; +assign core_clk_out[1:0] = {2{nfrzdrv}} & core_clk_x[1:0]; +assign periphery_clk_out[1:0] = {2{nfrzdrv}} & periphery_clk_x[1:0]; + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_pa_phs_gated.v b/maib_rtl/io_common_custom/rtl/block_function/io_pa_phs_gated.v new file mode 100644 index 0000000..ec66f26 --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_pa_phs_gated.v @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #1 $ +// Date: $DateTime: 2014/11/15 16:17:29 $ +//------------------------------------------------------------------------ +// Description: gated 8 clock phases for powerdown and regulator power domain crossing +// +//------------------------------------------------------------------------ + +module io_pa_phs_gated ( +input nfrzdrv, // power down active low +input [7:0] phy_clk_phs, // 8 phase 1.6GHz local clock +output [7:0] phy_clk_phs_gated // gated 8 phase 1.6GHz local clock +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter INV_DELAY = 15; // 15ps + +assign #(2 * INV_DELAY) phy_clk_phs_gated[3:0] = phy_clk_phs[3:0] & {4{nfrzdrv}}; +assign #(2 * INV_DELAY) phy_clk_phs_gated[7:4] = phy_clk_phs[7:4] | {4{~nfrzdrv}}; + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_phdet_ff_ln.v b/maib_rtl/io_common_custom/rtl/block_function/io_phdet_ff_ln.v new file mode 100644 index 0000000..e0b7aba --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_phdet_ff_ln.v @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module io_phdet_ff_ln (dp, dn, clk_p, rst_n, q); +input dp, dn, clk_p, rst_n; +output q; +reg q; + +always @(posedge clk_p or negedge rst_n) + if (~rst_n) q <= 1'b0; + else q <= dp; + +endmodule // io_phdet_ff_ln + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_phs_check.v b/maib_rtl/io_common_custom/rtl/block_function/io_phs_check.v new file mode 100644 index 0000000..ed9f6bc --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_phs_check.v @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module io_phs_check ( +input rst_n, +input sample_clk, +input [7:0] ph_in, +output [7:0] ph_and_sample, +output [3:0] ph_sample +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +wire [7:0] ph_and; // and neighboring phases +wire [7:0] ph_or; // or neighboring phases + +parameter FF_DELAY = 100; + +assign ph_and[7:0] = ph_in[7:0] & {ph_in[0],ph_in[7:1]}; +assign ph_or[7:0] = {ph_in[3:0],ph_in[7:4]} | {ph_in[4:0],ph_in[7:5]}; + +io_phdet_ff_ln ph_sample_reg_0 ( +.dp ( ph_in[0] ), +.dn ( ph_in[4] ), +.clk_p ( sample_clk ), +.rst_n ( rst_n ), +.q ( ph_sample[0] ) +); + +io_phdet_ff_ln ph_sample_reg_1 ( +.dp ( ph_in[1] ), +.dn ( ph_in[5] ), +.clk_p ( sample_clk ), +.rst_n ( rst_n ), +.q ( ph_sample[1] ) +); + +io_phdet_ff_ln ph_sample_reg_2 ( +.dp ( ph_in[2] ), +.dn ( ph_in[6] ), +.clk_p ( sample_clk ), +.rst_n ( rst_n ), +.q ( ph_sample[2] ) +); + +io_phdet_ff_ln ph_sample_reg_3 ( +.dp ( ph_in[3] ), +.dn ( ph_in[7] ), +.clk_p ( sample_clk ), +.rst_n ( rst_n ), +.q ( ph_sample[3] ) +); + +io_phdet_ff_ln ph_and_sample_reg_0 ( +.dp ( ph_and[0] ), +.dn ( ph_or[0] ), +.clk_p ( sample_clk ), +.rst_n ( rst_n ), +.q ( ph_and_sample[0] ) +); + +io_phdet_ff_ln ph_and_sample_reg_1 ( +.dp ( ph_and[1] ), +.dn ( ph_or[1] ), +.clk_p ( sample_clk ), +.rst_n ( rst_n ), +.q ( ph_and_sample[1] ) +); + +io_phdet_ff_ln ph_and_sample_reg_2 ( +.dp ( ph_and[2] ), +.dn ( ph_or[2] ), +.clk_p ( sample_clk ), +.rst_n ( rst_n ), +.q ( ph_and_sample[2] ) +); + +io_phdet_ff_ln ph_and_sample_reg_3 ( +.dp ( ph_and[3] ), +.dn ( ph_or[3] ), +.clk_p ( sample_clk ), +.rst_n ( rst_n ), +.q ( ph_and_sample[3] ) +); + +io_phdet_ff_ln ph_and_sample_reg_4 ( +.dp ( ph_and[4] ), +.dn ( ph_or[4] ), +.clk_p ( sample_clk ), +.rst_n ( rst_n ), +.q ( ph_and_sample[4] ) +); + +io_phdet_ff_ln ph_and_sample_reg_5 ( +.dp ( ph_and[5] ), +.dn ( ph_or[5] ), +.clk_p ( sample_clk ), +.rst_n ( rst_n ), +.q ( ph_and_sample[5] ) +); + +io_phdet_ff_ln ph_and_sample_reg_6 ( +.dp ( ph_and[6] ), +.dn ( ph_or[6] ), +.clk_p ( sample_clk ), +.rst_n ( rst_n ), +.q ( ph_and_sample[6] ) +); + +io_phdet_ff_ln ph_and_sample_reg_7 ( +.dp ( ph_and[7] ), +.dn ( ph_or[7] ), +.clk_p ( sample_clk ), +.rst_n ( rst_n ), +.q ( ph_and_sample[7] ) +); + +endmodule diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_phs_gated.v b/maib_rtl/io_common_custom/rtl/block_function/io_phs_gated.v new file mode 100644 index 0000000..083ad5f --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_phs_gated.v @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #1 $ +// Date: $DateTime: 2014/09/20 12:06:43 $ +//------------------------------------------------------------------------ +// Description: gated 8 clock phases for powerdown and regulator power domain crossing +// +//------------------------------------------------------------------------ + +module io_phs_gated ( +input nfrzdrv, // power down active low +input [7:0] phy_clk_phs, // 8 phase 1.6GHz local clock +output [7:0] phy_clk_phs_gated // gated 8 phase 1.6GHz local clock +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter INV_DELAY = 15; // 15ps + +assign #(2 * INV_DELAY) phy_clk_phs_gated[3:0] = phy_clk_phs[3:0] & {4{nfrzdrv}}; +assign #(2 * INV_DELAY) phy_clk_phs_gated[7:4] = phy_clk_phs[7:4] | {4{~nfrzdrv}}; + +endmodule + + diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_phs_pair_couple_x48.v b/maib_rtl/io_common_custom/rtl/block_function/io_phs_pair_couple_x48.v new file mode 100644 index 0000000..5b1629c --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_phs_pair_couple_x48.v @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module io_phs_pair_couple_x48 ( +input c_in_p, +input c_in_n, +input phy_clk_phs_ctrl, +input snc, +input spc, +input [5:0] r_gray, +input [5:0] f_gray, +output c_out_p, +output c_out_n +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter STEP_DELAY = 40; + +reg c_in_del; + +wire c_in_p_gated; +wire c_in_n_gated; +wire [48:0] c_in_p_f; +wire [48:0] c_in_p_r; + +assign {c_in_n_gated,c_in_p_gated} = phy_clk_phs_ctrl? {c_in_n,c_in_p}: 2'b10; + +assign #54 c_in_p_f[0] = c_in_p_gated; +assign #57 c_in_p_f[1] = c_in_p_gated; +assign #60 c_in_p_f[2] = c_in_p_gated; +assign #63 c_in_p_f[3] = c_in_p_gated; +assign #66 c_in_p_f[4] = c_in_p_gated; +assign #69 c_in_p_f[5] = c_in_p_gated; +assign #72 c_in_p_f[6] = c_in_p_gated; +assign #75 c_in_p_f[7] = c_in_p_gated; +assign #78 c_in_p_f[8] = c_in_p_gated; +assign #81 c_in_p_f[9] = c_in_p_gated; +assign #84 c_in_p_f[10] = c_in_p_gated; +assign #87 c_in_p_f[11] = c_in_p_gated; +assign #90 c_in_p_f[12] = c_in_p_gated; +assign #93 c_in_p_f[13] = c_in_p_gated; +assign #96 c_in_p_f[14] = c_in_p_gated; +assign #99 c_in_p_f[15] = c_in_p_gated; +assign #102 c_in_p_f[16] = c_in_p_gated; +assign #105 c_in_p_f[17] = c_in_p_gated; +assign #108 c_in_p_f[18] = c_in_p_gated; +assign #111 c_in_p_f[19] = c_in_p_gated; +assign #114 c_in_p_f[20] = c_in_p_gated; +assign #117 c_in_p_f[21] = c_in_p_gated; +assign #120 c_in_p_f[22] = c_in_p_gated; +assign #123 c_in_p_f[23] = c_in_p_gated; +assign #126 c_in_p_f[24] = c_in_p_gated; +assign #129 c_in_p_f[25] = c_in_p_gated; +assign #132 c_in_p_f[26] = c_in_p_gated; +assign #135 c_in_p_f[27] = c_in_p_gated; +assign #138 c_in_p_f[28] = c_in_p_gated; +assign #141 c_in_p_f[29] = c_in_p_gated; +assign #144 c_in_p_f[30] = c_in_p_gated; +assign #147 c_in_p_f[31] = c_in_p_gated; +assign #150 c_in_p_f[32] = c_in_p_gated; +assign #153 c_in_p_f[33] = c_in_p_gated; +assign #156 c_in_p_f[34] = c_in_p_gated; +assign #159 c_in_p_f[35] = c_in_p_gated; +assign #162 c_in_p_f[36] = c_in_p_gated; +assign #165 c_in_p_f[37] = c_in_p_gated; +assign #168 c_in_p_f[38] = c_in_p_gated; +assign #171 c_in_p_f[39] = c_in_p_gated; +assign #174 c_in_p_f[40] = c_in_p_gated; +assign #177 c_in_p_f[41] = c_in_p_gated; +assign #180 c_in_p_f[42] = c_in_p_gated; +assign #183 c_in_p_f[43] = c_in_p_gated; +assign #186 c_in_p_f[44] = c_in_p_gated; +assign #189 c_in_p_f[45] = c_in_p_gated; +assign #192 c_in_p_f[46] = c_in_p_gated; +assign #195 c_in_p_f[47] = c_in_p_gated; +assign #198 c_in_p_f[48] = c_in_p_gated; + +assign #54 c_in_p_r[0] = c_in_p_gated; +assign #57 c_in_p_r[1] = c_in_p_gated; +assign #60 c_in_p_r[2] = c_in_p_gated; +assign #63 c_in_p_r[3] = c_in_p_gated; +assign #66 c_in_p_r[4] = c_in_p_gated; +assign #69 c_in_p_r[5] = c_in_p_gated; +assign #72 c_in_p_r[6] = c_in_p_gated; +assign #75 c_in_p_r[7] = c_in_p_gated; +assign #78 c_in_p_r[8] = c_in_p_gated; +assign #81 c_in_p_r[9] = c_in_p_gated; +assign #84 c_in_p_r[10] = c_in_p_gated; +assign #87 c_in_p_r[11] = c_in_p_gated; +assign #90 c_in_p_r[12] = c_in_p_gated; +assign #93 c_in_p_r[13] = c_in_p_gated; +assign #96 c_in_p_r[14] = c_in_p_gated; +assign #99 c_in_p_r[15] = c_in_p_gated; +assign #102 c_in_p_r[16] = c_in_p_gated; +assign #105 c_in_p_r[17] = c_in_p_gated; +assign #108 c_in_p_r[18] = c_in_p_gated; +assign #111 c_in_p_r[19] = c_in_p_gated; +assign #114 c_in_p_r[20] = c_in_p_gated; +assign #117 c_in_p_r[21] = c_in_p_gated; +assign #120 c_in_p_r[22] = c_in_p_gated; +assign #123 c_in_p_r[23] = c_in_p_gated; +assign #126 c_in_p_r[24] = c_in_p_gated; +assign #129 c_in_p_r[25] = c_in_p_gated; +assign #132 c_in_p_r[26] = c_in_p_gated; +assign #135 c_in_p_r[27] = c_in_p_gated; +assign #138 c_in_p_r[28] = c_in_p_gated; +assign #141 c_in_p_r[29] = c_in_p_gated; +assign #144 c_in_p_r[30] = c_in_p_gated; +assign #147 c_in_p_r[31] = c_in_p_gated; +assign #150 c_in_p_r[32] = c_in_p_gated; +assign #153 c_in_p_r[33] = c_in_p_gated; +assign #156 c_in_p_r[34] = c_in_p_gated; +assign #159 c_in_p_r[35] = c_in_p_gated; +assign #162 c_in_p_r[36] = c_in_p_gated; +assign #165 c_in_p_r[37] = c_in_p_gated; +assign #168 c_in_p_r[38] = c_in_p_gated; +assign #171 c_in_p_r[39] = c_in_p_gated; +assign #174 c_in_p_r[40] = c_in_p_gated; +assign #177 c_in_p_r[41] = c_in_p_gated; +assign #180 c_in_p_r[42] = c_in_p_gated; +assign #183 c_in_p_r[43] = c_in_p_gated; +assign #186 c_in_p_r[44] = c_in_p_gated; +assign #189 c_in_p_r[45] = c_in_p_gated; +assign #192 c_in_p_r[46] = c_in_p_gated; +assign #195 c_in_p_r[47] = c_in_p_gated; +assign #198 c_in_p_r[48] = c_in_p_gated; + +always @(*) + if (c_in_p == 1'b0) + begin + case (f_gray[5:0]) + 6'h00 : c_in_del = c_in_p_f[0]; + 6'h01 : c_in_del = c_in_p_f[1]; + 6'h03 : c_in_del = c_in_p_f[2]; + 6'h02 : c_in_del = c_in_p_f[3]; + 6'h06 : c_in_del = c_in_p_f[4]; + 6'h07 : c_in_del = c_in_p_f[5]; + 6'h05 : c_in_del = c_in_p_f[6]; + 6'h04 : c_in_del = c_in_p_f[7]; + 6'h0C : c_in_del = c_in_p_f[8]; + 6'h0D : c_in_del = c_in_p_f[9]; + 6'h0F : c_in_del = c_in_p_f[10]; + 6'h0E : c_in_del = c_in_p_f[11]; + 6'h0A : c_in_del = c_in_p_f[12]; + 6'h0B : c_in_del = c_in_p_f[13]; + 6'h09 : c_in_del = c_in_p_f[14]; + 6'h08 : c_in_del = c_in_p_f[15]; + 6'h18 : c_in_del = c_in_p_f[16]; + 6'h19 : c_in_del = c_in_p_f[17]; + 6'h1B : c_in_del = c_in_p_f[18]; + 6'h1A : c_in_del = c_in_p_f[19]; + 6'h1E : c_in_del = c_in_p_f[20]; + 6'h1F : c_in_del = c_in_p_f[21]; + 6'h1D : c_in_del = c_in_p_f[22]; + 6'h1C : c_in_del = c_in_p_f[23]; + 6'h14 : c_in_del = c_in_p_f[24]; + 6'h15 : c_in_del = c_in_p_f[25]; + 6'h17 : c_in_del = c_in_p_f[26]; + 6'h16 : c_in_del = c_in_p_f[27]; + 6'h12 : c_in_del = c_in_p_f[28]; + 6'h13 : c_in_del = c_in_p_f[29]; + 6'h11 : c_in_del = c_in_p_f[30]; + 6'h10 : c_in_del = c_in_p_f[31]; + 6'h30 : c_in_del = c_in_p_f[32]; + 6'h31 : c_in_del = c_in_p_f[33]; + 6'h33 : c_in_del = c_in_p_f[34]; + 6'h32 : c_in_del = c_in_p_f[35]; + 6'h36 : c_in_del = c_in_p_f[36]; + 6'h37 : c_in_del = c_in_p_f[37]; + 6'h35 : c_in_del = c_in_p_f[38]; + 6'h34 : c_in_del = c_in_p_f[39]; + 6'h3C : c_in_del = c_in_p_f[40]; + 6'h3D : c_in_del = c_in_p_f[41]; + 6'h3F : c_in_del = c_in_p_f[42]; + 6'h3E : c_in_del = c_in_p_f[43]; + 6'h3A : c_in_del = c_in_p_f[44]; + 6'h3B : c_in_del = c_in_p_f[45]; + 6'h39 : c_in_del = c_in_p_f[46]; + 6'h38 : c_in_del = c_in_p_f[47]; + default : c_in_del = c_in_p_f[48]; + endcase + end + else if (c_in_p == 1'b1) + begin + case (r_gray[5:0]) + 6'h00 : c_in_del = c_in_p_r[0]; + 6'h01 : c_in_del = c_in_p_r[1]; + 6'h03 : c_in_del = c_in_p_r[2]; + 6'h02 : c_in_del = c_in_p_r[3]; + 6'h06 : c_in_del = c_in_p_r[4]; + 6'h07 : c_in_del = c_in_p_r[5]; + 6'h05 : c_in_del = c_in_p_r[6]; + 6'h04 : c_in_del = c_in_p_r[7]; + 6'h0C : c_in_del = c_in_p_r[8]; + 6'h0D : c_in_del = c_in_p_r[9]; + 6'h0F : c_in_del = c_in_p_r[10]; + 6'h0E : c_in_del = c_in_p_r[11]; + 6'h0A : c_in_del = c_in_p_r[12]; + 6'h0B : c_in_del = c_in_p_r[13]; + 6'h09 : c_in_del = c_in_p_r[14]; + 6'h08 : c_in_del = c_in_p_r[15]; + 6'h18 : c_in_del = c_in_p_r[16]; + 6'h19 : c_in_del = c_in_p_r[17]; + 6'h1B : c_in_del = c_in_p_r[18]; + 6'h1A : c_in_del = c_in_p_r[19]; + 6'h1E : c_in_del = c_in_p_r[20]; + 6'h1F : c_in_del = c_in_p_r[21]; + 6'h1D : c_in_del = c_in_p_r[22]; + 6'h1C : c_in_del = c_in_p_r[23]; + 6'h14 : c_in_del = c_in_p_r[24]; + 6'h15 : c_in_del = c_in_p_r[25]; + 6'h17 : c_in_del = c_in_p_r[26]; + 6'h16 : c_in_del = c_in_p_r[27]; + 6'h12 : c_in_del = c_in_p_r[28]; + 6'h13 : c_in_del = c_in_p_r[29]; + 6'h11 : c_in_del = c_in_p_r[30]; + 6'h10 : c_in_del = c_in_p_r[31]; + 6'h30 : c_in_del = c_in_p_r[32]; + 6'h31 : c_in_del = c_in_p_r[33]; + 6'h33 : c_in_del = c_in_p_r[34]; + 6'h32 : c_in_del = c_in_p_r[35]; + 6'h36 : c_in_del = c_in_p_r[36]; + 6'h37 : c_in_del = c_in_p_r[37]; + 6'h35 : c_in_del = c_in_p_r[38]; + 6'h34 : c_in_del = c_in_p_r[39]; + 6'h3C : c_in_del = c_in_p_r[40]; + 6'h3D : c_in_del = c_in_p_r[41]; + 6'h3F : c_in_del = c_in_p_r[42]; + 6'h3E : c_in_del = c_in_p_r[43]; + 6'h3A : c_in_del = c_in_p_r[44]; + 6'h3B : c_in_del = c_in_p_r[45]; + 6'h39 : c_in_del = c_in_p_r[46]; + 6'h38 : c_in_del = c_in_p_r[47]; + default : c_in_del = c_in_p_r[48]; + endcase + end + +assign c_out_p = c_in_del; +assign c_out_n = ~c_in_del; + +endmodule + +//====================================================================== +// +// r_delay(f_gray=5'b0) f_delay(r_gray=5'b0) +// x48_delay_wc x48_delay_tt x48_delay_bc x48_delay_wc x48_delay_tt x48_delay_bc +// 1 2.047E-10 1.544E-10 1.108E-10 1 2.042E-10 1.544E-10 1.109E-10 +// 2 2.063E-10 1.561E-10 1.126E-10 2 2.053E-10 1.556E-10 1.123E-10 +// 3 2.074E-10 1.573E-10 1.141E-10 3 2.071E-10 1.575E-10 1.143E-10 +// 4 2.089E-10 1.591E-10 1.162E-10 4 2.083E-10 1.589E-10 1.160E-10 +// 5 2.100E-10 1.604E-10 1.177E-10 5 2.101E-10 1.608E-10 1.181E-10 +// 6 2.115E-10 1.621E-10 1.197E-10 6 2.113E-10 1.621E-10 1.197E-10 +// 7 2.127E-10 1.634E-10 1.213E-10 7 2.128E-10 1.639E-10 1.216E-10 +// 8 2.143E-10 1.650E-10 1.232E-10 8 2.143E-10 1.655E-10 1.236E-10 +// 9 2.158E-10 1.667E-10 1.254E-10 9 2.161E-10 1.674E-10 1.259E-10 +// 10 2.174E-10 1.686E-10 1.277E-10 10 2.176E-10 1.691E-10 1.280E-10 +// 11 2.189E-10 1.703E-10 1.298E-10 11 2.194E-10 1.711E-10 1.304E-10 +// 12 2.208E-10 1.723E-10 1.323E-10 12 2.209E-10 1.727E-10 1.325E-10 +// 13 2.221E-10 1.737E-10 1.341E-10 13 2.227E-10 1.747E-10 1.348E-10 +// 14 2.237E-10 1.756E-10 1.365E-10 14 2.244E-10 1.766E-10 1.373E-10 +// 15 2.256E-10 1.777E-10 1.393E-10 15 2.263E-10 1.787E-10 1.401E-10 +// 16 2.274E-10 1.798E-10 1.422E-10 16 2.281E-10 1.808E-10 1.429E-10 +// 17 2.292E-10 1.818E-10 1.450E-10 17 2.300E-10 1.829E-10 1.458E-10 +// 18 2.312E-10 1.841E-10 1.480E-10 18 2.317E-10 1.849E-10 1.485E-10 +// 19 2.326E-10 1.858E-10 1.503E-10 19 2.337E-10 1.871E-10 1.513E-10 +// 20 2.346E-10 1.879E-10 1.534E-10 20 2.356E-10 1.893E-10 1.544E-10 +// 21 2.366E-10 1.904E-10 1.570E-10 21 2.376E-10 1.917E-10 1.581E-10 +// 22 2.387E-10 1.929E-10 1.606E-10 22 2.397E-10 1.942E-10 1.617E-10 +// 23 2.407E-10 1.954E-10 1.642E-10 23 2.418E-10 1.967E-10 1.653E-10 +// 24 2.429E-10 1.979E-10 1.679E-10 24 2.438E-10 1.991E-10 1.688E-10 +// 25 2.445E-10 1.999E-10 1.708E-10 25 2.459E-10 2.016E-10 1.722E-10 +// 26 2.466E-10 2.024E-10 1.750E-10 26 2.480E-10 2.040E-10 1.763E-10 +// 27 2.490E-10 2.053E-10 1.798E-10 27 2.504E-10 2.069E-10 1.812E-10 +// 28 2.514E-10 2.082E-10 1.846E-10 28 2.526E-10 2.097E-10 1.860E-10 +// 29 2.536E-10 2.110E-10 1.895E-10 29 2.550E-10 2.126E-10 1.909E-10 +// 30 2.560E-10 2.139E-10 1.944E-10 30 2.573E-10 2.154E-10 1.958E-10 +// 31 2.579E-10 2.163E-10 1.986E-10 31 2.597E-10 2.183E-10 2.002E-10 +// 32 2.603E-10 2.193E-10 2.047E-10 32 2.621E-10 2.212E-10 2.064E-10 +// 33 2.628E-10 2.228E-10 2.119E-10 33 2.646E-10 2.247E-10 2.134E-10 +// 34 2.655E-10 2.261E-10 2.188E-10 34 2.674E-10 2.281E-10 2.204E-10 +// 35 2.682E-10 2.297E-10 2.259E-10 35 2.700E-10 2.316E-10 2.276E-10 +// 36 2.708E-10 2.331E-10 2.329E-10 36 2.725E-10 2.350E-10 2.345E-10 +// 37 2.733E-10 2.362E-10 2.393E-10 37 2.752E-10 2.383E-10 2.410E-10 +// 38 2.758E-10 2.399E-10 2.505E-10 38 2.780E-10 2.419E-10 2.523E-10 +// 39 2.789E-10 2.441E-10 2.631E-10 39 2.808E-10 2.463E-10 2.647E-10 +// 40 2.818E-10 2.484E-10 2.754E-10 40 2.840E-10 2.505E-10 2.772E-10 +// 41 2.849E-10 2.527E-10 2.878E-10 41 2.870E-10 2.549E-10 2.896E-10 +// 42 2.879E-10 2.570E-10 3.002E-10 42 2.902E-10 2.591E-10 3.021E-10 +// 43 2.908E-10 2.609E-10 3.123E-10 43 2.932E-10 2.632E-10 3.137E-10 +// 44 2.937E-10 2.657E-10 3.496E-10 44 2.961E-10 2.681E-10 3.511E-10 +// 45 2.971E-10 2.712E-10 3.917E-10 45 2.995E-10 2.735E-10 3.932E-10 +// 46 3.006E-10 2.769E-10 4.335E-10 46 3.031E-10 2.791E-10 4.354E-10 +// 47 3.040E-10 2.825E-10 failed 47 3.064E-10 2.848E-10 failed +// 48 3.106E-10 2.931E-10 failed 48 3.133E-10 2.957E-10 failed +// +//====================================================================== +// diff --git a/maib_rtl/io_common_custom/rtl/block_function/io_split_align.v b/maib_rtl/io_common_custom/rtl/block_function/io_split_align.v new file mode 100644 index 0000000..4efaacc --- /dev/null +++ b/maib_rtl/io_common_custom/rtl/block_function/io_split_align.v @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//------------------------------------------------------------------------ +// +// Revision: $Revision: #1 $ +// Date: $DateTime: 2014/09/20 12:06:43 $ +//------------------------------------------------------------------------ +// Description: gated 8 clock phases for powerdown and regulator power domain crossing +// +//------------------------------------------------------------------------ + +module io_split_align ( +input din, // input +output dout_p, // splitted output positive +output dout_n // splitted output negative +); + +`ifdef TIMESCALE_EN + timeunit 1ps; + timeprecision 1ps; +`endif + +parameter INV_DELAY = 15; // 15ps + +assign #(2 * INV_DELAY) dout_p = din; +assign #(2 * INV_DELAY) dout_n = ~din; + +endmodule + + diff --git a/maib_rtl/s10aib/rtl/an.v b/maib_rtl/s10aib/rtl/an.v new file mode 100644 index 0000000..cee0143 --- /dev/null +++ b/maib_rtl/s10aib/rtl/an.v @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// Verilog for library verilog/final_custom created by Liberate 13.1.3 on Thu Nov 20 18:25:10 MST 2014 for SDF version 3.0 +// +`celldefine + +module an_io_double_edge_ff (clk_in, reset_n, test_enable_n, data_in, data_out `ifndef INTCNOPWR ,vcc ,vss `endif); +input [1:0] clk_in; // clk_in[0] is p, clk_in[1] is n +input reset_n; // Reset active low +input test_enable_n; // Reset active low +input [1:0] data_in; +output [1:0] data_out; // Complimentary output +reg notifier; + +`ifndef INTCNOPWR +input vcc, vss; +`endif +wire [1:0] clk_buf_n; + +assign clk_buf_n[1] = ~(test_enable_n & clk_in[1]); +assign clk_buf_n[0] = ~(test_enable_n & clk_in[0]); +wire delayed_clk_in_1; +wire delayed_clk_in_0; +wire delayed_data_in_1; +wire delayed_data_in_0; + +reg [1:0] lat; +always @(reset_n or clk_buf_n[0] or data_in[0]) + if (~reset_n) lat[0] <= 1'b0; + else if (clk_buf_n[0]) lat[0] <= data_in[0]; + +always @(reset_n or clk_buf_n[1] or data_in[1]) + if (~reset_n) lat[1] <= 1'b0; + else if (clk_buf_n[1]) lat[1] <= data_in[1]; + +assign data_out[0] = (clk_in[0] & lat[0]) | (clk_in[1] & lat[1]) | ( lat[0] & lat[1]); +assign data_out[1] = (clk_in[0] & ~lat[0]) | (clk_in[1] & ~lat[1]) | (~lat[0] & ~lat[1]); + specify + if (~test_enable_n) + (data_in[0] => data_out[1]) = 0; + if (~test_enable_n) + (data_in[1] => data_out[1]) = 0; + if (~test_enable_n) + (clk_in[0] => data_out[1]) = 0; + if (test_enable_n) + (posedge clk_in[0] => (data_out[1]:data_in[0])) = (0,0); + if (test_enable_n) + (posedge clk_in[1] => (data_out[1]:data_in[1])) = (0,0); + if (~test_enable_n) + (posedge clk_in[1] => (data_out[1]:data_in[1])) = (0,0); + if (~test_enable_n) + (data_in[0] => data_out[0]) = 0; + if (~test_enable_n) + (data_in[1] => data_out[0]) = 0; + if (~test_enable_n) + (clk_in[0] => data_out[0]) = 0; + if (test_enable_n) + (posedge clk_in[0] => (data_out[0]:data_in[0])) = (0,0); + if (test_enable_n) + (posedge clk_in[1] => (data_out[0]:data_in[1])) = (0,0); + if (~test_enable_n) + (posedge clk_in[1] => (data_out[0]:data_in[1])) = (0,0); + $setuphold (posedge clk_in[1], posedge data_in[1], 0, 0, notifier,,, delayed_clk_in_1, delayed_data_in_1); + $setuphold (posedge clk_in[1], negedge data_in[1], 0, 0, notifier,,, delayed_clk_in_1, delayed_data_in_1); + $setuphold (posedge clk_in[0], posedge data_in[0], 0, 0, notifier,,, delayed_clk_in_0, delayed_data_in_0); + $setuphold (posedge clk_in[0], negedge data_in[0], 0, 0, notifier,,, delayed_clk_in_0, delayed_data_in_0); + $width (posedge clk_in[1], 0, 0, notifier); + $width (posedge clk_in[0], 0, 0, notifier); + endspecify +endmodule +`endcelldefine + +// type: +`celldefine +module an_io_phdet_ff_ln (q, dn, dp, rst_n, clk_p `ifndef INTCNOPWR ,vcc ,vss `endif); + output q; + input dn, dp, rst_n, clk_p; + reg notifier; + wire delayed_dn, delayed_dp, delayed_clk_p; +`ifndef INTCNOPWR +input vcc, vss; +`endif + + // Function + wire int_fwire_Iq, int_fwire_r, xcr_0; + + not (int_fwire_r, rst_n); + altos_dff_r_err (xcr_0, delayed_clk_p, delayed_dp, int_fwire_r); + altos_dff_r (int_fwire_Iq, notifier, delayed_clk_p, delayed_dp, int_fwire_r, xcr_0); + buf (q, int_fwire_Iq); + + // Timing + specify + (posedge clk_p => (q+:dp)) = 0; + $setuphold (posedge clk_p, posedge dn, 0, 0, notifier,,, delayed_clk_p, delayed_dn); + $setuphold (posedge clk_p, negedge dn, 0, 0, notifier,,, delayed_clk_p, delayed_dn); + $setuphold (posedge clk_p, posedge dp, 0, 0, notifier,,, delayed_clk_p, delayed_dp); + $setuphold (posedge clk_p, negedge dp, 0, 0, notifier,,, delayed_clk_p, delayed_dp); + $width (posedge clk_p, 0, 0, notifier); + endspecify +endmodule +`endcelldefine + +// type: +primitive altos_dff_r_err (q, clk, d, r); + output q; + reg q; + input clk, d, r; + + table + ? 0 (0x) : ? : -; + ? 0 (x0) : ? : -; + (0x) ? 0 : ? : 0; + (0x) 0 x : ? : 0; + (1x) ? 0 : ? : 1; + (1x) 0 x : ? : 1; + endtable +endprimitive + +primitive altos_dff_r (q, v, clk, d, r, xcr); + output q; + reg q; + input v, clk, d, r, xcr; + + table + * ? ? ? ? : ? : x; + ? ? ? 1 ? : ? : 0; + ? b ? (1?) ? : 0 : -; + ? x 0 (1?) ? : 0 : -; + ? ? ? (10) ? : ? : -; + ? ? ? (x0) ? : ? : -; + ? ? ? (0x) ? : 0 : -; + ? (x1) 0 ? 0 : ? : 0; + ? (x1) 1 0 0 : ? : 1; + ? (x1) 0 ? 1 : 0 : 0; + ? (x1) 1 0 1 : 1 : 1; + ? (x1) ? ? x : ? : -; + ? (bx) 0 ? ? : 0 : -; + ? (bx) 1 0 ? : 1 : -; + ? (x0) 0 ? ? : ? : -; + ? (x0) 1 0 ? : ? : -; + ? (x0) ? 0 x : ? : -; + ? (01) 0 ? ? : ? : 0; + ? (01) 1 0 ? : ? : 1; + ? (10) ? ? ? : ? : -; + ? b * ? ? : ? : -; + ? ? ? ? * : ? : -; + endtable +endprimitive + +primitive altos_dff_err (q, clk, d); + output q; + reg q; + input clk, d; + + table + (0x) ? : ? : 0; + (1x) ? : ? : 1; + endtable +endprimitive diff --git a/ndsimslv/ndaibadapt_wrap.v b/maib_rtl/s10aib/rtl/ndaibadapt_wrap.v similarity index 85% rename from ndsimslv/ndaibadapt_wrap.v rename to maib_rtl/s10aib/rtl/ndaibadapt_wrap.v index 50af4f0..0bec6fd 100644 --- a/ndsimslv/ndaibadapt_wrap.v +++ b/maib_rtl/s10aib/rtl/ndaibadapt_wrap.v @@ -122,7 +122,7 @@ module ndaibadapt_wrap ( input wire bond_tx_hrdrst_ds_in_fabric_tx_dcd_cal_req, input wire bond_tx_hrdrst_us_in_fabric_tx_dcd_cal_req, - // Config + // Config (These are required for reset, look properly and configure as is in previous project input wire [2:0] csr_config, input wire csr_clk_in, input wire [2:0] csr_in, @@ -226,7 +226,7 @@ module ndaibadapt_wrap ( input wire pld_pma_tx_qpi_pulldn, input wire pld_pma_tx_qpi_pullup, input wire pld_pma_rx_qpi_pullup, - + input wire pld_pma_aib_tx_clk, //Pull out for AIB spec. purpose. JZ 11/9/2018 // PLD DCM input wire pld_rx_clk1_dcm, input wire pld_tx_clk1_dcm, @@ -381,6 +381,8 @@ module ndaibadapt_wrap ( output wire pld_pcs_tx_clk_out2_hioint, output wire pld_pll_cal_done, output wire pld_pma_adapt_done, + output wire pld_pma_clkdiv_rx_user, //Pull out for AIB spec. purpose. JZ 11/9/2018 + output wire pld_pma_clkdiv_tx_user, //Pull out for AIB spec. purpose. JZ 11/9/2018 output wire pld_pma_fpll_clk0bad, output wire pld_pma_fpll_clk1bad, output wire pld_pma_fpll_clksel, @@ -409,6 +411,7 @@ module ndaibadapt_wrap ( output wire pld_rx_hssi_fifo_latency_pulse, output wire pld_rx_prbs_done, output wire pld_rx_prbs_err, + output wire pld_sr_clk_out, //Pull out for AIB spec. purpose. JZ 11/9/2018 output wire pld_ssr_load, output wire [19:0] pld_test_data, output wire pld_tx_fabric_fifo_empty, @@ -432,6 +435,8 @@ module ndaibadapt_wrap ( output wire pld_fabric_asn_dll_lock_en, output wire [2:0] pld_tx_ssr_reserved_out, output wire [1:0] pld_rx_ssr_reserved_out, + output wire [117:0] ssrin_parallel_in, + output wire [93:0] ssrout_parallel_out_latch, // PLD DCM output wire pld_pcs_rx_clk_out1_dcm, @@ -603,7 +608,10 @@ wire aib_fabric_tx_dcd_cal_req; wire aib_fabric_tx_sr_clk_out; wire aib_fabric_tx_transfer_clk; - +assign pld_pma_clkdiv_rx_user = aib_fabric_pld_pma_clkdiv_rx_user; +assign pld_pma_clkdiv_tx_user = aib_fabric_pld_pma_clkdiv_tx_user; +assign pld_pma_aib_tx_clk = aib_fabric_pma_aib_tx_clk; +assign pld_sr_clk_out = aib_fabric_tx_sr_clk_out; hdpldadapt hdpldadapt ( // AIB @@ -1055,6 +1063,8 @@ hdpldadapt hdpldadapt ( .pld_fabric_asn_dll_lock_en (pld_fabric_asn_dll_lock_en), .pld_tx_ssr_reserved_out (pld_tx_ssr_reserved_out), .pld_rx_ssr_reserved_out (pld_rx_ssr_reserved_out), + .ssrin_parallel_in (ssrin_parallel_in), + .ssrout_parallel_out_latch (ssrout_parallel_out_latch), // PLD DCM .pld_pcs_rx_clk_out1_dcm (pld_pcs_rx_clk_out1_dcm), @@ -1063,96 +1073,46 @@ hdpldadapt hdpldadapt ( .pld_pcs_tx_clk_out2_dcm (pld_pcs_tx_clk_out2_dcm) ); -/*** aibnd_top_wrp aibnd_top_wrp ( - .aib0 (), // Templated - .aib1 (), // Templated - .aib2 (), // Templated - .aib3 (), // Templated - .aib4 (), // Templated - .aib5 (), // Templated - .aib6 (), // Templated - .aib7 (), // Templated - .aib8 (), // Templated - .aib9 (), // Templated - .aib10 (), // Templated - .aib11 (), // Templated - .aib12 (), // Templated - .aib13 (), // Templated - .aib14 (), // Templated - .aib15 (), // Templated - .aib16 (), // Templated - .aib17 (), // Templated - .aib18 (), // Templated - .aib19 (), // Templated - .aib20 (), // Templated - .aib21 (), // Templated - .aib22 (), // Templated - .aib23 (), // Templated - .aib24 (), // Templated - .aib25 (), // Templated - .aib26 (), // Templated - .aib27 (), // Templated - .aib28 (), // Templated - .aib29 (), // Templated - .aib30 (), // Templated - .aib31 (), // Templated - .aib32 (), // Templated - .aib33 (), // Templated - .aib34 (), // Templated - .aib35 (), // Templated - .aib36 (), // Templated - .aib37 (), // Templated - .aib38 (), // Templated - .aib39 (), // Templated - .aib40 (), // Templated - .aib41 (), // Templated - .aib42 (), // Templated - .aib43 (), // Templated - //.aib0 (io_aib0), // Templated - //.aib1 (io_aib1), // Templated - //.aib2 (io_aib2), // Templated - //.aib3 (io_aib3), // Templated - //.aib4 (io_aib4), // Templated - //.aib5 (io_aib5), // Templated - //.aib6 (io_aib6), // Templated - //.aib7 (io_aib7), // Templated - //.aib8 (io_aib8), // Templated - //.aib9 (io_aib9), // Templated - //.aib10 (io_aib10), // Templated - //.aib11 (io_aib11), // Templated - //.aib12 (io_aib12), // Templated - //.aib13 (io_aib13), // Templated - //.aib14 (io_aib14), // Templated - //.aib15 (io_aib15), // Templated - //.aib16 (io_aib16), // Templated - //.aib17 (io_aib17), // Templated - //.aib18 (io_aib18), // Templated - //.aib19 (io_aib19), // Templated - //.aib20 (io_aib20), // Templated - //.aib21 (io_aib21), // Templated - //.aib22 (io_aib22), // Templated - //.aib23 (io_aib23), // Templated - //.aib24 (io_aib24), // Templated - //.aib25 (io_aib25), // Templated - //.aib26 (io_aib26), // Templated - //.aib27 (io_aib27), // Templated - //.aib28 (io_aib28), // Templated - //.aib29 (io_aib29), // Templated - //.aib30 (io_aib30), // Templated - //.aib31 (io_aib31), // Templated - //.aib32 (io_aib32), // Templated - //.aib33 (io_aib33), // Templated - //.aib34 (io_aib34), // Templated - //.aib35 (io_aib35), // Templated - //.aib36 (io_aib36), // Templated - //.aib37 (io_aib37), // Templated - //.aib38 (io_aib38), // Templated - //.aib39 (io_aib39), // Templated - //.aib40 (io_aib40), // Templated - //.aib41 (io_aib41), // Templated - //.aib42 (io_aib42), // Templated - //.aib43 (io_aib43), // Templated + .aib0 (io_aib0), + .aib1 (io_aib1), + .aib10 (io_aib10), + .aib11 (io_aib11), + .aib12 (io_aib12), + .aib13 (io_aib13), + .aib14 (io_aib14), + .aib15 (io_aib15), + .aib16 (io_aib16), + .aib17 (io_aib17), + .aib18 (io_aib18), + .aib19 (io_aib19), + .aib2 (io_aib2), + .aib20 (io_aib20), + .aib21 (io_aib21), + .aib22 (io_aib22), + .aib23 (io_aib23), + .aib24 (io_aib24), + .aib25 (io_aib25), + .aib26 (io_aib26), + .aib27 (io_aib27), + .aib28 (io_aib28), + .aib29 (io_aib29), + .aib3 (io_aib3), + .aib30 (io_aib30), + .aib31 (io_aib31), + .aib32 (io_aib32), + .aib33 (io_aib33), + .aib34 (io_aib34), + .aib35 (io_aib35), + .aib36 (io_aib36), + .aib37 (io_aib37), + .aib38 (io_aib38), + .aib39 (io_aib39), + .aib4 (io_aib4), + .aib40 (io_aib40), + .aib41 (io_aib41), + .aib42 (io_aib42), + .aib43 (io_aib43), .aib44 (io_aib44), .aib45 (io_aib45), .aib46 (io_aib46), @@ -1195,14 +1155,10 @@ aibnd_top_wrp aibnd_top_wrp ( .aib8 (io_aib8), .aib80 (io_aib80), .aib81 (io_aib81), - .aib82 (), // Templated - .aib83 (), // Templated - .aib84 (), // Templated - .aib85 (), // Templated - //.aib82 (io_aib82), - //.aib83 (io_aib83), - //.aib84 (io_aib84), - //.aib85 (io_aib85), + .aib82 (io_aib82), + .aib83 (io_aib83), + .aib84 (io_aib84), + .aib85 (io_aib85), .aib86 (io_aib86), .aib87 (io_aib87), .aib88 (io_aib88), @@ -1210,14 +1166,10 @@ aibnd_top_wrp aibnd_top_wrp ( .aib9 (io_aib9), .aib90 (io_aib90), .aib91 (io_aib91), - //.aib92 (io_aib92), - //.aib93 (io_aib93), - //.aib94 (io_aib94), - //.aib95 (io_aib95), - .aib92 (), // Templated - .aib93 (), // Templated - .aib94 (), // Templated - .aib95 (), // Templated + .aib92 (io_aib92), + .aib93 (io_aib93), + .aib94 (io_aib94), + .aib95 (io_aib95), .aib_fabric_adapter_rx_pld_rst_n (aib_fabric_adapter_rx_pld_rst_n), .aib_fabric_adapter_tx_pld_rst_n (aib_fabric_adapter_tx_pld_rst_n), .aib_fabric_avmm1_data_in (aib_fabric_avmm1_data_in), @@ -1376,108 +1328,4 @@ aibnd_top_wrp aibnd_top_wrp ( .ored_shift_en_out_chain1 (ored_shift_en_out_chain1), .ored_shift_en_out_chain2 (ored_shift_en_out_chain2) ); -***/ -wire [19:0] sl_dataout0,sl_dataout1; - - parameter DATAWIDTH = 20; -aib #(.DATAWIDTH(DATAWIDTH)) slave - ( - .iopad_tx({io_aib39, io_aib38, - io_aib37, io_aib36, io_aib35, io_aib34, io_aib33, io_aib32, io_aib31, io_aib30, io_aib29, - io_aib28, io_aib27, io_aib26, io_aib25, io_aib24, io_aib23, io_aib22, io_aib21, io_aib20}), - .iopad_rx({io_aib19, io_aib18, io_aib17, - io_aib16, io_aib15, io_aib14, io_aib13, io_aib12, io_aib11, io_aib10, io_aib9, io_aib8, io_aib7, - io_aib6, io_aib5, io_aib4, io_aib3, io_aib2, io_aib1, io_aib0}), - .iopad_ns_rcv_clkb(io_aib59), - .iopad_ns_rcv_clk(io_aib57), - //.iopad_ns_fwd_clk(aib43), - //.iopad_ns_fwd_clkb(aib42), - .iopad_ns_fwd_clk(io_aib43), - .iopad_ns_fwd_clkb(io_aib42), - .iopad_ns_sr_clk(io_aib83), - .iopad_ns_sr_clkb(io_aib82), - .iopad_ns_sr_load(io_aib92), - .iopad_ns_sr_data(io_aib93), - //.iopad_ns_mac_rdy(sl_rstno), - //.iopad_ns_adapter_rstn(sl_arstno), - .iopad_ns_mac_rdy(io_aib44), - .iopad_ns_adapter_rstn(io_aib65), - .iopad_spare1(), - .iopad_spare0(), - .iopad_fs_rcv_clkb(io_aib86), - .iopad_fs_rcv_clk(io_aib87), - .iopad_fs_fwd_clkb(io_aib40), - .iopad_fs_fwd_clk(io_aib41), - .iopad_fs_sr_clkb(io_aib84), - .iopad_fs_sr_clk(io_aib85), - .iopad_fs_sr_load(io_aib94), - .iopad_fs_sr_data(io_aib95), - //.iopad_fs_mac_rdy(pld_adapter_rx_pld_rst_n), - //.iopad_fs_adapter_rstn(pld_adapter_tx_pld_rst_n), - .iopad_fs_mac_rdy(io_aib49), - .iopad_fs_adapter_rstn(io_aib56), - - .iopad_device_detect(device_detect), - .iopad_device_detect_copy(device_detectrdcy), - .iopad_por(), - .iopad_por_copy(), - - .data_in({sl_dataout1[19:0],sl_dataout0[19:0]}), //output data to pad - .data_out({sl_dataout1[19:0],sl_dataout0[19:0]}), //input data from pad - .m_ns_fwd_clk(pld_tx_clk1_rowclk), //output data clock - .m_fs_rvc_clk(), - .m_fs_fwd_clk(), - .m_ns_rvc_clk(pld_tx_clk1_rowclk), - - .ms_ns_adapter_rstn(pld_adapter_tx_pld_rst_n), - .sl_ns_adapter_rstn(pld_adapter_tx_pld_rst_n), - .ms_ns_mac_rdy(pld_adapter_rx_pld_rst_n), - .sl_ns_mac_rdy(pld_adapter_rx_pld_rst_n), - .fs_mac_rdy(), - - .ms_config_done(1'b1), - .ms_rx_dcc_dll_lock_req(1'b0), - .ms_tx_dcc_dll_lock_req(1'b0), - .sl_config_done(pld_adapter_rx_pld_rst_n), - .sl_rx_dcc_dll_lock_req(pld_rx_dll_lock_req), - .sl_tx_dcc_dll_lock_req(pld_tx_dll_lock_req), - .ms_tx_transfer_en(), - .ms_rx_transfer_en(), - .sl_tx_transfer_en(), - .sl_rx_transfer_en(), - .sr_ms_tomac(), - .sr_sl_tomac(), - .ms_nsl(1'b0), - - .iddren(1'b1), - .idataselb(1'b0), //output async data selection - .itxen(1'b1), //data tx enable - .irxen(3'b111),//data input enable - - .ms_device_detect(), - .sl_por(pld_adapter_rx_pld_rst_n), - - .jtag_clkdr_in(1'b0), - .scan_out(), - .jtag_intest(1'b0), - .jtag_mode_in(1'b0), - .jtag_rstb(1'b0), - .jtag_rstb_en(1'b0), - .jtag_weakpdn(1'b0), - .jtag_weakpu(1'b0), - .jtag_tx_scanen_in(1'b0), - .scan_in(1'b0), - -//Redundancy control signals -`include "redundancy_ctrl_sim.vh" - .sl_external_cntl_26_0({1'b1,26'b0}), - .sl_external_cntl_30_28(3'b0), - .sl_external_cntl_57_32(26'b0), - - .ms_external_cntl_4_0(5'b0), - .ms_external_cntl_65_8(58'b0), - - .vccl_aib(1'b1), - .vssl_aib(1'b0) ); - endmodule diff --git a/maib_rtl/s10aib/rtl/s10aib.v b/maib_rtl/s10aib/rtl/s10aib.v new file mode 100644 index 0000000..75ab293 --- /dev/null +++ b/maib_rtl/s10aib/rtl/s10aib.v @@ -0,0 +1,640 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// + +module s10aib ( + +//***** symmetrical Microbump *******// +inout wire iopad_ns_mac_rdy, +inout wire iopad_fs_mac_rdy, +inout wire iopad_ns_adapter_rstn, +inout wire iopad_fs_adapter_rstn, + +inout [19:0] iopad_tx, +inout wire iopad_ns_fwd_clk, +inout wire iopad_ns_fwd_clkb, +inout wire iopad_ns_rcv_clk, +inout wire iopad_ns_rcv_clkb, + + +inout [19:0] iopad_rx, +inout wire iopad_fs_fwd_clk, +inout wire iopad_fs_fwd_clkb, +inout wire iopad_fs_fwd_div2_clk, +inout wire iopad_fs_fwd_div2_clkb, +inout wire iopad_fs_rcv_clk, +inout wire iopad_fs_rcv_clkb, +inout wire iopad_fs_rcv_div2_clk, +inout wire iopad_fs_rcv_div2_clkb, + +inout wire iopad_ns_sr_data, +inout wire iopad_ns_sr_load, +inout wire iopad_ns_sr_clk, +inout wire iopad_ns_sr_clkb, + + +inout wire iopad_fs_sr_clk, +inout wire iopad_fs_sr_clkb, +inout wire iopad_fs_sr_data, +inout wire iopad_fs_sr_load, + +inout iopad_unused_aib45, +inout iopad_unused_aib46, +inout iopad_unused_aib47, +inout iopad_unused_aib50, +inout iopad_unused_aib51, +inout iopad_unused_aib52, +inout iopad_unused_aib58, +inout iopad_unused_aib60, +inout iopad_unused_aib61, +inout iopad_unused_aib62, +inout iopad_unused_aib63, +inout iopad_unused_aib64, +inout iopad_unused_aib66, +inout iopad_unused_aib67, +inout iopad_unused_aib68, +inout iopad_unused_aib69, +inout iopad_unused_aib70, +inout iopad_unused_aib71, +inout iopad_unused_aib72, +inout iopad_unused_aib73, +inout iopad_unused_aib74, +inout iopad_unused_aib75, +inout iopad_unused_aib76, +inout iopad_unused_aib77, +inout iopad_unused_aib78, +inout iopad_unused_aib79, +inout iopad_unused_aib80, +inout iopad_unused_aib81, +inout iopad_unused_aib88, +inout iopad_unused_aib89, +inout iopad_unused_aib90, +inout iopad_unused_aib91, + + +//***** MAC signals Corresponded to Microbump *******// +//MAC data interface +input wire [79:0] tx_parallel_data, // This name mapped to quartus generated user interface signals. connect to pld_tx_fabric_data_in +output wire [79:0] rx_parallel_data, // This name mapped to quartus generated user interface signals. connect to pld_rx_fabric_data_out +input wire tx_coreclkin, // This name mapped to quartus generated user interface signals.connect to pld_tx_clk1_dcm. Half of m_fs_fwd_clk +output wire tx_clkout, // This name mapped to quartus generated user interface signals.connect to pld_pcs_tx_clk_out1_dcm. +input wire rx_coreclkin, // This name mapped to quartus generated user interface signals.connect to pld_rx_clk1_dcm. + // Also connect to pld_pma_coreclkin_rowclk which go to iopad_ns_rcv_clk. +output wire rx_clkout, // connect to pld_pcs_rx_clk_out1_dcm. 1GHz. Available to MAC. Half of m_fs_fwd_clk. +input m_ns_fwd_clk, // connect to pld_tx_clk2_dcm. This clock needs to be supplied if tx phase compensation fifo read clock + // It is optional if FIFO read clock is from master. +output m_fs_fwd_clk, // connect to pld_pcs_rx_clk_out2_dcm + +output wire fs_mac_rdy, //(use c3 pld_pma_clkdiv_rx_user pin). Drive by Master +input wire ns_mac_rdy, //corresponding to nd pld_pma_rxpma_rstb. This signal should be high before ns_adapter_rstn go high. +input wire ns_adapter_rstn, //Reset Main adapter and pass over to the fs. +input wire config_done, //This is csr_rdy_in + +input wire sl_rx_dcc_dll_lock_req, //Drive reset statemachine at the farside +input wire sl_tx_dcc_dll_lock_req, //Drive reset statemachine at the farside + +//*** config bit **** /// +//sdr or ddr mode, dcc, dll bypass or not. register mode or not ***/ + +//**** ns ready status The following signals can be found from ms_sideband and sl_sideband. Listed explicitly for convinience***// +output wire ms_osc_transfer_en, +output wire ms_rx_transfer_en, +output wire ms_tx_transfer_en, +output wire sl_osc_transfer_en, +output wire sl_rx_transfer_en, +output wire sl_tx_transfer_en, + +//Put MS to SL sideband signal and SL to MS sideband signal +output wire [80:0] ms_sideband, +output wire [72:0] sl_sideband +//Put side band 80 bit from ms and sl for debugging purpose +); //Should be triggered for initialization + +logic csr_rdy_dly_in; //1 micro second after csr_rdy_in. Config done +logic nfrzdrv_in; //Before config done, this signal is zero to freeze PLD output to 1. +logic usermode_in; +logic [93:0] ssrout_parallel_out_latch; +logic [117:0] ssrin_parallel_in; + +wire HI, LO; +assign HI = 1'b1; +assign LO = 1'b0; + + + +initial begin + csr_rdy_dly_in = 1'b0; + nfrzdrv_in = 1'b0; + usermode_in = 1'b0; + + @(config_done) + #1000ns; + csr_rdy_dly_in = 1'b1; + nfrzdrv_in = 1'b1; + #1000ns; + usermode_in = 1'b1; + +end + +assign ms_osc_transfer_en = ssrout_parallel_out_latch[80]; +assign ms_tx_transfer_en = ssrout_parallel_out_latch[78]; +assign ms_rx_transfer_en = ssrout_parallel_out_latch[75]; +assign ms_sideband = ssrout_parallel_out_latch[80:0]; +assign sl_osc_transfer_en = ssrin_parallel_in[72]; +assign sl_rx_transfer_en = ssrin_parallel_in[70]; +assign sl_tx_transfer_en = ssrin_parallel_in[64]; +assign sl_sideband = ssrin_parallel_in[72:0]; + +ndaibadapt_wrap ndut( + +// EMIB inout + .io_aib0(iopad_rx[0]), + .io_aib1(iopad_rx[1]), + .io_aib10(iopad_rx[10]), + .io_aib11(iopad_rx[11]), + .io_aib12(iopad_rx[12]), + .io_aib13(iopad_rx[13]), + .io_aib14(iopad_rx[14]), + .io_aib15(iopad_rx[15]), + .io_aib16(iopad_rx[16]), + .io_aib17(iopad_rx[17]), + .io_aib18(iopad_rx[18]), + .io_aib19(iopad_rx[19]), + .io_aib2(iopad_rx[2]), + .io_aib20(iopad_tx[0]), + .io_aib21(iopad_tx[1]), + .io_aib22(iopad_tx[2]), + .io_aib23(iopad_tx[3]), + .io_aib24(iopad_tx[4]), + .io_aib25(iopad_tx[5]), + .io_aib26(iopad_tx[6]), + .io_aib27(iopad_tx[7]), + .io_aib28(iopad_tx[8]), + .io_aib29(iopad_tx[9]), + .io_aib3(iopad_rx[3]), + .io_aib30(iopad_tx[10]), + .io_aib31(iopad_tx[11]), + .io_aib32(iopad_tx[12]), + .io_aib33(iopad_tx[13]), + .io_aib34(iopad_tx[14]), + .io_aib35(iopad_tx[15]), + .io_aib36(iopad_tx[16]), + .io_aib37(iopad_tx[17]), + .io_aib38(iopad_tx[18]), + .io_aib39(iopad_tx[19]), + .io_aib4(iopad_rx[4]), + .io_aib40(iopad_fs_fwd_clkb), + .io_aib41(iopad_fs_fwd_clk), + .io_aib42(iopad_ns_fwd_clkb), + .io_aib43(iopad_ns_fwd_clk), + .io_aib44(iopad_ns_mac_rdy), + .io_aib45(iopad_unused_aib45), //From Tim's 3/26 aib_bump_map + .io_aib46(iopad_unused_aib46), //spare[0] + .io_aib47(iopad_unused_aib47), //spare[1] + .io_aib48(iopad_fs_rcv_div2_clk), + .io_aib49(iopad_fs_mac_rdy), + .io_aib5(iopad_rx[5]), + .io_aib50(iopad_unused_aib50), //From Tim's 3/26 aib_bump_map + .io_aib51(iopad_unused_aib51), //From Tim's 3/26 aib_bump_map + .io_aib52(iopad_unused_aib52), //From Tim's 3/26 aib_bump_map + .io_aib53(iopad_fs_fwd_div2_clk), //From Tim's 3/26 aib_bump_map + .io_aib54(iopad_fs_fwd_div2_clkb), //From Tim's 3/26 aib_bump_map + .io_aib55(iopad_fs_rcv_div2_clkb), + .io_aib56(iopad_fs_adapter_rstn), + .io_aib57(iopad_ns_rcv_clk), + .io_aib58(iopad_unused_aib58), //From Tim's 3/26 aib_bump_map + .io_aib59(iopad_ns_rcv_clkb), + .io_aib6(iopad_rx[6]), + .io_aib60(iopad_unused_aib60), //From Tim's 3/26 aib_bump_map + .io_aib61(iopad_unused_aib61), // From Tim's 3/26 aib_bump_map + .io_aib62(iopad_unused_aib62), // From Tim's 3/26 aib_bump_map + .io_aib63(iopad_unused_aib63), //unused + .io_aib64(iopad_unused_aib64), //unused + .io_aib65(iopad_ns_adapter_rstn), + .io_aib66(iopad_unused_aib66), //From Tim's 3/26 aib_bump_map + .io_aib67(iopad_unused_aib67), //From Tim's 3/26 aib_bump_map + .io_aib68(iopad_unused_aib68), //From Tim's 3/26 aib_bump_map + .io_aib69(iopad_unused_aib69), //From Tim's 3/26 aib_bump_map + .io_aib7(iopad_rx[7]), + .io_aib70(iopad_unused_aib70), //From Tim's 3/26 aib_bump_map + .io_aib71(iopad_unused_aib71), //From Tim's 3/26 aib_bump_map + .io_aib72(iopad_unused_aib72), //From Tim's 3/26 aib_bump_map + .io_aib73(iopad_unused_aib73), //From Tim's 3/26 aib_bump_map + .io_aib74(iopad_unused_aib74), //From Tim's 3/26 aib_bump_map + .io_aib75(iopad_unused_aib75), //From Tim's 3/26 aib_bump_map + .io_aib76(iopad_unused_aib76), //From Tim's 3/26 aib_bump_map + .io_aib77(iopad_unused_aib77), //From Tim's 3/26 aib_bump_map + .io_aib78(iopad_unused_aib78), //unused + .io_aib79(iopad_unused_aib79), //unused + .io_aib8(iopad_rx[8]), + .io_aib80(iopad_unused_aib80), //unused + .io_aib81(iopad_unused_aib81), //unused + .io_aib82(iopad_ns_sr_clkb), + .io_aib83(iopad_ns_sr_clk), + .io_aib84(iopad_fs_sr_clkb), + .io_aib85(iopad_fs_sr_clk), + .io_aib86(iopad_fs_rcv_clkb), + .io_aib87(iopad_fs_rcv_clk), + .io_aib88(iopad_unused_aib88), //unused + .io_aib89(iopad_unused_aib89), //unused + .io_aib9(iopad_rx[9]), + .io_aib90(iopad_unused_aib90), //From Tim's 3/26 aib_bump_map + .io_aib91(iopad_unused_aib91), //From Tim's 3/26 aib_bump_map + .io_aib92(iopad_ns_sr_load), + .io_aib93(iopad_ns_sr_data), + .io_aib94(iopad_fs_sr_load), + .io_aib95(iopad_fs_sr_data), + + // Adapter input + .bond_rx_asn_ds_in_fifo_hold(1'b0), + .bond_rx_asn_us_in_fifo_hold(1'b0), + .bond_rx_fifo_ds_in_rden(1'b0), + .bond_rx_fifo_ds_in_wren(1'b0), + .bond_rx_fifo_us_in_rden(1'b0), + .bond_rx_fifo_us_in_wren(1'b0), + .bond_rx_hrdrst_ds_in_fabric_rx_dll_lock(1'b0), + .bond_rx_hrdrst_us_in_fabric_rx_dll_lock(1'b0), + .bond_rx_hrdrst_ds_in_fabric_rx_dll_lock_req(1'b0), + .bond_rx_hrdrst_us_in_fabric_rx_dll_lock_req(1'b0), + .bond_tx_fifo_ds_in_dv(1'b0), + .bond_tx_fifo_ds_in_rden(1'b0), + .bond_tx_fifo_ds_in_wren(1'b0), + .bond_tx_fifo_us_in_dv(1'b0), + .bond_tx_fifo_us_in_rden(1'b0), + .bond_tx_fifo_us_in_wren(1'b0), + .bond_tx_hrdrst_ds_in_fabric_tx_dcd_cal_done(1'b0), + .bond_tx_hrdrst_us_in_fabric_tx_dcd_cal_done(1'b0), + .bond_tx_hrdrst_ds_in_fabric_tx_dcd_cal_req(1'b0), + .bond_tx_hrdrst_us_in_fabric_tx_dcd_cal_req(1'b0), + + // Config input (These are required for reset(), look properly and configure as is in previous project + .csr_config(3'h1), + .csr_clk_in(1'b0), + .csr_in(3'h0), + .csr_pipe_in(3'h0), + .csr_rdy_dly_in(csr_rdy_dly_in), + .csr_rdy_in(config_done), + .nfrzdrv_in(nfrzdrv_in), + .usermode_in(usermode_in), + + // PLD input + .hip_aib_fsr_in(4'h0), + .hip_aib_ssr_in(40'h0), + .hip_avmm_read(1'b0), + .hip_avmm_reg_addr(21'h0), + .hip_avmm_write(1'b0), + .hip_avmm_writedata(8'h0), + .pld_10g_krfec_rx_clr_errblk_cnt(1'b0), + .pld_10g_rx_align_clr(1'b0), + .pld_10g_rx_clr_ber_count(1'b0), + .pld_10g_tx_bitslip(7'h0), + .pld_10g_tx_burst_en(1'b0), + .pld_10g_tx_diag_status(2'b0), + .pld_10g_tx_wordslip(1'b0), + .pld_8g_a1a2_size(1'b0), + .pld_8g_bitloc_rev_en(1'b0), + .pld_8g_byte_rev_en(1'b0), + .pld_8g_eidleinfersel(3'h0), + .pld_8g_encdt(1'b0), + .pld_8g_tx_boundary_sel(5'h0), + .pld_adapter_rx_pld_rst_n(ns_adapter_rstn), + .pld_adapter_tx_pld_rst_n(ns_adapter_rstn), + .pld_avmm1_clk_rowclk(1'b0), + .pld_avmm1_read(1'b0), + .pld_avmm1_reg_addr(10'h0), + .pld_avmm1_request(1'b0), + .pld_avmm1_write(1'b0), + .pld_avmm1_writedata(8'h0), + .pld_avmm1_reserved_in(9'h0), + .pld_avmm2_clk_rowclk(1'b0), + .pld_avmm2_read(1'b0), + .pld_avmm2_reg_addr(9'h0), + .pld_avmm2_request(1'b0), + .pld_avmm2_write(1'b0), + .pld_avmm2_writedata(8'h0), + .pld_avmm2_reserved_in(10'h0), + .pld_bitslip(1'b0), + .pld_fpll_shared_direct_async_in(2'b0), + .pld_fpll_shared_direct_async_in_rowclk(1'b0), + .pld_fpll_shared_direct_async_in_dcm(1'b0), + .pld_ltr(1'b0), + .pr_channel_freeze_n(1'b1), + .pld_pcs_rx_pld_rst_n(1'b0), + .pld_pcs_tx_pld_rst_n(1'b0), + .pld_pma_adapt_start(1'b0), + .pld_pma_coreclkin_rowclk(rx_coreclkin), + .pld_pma_csr_test_dis(1'b0), + .pld_pma_early_eios(1'b0), + .pld_pma_eye_monitor(6'b0), + .pld_pma_fpll_cnt_sel(4'b0), + .pld_pma_fpll_extswitch(1'b0), + .pld_pma_fpll_lc_csr_test_dis(1'b0), + .pld_pma_fpll_num_phase_shifts(3'b0), + .pld_pma_fpll_pfden(1'b0), + .pld_pma_fpll_up_dn_lc_lf_rstn(1'b0), + .pld_pma_ltd_b(1'b0), + .pld_pma_nrpi_freeze(1'b0), + .pld_pma_pcie_switch(2'h0), + .pld_pma_ppm_lock(1'b0), + .pld_pma_reserved_out(5'b0), + .pld_pma_rs_lpbk_b(1'b0), + .pld_pma_rxpma_rstb(ns_mac_rdy), + .pld_pma_tx_bitslip(1'b0), + .pld_pma_txdetectrx(1'b0), + .pld_pma_txpma_rstb(1'b0), + .pld_pmaif_rxclkslip(1'b0), + .pld_polinv_rx(1'b0), + .pld_polinv_tx(1'b0), + .pld_rx_clk1_rowclk(1'b0), + .pld_rx_clk2_rowclk(1'b0), + .pld_rx_dll_lock_req(sl_rx_dcc_dll_lock_req), + .pld_rx_fabric_fifo_align_clr(1'b0), + `ifdef SS_EN_ND_FIFO_ELASTIC_BUF // For Testing ND FIFO Elastic Mode + .pld_rx_fabric_fifo_rd_en(1'b1), + `else + .pld_rx_fabric_fifo_rd_en(1'b0), + `endif + .pld_rx_prbs_err_clr(1'b0), + .pld_sclk1_rowclk(1'b0), + .pld_sclk2_rowclk(1'b0), + .pld_syncsm_en(1'b0), + .pld_tx_clk1_rowclk(tx_coreclkin), + .pld_tx_clk2_rowclk(m_ns_fwd_clk), + .pld_tx_fabric_data_in(tx_parallel_data), //Loopback from rx + .pld_txelecidle(1'b0), + .pld_tx_dll_lock_req(sl_tx_dcc_dll_lock_req), + .pld_tx_fifo_latency_adj_en(1'b0), + .pld_rx_fifo_latency_adj_en(1'b0), + .pld_aib_fabric_rx_dll_lock_req(1'b0), + .pld_aib_fabric_tx_dcd_cal_req(1'b0), + .pld_aib_hssi_tx_dcd_cal_req(1'b0), + .pld_aib_hssi_tx_dll_lock_req(1'b0), + .pld_aib_hssi_rx_dcd_cal_req(1'b0), + .pld_tx_ssr_reserved_in(3'b11), + .pld_rx_ssr_reserved_in(2'b00), + .pld_pma_tx_qpi_pulldn(1'b0), + .pld_pma_tx_qpi_pullup(1'b1), + .pld_pma_rx_qpi_pullup(1'b1), + + // PLD DCM input + .pld_rx_clk1_dcm(rx_coreclkin), + .pld_tx_clk1_dcm(tx_coreclkin), + .pld_tx_clk2_dcm(m_ns_fwd_clk), + + // uC AVMM + + // DFT input + .dft_adpt_aibiobsr_fastclkn(1'b1), + .adapter_scan_rst_n(1'b1), + .adapter_scan_mode_n(1'b1), + .adapter_scan_shift_n(1'b1), + .adapter_scan_shift_clk(1'b0), + .adapter_scan_user_clk0(1'b0), // 125MHz + .adapter_scan_user_clk1(1'b0), // 250MHz + .adapter_scan_user_clk2(1'b0), // 500MHz + .adapter_scan_user_clk3(1'b0), // 1GHz + .adapter_clk_sel_n(1'b0), + .adapter_occ_enable(1'b0), + .adapter_global_pipe_se(1'b1), + .adapter_config_scan_in(4'h0), + .adapter_scan_in_occ1(2'h0), + .adapter_scan_in_occ2(5'h0), + .adapter_scan_in_occ3(1'b0), + .adapter_scan_in_occ4(1'b0), + .adapter_scan_in_occ5(2'h0), + .adapter_scan_in_occ6(11'h0), + .adapter_scan_in_occ7(1'b0), + .adapter_scan_in_occ8(1'b0), + .adapter_scan_in_occ9(1'b0), + .adapter_scan_in_occ10(1'b0), + .adapter_scan_in_occ11(1'b0), + .adapter_scan_in_occ12(1'b0), + .adapter_scan_in_occ13(1'b0), + .adapter_scan_in_occ14(1'b0), + .adapter_scan_in_occ15(1'b0), + .adapter_scan_in_occ16(1'b0), + .adapter_scan_in_occ17(1'b0), + .adapter_scan_in_occ18(2'h0), + .adapter_scan_in_occ19(1'h0), + .adapter_scan_in_occ20(1'h0), + .adapter_scan_in_occ21(2'h0), + .adapter_non_occ_scan_in(1'b0), + .adapter_occ_scan_in(1'b0), + .dft_fabric_iaibdftcore2dll(3'h0), + + + // DFT output + .adapter_config_scan_out(), + .adapter_scan_out_occ1(), + .adapter_scan_out_occ2(), + .adapter_scan_out_occ3(), + .adapter_scan_out_occ4(), + .adapter_scan_out_occ5(), + .adapter_scan_out_occ6(), + .adapter_scan_out_occ7(), + .adapter_scan_out_occ8(), + .adapter_scan_out_occ9(), + .adapter_scan_out_occ10(), + .adapter_scan_out_occ11(), + .adapter_scan_out_occ12(), + .adapter_scan_out_occ13(), + .adapter_scan_out_occ14(), + .adapter_scan_out_occ15(), + .adapter_scan_out_occ16(), + .adapter_scan_out_occ17(), + .adapter_scan_out_occ18(), + .adapter_scan_out_occ19(), + .adapter_scan_out_occ20(), + .adapter_scan_out_occ21(), + .adapter_non_occ_scan_out(), + .adapter_occ_scan_out(), + .dft_fabric_oaibdftdll2core(), + + // Adapter output + .bond_rx_asn_ds_out_fifo_hold(), + .bond_rx_asn_us_out_fifo_hold(), + .bond_rx_fifo_ds_out_rden(), + .bond_rx_fifo_ds_out_wren(), + .bond_rx_fifo_us_out_rden(), + .bond_rx_fifo_us_out_wren(), + .bond_rx_hrdrst_ds_out_fabric_rx_dll_lock(), + .bond_rx_hrdrst_us_out_fabric_rx_dll_lock(), + .bond_rx_hrdrst_ds_out_fabric_rx_dll_lock_req(), + .bond_rx_hrdrst_us_out_fabric_rx_dll_lock_req(), + .bond_tx_fifo_ds_out_dv(), + .bond_tx_fifo_ds_out_rden(), + .bond_tx_fifo_ds_out_wren(), + .bond_tx_fifo_us_out_dv(), + .bond_tx_fifo_us_out_rden(), + .bond_tx_fifo_us_out_wren(), + .bond_tx_hrdrst_ds_out_fabric_tx_dcd_cal_done(), + .bond_tx_hrdrst_us_out_fabric_tx_dcd_cal_done(), + .bond_tx_hrdrst_ds_out_fabric_tx_dcd_cal_req(), + .bond_tx_hrdrst_us_out_fabric_tx_dcd_cal_req(), + // Config output + .csr_clk_out(), + .csr_out(), + .csr_pipe_out(), + .csr_rdy_dly_out(), + .csr_rdy_out(), + .nfrzdrv_out(), + .usermode_out(), + // PLD output + .hip_aib_fsr_out(), + .hip_aib_ssr_out(), + .hip_avmm_readdata(), + .hip_avmm_readdatavalid(), + .hip_avmm_writedone(), + .hip_avmm_reserved_out(), + .pld_10g_krfec_rx_blk_lock(), + .pld_10g_krfec_rx_diag_data_status(), + .pld_10g_krfec_rx_frame(), + .pld_10g_krfec_tx_frame(), + .pld_krfec_tx_alignment(), + .pld_10g_rx_crc32_err(), + .pld_rx_fabric_fifo_insert(), + .pld_rx_fabric_fifo_del(), + + .pld_10g_rx_frame_lock(), + .pld_10g_rx_hi_ber(), + .pld_10g_tx_burst_en_exe(), + .pld_8g_a1a2_k1k2_flag(), + .pld_8g_empty_rmf(), + .pld_8g_full_rmf(), + .pld_8g_rxelecidle(), + .pld_8g_signal_detect_out(), + .pld_8g_wa_boundary(), + .pld_avmm1_busy(), + .pld_avmm1_cmdfifo_wr_full(), + .pld_avmm1_cmdfifo_wr_pfull(), + .pld_avmm1_readdata(), + .pld_avmm1_readdatavalid(), + .pld_avmm1_reserved_out(), + .pld_avmm2_busy(), + .pld_avmm2_cmdfifo_wr_full(), + .pld_avmm2_cmdfifo_wr_pfull(), + .pld_avmm2_readdata(), + .pld_avmm2_readdatavalid(), + .pld_avmm2_reserved_out(), + .pld_chnl_cal_done(), + .pld_fpll_shared_direct_async_out(), + .pld_fpll_shared_direct_async_out_hioint(), + .pld_fpll_shared_direct_async_out_dcm(), + .pld_fsr_load(), + .pld_pcs_rx_clk_out1_hioint(), + .pld_pcs_rx_clk_out2_hioint(), + .pld_pcs_tx_clk_out1_hioint(), + .pld_pcs_tx_clk_out2_hioint(), + .pld_pll_cal_done(), + .pld_pma_adapt_done(), + .pld_pma_clkdiv_rx_user(fs_mac_rdy), + .pld_pma_fpll_clk0bad(), + .pld_pma_fpll_clk1bad(), + .pld_pma_fpll_clksel(), + .pld_pma_fpll_phase_done(), + .pld_pma_hclk_hioint(), + .pld_pma_internal_clk1_hioint(), + .pld_pma_internal_clk2_hioint(), + .pld_pma_pcie_sw_done(), + .pld_pma_pfdmode_lock(), + .pld_pma_reserved_in(), + .pld_pma_rx_detect_valid(), + .pld_pma_rx_found(), + .pld_pma_rxpll_lock(), + .pld_pma_signal_ok(), + .pld_pma_testbus(), + .pld_pmaif_mask_tx_pll(), + .pld_rx_fabric_align_done(), + .pld_rx_fabric_data_out(rx_parallel_data), + .pld_rx_fabric_fifo_empty(), + .pld_rx_fabric_fifo_full(), + .pld_rx_fabric_fifo_latency_pulse(), + .pld_rx_fabric_fifo_pempty(), + .pld_rx_fabric_fifo_pfull(), + .pld_rx_hssi_fifo_empty(), + .pld_rx_hssi_fifo_full(), + .pld_rx_hssi_fifo_latency_pulse(), + .pld_rx_prbs_done(), + .pld_rx_prbs_err(), + .pld_sr_clk_out(pld_ns_clk), + .pld_ssr_load(), + .pld_test_data(), + .pld_tx_fabric_fifo_empty(), + .pld_tx_fabric_fifo_full(), + .pld_tx_fabric_fifo_latency_pulse(), + .pld_tx_fabric_fifo_pempty(), + .pld_tx_fabric_fifo_pfull(), + .pld_tx_hssi_align_done(), + .pld_tx_hssi_fifo_empty(), + .pld_tx_hssi_fifo_full(), + .pld_tx_hssi_fifo_latency_pulse(), + .pld_hssi_osc_transfer_en(), + .pld_hssi_rx_transfer_en(), + .pld_fabric_tx_transfer_en(), + .pld_aib_fabric_rx_dll_lock(), + .pld_aib_fabric_tx_dcd_cal_done(), + .pld_aib_hssi_rx_dcd_cal_done(), + .pld_aib_hssi_tx_dcd_cal_done(), + .pld_aib_hssi_tx_dll_lock(), + .pld_hssi_asn_dll_lock_en(), + .pld_fabric_asn_dll_lock_en(), + .pld_tx_ssr_reserved_out(), + .pld_rx_ssr_reserved_out(), + .ssrin_parallel_in(ssrin_parallel_in[117:0]), + .ssrout_parallel_out_latch(ssrout_parallel_out_latch[93:0]), + + // PLD DCM output + .pld_pcs_rx_clk_out1_dcm(rx_clkout), + .pld_pcs_rx_clk_out2_dcm(m_fs_fwd_clk), + .pld_pcs_tx_clk_out1_dcm(tx_clkout), + .pld_pcs_tx_clk_out2_dcm(), + + //JTAG input + .iatpg_scan_clk_in0(1'b1), + .iatpg_scan_clk_in1(1'b1), + .iatpg_scan_in0(1'b0), + .iatpg_scan_in1(1'b0), + .iatpg_scan_shift_n(1'b1), + .iatpg_scan_mode_n(1'b1), + .iatpg_scan_rst_n(1'b1), + .ijtag_clkdr_in_chain(1'b0), + .ijtag_last_bs_in_chain(1'b0), + .ijtag_tx_scan_in_chain(1'b0), + .ired_directin_data_in_chain1(1'b0), + .ired_directin_data_in_chain2(1'b0), + .ired_irxen_in_chain1(3'h0), + .ired_irxen_in_chain2(3'h0), + .ired_shift_en_in_chain1(1'b0), + .ired_shift_en_in_chain2(1'b0), + .jtag_clksel(1'b0), + .jtag_intest(1'b0), + .jtag_mode_in(1'b0), + .jtag_rstb(1'b1), + .jtag_rstb_en(1'b0), + .jtag_tx_scanen_in(1'b0), + .jtag_weakpdn(1'b0), + .jtag_weakpu(1'b0), + + //Jtag output + .jtag_clksel_out(), + .jtag_intest_out(), + .jtag_mode_out(), + .jtag_rstb_en_out(), + .jtag_rstb_out(), + .jtag_tx_scanen_out(), + .jtag_weakpdn_out(), + .jtag_weakpu_out(), + .oatpg_scan_out0(), + .oatpg_scan_out1(), + .ojtag_clkdr_out_chain(), + .ojtag_last_bs_out_chain(), + .ojtag_rx_scan_out_chain(), + .ored_directin_data_out0_chain1(), + .ored_directin_data_out0_chain2(), + .ored_rxen_out_chain1(), + .ored_rxen_out_chain2(), + .ored_shift_en_out_chain1(), + .ored_shift_en_out_chain2() +); + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async/altr_hps_1r1w_4x2_rfifo_async b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async/altr_hps_1r1w_4x2_rfifo_async new file mode 100644 index 0000000..e69de29 diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async/altr_hps_1r1w_4x2_rfifo_async_read.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async/altr_hps_1r1w_4x2_rfifo_async_read.v new file mode 100644 index 0000000..95956c1 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async/altr_hps_1r1w_4x2_rfifo_async_read.v @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module altr_hps_1r1w_4x2_rfifo_async_read ( + read_clk, + read_rst_n, + read_ready, + r_data_in, + r_data_out, + w_addr_gray_in, + r_addr_out, + r_addr_gray_out, + rd_valid +); + +input read_clk; // read clock +input read_rst_n; // Read reset +input read_ready; // read device is ready for read +input [2:0] w_addr_gray_in; // write pointer gray code in +output rd_valid; // read data valid +output [2:0] r_addr_gray_out; // read pointer gray code floped for de-glitches +output [1:0] r_addr_out; // read pointer gray code floped for de-glitches + +input [1:0] r_data_in; // the read data in +output [1:0] r_data_out; // read data just pass through but we can pipeline a flop if the timing issue + +// read side wire and reg definition +// ---------------------------------------------------- +wire [2:0] w_addr_gray_in; // write pointer gray code in +wire [2:0] w_addr_sync; // write pointer gray code in synchronized out +wire [2:0] w_addr_bin; // write pointer synced binary out +reg [2:0] r_addr; // read pointer +wire [2:0] r_addr_gray; // read pointer gray code +wire [1:0] r_addr_out; // read pointer gray code +reg [2:0] r_addr_gray_out; // read pointer gray code floped for de-glitches +wire r_enable; // read enable +wire fifo_empty; // fifo empty +wire rd_valid; // Output data valid +wire [1:0] r_data_in; // read pointer gray code floped for de-glitches +wire [1:0] r_data_out; // read pointer gray code floped for de-glitches + +//wire [1:0] r_data_out; // read data just pass through but we can add a flop if the timing issue + +assign r_addr_out[1:0] = r_addr[1:0]; + +// read counter increment when it is enabled +// ---------------------------------------------------- +always @(posedge read_clk or negedge read_rst_n) +begin + if (~read_rst_n) begin + r_addr[2:0] <= 3'd0; + end + else if (r_enable) begin + r_addr[2:0] <= r_addr[2:0] + 3'd1; + end +end + +// --------------------------------------------------------------------------------- +// READ SIDE LOGIC +// --------------------------------------------------------------------------------- + +//Using gray code +//---------------------------------------------------- +altr_hps_bin2gray bin2gray_r( + .bin_in(r_addr[2:0]), + .gray_out(r_addr_gray[2:0]) +); + +// Flop out the w_addr_gray_out +// -------------------------------------------------- +always @(posedge read_clk or negedge read_rst_n) +begin + if (~read_rst_n) + r_addr_gray_out[2:0] <= 3'd0; + else + r_addr_gray_out[2:0] <= r_addr_gray[2:0]; +end + +altr_hps_bitsync + #(.DWIDTH(3),.RESET_VAL(0)) + w_pointer_sync ( + .clk(read_clk), + .rst_n(read_rst_n), + .data_in(w_addr_gray_in[2:0]), + .data_out(w_addr_sync[2:0]) + ); +// defparam altr_hps_1r1w_4x2_rfifo_async_read.w_pointer_sync.DWIDTH=3'd3; +// defparam altr_hps_1r1w_4x2_rfifo_async_read.w_pointer_sync.RESET_VAL=1'd0; + +// gray to binary for read pointer +// --------------------------------------------------------- +altr_hps_gray2bin gray2bin_wp ( + .gray_in(w_addr_sync[2:0]), + .bin_out(w_addr_bin[2:0]) +); + +// compare logic for fifo empth and read enable signals +// ---------------------------------------------------------------------------------- +assign fifo_empty = (w_addr_bin[2] == r_addr[2]) & (w_addr_bin[1:0] == r_addr[1:0]); +assign r_enable = read_ready & !fifo_empty; +assign rd_valid = !fifo_empty; + +assign r_data_out[1:0] = rd_valid ? r_data_in[1:0] : 2'b00; + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async/altr_hps_1r1w_4x2_rfifo_async_write.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async/altr_hps_1r1w_4x2_rfifo_async_write.v new file mode 100644 index 0000000..d1d7d77 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async/altr_hps_1r1w_4x2_rfifo_async_write.v @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module altr_hps_1r1w_4x2_rfifo_async_write ( + write_clk, + write_rst_n, + wr_valid, + w_data, + write_ready, + w_addr_gray_out, + + r_addr, + r_addr_gray_in, + r_data + ); + +// General inputs and outputs +// ---------------------------------------------------- +input write_clk; +input write_rst_n; +input wr_valid; +output write_ready; // Tell the source device the fifo is ready to write +input [1:0] w_data; +output [2:0] w_addr_gray_out; // write pointer flop the gray code for write ponter + +input [1:0] r_addr; +output [1:0] r_data; +input [2:0] r_addr_gray_in; // write pointer flop the gray code for write ponter + +// ----------------------------------------------------------------------------------- +// WRITE SIDE LOGIC +// ----------------------------------------------------------------------------------- + +// Write side wire and reg definition +// ---------------------------------------------------- +reg [1:0] r_data; +reg [2:0] w_addr; // write pointer +wire [1:0] w_data; +wire [2:0] w_addr_gray; // write pointer gray code out +reg [2:0] w_addr_gray_out; // write pointer flop the gray code for write ponter +wire w_enable; // read enable +wire fifo_full; // fifo full + +// read side wire and reg definition +// ---------------------------------------------------- +wire [2:0] r_addr_gray_in; // read pointer gray code out +wire [2:0] r_addr_sync; // read pointer sync r_addr to write_clk +wire [2:0] r_addr_bin; // read pointer sync r_addr to write_clk + +// write counter increment when it is enabled +// ---------------------------------------------------- +always @(posedge write_clk or negedge write_rst_n) +begin + if (~write_rst_n) begin + w_addr[2:0] <= 3'd0; + end + else if (w_enable) begin + w_addr[2:0] <= w_addr[2:0] + 3'd1; + end +end + +//---------------------------------------------------- +altr_hps_bin2gray bin2gray_w( + .bin_in(w_addr[2:0]), + .gray_out(w_addr_gray[2:0]) +); + +// Flop out the w_addr_gray_out +// -------------------------------------------------- +always @(posedge write_clk or negedge write_rst_n) +begin + if (~write_rst_n) + w_addr_gray_out[2:0] <= 3'd0; + else + w_addr_gray_out[2:0] <= w_addr_gray[2:0]; +end + +// Read address synced by write clk (two flop synchronizer) +// ----------------------------------------------------- +altr_hps_bitsync + #(.DWIDTH(3),.RESET_VAL(0)) + r_pointer_sync ( + .clk(write_clk), + .rst_n(write_rst_n), + .data_in(r_addr_gray_in[2:0]), + .data_out(r_addr_sync[2:0]) + ); + +// defparam altr_hps_1r1w_4x2_rfifo_async_write.r_pointer_sync.DWIDTH=3'd3; +// defparam altr_hps_1r1w_4x2_rfifo_async_write.r_pointer_sync.RESET_VAL=1'd1; + +// gray to binary for read pointer +// --------------------------------------------------------- +altr_hps_gray2bin gray2bin_rp ( + .gray_in(r_addr_sync[2:0]), + .bin_out(r_addr_bin[2:0]) +); + +// generate the fifo full and write enable signals +// ---------------------------------------------------------------------------------- +assign fifo_full = (r_addr_bin[2] ^ w_addr[2]) & (r_addr_bin[1:0] == w_addr[1:0]); +assign w_enable = wr_valid & !fifo_full; +assign write_ready = !fifo_full; + +// ---------------------------------------------------------------------------------- +// define flop based memory 4x2 +// ---------------------------------------------------------------------------------- +reg [1:0] mem0; +reg [1:0] mem1; +reg [1:0] mem2; +reg [1:0] mem3; + +// write the data into memory (flop based) +// ---------------------------------------------------- +always @(posedge write_clk or negedge write_rst_n) +begin + if (~write_rst_n) begin + mem0[1:0] <= 2'd0; + mem1[1:0] <= 2'd0; + mem2[1:0] <= 2'd0; + mem3[1:0] <= 2'd0; + end + else if (w_enable) begin + case (w_addr[1:0]) + 2'b00 : mem0[1:0] <= w_data[1:0]; + 2'b01 : mem1[1:0] <= w_data[1:0]; + 2'b10 : mem2[1:0] <= w_data[1:0]; + 2'b11 : mem3[1:0] <= w_data[1:0]; + default : mem0[1:0] <= w_data[1:0]; + endcase + end +end + +// Read out the data (floped data) out +// ---------------------------------------------------- +always @(*) begin + case (r_addr[1:0]) + 2'b00 : r_data[1:0] = mem0[1:0]; + 2'b01 : r_data[1:0] = mem1[1:0]; + 2'b10 : r_data[1:0] = mem2[1:0]; + 2'b11 : r_data[1:0] = mem3[1:0]; + default: r_data[1:0] = 2'b00; + endcase +end + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async/altr_hps_bin2gray.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async/altr_hps_bin2gray.v new file mode 100644 index 0000000..182f819 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async/altr_hps_bin2gray.v @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module altr_hps_bin2gray ( + bin_in, + gray_out +); + +input [2:0] bin_in; +output [2:0] gray_out; +reg [2:0] gray_out; + +always @(*) +begin // 3 bit gray code + case(bin_in) + 3'b000 : gray_out = 3'b000; + 3'b001 : gray_out = 3'b001; + 3'b010 : gray_out = 3'b011; + 3'b011 : gray_out = 3'b010; + 3'b100 : gray_out = 3'b110; + 3'b101 : gray_out = 3'b111; + 3'b110 : gray_out = 3'b101; + 3'b111 : gray_out = 3'b100; + default: gray_out = 3'b000; + endcase +end + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async/altr_hps_gray2bin.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async/altr_hps_gray2bin.v new file mode 100644 index 0000000..8bcb9cb --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async/altr_hps_gray2bin.v @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module altr_hps_gray2bin ( + gray_in, + bin_out +); +input [2:0] gray_in; +output [2:0] bin_out; +reg [2:0] bin_out; + +always @(*) +begin // gray to binary converting + case(gray_in) + 3'b000: bin_out = 3'b000; + 3'b001: bin_out = 3'b001; + 3'b011: bin_out = 3'b010; + 3'b010: bin_out = 3'b011; + 3'b110: bin_out = 3'b100; + 3'b111: bin_out = 3'b101; + 3'b101: bin_out = 3'b110; + 3'b100: bin_out = 3'b111; + default:bin_out = 3'b000; + endcase +end +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async_read.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async_read.v new file mode 100644 index 0000000..95956c1 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async_read.v @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module altr_hps_1r1w_4x2_rfifo_async_read ( + read_clk, + read_rst_n, + read_ready, + r_data_in, + r_data_out, + w_addr_gray_in, + r_addr_out, + r_addr_gray_out, + rd_valid +); + +input read_clk; // read clock +input read_rst_n; // Read reset +input read_ready; // read device is ready for read +input [2:0] w_addr_gray_in; // write pointer gray code in +output rd_valid; // read data valid +output [2:0] r_addr_gray_out; // read pointer gray code floped for de-glitches +output [1:0] r_addr_out; // read pointer gray code floped for de-glitches + +input [1:0] r_data_in; // the read data in +output [1:0] r_data_out; // read data just pass through but we can pipeline a flop if the timing issue + +// read side wire and reg definition +// ---------------------------------------------------- +wire [2:0] w_addr_gray_in; // write pointer gray code in +wire [2:0] w_addr_sync; // write pointer gray code in synchronized out +wire [2:0] w_addr_bin; // write pointer synced binary out +reg [2:0] r_addr; // read pointer +wire [2:0] r_addr_gray; // read pointer gray code +wire [1:0] r_addr_out; // read pointer gray code +reg [2:0] r_addr_gray_out; // read pointer gray code floped for de-glitches +wire r_enable; // read enable +wire fifo_empty; // fifo empty +wire rd_valid; // Output data valid +wire [1:0] r_data_in; // read pointer gray code floped for de-glitches +wire [1:0] r_data_out; // read pointer gray code floped for de-glitches + +//wire [1:0] r_data_out; // read data just pass through but we can add a flop if the timing issue + +assign r_addr_out[1:0] = r_addr[1:0]; + +// read counter increment when it is enabled +// ---------------------------------------------------- +always @(posedge read_clk or negedge read_rst_n) +begin + if (~read_rst_n) begin + r_addr[2:0] <= 3'd0; + end + else if (r_enable) begin + r_addr[2:0] <= r_addr[2:0] + 3'd1; + end +end + +// --------------------------------------------------------------------------------- +// READ SIDE LOGIC +// --------------------------------------------------------------------------------- + +//Using gray code +//---------------------------------------------------- +altr_hps_bin2gray bin2gray_r( + .bin_in(r_addr[2:0]), + .gray_out(r_addr_gray[2:0]) +); + +// Flop out the w_addr_gray_out +// -------------------------------------------------- +always @(posedge read_clk or negedge read_rst_n) +begin + if (~read_rst_n) + r_addr_gray_out[2:0] <= 3'd0; + else + r_addr_gray_out[2:0] <= r_addr_gray[2:0]; +end + +altr_hps_bitsync + #(.DWIDTH(3),.RESET_VAL(0)) + w_pointer_sync ( + .clk(read_clk), + .rst_n(read_rst_n), + .data_in(w_addr_gray_in[2:0]), + .data_out(w_addr_sync[2:0]) + ); +// defparam altr_hps_1r1w_4x2_rfifo_async_read.w_pointer_sync.DWIDTH=3'd3; +// defparam altr_hps_1r1w_4x2_rfifo_async_read.w_pointer_sync.RESET_VAL=1'd0; + +// gray to binary for read pointer +// --------------------------------------------------------- +altr_hps_gray2bin gray2bin_wp ( + .gray_in(w_addr_sync[2:0]), + .bin_out(w_addr_bin[2:0]) +); + +// compare logic for fifo empth and read enable signals +// ---------------------------------------------------------------------------------- +assign fifo_empty = (w_addr_bin[2] == r_addr[2]) & (w_addr_bin[1:0] == r_addr[1:0]); +assign r_enable = read_ready & !fifo_empty; +assign rd_valid = !fifo_empty; + +assign r_data_out[1:0] = rd_valid ? r_data_in[1:0] : 2'b00; + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async_write.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async_write.v new file mode 100644 index 0000000..d1d7d77 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_1r1w_4x2_rfifo_async_write.v @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module altr_hps_1r1w_4x2_rfifo_async_write ( + write_clk, + write_rst_n, + wr_valid, + w_data, + write_ready, + w_addr_gray_out, + + r_addr, + r_addr_gray_in, + r_data + ); + +// General inputs and outputs +// ---------------------------------------------------- +input write_clk; +input write_rst_n; +input wr_valid; +output write_ready; // Tell the source device the fifo is ready to write +input [1:0] w_data; +output [2:0] w_addr_gray_out; // write pointer flop the gray code for write ponter + +input [1:0] r_addr; +output [1:0] r_data; +input [2:0] r_addr_gray_in; // write pointer flop the gray code for write ponter + +// ----------------------------------------------------------------------------------- +// WRITE SIDE LOGIC +// ----------------------------------------------------------------------------------- + +// Write side wire and reg definition +// ---------------------------------------------------- +reg [1:0] r_data; +reg [2:0] w_addr; // write pointer +wire [1:0] w_data; +wire [2:0] w_addr_gray; // write pointer gray code out +reg [2:0] w_addr_gray_out; // write pointer flop the gray code for write ponter +wire w_enable; // read enable +wire fifo_full; // fifo full + +// read side wire and reg definition +// ---------------------------------------------------- +wire [2:0] r_addr_gray_in; // read pointer gray code out +wire [2:0] r_addr_sync; // read pointer sync r_addr to write_clk +wire [2:0] r_addr_bin; // read pointer sync r_addr to write_clk + +// write counter increment when it is enabled +// ---------------------------------------------------- +always @(posedge write_clk or negedge write_rst_n) +begin + if (~write_rst_n) begin + w_addr[2:0] <= 3'd0; + end + else if (w_enable) begin + w_addr[2:0] <= w_addr[2:0] + 3'd1; + end +end + +//---------------------------------------------------- +altr_hps_bin2gray bin2gray_w( + .bin_in(w_addr[2:0]), + .gray_out(w_addr_gray[2:0]) +); + +// Flop out the w_addr_gray_out +// -------------------------------------------------- +always @(posedge write_clk or negedge write_rst_n) +begin + if (~write_rst_n) + w_addr_gray_out[2:0] <= 3'd0; + else + w_addr_gray_out[2:0] <= w_addr_gray[2:0]; +end + +// Read address synced by write clk (two flop synchronizer) +// ----------------------------------------------------- +altr_hps_bitsync + #(.DWIDTH(3),.RESET_VAL(0)) + r_pointer_sync ( + .clk(write_clk), + .rst_n(write_rst_n), + .data_in(r_addr_gray_in[2:0]), + .data_out(r_addr_sync[2:0]) + ); + +// defparam altr_hps_1r1w_4x2_rfifo_async_write.r_pointer_sync.DWIDTH=3'd3; +// defparam altr_hps_1r1w_4x2_rfifo_async_write.r_pointer_sync.RESET_VAL=1'd1; + +// gray to binary for read pointer +// --------------------------------------------------------- +altr_hps_gray2bin gray2bin_rp ( + .gray_in(r_addr_sync[2:0]), + .bin_out(r_addr_bin[2:0]) +); + +// generate the fifo full and write enable signals +// ---------------------------------------------------------------------------------- +assign fifo_full = (r_addr_bin[2] ^ w_addr[2]) & (r_addr_bin[1:0] == w_addr[1:0]); +assign w_enable = wr_valid & !fifo_full; +assign write_ready = !fifo_full; + +// ---------------------------------------------------------------------------------- +// define flop based memory 4x2 +// ---------------------------------------------------------------------------------- +reg [1:0] mem0; +reg [1:0] mem1; +reg [1:0] mem2; +reg [1:0] mem3; + +// write the data into memory (flop based) +// ---------------------------------------------------- +always @(posedge write_clk or negedge write_rst_n) +begin + if (~write_rst_n) begin + mem0[1:0] <= 2'd0; + mem1[1:0] <= 2'd0; + mem2[1:0] <= 2'd0; + mem3[1:0] <= 2'd0; + end + else if (w_enable) begin + case (w_addr[1:0]) + 2'b00 : mem0[1:0] <= w_data[1:0]; + 2'b01 : mem1[1:0] <= w_data[1:0]; + 2'b10 : mem2[1:0] <= w_data[1:0]; + 2'b11 : mem3[1:0] <= w_data[1:0]; + default : mem0[1:0] <= w_data[1:0]; + endcase + end +end + +// Read out the data (floped data) out +// ---------------------------------------------------- +always @(*) begin + case (r_addr[1:0]) + 2'b00 : r_data[1:0] = mem0[1:0]; + 2'b01 : r_data[1:0] = mem1[1:0]; + 2'b10 : r_data[1:0] = mem2[1:0]; + 2'b11 : r_data[1:0] = mem3[1:0]; + default: r_data[1:0] = 2'b00; + endcase +end + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_and.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_and.v new file mode 100644 index 0000000..d09c7c6 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_and.v @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: standard and gate +// +//------------------------------------------------------------------------ + +module altr_hps_and + ( + input wire and_in1, // and input 1 + input wire and_in2, // and input 2 + output wire and_out // and output + ); + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + assign and_out = and_in1 & and_in2; +`else + +`endif + +endmodule // altr_hps_and diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_bin2gray.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_bin2gray.v new file mode 100644 index 0000000..182f819 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_bin2gray.v @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module altr_hps_bin2gray ( + bin_in, + gray_out +); + +input [2:0] bin_in; +output [2:0] gray_out; +reg [2:0] gray_out; + +always @(*) +begin // 3 bit gray code + case(bin_in) + 3'b000 : gray_out = 3'b000; + 3'b001 : gray_out = 3'b001; + 3'b010 : gray_out = 3'b011; + 3'b011 : gray_out = 3'b010; + 3'b100 : gray_out = 3'b110; + 3'b101 : gray_out = 3'b111; + 3'b110 : gray_out = 3'b101; + 3'b111 : gray_out = 3'b100; + default: gray_out = 3'b000; + endcase +end + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_bitsync.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_bitsync.v new file mode 100644 index 0000000..602060f --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_bitsync.v @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: 28-nm standard cell harden FF synchronizer +// +// Note on RESET_VAL: +// if a "set" or "reset" type synchronizer should be used. If RESET_VAL evaluates +// to zero, a reset type synchronizer is chosen. All other values of RESET_VAL +// will lead to a set type synchronizer +// +// when multi-bit crossing is required (note: async handshake macros are also available and is +// usually recommended for multi-bit CDC - ensure your use case is fine with double-synchronizers +// if you choose this macro) +// +// However, choosing this method excludes 1 use case: There's is no mechanism to choose individual +// reset value for each bit of a multi-bit signal through this macro. e.g: RESET_VAL == 3'b101 is +// not supported. It is assumed that this use case is not required for users of this macro +// +//------------------------------------------------------------------------ + +module altr_hps_bitsync + #( + parameter DWIDTH = 1'b1, // Sync Data input + //parameter SYNCSTAGE = 2, // Sync stages + parameter RESET_VAL = 1'b0 // Reset value + ) + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire [DWIDTH-1:0] data_in, // data in + output wire [DWIDTH-1:0] data_out // data out + ); + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + + // End users may pass in RESET_VAL with a width exceeding 1 bit + // Evaluate the value first and use 1 bit value + localparam RESET_VAL_1B = (RESET_VAL == 'd0) ? 1'b0 : 1'b1; + + reg [DWIDTH-1:0] dff2; + reg [DWIDTH-1:0] dff1; + + always @(posedge clk or negedge rst_n) + if (!rst_n) begin + dff2 <= {DWIDTH{RESET_VAL_1B}}; + dff1 <= {DWIDTH{RESET_VAL_1B}}; + end + else begin + dff2 <= dff1; + dff1 <= data_in; + end + + // data_out has to be a wire since it needs to also hook up to the TSMC cell + assign data_out = dff2; + +`else + + +`endif + +endmodule // altr_hps_bitsync + diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_bitsync4.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_bitsync4.v new file mode 100644 index 0000000..c53897a --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_bitsync4.v @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: 28-nm standard cell harden FF synchronizer. +// synchronizer with 4 flop stages. +// +// Note on RESET_VAL: +// if a "set" or "reset" type synchronizer should be used. If RESET_VAL evaluates +// to zero, a reset type synchronizer is chosen. All other values of RESET_VAL +// will lead to a set type synchronizer +// +// when multi-bit crossing is required (note: async handshake macros are also available and is +// usually recommended for multi-bit CDC - ensure your use case is fine with double-synchronizers +// if you choose this macro) +// +// However, choosing this method excludes 1 use case: There's is no mechanism to choose individual +// reset value for each bit of a multi-bit signal through this macro. e.g: RESET_VAL == 3'b101 is +// not supported. It is assumed that this use case is not required for users of this macro +// +//------------------------------------------------------------------------ + +module altr_hps_bitsync4 + #( + parameter DWIDTH = 1'b1, // Sync Data input + //parameter SYNCSTAGE = 4, // Sync stages + parameter RESET_VAL = 1'b0 // Reset value + ) + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire [DWIDTH-1:0] data_in, // data in + output wire [DWIDTH-1:0] data_out // data out + ); + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + + // End users may pass in RESET_VAL with a width exceeding 1 bit + // Evaluate the value first and use 1 bit value + localparam RESET_VAL_1B = (RESET_VAL == 'd0) ? 1'b0 : 1'b1; + + reg [DWIDTH-1:0] dff4; + reg [DWIDTH-1:0] dff3; + reg [DWIDTH-1:0] dff2; + reg [DWIDTH-1:0] dff1; + + always @(posedge clk or negedge rst_n) + if (!rst_n) begin + dff4 <= {DWIDTH{RESET_VAL_1B}}; + dff3 <= {DWIDTH{RESET_VAL_1B}}; + dff2 <= {DWIDTH{RESET_VAL_1B}}; + dff1 <= {DWIDTH{RESET_VAL_1B}}; + end + else begin + dff4 <= dff3; + dff3 <= dff2; + dff2 <= dff1; + dff1 <= data_in; + end + + // data_out has to be a wire since it needs to also hook up to the TSMC cell + assign data_out = dff4; + +`else +`endif + +endmodule // altr_hps_bitsync4 + diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_bitsync_generator.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_bitsync_generator.v new file mode 100644 index 0000000..03db56b --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_bitsync_generator.v @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// � 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: BITSYNC Generator +// +// multi-bit signal through this macro, e.g: RESET == 3'b101 is supported +// Due to this is not supported on normal bitsync macro. +// +//------------------------------------------------------------------------ + + +module altr_hps_bitsync_generator #( parameter DWIDTH = 1, parameter [DWIDTH-1:0] RESET_VAL = 'd0 ) +( + input wire clk, //clock + input wire rst_n, //async reset + input wire [DWIDTH-1:0] data_in, //data in + output wire [DWIDTH-1:0] data_out //data out +); + +genvar i; + +generate + for(i = 0; i < DWIDTH; i=i+1) + begin: bit_sync_i + if(RESET_VAL[i] == 1'b0) + begin + altr_hps_bitsync #(.DWIDTH(1), .RESET_VAL(1'b0) ) bitsync_clr_inst ( + .clk(clk), + .rst_n(rst_n), + .data_in(data_in[i]), + .data_out(data_out[i]) + ); + end + else + begin + altr_hps_bitsync #(.DWIDTH(1), .RESET_VAL(1'b1) ) bitsync_pst_inst ( + .clk(clk), + .rst_n(rst_n), + .data_in(data_in[i]), + .data_out(data_out[i]) + ); + end + end //end for +endgenerate // endgenerate + +endmodule // altr_hps_bitsync_generator diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_buf.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_buf.v new file mode 100644 index 0000000..47a13e6 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_buf.v @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// 20(C)11 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: standard clock buf +// +// A simple clock buffer. +// Use this as a convenient point for clock definition for internally generated clocks +// All "create_clock" commands can then refer to this buffer +// +//------------------------------------------------------------------------ + +module altr_hps_buf ( + input wire buf_in, // clock input + output wire buf_out // clock output +); + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + assign buf_out = buf_in; +`else +`endif + +endmodule // altr_hps_ckbuf diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckand.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckand.v new file mode 100644 index 0000000..ed1d692 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckand.v @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//----------------------------------------------------------------------------- +// Clock XOR macro +//----------------------------------------------------------------------------- + +module altr_hps_ckand ( + input wire and_in1, // and input 1 + input wire and_in2, // and input 2 + output wire and_out // and output +); + +// ------------------- +// Port declarations +// ------------------- + +wire and_out_n; + +// ----- +// RTL +// ----- + +`ifdef ALTR_HPS_INTEL_MACROS_OFF +assign and_out = and_in1 & and_in2; + +`else + + + + +`endif + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckand_gate.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckand_gate.v new file mode 100644 index 0000000..a16026b --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckand_gate.v @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//----------------------------------------------------------------------------- +// Clock XOR macro +//----------------------------------------------------------------------------- + +module altr_hps_ckand_gate ( + input wire and_clk, // and input 1 + input wire and_en, // and input 2 + output wire and_out // and output +); + +// ------------------- +// Port declarations +// ------------------- + +// ----- +// RTL +// ----- + +`ifdef ALTR_HPS_INTEL_MACROS_OFF +assign and_out = and_clk & and_en; + +`else + + + +`endif + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckbuf.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckbuf.v new file mode 100644 index 0000000..aa649f7 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckbuf.v @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: standard clock buf +// +// A simple clock buffer. +// Use this as a convenient point for clock definition for internally generated clocks +// All "create_clock" commands can then refer to this buffer +// +//------------------------------------------------------------------------ + +module altr_hps_ckbuf ( + input wire ck_in, // clock input + output wire ck_out // clock output +); + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + assign ck_out = ck_in; +`else + + +`endif + +endmodule // altr_hps_ckbuf diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckinv.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckinv.v new file mode 100644 index 0000000..45d9e01 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckinv.v @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//----------------------------------------------------------------------------- +// Clock inverter macro +//----------------------------------------------------------------------------- + +module altr_hps_ckinv ( + clk, + clk_inv +); + +// ------------------- +// Port declarations +// ------------------- + +input clk; +output clk_inv; + +// ----- +// RTL +// ----- + +`ifdef ALTR_HPS_INTEL_MACROS_OFF +assign clk_inv = !clk; + +`else + + + +`endif + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckmux21.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckmux21.v new file mode 100644 index 0000000..9bb957f --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckmux21.v @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: standard clock mux +// +//------------------------------------------------------------------------ + +module altr_hps_ckmux21 + ( + input wire clk_0, // clock 0 + input wire clk_1, // clock 1 + input wire clk_sel, // clock selector + output wire clk_o // clock out + ); + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + assign clk_o = clk_sel ? clk_1 : clk_0; +`else + +`endif + +endmodule // altr_hps_ckmux21 diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckmux32to1.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckmux32to1.v new file mode 100644 index 0000000..d721dea --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckmux32to1.v @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// � 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: standard 4:1 clock mux, built of three 2:1 muxes +// clk_sel = 00, clk_o = clk_0 +// clk_sel = 01, clk_o = clk_1 +// clk_sel = 10, clk_o = clk_2 +// clk_sel = 11, clk_o = clk_3 +//------------------------------------------------------------------------ + +module altr_hps_ckmux32to1 + ( + input wire [31:0] clk_i, + + input wire [4:0] clk_sel, // clock selector + output wire clk_o // clock out + ); + + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + + reg clk_o_reg; + + always @* + begin : clk_sel_mux + case(clk_sel[4:0]) + 5'b00000: clk_o_reg = clk_i[0]; + 5'b00001: clk_o_reg = clk_i[1]; + 5'b00010: clk_o_reg = clk_i[2]; + 5'b00011: clk_o_reg = clk_i[3]; + 5'b00100: clk_o_reg = clk_i[4]; + 5'b00101: clk_o_reg = clk_i[5]; + 5'b00110: clk_o_reg = clk_i[6]; + 5'b00111: clk_o_reg = clk_i[7]; + 5'b01000: clk_o_reg = clk_i[8]; + 5'b01001: clk_o_reg = clk_i[9]; + 5'b01010: clk_o_reg = clk_i[10]; + 5'b01011: clk_o_reg = clk_i[11]; + 5'b01100: clk_o_reg = clk_i[12]; + 5'b01101: clk_o_reg = clk_i[13]; + 5'b01110: clk_o_reg = clk_i[14]; + 5'b01111: clk_o_reg = clk_i[15]; + 5'b10000: clk_o_reg = clk_i[16]; + 5'b10001: clk_o_reg = clk_i[17]; + 5'b10010: clk_o_reg = clk_i[18]; + 5'b10011: clk_o_reg = clk_i[19]; + 5'b10100: clk_o_reg = clk_i[20]; + 5'b10101: clk_o_reg = clk_i[21]; + 5'b10110: clk_o_reg = clk_i[22]; + 5'b10111: clk_o_reg = clk_i[23]; + 5'b11000: clk_o_reg = clk_i[24]; + 5'b11001: clk_o_reg = clk_i[25]; + 5'b11010: clk_o_reg = clk_i[26]; + 5'b11011: clk_o_reg = clk_i[27]; + 5'b11100: clk_o_reg = clk_i[28]; + 5'b11101: clk_o_reg = clk_i[29]; + 5'b11110: clk_o_reg = clk_i[30]; + 5'b11111: clk_o_reg = clk_i[31]; + default: clk_o_reg = 1'bx; + endcase + end + + assign clk_o = clk_o_reg; + +`else + +`endif + +endmodule // altr_hps_ckmux32to1 diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckmux41.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckmux41.v new file mode 100644 index 0000000..1844b0c --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckmux41.v @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// � 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: standard 4:1 clock mux, built of three 2:1 muxes +// clk_sel = 00, clk_o = clk_0 +// clk_sel = 01, clk_o = clk_1 +// clk_sel = 10, clk_o = clk_2 +// clk_sel = 11, clk_o = clk_3 +//------------------------------------------------------------------------ + +module altr_hps_ckmux41 + ( + input wire clk_0, // clock 0 + input wire clk_1, // clock 1 + input wire clk_2, // clock 2 + input wire clk_3, // clock 3 + input wire [1:0] clk_sel, // clock selector + output wire clk_o // clock out + ); + + wire clk_mux_a; + wire clk_mux_b; + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + assign clk_mux_a = clk_sel[0] ? clk_1 : clk_0; + assign clk_mux_b = clk_sel[0] ? clk_3 : clk_2; + + assign clk_o = clk_sel[1] ? clk_mux_b : clk_mux_a; +`else + +`endif + +endmodule // altr_hps_ckmux41 diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_cknand.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_cknand.v new file mode 100644 index 0000000..a000803 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_cknand.v @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//----------------------------------------------------------------------------- +// Clock XOR macro +//----------------------------------------------------------------------------- + +module altr_hps_cknand ( + input wire nand_in1, // and input 1 + input wire nand_in2, // and input 2 + output wire nand_out // and output +); + +// ------------------- +// Port declarations +// ------------------- + +// ----- +// RTL +// ----- + +`ifdef ALTR_HPS_INTEL_MACROS_OFF +assign nand_out = ~(nand_in1 & nand_in2); + +`else + + +`endif + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_cknor.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_cknor.v new file mode 100644 index 0000000..b2e73c3 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_cknor.v @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//----------------------------------------------------------------------------- +// Clock OR macro +//----------------------------------------------------------------------------- + +module altr_hps_cknor ( + input wire nor_in1, // or input 1 + input wire nor_in2, // or input 2 + output wire nor_out // or output +); + +// ------------------- +// Port declarations +// ------------------- + +// ----- +// RTL +// ----- + +`ifdef ALTR_HPS_INTEL_MACROS_OFF +assign nor_out = ~(nor_in1 | nor_in2); + +`else + + +`endif + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckor.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckor.v new file mode 100644 index 0000000..336bf6d --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckor.v @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//----------------------------------------------------------------------------- +// Clock OR macro +//----------------------------------------------------------------------------- + +module altr_hps_ckor ( + input wire or_in1, // or input 1 + input wire or_in2, // or input 2 + output wire or_out // or output +); + +// ------------------- +// Port declarations +// ------------------- + +// ----- +// RTL +// ----- + +wire or_out_n; + +`ifdef ALTR_HPS_INTEL_MACROS_OFF +assign or_out = or_in1 | or_in2; + +`else + + + +`endif + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckor_gate.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckor_gate.v new file mode 100644 index 0000000..e3de0d4 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckor_gate.v @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//----------------------------------------------------------------------------- +// Clock OR macro +//----------------------------------------------------------------------------- + +module altr_hps_ckor_gate ( + input wire or_clk, // or input 1 + input wire or_en, // or input 2 + output wire or_out // or output +); + +// ------------------- +// Port declarations +// ------------------- + +// ----- +// RTL +// ----- + +`ifdef ALTR_HPS_INTEL_MACROS_OFF +assign or_out = or_clk | or_en; + +`else + + + +`endif + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_clkgate.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_clkgate.v new file mode 100644 index 0000000..ee71880 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_clkgate.v @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** +//----------------------------------------------------------------------------- +// Gated-clock cell model +//----------------------------------------------------------------------------- + + +module altr_hps_clkgate ( + clk, + clk_enable_i, + clk_o + ); + +input clk; +input clk_enable_i; + +output clk_o; + +reg clk_enable_lat; + +`ifdef ALTR_HPS_INTEL_MACROS_OFF +always @ (clk or clk_enable_i) + begin + if (~clk) + clk_enable_lat <= clk_enable_i; + end + +assign clk_o = clk & clk_enable_lat; + +`else + + +`endif +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_clkgate_or.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_clkgate_or.v new file mode 100644 index 0000000..a5fa7cb --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_clkgate_or.v @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//----------------------------------------------------------------------------- +// Clock gate using OR. +//----------------------------------------------------------------------------- +//Gates output clock to 1'b1 when clk_gate=1 +//Allows clk --> clk_o when clk_gate=0 + +module altr_hps_clkgate_or ( + clk, + clk_gate, + clk_o +); + +// ------------------- +// Port declarations +// ------------------- + +input clk; +input clk_gate; +output clk_o; + +// ----- +// RTL +// ----- + +`ifdef ALTR_HPS_INTEL_MACROS_OFF +//assign clk_o = clk | clk_gate; +//fixed behavioral model to match cgc81 +reg clk_enable_lat; + +always @ (clk or clk_gate) + begin + if (clk) + clk_enable_lat <= clk_gate; + end + +assign clk_o = clk | clk_enable_lat; + +`else + +`endif + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_cyc_dly.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_cyc_dly.v new file mode 100644 index 0000000..34e269f --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_cyc_dly.v @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//--------------------------------------------------------------------------------------- +// Description: delay the de-assertion edge of reset by parameterized delay. +// there is no delay for the assertion edge of reset. +// When reset is de-asserted, an internal counter counts up. When it counts +// to parameter value, dly_rst_n is de-asserted. +// +//--------------------------------------------------------------------------------------- + +module altr_hps_cyc_dly + ( + input wire clk, + input wire i_rst_n, + output reg dly_rst_n + ); + + parameter DLY = 'd8; + // counter size: + // counter counts from 0 to DLY-1, then saturates. minimum size should cover DLY-1. + // To be safe, counter size can cover DLY in case there is one run-over. + // e.g.: DLY = 2, counter size = 2 (instead of 1). DLY = 3, size = 3 (instead of 2) ; + // DLY =3~6, size =3. DLY=7~14, size=4... + // + parameter CNT_WIDTH = DLY > 'd1022 ? 'd11 : + DLY > 'd510 ? 'd10 : + DLY > 'd254 ? 'd9 : + DLY > 'd126 ? 'd8 : + DLY > 'd62 ? 'd7 : + DLY > 'd30 ? 'd6 : + DLY > 'd14 ? 'd5 : + DLY > 'd6 ? 'd4 : + DLY > 'd2 ? 'd3 : + DLY > 'd1 ? 'd2 : + 'd1; + +`ifdef ALTR_HPS_SIMULATION +initial // check parameters + begin + + if( DLY > 'd2046) + begin + $display("ERROR : %m : DELAY parameter is too big , MAX Value is 2046."); + $finish; + end + + if( DLY == 'd0) + begin + $display("ERROR : %m : DELAY parameter is 0, no need to instantiate this cell."); + $finish; + end + + end +`endif + + reg [CNT_WIDTH-1:0] dly_cntr; + wire cntr_reached = (dly_cntr >= (DLY-'d1)); + + + always @(posedge clk or negedge i_rst_n) + if (!i_rst_n) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + dly_cntr <= {(1+(CNT_WIDTH-1)){1'b0}}; + dly_rst_n <= 1'h0; + // End of automatics + end + else begin + dly_cntr <= cntr_reached ? + dly_cntr : + dly_cntr + { {CNT_WIDTH-1{1'b0}}, 1'b1 }; + dly_rst_n <= cntr_reached; + end + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_eccsync.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_eccsync.v new file mode 100644 index 0000000..f28c5d2 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_eccsync.v @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// +// Name : ECC Hand-shake Synchronizer + +module altr_hps_eccsync ( + input wire rst_n, // Reset (active low) + input wire clk, // Clock + input wire err, // Error interrupt (from ECC RAM, serr/derr) + input wire err_ack, // Error interrupt request (from System Manager) + output reg err_req // Error interrupt acknowledge (to GIC) +); + +// Declaration +localparam IDLE = 1'b0, + REQ = 1'b1; + +reg err_d, ack_d; +wire err_p, ack_p; + +// Positive edge detection +assign err_p = err & ~err_d; +assign ack_p = err_ack & ~ack_d; + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + err_d <= 1'b0; + ack_d <= 1'b0; + end + else begin + err_d <= err; + ack_d <= err_ack; + end + end + +// Hand-shake states +always @(posedge clk, negedge rst_n) begin + if (~rst_n) + err_req <= 1'b0; + else + case (err_req) + IDLE: err_req <= err_p & ~err_ack; + REQ : err_req <= ~ack_p; + default: err_req <= 1'bx; // simulation purpose + endcase +end + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_en_bitsync.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_en_bitsync.v new file mode 100644 index 0000000..60b7409 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_en_bitsync.v @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module altr_hps_en_bitsync +#( + parameter DWIDTH = 1, // Sync Data input + parameter RESET_VAL = 0 // Reset value + ) + ( + input clk, // clock + input rst_n, // async reset + input clk_en, // clock enable + input [DWIDTH-1:0] data_in, // data in + output [DWIDTH-1:0] data_out // data out + ); + +wire clk_o; + +altr_hps_clkgate clkgate ( + .clk (clk), + .clk_enable_i (clk_en), + .clk_o (clk_o) +); + +altr_hps_bitsync #( + .DWIDTH (DWIDTH), + .RESET_VAL (RESET_VAL) +) bitsync ( + .clk (clk_o), + .rst_n (rst_n), + .data_in (data_in), + .data_out (data_out) +); + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_en_bitsync4.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_en_bitsync4.v new file mode 100644 index 0000000..d71ee55 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_en_bitsync4.v @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module altr_hps_en_bitsync4 +#( + parameter DWIDTH = 1, // Sync Data input + parameter RESET_VAL = 0 // Reset value + ) + ( + input clk, // clock + input rst_n, // async reset + input clk_en, // clock enable + input [DWIDTH-1:0] data_in, // data in + output [DWIDTH-1:0] data_out // data out + ); + +wire clk_o; + +altr_hps_clkgate clkgate ( + .clk (clk), + .clk_enable_i (clk_en), + .clk_o (clk_o) +); + +altr_hps_bitsync4 #( + .DWIDTH (DWIDTH), + .RESET_VAL (RESET_VAL) +) bitsync ( + .clk (clk_o), + .rst_n (rst_n), + .data_in (data_in), + .data_out (data_out) +); + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_gltchfltr.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_gltchfltr.v new file mode 100644 index 0000000..1027f8b --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_gltchfltr.v @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// © 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: altr_hps_gltchfltr: +// Simple low cost in terms of gate single bit glitch filter. +// This macro is created for FPGA Manager as CB inputs could glitch. +// +// This macro assumes the input bits make transitions infrequently, +// such that the sampling window is large. It is best used for +// bits sampled in software or used as static configuration that +// changes every once in awhile. +// +// The design has 1 syncflop and 2 extra flops. There is a 3 bit +// counter which enables the output flop (4th flop) to be loaded +// every 8 clock cycles. The counter is reset if a transition +// occurs. So the din synchronized value must be stable for +// 8 clocks for the value to be propigated to the output. +// +//------------------------------------------------------------------------ + +module altr_hps_gltchfltr + #(parameter RESET_VAL = 'd0) ( // Reset value + + // src_clk domain signals. + input clk, + input rst_n, + + input wire din, // Async. input + output reg dout_clean // Synchronous output to clk. + // Glitch free output signal. + ); + +// signals +wire din_sync; +reg din_sync_r; +wire detect_transition; +wire dout_enable; +reg [ 2: 0] cntr; + + +altr_hps_bitsync #(.DWIDTH(1), .RESET_VAL(RESET_VAL)) gltchfltr_sync ( + .clk(clk), + .rst_n(rst_n), + .data_in(din), + .data_out(din_sync) +); + +// 2 extra flops +always @(posedge clk or negedge rst_n) begin + if (~rst_n) begin + + din_sync_r <= RESET_VAL; + dout_clean <= RESET_VAL; + + end else begin + + din_sync_r <= din_sync; + + if (dout_enable) begin + dout_clean <= din_sync_r; + end + + end +end + +// Transition when bits are not equal (xor) +assign detect_transition = din_sync ^ din_sync_r; + +// Enable output flop only when count is equal to 3'b111 and not transition. +assign dout_enable = (cntr == 3'b111) & ~detect_transition; + +// 3 bit counter for 8 stable clocks without a transition. +always @(posedge clk or negedge rst_n) begin + if (~rst_n) begin + + cntr <= 3'd0; + + end else begin + + cntr <= detect_transition ? 3'd0: cntr + 3'd1; + + end +end + + +endmodule + + + diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_gltchfltr_vec.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_gltchfltr_vec.v new file mode 100644 index 0000000..42b2880 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_gltchfltr_vec.v @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// © 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: altr_hps_gltchfltr_vec: +// +// This is a vector version of altr_hps_gltchfltr +// Notable differences are: +// Parameterized width: DWIDTH +// Parameterized counter value: COUNT +// Parameterized behavior: RELOAD +// +// Some notable behavioral differences with altr_hps_gltchfltr: +// RESET_VAL is evaluated and used the same way as altr_hps_bitsync +// This doesn't matter to altr_hps_gltchfltr since it's 1 bit +// but it matters to this due to the multiple bit requirement +// +// How often a new dout_clean is registered can be changed +// using the RELOAD parameter: +// RELOAD == 0 : Load a new dout_clean once the deglitching count reaches +// COUNT. Always recirculate old value otherwise. +// RELOAD == 1 : Load a new dout_clean every COUNT clocks - regardless +// of the fact that din never changed +// This matches altr_hps_gltchfltr behavior +// +// The following comment come from altr_hps_gltchfltr +// Simple low cost in terms of gate single bit glitch filter. +// This macro is created for FPGA Manager as CB inputs could glitch. +// +// This macro assumes the input bits make transitions infrequently, +// such that the sampling window is large. It is best used for +// bits sampled in software or used as static configuration that +// changes every once in awhile. +// +// The design has 1 syncflop and 2 extra flops. There is a 3 bit +// counter which enables the output flop (4th flop) to be loaded +// every 8 clock cycles. The counter is reset if a transition +// occurs. So the din synchronized value must be stable for +// 8 clocks for the value to be propigated to the output. +// +//------------------------------------------------------------------------ + +module altr_hps_gltchfltr_vec + #(parameter RESET_VAL = 'd0, // Reset value + parameter DWIDTH = 'd2, + parameter COUNT = 'd8, + parameter RELOAD = 'd1 ) ( + + // src_clk domain signals. + input clk, + input rst_n, + + input wire [DWIDTH-1:0] din, // Async. input + output reg [DWIDTH-1:0] dout_clean // Synchronous output to clk. + // Glitch free output signal. + ); + +function integer clog2; + input [31:0] value; // Input variable + for (clog2=0; value>0; clog2=clog2+1) + value = value>>'d1; +endfunction + +localparam FULL = COUNT - 'd1; +localparam CWIDTH = clog2(FULL); + +// The reset methodology will follow altr_hps_bitsync +localparam RESET_VAL_1B = (RESET_VAL == 'd0) ? 1'b0 : 1'b1; + +// signals +wire [DWIDTH-1:0] din_sync; +reg [DWIDTH-1:0] din_sync_r; +wire detect_transition; +wire dout_enable; +wire deglitching; +reg [CWIDTH-1:0] cntr; + + +altr_hps_bitsync #(.DWIDTH(DWIDTH), .RESET_VAL(RESET_VAL)) gltchfltr_sync ( + .clk(clk), + .rst_n(rst_n), + .data_in(din), + .data_out(din_sync) +); + +// 2 extra flops per bit +always @(posedge clk or negedge rst_n) begin + if (~rst_n) begin + + din_sync_r <= {DWIDTH{RESET_VAL_1B}}; + dout_clean <= {DWIDTH{RESET_VAL_1B}}; + + end else begin + + din_sync_r <= din_sync; + + if (dout_enable) begin + dout_clean <= din_sync_r; + end + + end +end + +// Transition when bits are not equal (xor) +assign detect_transition = |(din_sync ^ din_sync_r); + +// RELOAD == 1 causes it's behavior to match with altr_hps_gltchfltr +assign deglitching = (RELOAD == 'd1 ) ? 1'b1 : ( |(din_sync ^ dout_clean) ); + +// Enable output flop only when count is equal to 3'b111 and not transition. +assign dout_enable = (cntr == FULL) & ~detect_transition; + +// 3 bit counter for 8 stable clocks without a transition. +always @(posedge clk or negedge rst_n) begin + if (~rst_n) begin + + cntr <= {CWIDTH{1'b0}}; + + end else begin + + // Some seriously long cascaded muxes + cntr <= deglitching ? ( detect_transition ? {CWIDTH{1'b0}} : (cntr == FULL) ? {CWIDTH{1'b0}} : cntr + {{CWIDTH-1{1'b0}}, 1'b1} ) : {CWIDTH{1'b0}}; + + // Here's what it means + // if (deglitching) -- it means a new input is sampled and is different from current output + // if (detect_transition) -- 1 pulse signal indicating a change in the synchronized input + // -- detect_transition pulses when a new input is sampled and will also pulse if the input changes again while deglitching + // reset counter to zero + // else if (counter == FULL) -- has the counter his FULL count yet? + // reset counter to zero + // else + // increment the counter + // else -- this "else" matches with "if (deglitching)" + // -- when deglitching is no longer required - reset the counter to zero + // reset counter to zero + + end + +end + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_gray2bin.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_gray2bin.v new file mode 100644 index 0000000..8bcb9cb --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_gray2bin.v @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +module altr_hps_gray2bin ( + gray_in, + bin_out +); +input [2:0] gray_in; +output [2:0] bin_out; +reg [2:0] bin_out; + +always @(*) +begin // gray to binary converting + case(gray_in) + 3'b000: bin_out = 3'b000; + 3'b001: bin_out = 3'b001; + 3'b011: bin_out = 3'b010; + 3'b010: bin_out = 3'b011; + 3'b110: bin_out = 3'b100; + 3'b111: bin_out = 3'b101; + 3'b101: bin_out = 3'b110; + 3'b100: bin_out = 3'b111; + default:bin_out = 3'b000; + endcase +end +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_gtie_generator.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_gtie_generator.v new file mode 100644 index 0000000..6b910f7 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_gtie_generator.v @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// � 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: GTIE Generator +// +// GTIE Generator takes a width and a constant values, and generates +// the necessary GTIEH and GTIEL instances to match. +// +//------------------------------------------------------------------------ + + +module altr_hps_gtie_generator #( + parameter TIE_WIDTH = 1, + parameter [TIE_WIDTH-1:0] TIE_VALUE = 'd0 + ) ( + output wire [TIE_WIDTH-1 : 0] z_out // output + ); + genvar i; + generate for(i = 0; i < TIE_WIDTH; i = i + 1) begin : gtie + + if (TIE_VALUE[i] == 1'b1) begin + // tie high + altr_hps_gtieh u_gtieh ( + .z_out (z_out[i]) + ); + end else begin + // tie low + altr_hps_gtiel u_gtiel ( + .z_out (z_out[i]) + ); + + end // if + end // for + + endgenerate // generate + +endmodule // altr_hps_gtie_generator diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_gtieh.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_gtieh.v new file mode 100644 index 0000000..630534f --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_gtieh.v @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: GTIEH cell +// +// GTIEH is a special "buffer" where the output polarity (1 or 0) can be changed +// at M2 layer +// +// GITEH will by default drive a constant "1" +// +//------------------------------------------------------------------------ + +module altr_hps_gtieh ( + output wire z_out // output +); + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + assign z_out = 1'b1; +`else +`endif + +endmodule // altr_hps_gtieh diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_gtiel.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_gtiel.v new file mode 100644 index 0000000..fda77b1 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_gtiel.v @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: GTIEL cell +// +// GTIEH is a special "buffer" where the output polarity (1 or 0) can be changed +// at M2 layer +// +// GITEL will by default drive a constant "0" +// +//------------------------------------------------------------------------ + +module altr_hps_gtiel ( + output wire z_out // output +); + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + assign z_out = 1'b0; +`else +`endif + +endmodule // altr_hps_gtiel diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_interface_register.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_interface_register.v new file mode 100644 index 0000000..c8d8035 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_interface_register.v @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: 28-nm standard cell harden FF synchronizer +// +// Note on RESET_VAL: +// if a "set" or "reset" type synchronizer should be used. If RESET_VAL evaluates +// to zero, a reset type synchronizer is chosen. All other values of RESET_VAL +// will lead to a set type synchronizer +// +// when multi-bit crossing is required (note: async handshake macros are also available and is +// usually recommended for multi-bit CDC - ensure your use case is fine with double-synchronizers +// if you choose this macro) +// +// However, choosing this method excludes 1 use case: There's is no mechanism to choose individual +// reset value for each bit of a multi-bit signal through this macro. e.g: RESET_VAL == 3'b101 is +// not supported. It is assumed that this use case is not required for users of this macro +// +//------------------------------------------------------------------------ + +module altr_hps_interface_register + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire test_ctrl, // test control + input wire scanen, // scan enable + input wire data_in, // data in + input wire scan_in, // scan in + output wire data_out // data out + ); + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + + reg dff1; + wire muxsel; + + assign muxsel = scanen | test_ctrl; + + + always @(posedge clk or negedge rst_n) + begin + if (!rst_n) + dff1 <= 1'b0; + else + dff1 <= muxsel ? scan_in : data_in; + end + assign data_out = dff1; + +`else + + +`endif + +endmodule // altr_hps_interface_register + diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_latch.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_latch.v new file mode 100644 index 0000000..57762e5 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_latch.v @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: altr_hps_latch: +// Active low transparent latch. +//------------------------------------------------------------------------ + +module altr_hps_latch( + d, // Latch input + q, // Latch output + e_n); // Enable + +input d, + e_n; +output q; + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + reg q; + + always @(e_n or d) + begin + if(~e_n) + q <= d; + end +`else +`endif + +endmodule // altr_hps_latch + + + diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_mux21.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_mux21.v new file mode 100644 index 0000000..c60dfad --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_mux21.v @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// © 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: standard 2 to 1 mux +// +//------------------------------------------------------------------------ + +module altr_hps_mux21 + ( + input wire mux_in0, // mux in 0 + input wire mux_in1, // mux in 1 + input wire mux_sel, // mux selector + output wire mux_out // mux out + ); + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + assign mux_out = mux_sel ? mux_in1 : mux_in0; +`else + +`endif + +endmodule // altr_hps_mux21 diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_mux41.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_mux41.v new file mode 100644 index 0000000..2049266 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_mux41.v @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// © 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: standard 4 to 1 mux +// +//------------------------------------------------------------------------ + +module altr_hps_mux41 + ( + input wire mux_in0, // mux in 0 + input wire mux_in1, // mux in 1 + input wire mux_in2, // mux in 1 + input wire mux_in3, // mux in 1 + input wire [1:0] mux_sel, // mux selector + output wire mux_out // mux out + ); + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + assign mux_out = mux_sel[1] ? + mux_sel[0] ? mux_in3 : mux_in2 : + mux_sel[0] ? mux_in1 : mux_in0; +`else +`endif + +endmodule // altr_hps_mux41 diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_nand3.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_nand3.v new file mode 100644 index 0000000..90187a8 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_nand3.v @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: standard nand4 gate +// +//------------------------------------------------------------------------ + +module altr_hps_nand3 + ( + input wire nand_in1, // and input 1 + input wire nand_in2, // and input 2 + input wire nand_in3, // and input 3 + output wire nand_out // and output + ); + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + assign nand_out = ~(nand_in1 & nand_in2 & nand_in3); +`else + +`endif + +endmodule // altr_hps_nand3 diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_nand4.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_nand4.v new file mode 100644 index 0000000..0c402f1 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_nand4.v @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: standard nand4 gate +// +//------------------------------------------------------------------------ + +module altr_hps_nand4 + ( + input wire nand_in1, // and input 1 + input wire nand_in2, // and input 2 + input wire nand_in3, // and input 3 + input wire nand_in4, // and input 4 + output wire nand_out // and output + ); + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + assign nand_out = ~(nand_in1 & nand_in2 & nand_in3 & nand_in4); +`else + +`endif + +endmodule // altr_hps_nand2 diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_nor2.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_nor2.v new file mode 100644 index 0000000..899cf92 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_nor2.v @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: standard nor2 gate +// +//------------------------------------------------------------------------ + +module altr_hps_nor2 + ( + input wire nor_in1, // and input 1 + input wire nor_in2, // and input 2 + output wire nor_out // and output + ); + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + assign nor_out = ~(nor_in1 | nor_in2); +`else +`endif + +endmodule // altr_hps_nor2 diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_nor3.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_nor3.v new file mode 100644 index 0000000..ff51b0a --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_nor3.v @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: standard nor2 gate +// +//------------------------------------------------------------------------ + +module altr_hps_nor3 + ( + input wire nor_in1, // and input 1 + input wire nor_in2, // and input 2 + input wire nor_in3, // and input 3 + output wire nor_out // and output + ); + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + assign nor_out = ~(nor_in1 | nor_in2 | nor_in3); +`else + +`endif + +endmodule // altr_hps_nor3 diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_or.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_or.v new file mode 100644 index 0000000..f1ba777 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_or.v @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//------------------------------------------------------------------------ +// Description: standard or gate +// +//------------------------------------------------------------------------ + +module altr_hps_or + ( + input wire or_in1, // and input 1 + input wire or_in2, // and input 2 + output wire or_out // or output + ); + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + assign or_out = or_in1 | or_in2; +`else +`endif + +endmodule // altr_hps_or diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_rstnsync.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_rstnsync.v new file mode 100644 index 0000000..5c05cc2 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_rstnsync.v @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//--------------------------------------------------------------------------------------- +// Description: For rst_n, asynchronously assertion and sychronously de-assertion (AASD) +// Assumptions: i_rst_n is assumed to be bypassed with scan_clk during scan_mode +//--------------------------------------------------------------------------------------- + +module altr_hps_rstnsync + ( + input wire clk, // Destination clock of reset to be synced + input wire i_rst_n, // Asynchronous reset input + input wire scan_mode, // Scan bypass for reset + output wire sync_rst_n // Synchronized reset output + + ); + + reg first_stg_rst_n; + wire prescan_sync_rst_n; + + always @(posedge clk or negedge i_rst_n) + if (!i_rst_n) + first_stg_rst_n <= 1'b0; + else + first_stg_rst_n <= 1'b1; + + altr_hps_bitsync + #(.DWIDTH(1), .RESET_VAL(0) ) + i_sync_rst_n + ( + .clk (clk ), + .rst_n (i_rst_n ), + .data_in (first_stg_rst_n ), + .data_out (prescan_sync_rst_n) + ); + + // Added scan bypass mux (Fogbugz #26486) + altr_hps_mux21 + i_rstsync_mux + ( + .mux_in0 (prescan_sync_rst_n), + .mux_in1 (i_rst_n), + .mux_sel (scan_mode), + .mux_out (sync_rst_n) + ); + + endmodule + diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_rstnsync4.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_rstnsync4.v new file mode 100644 index 0000000..986f825 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_rstnsync4.v @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +//--------------------------------------------------------------------------------------- +// Description: For rst_n, asynchronously assertion and sychronously de-assertion (AASD) +// +//--------------------------------------------------------------------------------------- + +module altr_hps_rstnsync4 + ( + input wire clk, + input wire i_rst_n, + input wire scan_mode, + output wire sync_rst_n + + ); + + reg first_stg_rst_n; + wire prescan_sync_rst_n; + + always @(posedge clk or negedge i_rst_n) + if (!i_rst_n) + first_stg_rst_n <= 1'b0; + else + first_stg_rst_n <= 1'b1; + + altr_hps_bitsync4 + #(.DWIDTH(1), .RESET_VAL(0) ) + i_sync_rst_n + ( + .clk (clk ), + .rst_n (i_rst_n ), + .data_in (first_stg_rst_n ), + .data_out (prescan_sync_rst_n) + ); + + // Added scan bypass mux (Fogbugz #26486) + altr_hps_mux21 + i_rstsync_mux + ( + .mux_in0 (prescan_sync_rst_n), + .mux_in1 (i_rst_n), + .mux_sel (scan_mode), + .mux_out (sync_rst_n) + ); + + endmodule + diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_sync_clr.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_sync_clr.v new file mode 100644 index 0000000..7f300b9 --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_sync_clr.v @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +// (C) 2001-2012 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + +//----------------------------------- +//2 stage flop synchronizer with AND clear +//DWIDTH | (this determine the width of the sync flop) +//The reset value is fixed to 1'b0 (not changeable) +//----------------------------------- + +module altr_hps_sync_clr +#(parameter DWIDTH='d1) +( + input clk, //main clk signal + input rst_n, //main reset signal + input clr, //active high clear signal (expected this clear signal to be quasi-static) + input [DWIDTH-1:0] data_in, //data in + output [DWIDTH-1:0] data_out //data out +); + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + +reg [DWIDTH-1:0] dff1; +reg [DWIDTH-1:0] dff2; + +always @(posedge clk or negedge rst_n) +begin + if(!rst_n) + begin + dff1 <= {DWIDTH{1'b0}}; + dff2 <= {DWIDTH{1'b0}}; + end + else + begin + dff1 <= data_in & ~clr; + dff2 <= dff1 & ~clr; + end +end + +assign data_out = dff2; + +`else + +`endif + +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_t2_register.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_t2_register.v new file mode 100644 index 0000000..468481f --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_t2_register.v @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** + +module altr_hps_t2_register + ( + input wire clk, // clock + input wire rst_n, // async reset + input wire scan_en, // scan enable + input wire data_in, // data in + input wire scan_in, // scan in + output wire data_out // data out + ); + +`ifdef ALTR_HPS_INTEL_MACROS_OFF + + reg dff1; + + always @(posedge clk or negedge rst_n) + begin + if (!rst_n) + dff1 <= 1'b0; + else + dff1 <= scan_en ? scan_in : data_in; + end + assign data_out = dff1; + +`else + + + + +`endif + +endmodule // altr_interface_register + diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_te_clkgate.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_te_clkgate.v new file mode 100644 index 0000000..c68da3d --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_te_clkgate.v @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//**************************************************************************************** +// (C) 2011 Altera Corporation. All rights reserved. +// +//**************************************************************************************** +//----------------------------------------------------------------------------- +// Gated-clock cell model +//----------------------------------------------------------------------------- + + +module altr_hps_te_clkgate ( + clk, + clk_enable_i, + test_enable_i, + clk_o + ); + +input clk; +input clk_enable_i; +input test_enable_i; + +output clk_o; + +reg clk_enable_lat; + +`ifdef ALTR_HPS_INTEL_MACROS_OFF +always @ (clk or clk_enable_i) + begin + if (~clk) + clk_enable_lat <= clk_enable_i; + end + +assign clk_o = clk & clk_enable_lat; + +`else + +`endif +endmodule diff --git a/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/soc_simulation_defines.v b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/soc_simulation_defines.v new file mode 100644 index 0000000..5d78ffb --- /dev/null +++ b/maib_rtl/soc_std_macro/rtl/block_function/i14socnd/soc_simulation_defines.v @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright (C) 2019 Intel Corporation. All rights reserved +//use functional RTL (no cells delay) for memory macro - intel +`define INTC_FUNCTIONAL + +//use fast-verilog model RTL for memory macro - synopsys +`define VIRAGE_FAST_VERILOG + +//use functional RTL (no cells delay) for std_cell +`define FUNCTIONAL + +//remove power ports from RTL macros +`define INTCNOPWR + +//use functional RTL (no cells delay) for ip734tsehv (temperature sensor) +`define functional + +//enforces STD_CELL MACRO to be always turned on +//`ifdef ALTR_HPS_INTEL_MACROS_OFF + //DO NOT COMPILE WITH TICK - ALTR_HPS_INTEL_MACROS_OFF +//`endif + +//enforces MEMORY macro to be always turn on +//`ifdef ALTR_HPS_MEMORY_OFF +// DO NOT COMPILE WITH TICK - ALTR_HPS_MEMORY_OFF +//`endif + +`timescale 1ns/1ps diff --git a/ndsimslv/README.txt b/ndsimslv/README.txt new file mode 100644 index 0000000..65a3dcb --- /dev/null +++ b/ndsimslv/README.txt @@ -0,0 +1,52 @@ +07/03/2019 + +============================================================ +Test bench(top.sv) description +============================================================ +c3aib c3aib_master and (CHIP AIB(aib) model or s10aib FPGA aib model) are instantiated in the test bench. the left side as master, the right side CHIP AIB model or s10aib as slave. +AS is illustrated below: + if S10_MODEL macro turn on rx_parallel_data will looped back to tx_parallel_data. + Two modes of operation are supported by macro REGISTER_MOD. + 1) if REGISTER_MOD on, FPGA side not using phasecom FIFO, lower speed, all 40 data bits are used. + 2) if REGISTER_MOD off, FPGA side is using phasecom FIFO at the half clock rate of master clock rate. 78 bit data width with alignment mark of bit 39/79. + + ------------ ----------- + random | | | |rx-->| + data tx---->| c3aib |<=========================>| s10aib | V (data loopback at FPGA fabric side) + | | | |tx<--| + data rx<----| | | | + checker | | | | + ----------- ----------- + master slave + + + + if S10_MODEL macro define not turn on, aib model is used at the slave side: + ------------ ----------- + random | | | |rx-->| + data tx---->| c3aib |<=========================>| aib | V (data loopback) + | | | |tx<--| + data rx<----| | | | + checker | | | |<---ms_nsl + ----------- ----------- (1'b0, slave) + master slave + + + +Random data will be sent out from the master to slave. The data will be looped back in the slave after it is received, then sent back to master. +The received data from the master will be compared with the data sent out. Test is pass when all the data match. + +This test bench is just an example for data transfer and checking. User can change the test bench, break the loop back on the slave, for independent simplex data transfer. + +c3aib and the CHIP AIB model in the test bench includes one channel. + +The following is the example of command to run simulation for different mode: + +1) master connect to s10 model in register mode. Typical usage is for AIB control channel for low latency low performance. +vcs -sverilog +v2k -full64 +vcs+vcdpluson -timescale=1ps/1ps +define+VCS+TIMESCALE_EN+ALTR_HPS_INTEL_MACROS_OFF+S10_MODEL+REGISTER_MOD -f ./multidie.f ./top.sv ./dut_io.sv ./test.sv -l compile.log + +2) master connect to s10 model in 1:2 phasecom FIFO mode. Typical usage is for AIB data channel for high bandwidth. +vcs -sverilog +v2k -full64 +vcs+vcdpluson -timescale=1ps/1ps +define+VCS+TIMESCALE_EN+ALTR_HPS_INTEL_MACROS_OFF+S10_MODEL -f ./multidie.f ./top.sv ./dut_io.sv ./test.sv -l compile.log + +3) master connect to AIB model. The model matches to AIB specification 1.1. +vcs -sverilog +v2k -full64 +vcs+vcdpluson -timescale=1ps/1ps +define+VCS+TIMESCALE_EN+ALTR_HPS_INTEL_MACROS_OFF -f ./multidie.f ./top.sv ./dut_io.sv ./test.sv -l compile.log diff --git a/ndsimslv/hdpldadapt.v b/ndsimslv/hdpldadapt.v deleted file mode 100644 index 087d883..0000000 --- a/ndsimslv/hdpldadapt.v +++ /dev/null @@ -1,763 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// Copyright (C) 2019 Intel Corporation. All rights reserved -module hdpldadapt -( - // AIB - input wire aib_fabric_avmm1_data_in, - input wire aib_fabric_avmm2_data_in, - input wire [4:0] aib_fabric_fpll_shared_direct_async_in, - input wire aib_fabric_fsr_data_in, - input wire aib_fabric_fsr_load_in, - //input wire aib_fabric_osc_dll_lock, - input wire aib_fabric_pld_8g_rxelecidle, - input wire aib_fabric_pld_pcs_rx_clk_out, - input wire aib_fabric_pld_pcs_tx_clk_out, - input wire aib_fabric_pld_pma_clkdiv_rx_user, - input wire aib_fabric_pld_pma_clkdiv_tx_user, - input wire aib_fabric_pld_pma_hclk, - input wire aib_fabric_pld_pma_internal_clk1, - input wire aib_fabric_pld_pma_internal_clk2, - input wire aib_fabric_pld_pma_pfdmode_lock, - input wire aib_fabric_pld_pma_rxpll_lock, - input wire aib_fabric_pld_rx_hssi_fifo_latency_pulse, - input wire aib_fabric_pld_tx_hssi_fifo_latency_pulse, - input wire aib_fabric_pma_aib_tx_clk, - input wire [39:0] aib_fabric_rx_data_in, - input wire aib_fabric_rx_dll_lock, - input wire aib_fabric_rx_sr_clk_in, - input wire aib_fabric_rx_transfer_clk, - input wire aib_fabric_ssr_data_in, - input wire aib_fabric_ssr_load_in, - input wire aib_fabric_tx_dcd_cal_done, - input wire aib_fabric_tx_sr_clk_in, - - // Adapter - //input wire bond_rx_asn_ds_in_dll_lock_en, - input wire bond_rx_asn_ds_in_fifo_hold, - //input wire bond_rx_asn_ds_in_gen3_sel, - //input wire bond_rx_asn_us_in_dll_lock_en, - input wire bond_rx_asn_us_in_fifo_hold, - //input wire bond_rx_asn_us_in_gen3_sel, - input wire bond_rx_fifo_ds_in_rden, - input wire bond_rx_fifo_ds_in_wren, - input wire bond_rx_fifo_us_in_rden, - input wire bond_rx_fifo_us_in_wren, - input wire bond_rx_hrdrst_ds_in_fabric_rx_dll_lock, - input wire bond_rx_hrdrst_us_in_fabric_rx_dll_lock, - input wire bond_rx_hrdrst_ds_in_fabric_rx_dll_lock_req, - input wire bond_rx_hrdrst_us_in_fabric_rx_dll_lock_req, - input wire bond_tx_fifo_ds_in_dv, - input wire bond_tx_fifo_ds_in_rden, - input wire bond_tx_fifo_ds_in_wren, - input wire bond_tx_fifo_us_in_dv, - input wire bond_tx_fifo_us_in_rden, - input wire bond_tx_fifo_us_in_wren, - input wire bond_tx_hrdrst_ds_in_fabric_tx_dcd_cal_done, - input wire bond_tx_hrdrst_us_in_fabric_tx_dcd_cal_done, - input wire bond_tx_hrdrst_ds_in_fabric_tx_dcd_cal_req, - input wire bond_tx_hrdrst_us_in_fabric_tx_dcd_cal_req, - - // Config - input wire [2:0] csr_config, - input wire csr_clk_in, - input wire [2:0] csr_in, - input wire [2:0] csr_pipe_in, - input wire csr_rdy_dly_in, - input wire csr_rdy_in, - input wire nfrzdrv_in, - input wire usermode_in, - - // PLD - input wire [3:0] hip_aib_fsr_in, - input wire [39:0] hip_aib_ssr_in, - input wire hip_avmm_read, - input wire [20:0] hip_avmm_reg_addr, - input wire hip_avmm_write, - input wire [7:0] hip_avmm_writedata, - input wire pld_10g_krfec_rx_clr_errblk_cnt, - input wire pld_10g_rx_align_clr, - input wire pld_10g_rx_clr_ber_count, - input wire [6:0] pld_10g_tx_bitslip, - input wire pld_10g_tx_burst_en, - input wire [1:0] pld_10g_tx_diag_status, - input wire pld_10g_tx_wordslip, - input wire pld_8g_a1a2_size, - input wire pld_8g_bitloc_rev_en, - input wire pld_8g_byte_rev_en, - input wire [2:0] pld_8g_eidleinfersel, - input wire pld_8g_encdt, - input wire [4:0] pld_8g_tx_boundary_sel, - input wire pld_adapter_rx_pld_rst_n, - input wire pld_adapter_tx_pld_rst_n, - //input wire pld_atpg_los_en_n, - input wire pld_avmm1_clk_rowclk, - input wire pld_avmm1_read, - input wire [9:0] pld_avmm1_reg_addr, - input wire pld_avmm1_request, - input wire pld_avmm1_write, - input wire [7:0] pld_avmm1_writedata, - input wire [8:0] pld_avmm1_reserved_in, - input wire pld_avmm2_clk_rowclk, - input wire pld_avmm2_read, - input wire [8:0] pld_avmm2_reg_addr, - input wire pld_avmm2_request, - input wire pld_avmm2_write, - input wire [7:0] pld_avmm2_writedata, - input wire [9:0] pld_avmm2_reserved_in, - input wire pld_bitslip, - input wire [1:0] pld_fpll_shared_direct_async_in, - input wire pld_fpll_shared_direct_async_in_rowclk, - input wire pld_fpll_shared_direct_async_in_dcm, - input wire pld_ltr, - //input wire pld_mem_atpg_rst_n, - input wire pr_channel_freeze_n, - input wire pld_pcs_rx_pld_rst_n, - input wire pld_pcs_tx_pld_rst_n, - input wire pld_pma_adapt_start, - input wire pld_pma_coreclkin_rowclk, - input wire pld_pma_csr_test_dis, - input wire pld_pma_early_eios, - input wire [5:0] pld_pma_eye_monitor, - input wire [3:0] pld_pma_fpll_cnt_sel, - input wire pld_pma_fpll_extswitch, - input wire pld_pma_fpll_lc_csr_test_dis, - input wire [2:0] pld_pma_fpll_num_phase_shifts, - input wire pld_pma_fpll_pfden, - input wire pld_pma_fpll_up_dn_lc_lf_rstn, - input wire pld_pma_ltd_b, - input wire pld_pma_nrpi_freeze, - input wire [1:0] pld_pma_pcie_switch, - input wire pld_pma_ppm_lock, - input wire [4:0] pld_pma_reserved_out, - input wire pld_pma_rs_lpbk_b, - input wire pld_pma_rxpma_rstb, - input wire pld_pma_tx_bitslip, - input wire pld_pma_txdetectrx, - input wire pld_pma_txpma_rstb, - input wire pld_pmaif_rxclkslip, - input wire pld_polinv_rx, - input wire pld_polinv_tx, - input wire pld_rx_clk1_rowclk, - input wire pld_rx_clk2_rowclk, -// input wire pld_rx_dll_lock_request, - input wire pld_rx_dll_lock_req, - input wire pld_rx_fabric_fifo_align_clr, - input wire pld_rx_fabric_fifo_rd_en, - input wire pld_rx_prbs_err_clr, - //input wire pld_scan_mode_n, - //input wire pld_scan_shift_n, - input wire pld_sclk1_rowclk, - input wire pld_sclk2_rowclk, - input wire pld_syncsm_en, - input wire pld_tx_clk1_rowclk, - input wire pld_tx_clk2_rowclk, -// input wire pld_tx_dll_lock_request, - input wire [79:0] pld_tx_fabric_data_in, - input wire pld_txelecidle, - input wire pld_tx_dll_lock_req, - input wire pld_tx_fifo_latency_adj_en, - input wire pld_rx_fifo_latency_adj_en, - input wire pld_aib_fabric_rx_dll_lock_req, - input wire pld_aib_fabric_tx_dcd_cal_req, - input wire pld_aib_hssi_tx_dcd_cal_req, - input wire pld_aib_hssi_tx_dll_lock_req, - input wire pld_aib_hssi_rx_dcd_cal_req, - input wire [2:0] pld_tx_ssr_reserved_in, - input wire [1:0] pld_rx_ssr_reserved_in, - input wire pld_pma_tx_qpi_pulldn, - input wire pld_pma_tx_qpi_pullup, - input wire pld_pma_rx_qpi_pullup, - - // PLD DCM - //input wire pld_pma_coreclkin_dcm, - input wire pld_rx_clk1_dcm, - //input wire pld_rx_clk2_dcm, - input wire pld_tx_clk1_dcm, - input wire pld_tx_clk2_dcm, - - // uC AVMM - - // DFT - input wire dft_adpt_aibiobsr_fastclkn, - input wire adapter_scan_rst_n, - input wire adapter_scan_mode_n, - input wire adapter_scan_shift_n, - input wire adapter_scan_shift_clk, - input wire adapter_scan_user_clk0, // 125MHz - input wire adapter_scan_user_clk1, // 250MHz - input wire adapter_scan_user_clk2, // 500MHz - input wire adapter_scan_user_clk3, // 1GHz - input wire adapter_clk_sel_n, - input wire adapter_occ_enable, - input wire adapter_global_pipe_se, - input wire [3:0] adapter_config_scan_in, - input wire [1:0] adapter_scan_in_occ1, - input wire [4:0] adapter_scan_in_occ2, - input wire adapter_scan_in_occ3, - input wire adapter_scan_in_occ4, - input wire [1:0] adapter_scan_in_occ5, - input wire [10:0] adapter_scan_in_occ6, - input wire adapter_scan_in_occ7, - input wire adapter_scan_in_occ8, - input wire adapter_scan_in_occ9, - input wire adapter_scan_in_occ10, - input wire adapter_scan_in_occ11, - input wire adapter_scan_in_occ12, - input wire adapter_scan_in_occ13, - input wire adapter_scan_in_occ14, - input wire adapter_scan_in_occ15, - input wire adapter_scan_in_occ16, - input wire adapter_scan_in_occ17, - input wire [1:0] adapter_scan_in_occ18, - input wire adapter_scan_in_occ19, - input wire adapter_scan_in_occ20, - input wire [1:0] adapter_scan_in_occ21, - input wire adapter_non_occ_scan_in, - input wire adapter_occ_scan_in, - input wire [2:0] dft_fabric_iaibdftcore2dll, - input wire [12:0] oaibdftdll2core, - - - // DFT - output wire [3:0] adapter_config_scan_out, - output wire [1:0] adapter_scan_out_occ1, - output wire [4:0] adapter_scan_out_occ2, - output wire adapter_scan_out_occ3, - output wire adapter_scan_out_occ4, - output wire [1:0] adapter_scan_out_occ5, - output wire [10:0] adapter_scan_out_occ6, - output wire adapter_scan_out_occ7, - output wire adapter_scan_out_occ8, - output wire adapter_scan_out_occ9, - output wire adapter_scan_out_occ10, - output wire adapter_scan_out_occ11, - output wire adapter_scan_out_occ12, - output wire adapter_scan_out_occ13, - output wire adapter_scan_out_occ14, - output wire adapter_scan_out_occ15, - output wire adapter_scan_out_occ16, - output wire adapter_scan_out_occ17, - output wire [1:0] adapter_scan_out_occ18, - output wire adapter_scan_out_occ19, - output wire adapter_scan_out_occ20, - output wire [1:0] adapter_scan_out_occ21, - output wire adapter_non_occ_scan_out, - output wire adapter_occ_scan_out, - output wire [2:0] iaibdftcore2dll, - output wire [12:0] dft_fabric_oaibdftdll2core, - - // AIB - output wire aib_fabric_csr_rdy_dly_in, - output wire aib_fabric_adapter_rx_pld_rst_n, - output wire aib_fabric_adapter_tx_pld_rst_n, - output wire [1:0] aib_fabric_avmm1_data_out, - output wire [1:0] aib_fabric_avmm2_data_out, - output wire [2:0] aib_fabric_fpll_shared_direct_async_out, - output wire aib_fabric_fsr_data_out, - output wire aib_fabric_fsr_load_out, - output wire aib_fabric_pcs_rx_pld_rst_n, - output wire aib_fabric_pcs_tx_pld_rst_n, - output wire aib_fabric_pld_pma_coreclkin, - output wire aib_fabric_pld_pma_rxpma_rstb, - output wire aib_fabric_pld_pma_txdetectrx, - output wire aib_fabric_pld_pma_txpma_rstb, - output wire aib_fabric_pld_sclk, - output wire aib_fabric_rx_dll_lock_req, - output wire aib_fabric_ssr_data_out, - output wire aib_fabric_ssr_load_out, - output wire [39:0] aib_fabric_tx_data_out, - output wire aib_fabric_tx_dcd_cal_req, - output wire aib_fabric_tx_sr_clk_out, - output wire aib_fabric_tx_transfer_clk, - output wire [7:0] r_aib_csr_ctrl_0, - output wire [7:0] r_aib_csr_ctrl_1, - output wire [7:0] r_aib_csr_ctrl_10, - output wire [7:0] r_aib_csr_ctrl_11, - output wire [7:0] r_aib_csr_ctrl_12, - output wire [7:0] r_aib_csr_ctrl_13, - output wire [7:0] r_aib_csr_ctrl_14, - output wire [7:0] r_aib_csr_ctrl_15, - output wire [7:0] r_aib_csr_ctrl_16, - output wire [7:0] r_aib_csr_ctrl_17, - output wire [7:0] r_aib_csr_ctrl_18, - output wire [7:0] r_aib_csr_ctrl_19, - output wire [7:0] r_aib_csr_ctrl_2, - output wire [7:0] r_aib_csr_ctrl_20, - output wire [7:0] r_aib_csr_ctrl_21, - output wire [7:0] r_aib_csr_ctrl_22, - output wire [7:0] r_aib_csr_ctrl_23, - output wire [7:0] r_aib_csr_ctrl_24, - output wire [7:0] r_aib_csr_ctrl_25, - output wire [7:0] r_aib_csr_ctrl_26, - output wire [7:0] r_aib_csr_ctrl_27, - output wire [7:0] r_aib_csr_ctrl_28, - output wire [7:0] r_aib_csr_ctrl_29, - output wire [7:0] r_aib_csr_ctrl_3, - output wire [7:0] r_aib_csr_ctrl_30, - output wire [7:0] r_aib_csr_ctrl_31, - output wire [7:0] r_aib_csr_ctrl_32, - output wire [7:0] r_aib_csr_ctrl_33, - output wire [7:0] r_aib_csr_ctrl_34, - output wire [7:0] r_aib_csr_ctrl_35, - output wire [7:0] r_aib_csr_ctrl_36, - output wire [7:0] r_aib_csr_ctrl_37, - output wire [7:0] r_aib_csr_ctrl_38, - output wire [7:0] r_aib_csr_ctrl_39, - output wire [7:0] r_aib_csr_ctrl_4, - output wire [7:0] r_aib_csr_ctrl_40, - output wire [7:0] r_aib_csr_ctrl_41, - output wire [7:0] r_aib_csr_ctrl_42, - output wire [7:0] r_aib_csr_ctrl_43, - output wire [7:0] r_aib_csr_ctrl_44, - output wire [7:0] r_aib_csr_ctrl_45, - output wire [7:0] r_aib_csr_ctrl_46, - output wire [7:0] r_aib_csr_ctrl_47, - output wire [7:0] r_aib_csr_ctrl_48, - output wire [7:0] r_aib_csr_ctrl_49, - output wire [7:0] r_aib_csr_ctrl_5, - output wire [7:0] r_aib_csr_ctrl_50, - output wire [7:0] r_aib_csr_ctrl_51, - output wire [7:0] r_aib_csr_ctrl_52, - output wire [7:0] r_aib_csr_ctrl_53, - output wire [7:0] r_aib_csr_ctrl_54, - output wire [7:0] r_aib_csr_ctrl_55, - output wire [7:0] r_aib_csr_ctrl_56, - output wire [7:0] r_aib_csr_ctrl_57, - output wire [7:0] r_aib_csr_ctrl_6, - output wire [7:0] r_aib_csr_ctrl_7, - output wire [7:0] r_aib_csr_ctrl_8, - output wire [7:0] r_aib_csr_ctrl_9, - output wire [7:0] r_aib_dprio_ctrl_0, - output wire [7:0] r_aib_dprio_ctrl_1, - output wire [7:0] r_aib_dprio_ctrl_2, - output wire [7:0] r_aib_dprio_ctrl_3, - output wire [7:0] r_aib_dprio_ctrl_4, - - // Adapter - //output wire bond_rx_asn_ds_out_dll_lock_en, - output wire bond_rx_asn_ds_out_fifo_hold, - //output wire bond_rx_asn_us_out_dll_lock_en, - output wire bond_rx_asn_us_out_fifo_hold, - output wire bond_rx_fifo_ds_out_rden, - output wire bond_rx_fifo_ds_out_wren, - output wire bond_rx_fifo_us_out_rden, - output wire bond_rx_fifo_us_out_wren, - output wire bond_rx_hrdrst_ds_out_fabric_rx_dll_lock, - output wire bond_rx_hrdrst_us_out_fabric_rx_dll_lock, - output wire bond_rx_hrdrst_ds_out_fabric_rx_dll_lock_req, - output wire bond_rx_hrdrst_us_out_fabric_rx_dll_lock_req, - output wire bond_tx_fifo_ds_out_dv, - output wire bond_tx_fifo_ds_out_rden, - output wire bond_tx_fifo_ds_out_wren, - output wire bond_tx_fifo_us_out_dv, - output wire bond_tx_fifo_us_out_rden, - output wire bond_tx_fifo_us_out_wren, - output wire bond_tx_hrdrst_ds_out_fabric_tx_dcd_cal_done, - output wire bond_tx_hrdrst_us_out_fabric_tx_dcd_cal_done, - output wire bond_tx_hrdrst_ds_out_fabric_tx_dcd_cal_req, - output wire bond_tx_hrdrst_us_out_fabric_tx_dcd_cal_req, - - - // Config - output wire csr_clk_out, - output wire [2:0] csr_out, - output wire [2:0] csr_pipe_out, - output wire csr_rdy_dly_out, - output wire csr_rdy_out, - output wire nfrzdrv_out, - output wire usermode_out, - - // PLD - output wire [3:0] hip_aib_fsr_out, - output wire [7:0] hip_aib_ssr_out, - output wire [7:0] hip_avmm_readdata, - output wire hip_avmm_readdatavalid, - output wire hip_avmm_writedone, - output wire [4:0] hip_avmm_reserved_out, - output wire pld_10g_krfec_rx_blk_lock, - output wire [1:0] pld_10g_krfec_rx_diag_data_status, - output wire pld_10g_krfec_rx_frame, - output wire pld_10g_krfec_tx_frame, - output wire pld_krfec_tx_alignment, -// output wire pld_10g_rx_align_val, - output wire pld_10g_rx_crc32_err, - output wire pld_rx_fabric_fifo_insert, - output wire pld_rx_fabric_fifo_del, - - output wire pld_10g_rx_frame_lock, - output wire pld_10g_rx_hi_ber, - output wire pld_10g_tx_burst_en_exe, - output wire [3:0] pld_8g_a1a2_k1k2_flag, - output wire pld_8g_empty_rmf, - output wire pld_8g_full_rmf, - output wire pld_8g_rxelecidle, - output wire pld_8g_signal_detect_out, - output wire [4:0] pld_8g_wa_boundary, - output wire pld_avmm1_busy, - output wire pld_avmm1_cmdfifo_wr_full, - output wire pld_avmm1_cmdfifo_wr_pfull, - output wire [7:0] pld_avmm1_readdata, - output wire pld_avmm1_readdatavalid, - output wire [2:0] pld_avmm1_reserved_out, - output wire pld_avmm2_busy, - output wire pld_avmm2_cmdfifo_wr_full, - output wire pld_avmm2_cmdfifo_wr_pfull, - output wire [7:0] pld_avmm2_readdata, - output wire pld_avmm2_readdatavalid, - output wire [2:0] pld_avmm2_reserved_out, - output wire pld_chnl_cal_done, - output wire pld_fpll_shared_direct_async_out, - output wire [3:0] pld_fpll_shared_direct_async_out_hioint, - output wire [3:0] pld_fpll_shared_direct_async_out_dcm, - output wire pld_fsr_load, - output wire pld_pcs_rx_clk_out1_hioint, - output wire pld_pcs_rx_clk_out2_hioint, - output wire pld_pcs_tx_clk_out1_hioint, - output wire pld_pcs_tx_clk_out2_hioint, - output wire pld_pll_cal_done, - output wire pld_pma_adapt_done, - output wire pld_pma_fpll_clk0bad, - output wire pld_pma_fpll_clk1bad, - output wire pld_pma_fpll_clksel, - output wire pld_pma_fpll_phase_done, - output wire pld_pma_hclk_hioint, - output wire pld_pma_internal_clk1_hioint, - output wire pld_pma_internal_clk2_hioint, - output wire [1:0] pld_pma_pcie_sw_done, - output wire pld_pma_pfdmode_lock, - output wire [4:0] pld_pma_reserved_in, - output wire pld_pma_rx_detect_valid, - output wire pld_pma_rx_found, - output wire pld_pma_rxpll_lock, - output wire pld_pma_signal_ok, - output wire [7:0] pld_pma_testbus, - output wire pld_pmaif_mask_tx_pll, - output wire pld_rx_fabric_align_done, - output wire [79:0] pld_rx_fabric_data_out, - output wire pld_rx_fabric_fifo_empty, - output wire pld_rx_fabric_fifo_full, - output wire pld_rx_fabric_fifo_latency_pulse, - output wire pld_rx_fabric_fifo_pempty, - output wire pld_rx_fabric_fifo_pfull, -// output wire pld_rx_fabric_realgin, - output wire pld_rx_hssi_fifo_empty, - output wire pld_rx_hssi_fifo_full, - output wire pld_rx_hssi_fifo_latency_pulse, - output wire pld_rx_prbs_done, - output wire pld_rx_prbs_err, - output wire pld_ssr_load, - output wire [19:0] pld_test_data, - output wire pld_tx_fabric_fifo_empty, - output wire pld_tx_fabric_fifo_full, - output wire pld_tx_fabric_fifo_latency_pulse, - output wire pld_tx_fabric_fifo_pempty, - output wire pld_tx_fabric_fifo_pfull, - output wire pld_tx_hssi_align_done, - output wire pld_tx_hssi_fifo_empty, - output wire pld_tx_hssi_fifo_full, - output wire pld_tx_hssi_fifo_latency_pulse, -// output wire pld_tx_hssi_realgin, - output wire pld_hssi_osc_transfer_en, - output wire pld_hssi_rx_transfer_en, - output wire pld_fabric_tx_transfer_en, - output wire pld_aib_fabric_rx_dll_lock, - output wire pld_aib_fabric_tx_dcd_cal_done, - output wire pld_aib_hssi_rx_dcd_cal_done, - output wire pld_aib_hssi_tx_dcd_cal_done, - output wire pld_aib_hssi_tx_dll_lock, - output wire pld_hssi_asn_dll_lock_en, - output wire pld_fabric_asn_dll_lock_en, - output wire [2:0] pld_tx_ssr_reserved_out, - output wire [1:0] pld_rx_ssr_reserved_out, - - // PLD DCM - output wire pld_pcs_rx_clk_out1_dcm, - output wire pld_pcs_rx_clk_out2_dcm, - output wire pld_pcs_tx_clk_out1_dcm, - output wire pld_pcs_tx_clk_out2_dcm - //output wire pld_pma_hclk_dcm, - //output wire pld_pma_internal_clk1_dcm, - //output wire pld_pma_internal_clk2_dcm, - - // uC AVMM -); -// Beginning of automatic wires (for undeclared instantiated-module outputs) -//wire aib_fabric_rx_dll_lock_req;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire aib_fabric_tx_transfer_clk;// From hdpldadapt_tx_chnl of hdpldadapt_tx_chnl.v -wire [1:0] avmm1_hssi_fabric_ssr_data;// From hdpldadapt_sr of hdpldadapt_sr.v -wire avmm1_hssi_fabric_ssr_load;// From hdpldadapt_sr of hdpldadapt_sr.v -wire [1:0] avmm2_hssi_fabric_ssr_data;// From hdpldadapt_sr of hdpldadapt_sr.v -wire avmm2_hssi_fabric_ssr_load;// From hdpldadapt_sr of hdpldadapt_sr.v -//wire avmm_hrdrst_data_transfer_en;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [3:0] hip_aib_async_fsr_in; // From hdpldadapt_tx_chnl of hdpldadapt_tx_chnl.v -wire [3:0] hip_aib_async_fsr_out; // From hdpldadapt_sr of hdpldadapt_sr.v -wire [39:0] hip_aib_async_ssr_in; // From hdpldadapt_tx_chnl of hdpldadapt_tx_chnl.v -wire [7:0] hip_aib_async_ssr_out; // From hdpldadapt_sr of hdpldadapt_sr.v -wire [1:0] r_rx_aib_clk1_sel; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [1:0] r_rx_aib_clk2_sel; // From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_rx_asn_bonding_dft_in_en;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_rx_asn_bonding_dft_in_value;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_rx_asn_bypass_data_transfer_en;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_asn_bypass_pma_pcie_sw_done;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_rx_asn_bypass_wait_clock_idle;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_rx_asn_dist_master_sel;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_asn_en; // From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire [1:0] r_rx_asn_master_sel; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [7:0] r_rx_asn_wait_for_fifo_flush_cnt;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [7:0] r_rx_asn_wait_for_dll_reset_cnt;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [7:0] r_rx_asn_wait_for_pma_pcie_sw_done_cnt;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_async_pld_10g_rx_crc32_err_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_async_pld_8g_signal_detect_out_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_async_pld_ltr_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_async_pld_pma_ltd_b_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_async_pld_rx_fifo_align_clr_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_async_prbs_flags_sr_enable;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_bonding_dft_in_en; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_bonding_dft_in_value;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [7:0] r_rx_comp_cnt; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [1:0] r_rx_compin_sel; // From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_rx_coreclkin_sel; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_double_read; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_ds_bypass_pipeln; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_ds_master; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [5:0] r_rx_fifo_empty; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [5:0] r_rx_fifo_full; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [2:0] r_rx_fifo_mode; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [5:0] r_rx_fifo_pempty; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [5:0] r_rx_fifo_pfull; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_fifo_rd_clk_scg_en;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [1:0] r_rx_fifo_rd_clk_sel; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_fifo_wr_clk_scg_en;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_fifo_wr_clk_sel; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_gb_dv_en; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_indv; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [2:0] r_rx_phcomp_rd_delay; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_pld_clk1_sel; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_pld_clk1_delay_en; -wire [3:0] r_rx_pld_clk1_delay_sel; -wire r_rx_pld_clk1_inv_en; -//wire r_rx_pld_clk2_sel; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_pma_hclk_scg_en; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_osc_clk_scg_en; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_fifo_wr_clk_del_sm_scg_en; -wire r_rx_fifo_rd_clk_ins_sm_scg_en; -wire r_rx_sclk_sel; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_internal_clk1_sel1; -wire r_rx_internal_clk1_sel2; -wire r_rx_txfiford_post_ct_sel; -wire r_rx_txfifowr_post_ct_sel; -wire r_rx_internal_clk2_sel1; -wire r_rx_internal_clk2_sel2; -wire r_rx_rxfifowr_post_ct_sel; -wire r_rx_rxfiford_post_ct_sel; -wire r_rx_stop_read; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_stop_write; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_truebac2bac; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_us_bypass_pipeln; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_us_master; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_rx_wa_en; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_sr_hip_en; // From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_sr_hip_fsr_in_bit0_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_sr_hip_fsr_in_bit1_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_sr_hip_fsr_in_bit2_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_sr_hip_fsr_in_bit3_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_sr_hip_fsr_out_bit0_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_sr_hip_fsr_out_bit1_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_sr_hip_fsr_out_bit2_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_sr_hip_fsr_out_bit3_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_sr_pld_10g_rx_crc32_err_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_sr_pld_8g_signal_detect_out_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_sr_pld_ltr_rst_val; // From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_sr_pld_pma_ltd_b_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_sr_pld_pmaif_mask_tx_pll_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_sr_pld_rx_fifo_align_clr_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_sr_pld_txelecidle_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_sr_osc_clk_scg_en; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [1:0] r_tx_aib_clk1_sel; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [1:0] r_tx_aib_clk2_sel; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_async_hip_aib_fsr_in_bit0_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_async_hip_aib_fsr_in_bit1_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_async_hip_aib_fsr_in_bit2_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_async_hip_aib_fsr_in_bit3_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_async_hip_aib_fsr_out_bit0_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_async_hip_aib_fsr_out_bit1_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_async_hip_aib_fsr_out_bit2_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_async_hip_aib_fsr_out_bit3_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_async_pld_pmaif_mask_tx_pll_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_async_pld_txelecidle_rst_val;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_bonding_dft_in_en; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_bonding_dft_in_value;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_burst_en; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_bypass_frmgen; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [7:0] r_tx_comp_cnt; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [1:0] r_tx_compin_sel; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_double_write; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_ds_bypass_pipeln; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_ds_master; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_dv_indv; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [4:0] r_tx_fifo_empty; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [4:0] r_tx_fifo_full; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [2:0] r_tx_fifo_mode; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [4:0] r_tx_fifo_pempty; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [4:0] r_tx_fifo_pfull; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_fifo_rd_clk_frm_gen_scg_en; -wire r_tx_fifo_rd_clk_scg_en;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [1:0] r_tx_fifo_rd_clk_sel; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_fifo_wr_clk_scg_en;// From hdpldadapt_avmm of hdpldadapt_avmm.v -//wire r_tx_fifo_wr_clk_sel; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_fpll_shared_direct_async_in_sel;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_gb_dv_en; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [2:0] r_tx_gb_idwidth; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [1:0] r_tx_gb_odwidth; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_indv; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [15:0] r_tx_mfrm_length; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire [2:0] r_tx_phcomp_rd_delay; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_pipeln_frmgen; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_pld_clk1_sel; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_pld_clk1_delay_en; -wire [3:0] r_tx_pld_clk1_delay_sel; -wire r_tx_pld_clk1_inv_en; -wire r_tx_pld_clk2_sel; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_pyld_ins; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_osc_clk_scg_en; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_sh_err; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_stop_read; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_stop_write; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_us_bypass_pipeln; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_us_master; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_wm_en; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire r_tx_wordslip; // From hdpldadapt_avmm of hdpldadapt_avmm.v -wire rx_asn_rate_change_in_progress; -wire rx_asn_dll_lock_en; // From hdpldadapt_rx_chnl of hdpldadapt_rx_chnl.v -//wire rx_asn_fifo_srst; // From hdpldadapt_rx_chnl of hdpldadapt_rx_chnl.v -//wire rx_asn_gen3_sel; // From hdpldadapt_rx_chnl of hdpldadapt_rx_chnl.v -wire [2:0] rx_async_fabric_hssi_fsr_data;// From hdpldadapt_rx_chnl of hdpldadapt_rx_chnl.v -wire rx_async_fabric_hssi_fsr_load;// From hdpldadapt_sr of hdpldadapt_sr.v -wire [35:0] rx_async_fabric_hssi_ssr_data;// From hdpldadapt_rx_chnl of hdpldadapt_rx_chnl.v -wire rx_async_fabric_hssi_ssr_load;// From hdpldadapt_sr of hdpldadapt_sr.v -wire [1:0] rx_async_hssi_fabric_fsr_data;// From hdpldadapt_sr of hdpldadapt_sr.v -wire rx_async_hssi_fabric_fsr_load;// From hdpldadapt_sr of hdpldadapt_sr.v -wire [62:0] rx_async_hssi_fabric_ssr_data;// From hdpldadapt_sr of hdpldadapt_sr.v -wire rx_async_hssi_fabric_ssr_load;// From hdpldadapt_sr of hdpldadapt_sr.v -wire [7:0] rx_chnl_dprio_status; // From hdpldadapt_rx_chnl of hdpldadapt_rx_chnl.v -wire rx_chnl_dprio_status_write_en;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire rx_chnl_dprio_status_write_en_ack;// From hdpldadapt_rx_chnl of hdpldadapt_rx_chnl.v -wire rx_fsr_mask_tx_pll; // From hdpldadapt_tx_chnl of hdpldadapt_tx_chnl.v -wire tx_async_fabric_hssi_fsr_data;// From hdpldadapt_tx_chnl of hdpldadapt_tx_chnl.v -wire tx_async_fabric_hssi_fsr_load;// From hdpldadapt_sr of hdpldadapt_sr.v -wire [35:0] tx_async_fabric_hssi_ssr_data;// From hdpldadapt_tx_chnl of hdpldadapt_tx_chnl.v -wire tx_async_fabric_hssi_ssr_load;// From hdpldadapt_sr of hdpldadapt_sr.v -wire tx_async_hssi_fabric_fsr_data;// From hdpldadapt_sr of hdpldadapt_sr.v -wire tx_async_hssi_fabric_fsr_load;// From hdpldadapt_sr of hdpldadapt_sr.v -wire [12:0] tx_async_hssi_fabric_ssr_data;// From hdpldadapt_sr of hdpldadapt_sr.v -wire tx_async_hssi_fabric_ssr_load;// From hdpldadapt_sr of hdpldadapt_sr.v -wire [7:0] tx_chnl_dprio_status; // From hdpldadapt_tx_chnl of hdpldadapt_tx_chnl.v -wire tx_chnl_dprio_status_write_en;// From hdpldadapt_avmm of hdpldadapt_avmm.v -wire tx_chnl_dprio_status_write_en_ack;// From hdpldadapt_tx_chnl of hdpldadapt_tx_chnl.v -wire r_rx_hrdrst_rx_osc_clk_scg_en; -wire r_rx_free_run_div_clk; -wire r_rx_hrdrst_rst_sm_dis; -wire r_rx_hrdrst_dll_lock_bypass; -wire r_rx_hrdrst_align_bypass; -wire r_rx_hrdrst_user_ctl_en; -//wire [1:0] r_rx_hrdrst_master_sel; -//wire r_rx_hrdrst_dist_master_sel; -wire r_rx_ds_last_chnl; -wire r_rx_us_last_chnl; -wire r_tx_hrdrst_rst_sm_dis; -wire r_tx_hrdrst_dcd_cal_done_bypass; -wire r_tx_hrdrst_user_ctl_en; -//wire [1:0] r_tx_hrdrst_master_sel; -//wire r_tx_hrdrst_dist_master_sel; -wire r_tx_ds_last_chnl; -wire r_tx_us_last_chnl; -wire r_tx_hrdrst_rx_osc_clk_scg_en; -wire r_tx_hip_osc_clk_scg_en; -wire avmm_hrdrst_fabric_osc_transfer_en_ssr_data; -wire avmm_hrdrst_fabric_osc_transfer_en_sync; -wire avmm_hrdrst_fabric_osc_transfer_en; -wire avmm_fabric_hssi_ssr_load; -wire avmm_hssi_fabric_ssr_load; -wire avmm_hrdrst_hssi_osc_transfer_en_ssr_data; - -wire [2:0] r_tx_fifo_power_mode; -wire [2:0] r_tx_stretch_num_stages; -wire [2:0] r_tx_datapath_tb_sel; -wire r_tx_wr_adj_en; -wire r_tx_rd_adj_en; - -wire r_rx_write_ctrl; -wire [2:0] r_rx_fifo_power_mode; -wire [2:0] r_rx_stretch_num_stages; -wire [3:0] r_rx_datapath_tb_sel; -wire r_rx_wr_adj_en; -wire r_rx_rd_adj_en; -wire r_rx_lpbk_en; -wire [1:0] rx_pld_rate; -wire [39:0] aib_fabric_tx_data_lpbk; - -wire tx_hrdrst_fabric_tx_transfer_en; -wire tx_clock_fifo_rd_clk; -wire tx_clock_fifo_wr_clk; - -wire [2:0] tx_async_fabric_hssi_ssr_reserved; -wire [2:0] tx_async_hssi_fabric_ssr_reserved; -wire [1:0] rx_async_fabric_hssi_ssr_reserved; -wire [1:0] rx_async_hssi_fabric_ssr_reserved; - -wire r_sr_reserbits_in_en; -wire r_sr_reserbits_out_en; -wire r_sr_testbus_sel; -wire r_sr_parity_en; -wire avmm1_transfer_error; -wire avmm2_transfer_error; -wire [19:0] avmm_testbus; -wire [19:0] sr_testbus; - -wire [3:0] r_tx_hip_aib_ssr_in_polling_bypass; -wire r_tx_pld_8g_tx_boundary_sel_polling_bypass; -wire r_tx_pld_10g_tx_bitslip_polling_bypass; -wire r_tx_pld_pma_fpll_cnt_sel_polling_bypass; -wire r_tx_pld_pma_fpll_num_phase_shifts_polling_bypass; -wire r_rx_pld_8g_eidleinfersel_polling_bypass; -wire r_rx_pld_pma_eye_monitor_polling_bypass; -wire r_rx_pld_pma_pcie_switch_polling_bypass; -wire r_rx_pld_pma_reser_out_polling_bypass; -wire hip_fsr_parity_checker_in; -wire [5:0] hip_ssr_parity_checker_in; -wire tx_fsr_parity_checker_in; -wire [15:0] tx_ssr_parity_checker_in; -wire [1:0] rx_fsr_parity_checker_in; -wire [64:0] rx_ssr_parity_checker_in; -wire [1:0] avmm1_ssr_parity_checker_in; -wire [1:0] avmm2_ssr_parity_checker_in; -wire sr_hssi_osc_transfer_en; -wire r_tx_usertest_sel; -wire r_rx_usertest_sel; -wire [19:0] sr_parity_error_flag; - -// End of automatics - -// ECO8 - wire [1:0] r_tx_wren_fastbond; - wire [1:0] r_tx_rden_fastbond; - wire [1:0] r_rx_wren_fastbond; - wire [1:0] r_rx_rden_fastbond; - -/* hdpldadapt_avmm AUTO_TEMPLATE ( -.scan_mode_n (pld_scan_mode_n), -.scan_shift_n (pld_scan_shift_n), -); -*/ - -// DFT -assign iaibdftcore2dll = dft_fabric_iaibdftcore2dll; -//assign dft_fabric_oaibdftdll2core = oaibdftdll2core; - -wire [19:0] tx_chnl_testbus; -wire rx_asn_fifo_hold; - - - - -endmodule diff --git a/ndsimslv/multidie.f b/ndsimslv/multidie.f index b2de077..ca9f384 100644 --- a/ndsimslv/multidie.f +++ b/ndsimslv/multidie.f @@ -355,8 +355,6 @@ ../aib_lib/c3aibadapt_wrap/rtl/c3aib_master.sv +incdir+../rtl/ +incdir+../ndsimslv/ -./ndaibadapt_wrap.v -./hdpldadapt.v ../rtl/aib_dcc.v ../rtl/aib_aux_channel.v @@ -376,3 +374,276 @@ ../rtl/dll.sv ../rtl/aib_channel.v ../rtl/aib.v + ++incdir+../maib_rtl/cfg_shared/rtl/block_function/hdpldadapt/rtl/block_function ++incdir+../maib_rtl/cfg_shared/rtl/block_function/cdclib/rtl/block_function ++incdir+../maib_rtl/cfg_shared/rtl/block_function/cfg_shared/rtl/block_function ++incdir+../maib_rtl/aibnd_lib/rtl/block_function ++incdir+../maib_rtl/io_common_custom/rtl/block_function ++incdir+../maib_rtl/aibndpnr_lib/rtl/block_function ++incdir+../maib_rtl/cdclib/rtl/block_function +../maib_rtl/s10aib/rtl/ndaibadapt_wrap.v +../maib_rtl/s10aib/rtl/an.v +../maib_rtl/s10aib/rtl/s10aib.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1_async.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1_config.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1_dprio_mapping.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1_transfer.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm2_async.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm2_transfer.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm2.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_async_update.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmmclk_ctl.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_cmdfifo.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_cmn_intf.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_dprio_reg.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_rdfifo.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmmrst_ctl.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_async.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_hrdrst_rstctrl.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_hrdrst_clkctl.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_fsr_in.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_fsr_out.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_srclk_ctl.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_sr_in_bit.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_sr_out_bit.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_srrst_ctl.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_sr_sm.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_sr.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_ssr_in.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_ssr_out.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_async_update.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_reserved_capture.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_reserved_update.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_hip_async_capture.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_hip_async_update.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_capture.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_direct.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_update.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_chnl.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_txclk_ctl.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_async_fifo.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_fifo_ram.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_fifo_pointers.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_chnl_testbus.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_cp_bond.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_dv_gen.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_fifo.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_frame_gen.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_word_mark.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_txrst_ctl.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_pulse_stretch.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_reserved_capture.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_reserved_update.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_capture.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_direct.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_update.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_chnl.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rxclk_ctl.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_asn.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_async_fifo.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_cp_bond.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_fifo.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_fifo_ram.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_fifo_pointers.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_insert_sm.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_del_sm.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_word_align.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rxrst_ctl.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_pulse_stretch.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_chnl_testbus.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_async_capture_bit.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_comp_cntr.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_pair_dw.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_async_capture_bus.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_dw.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_pair.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_latency_measure.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_pulse_stretch.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_parity_gen.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_parity_checker.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkand2.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay_map.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay_cell.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkgate.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkinv.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkmux2_cell.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkmux2.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkor2.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_dft_clock_controller.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_clkgate.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_enable_logic.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_gray_code_counter.v +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_test_control_register.v +../maib_rtl/cdclib/rtl/block_function/cdclib_bintogray.v +../maib_rtl/cdclib/rtl/block_function/cdclib_bintogray_inc8.v +../maib_rtl/cdclib/rtl/block_function/cdclib_bitsync2.v +../maib_rtl/cdclib/rtl/block_function/cdclib_sync2_reset_type_l_gate.v +../maib_rtl/cdclib/rtl/block_function/cdclib_sync2_reset_type_n_gate.v +../maib_rtl/cdclib/rtl/block_function/cdclib_sync2_reset_type_w_gate.v +../maib_rtl/cdclib/rtl/block_function/cdclib_sync2_set_type_l_gate.v +../maib_rtl/cdclib/rtl/block_function/cdclib_sync2_set_type_n_gate.v +../maib_rtl/cdclib/rtl/block_function/cdclib_sync2_set_type_w_gate.v +../maib_rtl/cdclib/rtl/block_function/cdclib_bitsync4.v +../maib_rtl/cdclib/rtl/block_function/cdclib_sync4_reset_type_l_gate.v +../maib_rtl/cdclib/rtl/block_function/cdclib_sync4_reset_type_w_gate.v +../maib_rtl/cdclib/rtl/block_function/cdclib_sync4_set_type_l_gate.v +../maib_rtl/cdclib/rtl/block_function/cdclib_sync4_set_type_w_gate.v +../maib_rtl/cdclib/rtl/block_function/cdclib_graytobin.v +../maib_rtl/cdclib/rtl/block_function/cdclib_graytobin_inc2.v +../maib_rtl/cdclib/rtl/block_function/cdclib_graytobin_inc8.v +../maib_rtl/cdclib/rtl/block_function/cdclib_rst_n_sync.v +../maib_rtl/cdclib/rtl/block_function/cdclib_rst_n_sync_core.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_csr_reg_bit.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_csr_reg_nbits.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_csr_reg_nregs.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_cmn_non_scan_reg.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_readdata_mux.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_interface_top.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_csr_test_mux.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_cmn_clk_mux.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_reg_bit.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_reg_nbits.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_reg_nregs.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_reg_chnl.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_reg_top.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_dis_ctrl_cvp.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_readdata_sel.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_status_reg_nbits.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_status_reg_nregs.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_status_sync_regs.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_shadow_status_regs.v +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_shadow_status_nregs.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_top_wrp.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_top.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dly_rep.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dly_mimic.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_io_dly_interpolator_rep.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_io_nand_delay_line_min_rep.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_latch.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_hgy_latch.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_ff_r.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_ff_rp.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_2ff_scan.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_aliasd.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_aliasv.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_2to4dec.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_analog.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_avmm1.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_avmm2.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_buffx1_top.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_buffx1.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clkbuf.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_avmm.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_avmm_mimic.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_avmm_pcs.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_mimic.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_pcs.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_fine_dly.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x6.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x1.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_d8xsesdd1.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_d8xsesdd2.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_5b_b2tc_x1.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_5b_b2tc.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dll.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_ff.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_fine_dly.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_mux.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_top.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_digital.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dll_phdet.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dll_custom.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_inv_split_align.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_quadph_code_gen.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_preclkbuf.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxdatapath_rx.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxdig.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_align.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_txdatapath_tx.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_txdig.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxanlg.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_txanlg.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_fine_dly_x1.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_fine_dly_x1.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dly_inv.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_fine_dly_inv.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_ff.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_helper.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_clktree_mimic.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dly.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_custom_dig.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_preclkbuf.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_nand_x64_delay_line.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_clktree.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_sync_ff.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x64.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_signal_buf.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_custom_dig2.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_avmm_rst_sync.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_data_buf.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_interface.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_rambit_buf.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_inv.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_nand2.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_nor2.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_clkmux2.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_clkmux3.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_txdat_mimic.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxdat_mimic.v +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clkmux2.v +//Looks fine to me. All behavior and from Nightfury + +../maib_rtl/io_common_custom/rtl/block_function/io_interp_mux.v +../maib_rtl/io_common_custom/rtl/block_function/io_ip16phs.v +../maib_rtl/io_common_custom/rtl/block_function/io_cmos_16ph_decode.v +../maib_rtl/io_common_custom/rtl/block_function/io_interp_misc.v +../maib_rtl/io_common_custom/rtl/block_function/io_interp_output.v +../maib_rtl/io_common_custom/rtl/block_function/io_interp_latch_in.v +../maib_rtl/io_common_custom/rtl/block_function/io_interp_mux_pair.v +../maib_rtl/io_common_custom/rtl/block_function/io_interp_pdn.v +../maib_rtl/io_common_custom/rtl/block_function/io_min_interp_mux.v +../maib_rtl/io_common_custom/rtl/block_function/io_min_ip16phs.v +../maib_rtl/io_common_custom/rtl/block_function/io_min_output.v +../maib_rtl/io_common_custom/rtl/block_function/io_min_misc.v +../maib_rtl/io_common_custom/rtl/block_function/io_min_pdn.v +../maib_rtl/io_common_custom/rtl/block_function/io_dly_interpolator.v +../maib_rtl/io_common_custom/rtl/block_function/io_dly_interpclk.v +../maib_rtl/io_common_custom/rtl/block_function/io_ip8phs_3in.v +../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x1.v +../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x128.v +../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x64_decode.v +../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x128_decode.v +../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x6.v +../maib_rtl/io_common_custom/rtl/block_function/io_nand_x128_delay_line.v +../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x64.v +../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x4.v +../maib_rtl/io_common_custom/rtl/block_function/io_split_align.v +../maib_rtl/io_common_custom/rtl/block_function/io_dll_phdet.v +../maib_rtl/io_common_custom/rtl/block_function/io_nand_delay_line_min.v +../maib_rtl/soc_std_macro/rtl/block_function/i14socnd/soc_simulation_defines.v +// Not used +// Standard Cell, OK to use with ALTR_HPS_INTEL_MACROS_OFF option +../maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckinv.v +../maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckmux21.v +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_redundancy.v +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_jtag_bscan.v +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_bsr_red_wrap.v +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_half_cycle_code_gen.v +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_self_lock_assertion.v +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_ctrl.v +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_core.v +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_pnr.v +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkgate_cgc00.v +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkgate_cgc01.v +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkmux.v diff --git a/ndsimslv/nda_drv.sv b/ndsimslv/nda_drv.sv index c4aeb94..c2728ea 100644 --- a/ndsimslv/nda_drv.sv +++ b/ndsimslv/nda_drv.sv @@ -1,31 +1,14 @@ // SPDX-License-Identifier: Apache-2.0 // Copyright (C) 2019 Intel Corporation. All rights reserved - // Clock generation - parameter CFG_CSR_CLK_PERIOD = 20000; - parameter PLD_PMA_ROWCLK_PERIOD = 2000; - parameter PLD_SCLK_ROWCLK_PERIOD = 3817; - parameter PLD_RX_CLK1_ROWCLK_PERIOD = 1000; - parameter PLD_RX_CLK2_ROWCLK_PERIOD = 2000; - parameter PLD_TX_CLK1_ROWCLK_PERIOD = 1000; - parameter PLD_TX_CLK2_ROWCLK_PERIOD = 64000; - parameter PLD_RX_CLK1_DCM_PERIOD = 2000; - parameter PLD_TX_CLK1_DCM_PERIOD = 64000; - parameter PLD_TX_CLK2_DCM_PERIOD = 1000; - logic [2:0] csr_config; logic [2:0] csr_in; logic nfrzdrv_in; logic csr_rdy_in; - logic csr_rdy_dly_in; logic usermode_in; + logic sl_ns_mac_rdy; reg csr_clk_in = 1'b0; -// reg pld_avmm1_clk_rowclk = 1'b0; -// reg pld_avmm2_clk_rowclk = 1'b0; -// reg pld_pma_coreclkin_rowclk = 1'b0; -// reg pld_sclk1_rowclk = 1'b0; -// reg pld_sclk2_rowclk = 1'b0; reg pld_rx_clk1_rowclk = 1'b0; reg pld_rx_clk2_rowclk = 1'b0; reg pld_tx_clk1_rowclk = 1'b0; @@ -36,37 +19,21 @@ reg pld_tx_clk2_dcm = 1'b0; - //clock gen - always #(CFG_CSR_CLK_PERIOD/2) csr_clk_in = ~csr_clk_in; - always #(CFG_CSR_CLK_PERIOD/2) pld_avmm1_clk_rowclk = ~pld_avmm1_clk_rowclk; - always #(CFG_CSR_CLK_PERIOD/2) pld_avmm2_clk_rowclk = ~pld_avmm2_clk_rowclk; - always #(PLD_PMA_ROWCLK_PERIOD/2) pld_pma_coreclkin_rowclk = ~pld_pma_coreclkin_rowclk; - always #(PLD_SCLK_ROWCLK_PERIOD/2) pld_sclk1_rowclk = ~pld_sclk1_rowclk; - always #(PLD_SCLK_ROWCLK_PERIOD/2) pld_sclk2_rowclk = ~pld_sclk2_rowclk; - always #(PLD_RX_CLK1_ROWCLK_PERIOD/2) pld_rx_clk1_rowclk = ~pld_rx_clk1_rowclk; //FIXME it does not start right away - always #(PLD_RX_CLK2_ROWCLK_PERIOD/2) pld_rx_clk2_rowclk = ~pld_rx_clk2_rowclk; - always #(PLD_TX_CLK1_ROWCLK_PERIOD/2) pld_tx_clk1_rowclk = ~pld_tx_clk1_rowclk; //FIXME it does not start right away - always #(PLD_TX_CLK2_ROWCLK_PERIOD/2) pld_tx_clk2_rowclk = ~pld_tx_clk2_rowclk; - always #(PLD_RX_CLK1_DCM_PERIOD/2) pld_rx_clk1_dcm = ~pld_rx_clk1_dcm; - always #(PLD_TX_CLK1_DCM_PERIOD/2) pld_tx_clk1_dcm = ~pld_tx_clk1_dcm; - always #(PLD_TX_CLK2_DCM_PERIOD/2) pld_tx_clk2_dcm = ~pld_tx_clk2_dcm; - //Default set value initial begin csr_config = 3'h1; csr_in = 3'h0; csr_rdy_in = 1'b0; - csr_rdy_dly_in = 1'b0; - + sl_ns_mac_rdy = 1'b0; pld_adapter_tx_pld_rst_n = 1'b0; pld_adapter_rx_pld_rst_n = 1'b0; usermode_in = 1'b0; @(dut.i_adpt_hard_rst_n) + sl_ns_mac_rdy = 1'b1; csr_rdy_in = 1'b1; #100000; - csr_rdy_dly_in = 1'b1; nfrzdrv_in = 1'b1; #100000; usermode_in = 1'b1; @@ -81,5 +48,49 @@ end //initial begin +`ifdef S10_MODEL + + //Nadder Adapter Forces + initial begin // { + @ (csr_rdy_in) + + //MAIB Configuration + // + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.aib_csr_ctrl[463:0] = 464'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_1200_7d1a_0000_0000_0004_0002_45d3_3b07_b000_0040_0002_0000_2699_0000_0000_0000_0000_0000_0000; +`ifdef REGISTER_MOD // For ND DCC/DLL bypass for low speed + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.aib_dprio_ctrl[39:0] = 40'h400; +`else + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.aib_dprio_ctrl[39:0] = 40'h18000000; +`endif +// force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.aib_dprio_ctrl[39:0] = 40'h0; + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.avmm1_csr_ctrl[55:0] = 56'h07_ff00_3000_f800; + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.avmm1_dprio_ctrl[7:0] = 8'h0; + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.avmm2_csr_ctrl[55:0] = 56'h07_ff00_3000_f800; + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.avmm2_dprio_ctrl[7:0] = 8'h0; + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.avmm_csr_ctrl[55:0] = 56'h00_0018_0000_0300; + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.avmm_res_csr_ctrl[7:0] = 8'h0; +// force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.rx_chnl_dprio_ctrl[167:0] = 168'hc8_17c8_c905_6c42_0040_4040_4c00_0303_0018_ca82_cf01; +`ifdef REGISTER_MOD +//Set rxfifo to be register mode bit 33:32 = 2'b11 r_double read is 0 + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.rx_chnl_dprio_ctrl[167:0] = 168'hc8_1788_8805_6c42_0040_4040_4c00_0303_001b_ca82_0f01; +`else +//set r_rx_aib_clk1_sel == 2'b01 to let half clock out. bit 137:136 + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.rx_chnl_dprio_ctrl[167:0] = 168'hc8_17c8_c905_6c42_0040_4040_4c00_0303_0018_ca82_4f01; +`endif + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.sr_dprio_ctrl[23:0] = 24'h0; +// force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.tx_chnl_dprio_ctrl[135:0] = 136'h2c_e086_11c5_00ce_2308_00cb_0300_6a22_ee00; +`ifdef REGISTER_MOD +//Set txfifo to be register mode bit [6:5] = 2'b11 r_tx_double_write is 0 bit 55. Turn off watermark r_tx_wm_en bit 77 + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.tx_chnl_dprio_ctrl[135:0] = 136'h2c_e086_15c5_00ce_0308_000b_0300_6a22_ee60; +`else + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.tx_chnl_dprio_ctrl[135:0] = 136'h2c_e086_15c5_00ce_2308_008b_0300_6a22_ee00; +`endif + force `NDADAPT_RTB.hdpldadapt_avmm.r_rx_async_pld_pma_ltd_b_rst_val = 1'b0; +// force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.avmm_csr_ctrl[17] = 1'b1; //r_sr_reserbits_in_en + force `NDADAPT_RTB.hdpldadapt_avmm.hdpldadapt_avmm1.hdpldadapt_avmm1_config.hdpldadapt_avmm1_dprio_mapping.avmm_csr_ctrl[18] = 1'b1; //r_sr_reserbits_out_en + //force `NDADAPT_RTB.hdpldadapt_sr.r_sr_reserbits_in_en = 1'b1; + //force `NDADAPT_RTB.hdpldadapt_sr.r_sr_reserbits_out_en = 1'b1; + end +`endif // S10_MODEL diff --git a/ndsimslv/nda_port.sv b/ndsimslv/nda_port.sv index 0e6182c..3aaa834 100644 --- a/ndsimslv/nda_port.sv +++ b/ndsimslv/nda_port.sv @@ -1,489 +1,188 @@ // SPDX-License-Identifier: Apache-2.0 // Copyright (C) 2019 Intel Corporation. All rights reserved + +`ifdef S10_MODEL + wire [79:0] pld_rx_fabric_data_out; -ndaibadapt_wrap ndut( +wire rx_clkout; + +s10aib s10_wrap ( + .iopad_ns_mac_rdy(ms_iopad_fs_mac_rdy), + .iopad_fs_mac_rdy(ms_iopad_ns_mac_rdy), + .iopad_ns_adapter_rstn(ms_iopad_fs_adapter_rstn), + .iopad_fs_adapter_rstn(ms_iopad_ns_adapter_rstn), + + .iopad_tx(ms_iopad_rx), + .iopad_ns_fwd_clk(ms_iopad_fs_fwd_clk), + .iopad_ns_fwd_clkb(ms_iopad_fs_fwd_clkb), + .iopad_ns_rcv_clk(ms_iopad_fs_rcv_clk), + .iopad_ns_rcv_clkb(ms_iopad_fs_rcv_clkb), + + + .iopad_rx(ms_iopad_tx), + .iopad_fs_fwd_clk(ms_iopad_ns_fwd_clk), + .iopad_fs_fwd_clkb(ms_iopad_ns_fwd_clkb), + .iopad_fs_fwd_div2_clk(ms_iopad_ns_fwd_div2_clk), + .iopad_fs_fwd_div2_clkb(ms_iopad_ns_fwd_div2_clkb), + .iopad_fs_rcv_clk(ms_iopad_ns_rcv_clk), + .iopad_fs_rcv_clkb(ms_iopad_ns_rcv_clkb), + .iopad_fs_rcv_div2_clk(ms_iopad_ns_rcv_div2_clk), + .iopad_fs_rcv_div2_clkb(ms_iopad_ns_rcv_div2_clkb), + + .iopad_ns_sr_data(ms_iopad_fs_sr_data), + .iopad_ns_sr_load(ms_iopad_fs_sr_load), + .iopad_ns_sr_clk(ms_iopad_fs_sr_clk), + .iopad_ns_sr_clkb(ms_iopad_fs_sr_clkb), + + + .iopad_fs_sr_clk(ms_iopad_ns_sr_clk), + .iopad_fs_sr_clkb(ms_iopad_ns_sr_clkb), + .iopad_fs_sr_data(ms_iopad_ns_sr_data), + .iopad_fs_sr_load(ms_iopad_ns_sr_load), + .iopad_unused_aib45, + .iopad_unused_aib46, + .iopad_unused_aib47, + .iopad_unused_aib50, + .iopad_unused_aib51, + .iopad_unused_aib52, + .iopad_unused_aib58, + .iopad_unused_aib60, + .iopad_unused_aib61, + .iopad_unused_aib62, + .iopad_unused_aib63, + .iopad_unused_aib64, + .iopad_unused_aib66, + .iopad_unused_aib67, + .iopad_unused_aib68, + .iopad_unused_aib69, + .iopad_unused_aib70, + .iopad_unused_aib71, + .iopad_unused_aib72, + .iopad_unused_aib73, + .iopad_unused_aib74, + .iopad_unused_aib75, + .iopad_unused_aib76, + .iopad_unused_aib77, + .iopad_unused_aib78, + .iopad_unused_aib79, + .iopad_unused_aib80, + .iopad_unused_aib81, + .iopad_unused_aib88, + .iopad_unused_aib89, + .iopad_unused_aib90, + .iopad_unused_aib91, + + + .tx_parallel_data(pld_rx_fabric_data_out), // pld_tx_fabric_data_in + .rx_parallel_data(pld_rx_fabric_data_out), // pld_rx_fabric_data_out + .tx_coreclkin(rx_clkout), // pld_tx_clk1_rowclk or pld_tx_clk1_dcm + .tx_clkout(), // pld_pcs_tx_clk_out1_dcm + .rx_coreclkin(rx_clkout), // pld_rx_clk1_dcm + .rx_clkout(rx_clkout), // pld_pcs_rx_clk_out1_dcm + .config_done(csr_rdy_in), + .fs_mac_rdy(fs_mac_rdy), //(use c3 pld_pma_clkdiv_rx_user pin). Drive by Master + .ns_mac_rdy(sl_ns_mac_rdy), //nd pld_pma_rxpma_rstb. This signal should be high before ns_adapter_rstn go high. + .ns_adapter_rstn(pld_adapter_rx_pld_rst_n), //Reset Main adapter and pass over to the fs. + + .sl_rx_dcc_dll_lock_req(pld_rx_dll_lock_req), + .sl_tx_dcc_dll_lock_req(pld_tx_dll_lock_req), + .ms_rx_transfer_en(), + .ms_tx_transfer_en(), + .sl_rx_transfer_en(), + .sl_tx_transfer_en(), + .ms_sideband(), + .sl_sideband()); +`else + +wire [19:0] sl_dataout0,sl_dataout1; + + parameter DATAWIDTH = 20; + aib #(.DATAWIDTH(DATAWIDTH)) slave ( + .iopad_tx(ms_iopad_rx), + .iopad_rx(ms_iopad_tx), + .iopad_ns_rcv_clkb(ms_iopad_fs_rcv_clkb), + .iopad_ns_rcv_clk(ms_iopad_fs_rcv_clk), + .iopad_ns_fwd_clk(ms_iopad_fs_fwd_clk), + .iopad_ns_fwd_clkb(ms_iopad_fs_fwd_clkb), + .iopad_ns_sr_clk(ms_iopad_fs_sr_clk), + .iopad_ns_sr_clkb(ms_iopad_fs_sr_clkb), + .iopad_ns_sr_load(ms_iopad_fs_sr_load), + .iopad_ns_sr_data(ms_iopad_fs_sr_data), + .iopad_ns_mac_rdy(ms_iopad_fs_mac_rdy), + .iopad_ns_adapter_rstn(ms_iopad_fs_adapter_rstn), + .iopad_spare1(), + .iopad_spare0(), + .iopad_fs_rcv_clkb(ms_iopad_ns_rcv_clkb), + .iopad_fs_rcv_clk(ms_iopad_ns_rcv_clk), + .iopad_fs_fwd_clkb(ms_iopad_ns_fwd_clkb), + .iopad_fs_fwd_clk(ms_iopad_ns_fwd_clk), + .iopad_fs_sr_clkb(ms_iopad_ns_sr_clkb), + .iopad_fs_sr_clk(ms_iopad_ns_sr_clk), + .iopad_fs_sr_load(ms_iopad_ns_sr_load), + .iopad_fs_sr_data(ms_iopad_ns_sr_data), + .iopad_fs_mac_rdy(ms_iopad_ns_mac_rdy), + .iopad_fs_adapter_rstn(ms_iopad_ns_adapter_rstn), + + .iopad_device_detect(device_detect), + .iopad_device_detect_copy(device_detectrdcy), + .iopad_por(), + .iopad_por_copy(), -// EMIB inout - .io_aib0(aib0), - .io_aib1(aib1), - .io_aib10(aib10), - .io_aib11(aib11), - .io_aib12(aib12), - .io_aib13(aib13), - .io_aib14(aib14), - .io_aib15(aib15), - .io_aib16(aib16), - .io_aib17(aib17), - .io_aib18(aib18), - .io_aib19(aib19), - .io_aib2(aib2), - .io_aib20(aib20), - .io_aib21(aib21), - .io_aib22(aib22), - .io_aib23(aib23), - .io_aib24(aib24), - .io_aib25(aib25), - .io_aib26(aib26), - .io_aib27(aib27), - .io_aib28(aib28), - .io_aib29(aib29), - .io_aib3(aib3), - .io_aib30(aib30), - .io_aib31(aib31), - .io_aib32(aib32), - .io_aib33(aib33), - .io_aib34(aib34), - .io_aib35(aib35), - .io_aib36(aib36), - .io_aib37(aib37), - .io_aib38(aib38), - .io_aib39(aib39), - .io_aib4(aib4), - .io_aib40(aib40), - .io_aib41(aib41), - .io_aib42(aib42), - .io_aib43(aib43), - .io_aib44(aib44), - .io_aib45(aib45), - .io_aib46(aib46), - .io_aib47(aib47), - .io_aib48(aib48), - .io_aib49(aib49), - .io_aib5(aib5), - .io_aib50(aib50), - .io_aib51(aib51), - .io_aib52(aib52), - .io_aib53(aib53), - .io_aib54(aib54), - .io_aib55(aib55), - .io_aib56(aib56), - .io_aib57(aib57), - .io_aib58(aib58), - .io_aib59(aib59), - .io_aib6(aib6), - .io_aib60(aib60), - .io_aib61(aib61), - .io_aib62(aib62), - .io_aib63(aib63), - .io_aib64(aib64), - .io_aib65(aib65), - .io_aib66(aib66), - .io_aib67(aib67), - .io_aib68(aib68), - .io_aib69(aib69), - .io_aib7(aib7), - .io_aib70(aib70), - .io_aib71(aib71), - .io_aib72(aib72), - .io_aib73(aib73), - .io_aib74(aib74), - .io_aib75(aib75), - .io_aib76(aib76), - .io_aib77(aib77), - .io_aib78(aib78), - .io_aib79(aib79), - .io_aib8(aib8), - .io_aib80(aib80), - .io_aib81(aib81), - .io_aib82(aib82), - .io_aib83(aib83), - .io_aib84(aib84), - .io_aib85(aib85), - .io_aib86(aib86), - .io_aib87(aib87), - .io_aib88(aib88), - .io_aib89(aib89), - .io_aib9(aib9), - .io_aib90(aib90), - .io_aib91(aib91), - .io_aib92(aib92), - .io_aib93(aib93), - .io_aib94(aib94), - .io_aib95(aib95), + .data_in({sl_dataout1[19:0],sl_dataout0[19:0]}), //output data to pad + .data_out({sl_dataout1[19:0],sl_dataout0[19:0]}), //input data from pad + .m_ns_fwd_clk(rx_clkout), //output data clock + .m_fs_rcv_clk(), + .m_fs_fwd_clk(rx_clkout), + .m_ns_rcv_clk(), - // Adapter input - .bond_rx_asn_ds_in_fifo_hold(1'b0), - .bond_rx_asn_us_in_fifo_hold(1'b0), - .bond_rx_fifo_ds_in_rden(1'b0), - .bond_rx_fifo_ds_in_wren(1'b0), - .bond_rx_fifo_us_in_rden(1'b0), - .bond_rx_fifo_us_in_wren(1'b0), - .bond_rx_hrdrst_ds_in_fabric_rx_dll_lock(1'b0), - .bond_rx_hrdrst_us_in_fabric_rx_dll_lock(1'b0), - .bond_rx_hrdrst_ds_in_fabric_rx_dll_lock_req(1'b0), - .bond_rx_hrdrst_us_in_fabric_rx_dll_lock_req(1'b0), - .bond_tx_fifo_ds_in_dv(1'b0), - .bond_tx_fifo_ds_in_rden(1'b0), - .bond_tx_fifo_ds_in_wren(1'b0), - .bond_tx_fifo_us_in_dv(1'b0), - .bond_tx_fifo_us_in_rden(1'b0), - .bond_tx_fifo_us_in_wren(1'b0), - .bond_tx_hrdrst_ds_in_fabric_tx_dcd_cal_done(1'b0), - .bond_tx_hrdrst_us_in_fabric_tx_dcd_cal_done(1'b0), - .bond_tx_hrdrst_ds_in_fabric_tx_dcd_cal_req(1'b0), - .bond_tx_hrdrst_us_in_fabric_tx_dcd_cal_req(1'b0), - - // Config input - .csr_config(csr_config), - .csr_clk_in(csr_clk_in), - .csr_in(csr_in), - .csr_pipe_in(csr_pipe_in), - .csr_rdy_dly_in(csr_rdy_dly_in), - .csr_rdy_in(csr_rdy_in), - .nfrzdrv_in(nfrzdrv_in), - .usermode_in(usermode_in), - - // PLD input - .hip_aib_fsr_in(hip_aib_fsr_in), - .hip_aib_ssr_in(hip_aib_ssr_in), - .hip_avmm_read(hip_avmm_read), - .hip_avmm_reg_addr(hip_avmm_reg_addr), - .hip_avmm_write(hip_avmm_write), - .hip_avmm_writedata(hip_avmm_writedata), - .pld_10g_krfec_rx_clr_errblk_cnt(pld_10g_krfec_rx_clr_errblk_cnt), - .pld_10g_rx_align_clr(pld_10g_rx_align_clr), - .pld_10g_rx_clr_ber_count(pld_10g_rx_clr_ber_count), - .pld_10g_tx_bitslip(pld_10g_tx_bitslip), - .pld_10g_tx_burst_en(pld_10g_tx_burst_en), - .pld_10g_tx_diag_status(pld_10g_tx_diag_status), - .pld_10g_tx_wordslip(pld_10g_tx_wordslip), - .pld_8g_a1a2_size(pld_8g_a1a2_size), - .pld_8g_bitloc_rev_en(pld_8g_bitloc_rev_en), - .pld_8g_byte_rev_en(pld_8g_byte_rev_en), - .pld_8g_eidleinfersel(pld_8g_eidleinfersel), - .pld_8g_encdt(pld_8g_encdt), - .pld_8g_tx_boundary_sel(pld_8g_tx_boundary_sel), - .pld_adapter_rx_pld_rst_n(pld_adapter_rx_pld_rst_n), - .pld_adapter_tx_pld_rst_n(pld_adapter_tx_pld_rst_n), - .pld_avmm1_clk_rowclk(pld_avmm1_clk_rowclk), - .pld_avmm1_read(pld_avmm1_read), - .pld_avmm1_reg_addr(pld_avmm1_reg_addr), - .pld_avmm1_request(pld_avmm1_request), - .pld_avmm1_write(pld_avmm1_write), - .pld_avmm1_writedata(pld_avmm1_writedata), - .pld_avmm1_reserved_in(pld_avmm1_reserved_in), - .pld_avmm2_clk_rowclk(pld_avmm2_clk_rowclk), - .pld_avmm2_read(pld_avmm2_read), - .pld_avmm2_reg_addr(pld_avmm2_reg_addr), - .pld_avmm2_request(pld_avmm2_request), - .pld_avmm2_write(pld_avmm2_write), - .pld_avmm2_writedata(pld_avmm2_writedata), - .pld_avmm2_reserved_in(pld_avmm2_reserved_in), - .pld_bitslip(pld_bitslip), - .pld_fpll_shared_direct_async_in(pld_fpll_shared_direct_async_in), - .pld_fpll_shared_direct_async_in_rowclk(pld_fpll_shared_direct_async_in_rowclk), - .pld_fpll_shared_direct_async_in_dcm(pld_fpll_shared_direct_async_in_dcm), - .pld_ltr(pld_ltr), - .pr_channel_freeze_n(pr_channel_freeze_n), - .pld_pcs_rx_pld_rst_n(pld_pcs_rx_pld_rst_n), - .pld_pcs_tx_pld_rst_n(pld_pcs_tx_pld_rst_n), - .pld_pma_adapt_start(pld_pma_adapt_start), - .pld_pma_coreclkin_rowclk(pld_pma_coreclkin_rowclk), - .pld_pma_csr_test_dis(pld_pma_csr_test_dis), - .pld_pma_early_eios(pld_pma_early_eios), - .pld_pma_eye_monitor(pld_pma_eye_monitor), - .pld_pma_fpll_cnt_sel(pld_pma_fpll_cnt_sel), - .pld_pma_fpll_extswitch(pld_pma_fpll_extswitch), - .pld_pma_fpll_lc_csr_test_dis(pld_pma_fpll_lc_csr_test_dis), - .pld_pma_fpll_num_phase_shifts(pld_pma_fpll_num_phase_shifts), - .pld_pma_fpll_pfden(pld_pma_fpll_pfden), - .pld_pma_fpll_up_dn_lc_lf_rstn(pld_pma_fpll_up_dn_lc_lf_rstn), - .pld_pma_ltd_b(pld_pma_ltd_b), - .pld_pma_nrpi_freeze(pld_pma_nrpi_freeze), - .pld_pma_pcie_switch(pld_pma_pcie_switch), - .pld_pma_ppm_lock(pld_pma_ppm_lock), - .pld_pma_reserved_out(pld_pma_reserved_out), - .pld_pma_rs_lpbk_b(pld_pma_rs_lpbk_b), - .pld_pma_rxpma_rstb(pld_pma_rxpma_rstb), - .pld_pma_tx_bitslip(pld_pma_tx_bitslip), - .pld_pma_txdetectrx(pld_pma_txdetectrx), - .pld_pma_txpma_rstb(pld_pma_txpma_rstb), - .pld_pmaif_rxclkslip(pld_pmaif_rxclkslip), - .pld_polinv_rx(pld_polinv_rx), - .pld_polinv_tx(pld_polinv_tx), - .pld_rx_clk1_rowclk(pld_rx_clk1_rowclk), - .pld_rx_clk2_rowclk(pld_rx_clk2_rowclk), - .pld_rx_dll_lock_req(pld_rx_dll_lock_req), - .pld_rx_fabric_fifo_align_clr(pld_rx_fabric_fifo_align_clr), - .pld_rx_fabric_fifo_rd_en(pld_rx_fabric_fifo_rd_en), - .pld_rx_prbs_err_clr(pld_rx_prbs_err_clr), - .pld_sclk1_rowclk(pld_sclk1_rowclk), - .pld_sclk2_rowclk(pld_sclk2_rowclk), - .pld_syncsm_en(pld_syncsm_en), - .pld_tx_clk1_rowclk(pld_rx_clk1_rowclk), - .pld_tx_clk2_rowclk(pld_rx_clk2_rowclk), - .pld_tx_fabric_data_in(pld_rx_fabric_data_out), //Loopback from rx - .pld_txelecidle(pld_txelecidle), - .pld_tx_dll_lock_req(pld_tx_dll_lock_req), - .pld_tx_fifo_latency_adj_en(pld_tx_fifo_latency_adj_en), - .pld_rx_fifo_latency_adj_en(pld_rx_fifo_latency_adj_en), - .pld_aib_fabric_rx_dll_lock_req(pld_aib_fabric_rx_dll_lock_req), - .pld_aib_fabric_tx_dcd_cal_req(pld_aib_fabric_tx_dcd_cal_req), - .pld_aib_hssi_tx_dcd_cal_req(pld_aib_hssi_tx_dcd_cal_req), - .pld_aib_hssi_tx_dll_lock_req(pld_aib_hssi_tx_dll_lock_req), - .pld_aib_hssi_rx_dcd_cal_req(pld_aib_hssi_rx_dcd_cal_req), - .pld_tx_ssr_reserved_in(pld_tx_ssr_reserved_in), - .pld_rx_ssr_reserved_in(pld_rx_ssr_reserved_in), - .pld_pma_tx_qpi_pulldn(pld_pma_tx_qpi_pulldn), - .pld_pma_tx_qpi_pullup(pld_pma_tx_qpi_pullup), - .pld_pma_rx_qpi_pullup(pld_pma_rx_qpi_pullup), - - // PLD DCM input - .pld_rx_clk1_dcm(pld_rx_clk1_dcm), - .pld_tx_clk1_dcm(pld_rx_clk1_dcm), - .pld_tx_clk2_dcm(pld_rx_clk2_dcm), - - // uC AVMM - - // DFT input - .dft_adpt_aibiobsr_fastclkn(1'b1), - .adapter_scan_rst_n(1'b1), - .adapter_scan_mode_n(1'b1), - .adapter_scan_shift_n(1'b1), - .adapter_scan_shift_clk(1'b0), - .adapter_scan_user_clk0(adapter_scan_user_clk0), // 125MHz - .adapter_scan_user_clk1(adapter_scan_user_clk1), // 250MHz - .adapter_scan_user_clk2(adapter_scan_user_clk2), // 500MHz - .adapter_scan_user_clk3(adapter_scan_user_clk3), // 1GHz - .adapter_clk_sel_n(1'b0), - .adapter_occ_enable(1'b0), - .adapter_global_pipe_se(1'b1), - .adapter_config_scan_in(4'h0), - .adapter_scan_in_occ1(2'h0), - .adapter_scan_in_occ2(5'h0), - .adapter_scan_in_occ3(1'b0), - .adapter_scan_in_occ4(1'b0), - .adapter_scan_in_occ5(2'h0), - .adapter_scan_in_occ6(11'h0), - .adapter_scan_in_occ7(1'b0), - .adapter_scan_in_occ8(1'b0), - .adapter_scan_in_occ9(1'b0), - .adapter_scan_in_occ10(1'b0), - .adapter_scan_in_occ11(1'b0), - .adapter_scan_in_occ12(1'b0), - .adapter_scan_in_occ13(1'b0), - .adapter_scan_in_occ14(1'b0), - .adapter_scan_in_occ15(1'b0), - .adapter_scan_in_occ16(1'b0), - .adapter_scan_in_occ17(1'b0), - .adapter_scan_in_occ18(2'h0), - .adapter_scan_in_occ19(1'h0), - .adapter_scan_in_occ20(1'h0), - .adapter_scan_in_occ21(2'h0), - .adapter_non_occ_scan_in(1'b0), - .adapter_occ_scan_in(1'b0), - .dft_fabric_iaibdftcore2dll(3'h0), - - - // DFT output - .adapter_config_scan_out(), - .adapter_scan_out_occ1(), - .adapter_scan_out_occ2(), - .adapter_scan_out_occ3(), - .adapter_scan_out_occ4(), - .adapter_scan_out_occ5(), - .adapter_scan_out_occ6(), - .adapter_scan_out_occ7(), - .adapter_scan_out_occ8(), - .adapter_scan_out_occ9(), - .adapter_scan_out_occ10(), - .adapter_scan_out_occ11(), - .adapter_scan_out_occ12(), - .adapter_scan_out_occ13(), - .adapter_scan_out_occ14(), - .adapter_scan_out_occ15(), - .adapter_scan_out_occ16(), - .adapter_scan_out_occ17(), - .adapter_scan_out_occ18(), - .adapter_scan_out_occ19(), - .adapter_scan_out_occ20(), - .adapter_scan_out_occ21(), - .adapter_non_occ_scan_out(), - .adapter_occ_scan_out(), - .dft_fabric_oaibdftdll2core(), - - // Adapter output - .bond_rx_asn_ds_out_fifo_hold(), - .bond_rx_asn_us_out_fifo_hold(), - .bond_rx_fifo_ds_out_rden(), - .bond_rx_fifo_ds_out_wren(), - .bond_rx_fifo_us_out_rden(), - .bond_rx_fifo_us_out_wren(), - .bond_rx_hrdrst_ds_out_fabric_rx_dll_lock(), - .bond_rx_hrdrst_us_out_fabric_rx_dll_lock(), - .bond_rx_hrdrst_ds_out_fabric_rx_dll_lock_req(), - .bond_rx_hrdrst_us_out_fabric_rx_dll_lock_req(), - .bond_tx_fifo_ds_out_dv(), - .bond_tx_fifo_ds_out_rden(), - .bond_tx_fifo_ds_out_wren(), - .bond_tx_fifo_us_out_dv(), - .bond_tx_fifo_us_out_rden(), - .bond_tx_fifo_us_out_wren(), - .bond_tx_hrdrst_ds_out_fabric_tx_dcd_cal_done(), - .bond_tx_hrdrst_us_out_fabric_tx_dcd_cal_done(), - .bond_tx_hrdrst_ds_out_fabric_tx_dcd_cal_req(), - .bond_tx_hrdrst_us_out_fabric_tx_dcd_cal_req(), - // Config output - .csr_clk_out(), - .csr_out(), - .csr_pipe_out(), - .csr_rdy_dly_out(), - .csr_rdy_out(), - .nfrzdrv_out(), - .usermode_out(), - // PLD output - .hip_aib_fsr_out(), - .hip_aib_ssr_out(), - .hip_avmm_readdata(), - .hip_avmm_readdatavalid(), - .hip_avmm_writedone(), - .hip_avmm_reserved_out(), - .pld_10g_krfec_rx_blk_lock(), - .pld_10g_krfec_rx_diag_data_status(), - .pld_10g_krfec_rx_frame(), - .pld_10g_krfec_tx_frame(), - .pld_krfec_tx_alignment(), - .pld_10g_rx_crc32_err(), - .pld_rx_fabric_fifo_insert(), - .pld_rx_fabric_fifo_del(), + .ms_ns_adapter_rstn(pld_adapter_tx_pld_rst_n), + .sl_ns_adapter_rstn(pld_adapter_tx_pld_rst_n), + .ms_ns_mac_rdy(pld_adapter_rx_pld_rst_n), + .sl_ns_mac_rdy(pld_adapter_rx_pld_rst_n), + .fs_mac_rdy(), - .pld_10g_rx_frame_lock(), - .pld_10g_rx_hi_ber(), - .pld_10g_tx_burst_en_exe(), - .pld_8g_a1a2_k1k2_flag(), - .pld_8g_empty_rmf(), - .pld_8g_full_rmf(), - .pld_8g_rxelecidle(), - .pld_8g_signal_detect_out(), - .pld_8g_wa_boundary(), - .pld_avmm1_busy(), - .pld_avmm1_cmdfifo_wr_full(), - .pld_avmm1_cmdfifo_wr_pfull(), - .pld_avmm1_readdata(), - .pld_avmm1_readdatavalid(), - .pld_avmm1_reserved_out(), - .pld_avmm2_busy(), - .pld_avmm2_cmdfifo_wr_full(), - .pld_avmm2_cmdfifo_wr_pfull(), - .pld_avmm2_readdata(), - .pld_avmm2_readdatavalid(), - .pld_avmm2_reserved_out(), - .pld_chnl_cal_done(), - .pld_fpll_shared_direct_async_out(), - .pld_fpll_shared_direct_async_out_hioint(), - .pld_fpll_shared_direct_async_out_dcm(), - .pld_fsr_load(), - .pld_pcs_rx_clk_out1_hioint(), - .pld_pcs_rx_clk_out2_hioint(), - .pld_pcs_tx_clk_out1_hioint(), - .pld_pcs_tx_clk_out2_hioint(), - .pld_pll_cal_done(), - .pld_pma_adapt_done(), - .pld_pma_fpll_clk0bad(), - .pld_pma_fpll_clk1bad(), - .pld_pma_fpll_clksel(), - .pld_pma_fpll_phase_done(), - .pld_pma_hclk_hioint(), - .pld_pma_internal_clk1_hioint(), - .pld_pma_internal_clk2_hioint(), - .pld_pma_pcie_sw_done(), - .pld_pma_pfdmode_lock(), - .pld_pma_reserved_in(), - .pld_pma_rx_detect_valid(), - .pld_pma_rx_found(), - .pld_pma_rxpll_lock(), - .pld_pma_signal_ok(), - .pld_pma_testbus(), - .pld_pmaif_mask_tx_pll(), - .pld_rx_fabric_align_done(), - .pld_rx_fabric_data_out(pld_rx_fabric_data_out), - .pld_rx_fabric_fifo_empty(), - .pld_rx_fabric_fifo_full(), - .pld_rx_fabric_fifo_latency_pulse(), - .pld_rx_fabric_fifo_pempty(), - .pld_rx_fabric_fifo_pfull(), - .pld_rx_hssi_fifo_empty(), - .pld_rx_hssi_fifo_full(), - .pld_rx_hssi_fifo_latency_pulse(), - .pld_rx_prbs_done(), - .pld_rx_prbs_err(), - .pld_ssr_load(), - .pld_test_data(), - .pld_tx_fabric_fifo_empty(), - .pld_tx_fabric_fifo_full(), - .pld_tx_fabric_fifo_latency_pulse(), - .pld_tx_fabric_fifo_pempty(), - .pld_tx_fabric_fifo_pfull(), - .pld_tx_hssi_align_done(), - .pld_tx_hssi_fifo_empty(), - .pld_tx_hssi_fifo_full(), - .pld_tx_hssi_fifo_latency_pulse(), - .pld_hssi_osc_transfer_en(), - .pld_hssi_rx_transfer_en(), - .pld_fabric_tx_transfer_en(), - .pld_aib_fabric_rx_dll_lock(), - .pld_aib_fabric_tx_dcd_cal_done(), - .pld_aib_hssi_rx_dcd_cal_done(), - .pld_aib_hssi_tx_dcd_cal_done(), - .pld_aib_hssi_tx_dll_lock(), - .pld_hssi_asn_dll_lock_en(), - .pld_fabric_asn_dll_lock_en(), - .pld_tx_ssr_reserved_out(), - .pld_rx_ssr_reserved_out(), - - // PLD DCM output - .pld_pcs_rx_clk_out1_dcm(), - .pld_pcs_rx_clk_out2_dcm(), - .pld_pcs_tx_clk_out1_dcm(), - .pld_pcs_tx_clk_out2_dcm(), + .ms_config_done(1'b1), + .ms_rx_dcc_dll_lock_req(1'b0), + .ms_tx_dcc_dll_lock_req(1'b0), + .sl_config_done(pld_adapter_rx_pld_rst_n), + .sl_rx_dcc_dll_lock_req(pld_rx_dll_lock_req), + .sl_tx_dcc_dll_lock_req(pld_tx_dll_lock_req), + .ms_tx_transfer_en(), + .ms_rx_transfer_en(), + .sl_tx_transfer_en(), + .sl_rx_transfer_en(), + .sr_ms_tomac(), + .sr_sl_tomac(), + .ms_nsl(1'b0), + + .iddren(1'b1), + .idataselb(1'b0), //output async data selection + .itxen(1'b1), //data tx enable + .irxen(3'b111),//data input enable + + .ms_device_detect(), + .sl_por(pld_adapter_rx_pld_rst_n), + + .jtag_clkdr_in(1'b0), + .scan_out(), + .jtag_intest(1'b0), + .jtag_mode_in(1'b0), + .jtag_rstb(1'b0), + .jtag_rstb_en(1'b0), + .jtag_weakpdn(1'b0), + .jtag_weakpu(1'b0), + .jtag_tx_scanen_in(1'b0), + .scan_in(1'b0), - //JTAG input - .iatpg_pipeline_global_en(1'b1), - .iatpg_scan_clk_in0(1'b1), - .iatpg_scan_clk_in1(1'b1), - .iatpg_scan_in0(1'b0), - .iatpg_scan_in1(1'b0), - .iatpg_scan_shift_n(1'b1), - .iatpg_scan_mode_n(1'b1), - .iatpg_scan_rst_n(1'b1), - .ijtag_clkdr_in_chain(1'b0), - .ijtag_last_bs_in_chain(1'b0), - .ijtag_tx_scan_in_chain(1'b0), - .ired_directin_data_in_chain1(ired_directin_data_in_chain1), - .ired_directin_data_in_chain2(ired_directin_data_in_chain2), - .ired_irxen_in_chain1(ired_irxen_in_chain1), - .ired_irxen_in_chain2(ired_irxen_in_chain2), - .ired_shift_en_in_chain1(ired_shift_en_in_chain1), - .ired_shift_en_in_chain2(ired_shift_en_in_chain2), - .jtag_clksel(1'b0), - .jtag_intest(1'b0), - .jtag_mode_in(1'b0), - .jtag_rstb(1'b1), - .jtag_rstb_en(1'b0), - .jtag_tx_scanen_in(1'b0), - .jtag_weakpdn(1'b0), - .jtag_weakpu(1'b0), + //Redundancy control signals + `include "redundancy_ctrl_sim.vh" + .sl_external_cntl_26_0({1'b1,26'b0}), + .sl_external_cntl_30_28(3'b0), + .sl_external_cntl_57_32(26'b0), - //Jtag output - .jtag_clksel_out(), - .jtag_intest_out(), - .jtag_mode_out(), - .jtag_rstb_en_out(), - .jtag_rstb_out(), - .jtag_tx_scanen_out(), - .jtag_weakpdn_out(), - .jtag_weakpu_out(), - .oatpg_scan_out0(), - .oatpg_scan_out1(), - .ojtag_clkdr_out_chain(), - .ojtag_last_bs_out_chain(), - .ojtag_rx_scan_out_chain(), - .ored_directin_data_out0_chain1(), - .ored_directin_data_out0_chain2(), - .ored_rxen_out_chain1(), - .ored_rxen_out_chain2(), - .ored_shift_en_out_chain1(), - .ored_shift_en_out_chain2() -); - + .ms_external_cntl_4_0(5'b0), + .ms_external_cntl_65_8(58'b0), + .vccl_aib(1'b1), + .vssl_aib(1'b0)); +`endif diff --git a/ndsimslv/runnc b/ndsimslv/runnc index f8d8ca5..fbdcd27 100644 --- a/ndsimslv/runnc +++ b/ndsimslv/runnc @@ -1,3 +1,3 @@ rm -rf INCA_libs -irun -sv -timescale 1ps/1ps -f ./multidie.f ./top.sv ./dut_io.sv ./test.sv -vlog_ext +.vh +define+TIMESCALE_EN -access rwc -input sim_input.tcl +irun -sv -timescale 1ps/1ps -f ./multidie.f ./top.sv ./dut_io.sv ./test.sv -vlog_ext +.vh +define+TIMESCALE_EN+ALTR_HPS_INTEL_MACROS_OFF+S10_MODEL -access rwc -input sim_input.tcl diff --git a/ndsimslv/runsim b/ndsimslv/runsim index 37e3765..41e5367 100644 --- a/ndsimslv/runsim +++ b/ndsimslv/runsim @@ -1,3 +1,3 @@ #!/bin/csh -fb rm -rf csrc simv simv.daidir -vcs -sverilog +v2k -full64 +vcs+vcdpluson -timescale=1ps/1ps +define+VCS+TIMESCALE_EN -f ./multidie.f ./top.sv ./dut_io.sv ./test.sv -l compile.log +vcs -sverilog +v2k -full64 +vcs+vcdpluson -timescale=1ps/1ps +define+VCS+TIMESCALE_EN+ALTR_HPS_INTEL_MACROS_OFF+S10_MODEL+REGISTER_MOD -f ./multidie.f ./top.sv ./dut_io.sv ./test.sv -l compile.log diff --git a/ndsimslv/self_test.do b/ndsimslv/self_test.do index 97747ed..bb2ddbf 100644 --- a/ndsimslv/self_test.do +++ b/ndsimslv/self_test.do @@ -2,6 +2,7 @@ onerror resume vlib work do vlog.do vsim -t 1ps top +add log -r vsim:/top/* add wave dut/* run -a quit diff --git a/ndsimslv/test.sv b/ndsimslv/test.sv index 27ba986..20735a6 100644 --- a/ndsimslv/test.sv +++ b/ndsimslv/test.sv @@ -243,7 +243,7 @@ program automatic test (dut_io.TB dut); bit [39:0] data = 0; while (toggle_gen < run_for_n_wa_cycle) begin - $display ("[%t] Generating data[%d] for naddar alignemnt = %x \n", $time, toggle_gen, data); + $display ("[%t] Generating data[%d] for slave alignemnt = %x \n", $time, toggle_gen, data); @(posedge top.i_rx_pma_clk); dut.cb_rx_pma.i_rx_pma_data <= data; diff --git a/ndsimslv/top.sv b/ndsimslv/top.sv index 918331d..8b2a9e9 100644 --- a/ndsimslv/top.sv +++ b/ndsimslv/top.sv @@ -2,7 +2,9 @@ // Copyright (C) 2019 Intel Corporation. All rights reserved `timescale 1ps/1fs -`define NDADAPT_RTB ndut.hdpldadapt +`ifdef S10_MODEL + `define NDADAPT_RTB top.s10_wrap.ndut.hdpldadapt +`endif `include "c3dfx.vh" module top; @@ -13,8 +15,11 @@ module top; parameter CFG_AVMM_CLK_PERIOD = 4000; parameter OSC_CLK_PERIOD = 1000; +`ifdef REGISTER_MOD + parameter PMA_CLK_PERIOD = 4000; +`else parameter PMA_CLK_PERIOD = 1000; - +`endif reg i_cfg_avmm_clk = 1'b0; reg i_osc_clk = 1'b0; reg i_rx_pma_clk = 1'b0; @@ -101,103 +106,63 @@ module top; //================================================================================= // AIB IOs - wire aib0; - wire aib1; - wire aib10; - wire aib11; - wire aib12; - wire aib13; - wire aib14; - wire aib15; - wire aib16; - wire aib17; - wire aib18; - wire aib19; - wire aib2; - wire aib20; - wire aib21; - wire aib22; - wire aib23; - wire aib24; - wire aib25; - wire aib26; - wire aib27; - wire aib28; - wire aib29; - wire aib3; - wire aib30; - wire aib31; - wire aib32; - wire aib33; - wire aib34; - wire aib35; - wire aib36; - wire aib37; - wire aib38; - wire aib39; - wire aib4; - wire aib40; - wire aib41; - wire aib42; - wire aib43; - wire aib44; - wire aib45; - wire aib46; - wire aib47; - wire aib48; - wire aib49; - wire aib5; - wire aib50; - wire aib51; - wire aib52; - wire aib53; - wire aib54; - wire aib55; - wire aib56; - wire aib57; - wire aib58; - wire aib59; - wire aib6; - wire aib60; - wire aib61; - wire aib62; - wire aib63; - wire aib64; - wire aib65; - wire aib66; - wire aib67; - wire aib68; - wire aib69; - wire aib7; - wire aib70; - wire aib71; - wire aib72; - wire aib73; - wire aib74; - wire aib75; - wire aib76; - wire aib77; - wire aib78; - wire aib79; - wire aib8; - wire aib80; - wire aib81; - wire aib82; - wire aib83; - wire aib84; - wire aib85; - wire aib86; - wire aib87; - wire aib88; - wire aib89; - wire aib9; - wire aib90; - wire aib91; - wire aib92; - wire aib93; - wire aib94; - wire aib95; + wire[19:0] ms_iopad_tx; + wire[19:0] ms_iopad_rx; + wire ms_iopad_ns_fwd_clkb; + wire ms_iopad_ns_fwd_clk; + wire ms_iopad_fs_fwd_clkb; + wire ms_iopad_fs_fwd_clk; + wire ms_iopad_fs_mac_rdy; + wire ms_iopad_ns_mac_rdy; + wire ms_iopad_ns_adapter_rstn; + wire ms_iopad_fs_rcv_clk; + wire ms_iopad_fs_rcv_clkb; + wire ms_iopad_fs_adapter_rstn; + wire ms_iopad_fs_sr_clkb; + wire ms_iopad_fs_sr_clk; + wire ms_iopad_ns_sr_clk; + wire ms_iopad_ns_sr_clkb; + wire ms_iopad_ns_rcv_clkb; + wire ms_iopad_ns_rcv_clk; + wire ms_iopad_fs_sr_load; + wire ms_iopad_fs_sr_data; + wire ms_iopad_ns_sr_load; + wire ms_iopad_ns_sr_data; +`ifdef S10_MODEL + wire iopad_unused_aib45; + wire iopad_unused_aib46; + wire iopad_unused_aib47; + wire iopad_unused_aib50; + wire iopad_unused_aib51; + wire iopad_unused_aib52; + wire iopad_unused_aib58; + wire iopad_unused_aib60; + wire iopad_unused_aib61; + wire iopad_unused_aib62; + wire iopad_unused_aib63; + wire iopad_unused_aib64; + wire iopad_unused_aib66; + wire iopad_unused_aib67; + wire iopad_unused_aib68; + wire iopad_unused_aib69; + wire iopad_unused_aib70; + wire iopad_unused_aib71; + wire iopad_unused_aib72; + wire iopad_unused_aib73; + wire iopad_unused_aib74; + wire iopad_unused_aib75; + wire iopad_unused_aib76; + wire iopad_unused_aib77; + wire iopad_unused_aib78; + wire iopad_unused_aib79; + wire iopad_unused_aib80; + wire iopad_unused_aib81; + wire iopad_unused_aib88; + wire iopad_unused_aib89; + wire iopad_unused_aib90; + wire iopad_unused_aib91; +`endif /*AUTOWIRE*/ @@ -317,30 +282,67 @@ module top; .o_directout_data_chain2_out(o_directout_data_chain2_out), .o_aibdftdll2adjch (o_aibdftdll2adjch[12:0]), // Inouts - .iopad_tx ({aib19,aib18,aib17,aib16,aib15,aib14,aib13,aib12,aib11,aib10, - aib9, aib8, aib7, aib6, aib5, aib4, aib3, aib2, aib1, aib0}), - .iopad_rx ({aib39,aib38,aib37,aib36,aib35,aib34,aib33,aib32,aib31,aib30, - aib29,aib28,aib27,aib26,aib25,aib24,aib23,aib22,aib21,aib20}), - .iopad_ns_fwd_clkb (aib40), - .iopad_ns_fwd_clk (aib41), - .iopad_fs_fwd_clkb (aib42), - .iopad_fs_fwd_clk (aib43), - .iopad_fs_mac_rdy (aib44), - .iopad_ns_mac_rdy (aib49), - .iopad_ns_adapt_rstn (aib56), - .iopad_fs_rcv_clk (aib57), - .iopad_fs_rcv_clkb (aib59), - .iopad_fs_adapt_rstn (aib65), - .iopad_fs_sr_clkb (aib82), - .iopad_fs_sr_clk (aib83), - .iopad_ns_sr_clk (aib84), - .iopad_ns_sr_clkb (aib85), - .iopad_ns_rcv_clkb (aib86), - .iopad_ns_rcv_clk (aib87), - .iopad_fs_sr_load (aib92), - .iopad_fs_sr_data (aib93), - .iopad_ns_sr_load (aib94), - .iopad_ns_sr_data (aib95), + .iopad_tx (ms_iopad_tx), + .iopad_rx (ms_iopad_rx), + .iopad_ns_fwd_clkb (ms_iopad_ns_fwd_clkb), + .iopad_ns_fwd_clk (ms_iopad_ns_fwd_clk), + .iopad_ns_fwd_div2_clkb(ms_iopad_ns_fwd_div2_clkb), + .iopad_ns_fwd_div2_clk (ms_iopad_ns_fwd_div2_clk), + .iopad_fs_fwd_clkb (ms_iopad_fs_fwd_clkb), + .iopad_fs_fwd_clk (ms_iopad_fs_fwd_clk), + .iopad_fs_mac_rdy (ms_iopad_fs_mac_rdy), + .iopad_ns_mac_rdy (ms_iopad_ns_mac_rdy), + .iopad_ns_adapter_rstn (ms_iopad_ns_adapter_rstn), + .iopad_fs_rcv_clk (ms_iopad_fs_rcv_clk), + .iopad_fs_rcv_clkb (ms_iopad_fs_rcv_clkb), + .iopad_fs_adapter_rstn (ms_iopad_fs_adapter_rstn), + .iopad_fs_sr_clkb (ms_iopad_fs_sr_clkb), + .iopad_fs_sr_clk (ms_iopad_fs_sr_clk), + .iopad_ns_sr_clk (ms_iopad_ns_sr_clk), + .iopad_ns_sr_clkb (ms_iopad_ns_sr_clkb), + .iopad_ns_rcv_clkb (ms_iopad_ns_rcv_clkb), + .iopad_ns_rcv_clk (ms_iopad_ns_rcv_clk), + .iopad_ns_rcv_div2_clkb(ms_iopad_ns_rcv_div2_clkb), + .iopad_ns_rcv_div2_clk (ms_iopad_ns_rcv_div2_clk), + .iopad_fs_sr_load (ms_iopad_fs_sr_load), + .iopad_fs_sr_data (ms_iopad_fs_sr_data), + .iopad_ns_sr_load (ms_iopad_ns_sr_load), + .iopad_ns_sr_data (ms_iopad_ns_sr_data), +`ifdef S10_MODEL + .iopad_unused_aib45, + .iopad_unused_aib46, + .iopad_unused_aib47, + .iopad_unused_aib50, + .iopad_unused_aib51, + .iopad_unused_aib52, + .iopad_unused_aib58, + .iopad_unused_aib60, + .iopad_unused_aib61, + .iopad_unused_aib62, + .iopad_unused_aib63, + .iopad_unused_aib64, + .iopad_unused_aib66, + .iopad_unused_aib67, + .iopad_unused_aib68, + .iopad_unused_aib69, + .iopad_unused_aib70, + .iopad_unused_aib71, + .iopad_unused_aib72, + .iopad_unused_aib73, + .iopad_unused_aib74, + .iopad_unused_aib75, + .iopad_unused_aib76, + .iopad_unused_aib77, + .iopad_unused_aib78, + .iopad_unused_aib79, + .iopad_unused_aib80, + .iopad_unused_aib81, + .iopad_unused_aib88, + .iopad_unused_aib89, + .iopad_unused_aib90, + .iopad_unused_aib91, + +`endif // Inputs .i_adpt_hard_rst_n (top_io.i_adpt_hard_rst_n), diff --git a/ndsimslv/vlog.do b/ndsimslv/vlog.do index 7f99464..e0b2a31 100644 --- a/ndsimslv/vlog.do +++ b/ndsimslv/vlog.do @@ -1,386 +1,577 @@ -set AIB_LIB ../aib_lib -set MODEL_RTL ../rtl - -vlog +acc -sv $AIB_LIB/c3lib/rtl/defines/c3lib_dv_defines.sv +incdir+$AIB_LIB/c3lib/rtl/defines -vlog +acc -sv $AIB_LIB/c3dfx/rtl/defines/c3dfx.vh +incdir+$AIB_LIB/c3dfx/rtl/defines - -## pointer to standalone DCC - DCC, c3 and DLL pnr block -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_8ph_intp.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_crsdlyline.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_dll.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_dlyline64.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_dlyline.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_dly.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_gry2thm64.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_helper.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_interpolator.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_phasedet.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_top.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_dll_custom.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_dll_lock_dly.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_dlycell_dcc.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_svt16_scdffcdn_cust.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_svt16_scdffsdn_cust.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_ulvt16_2xarstsyncdff1_b2.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_ulvt16_dffcdn_cust.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_io_cmos_nand_x64.v - -##aibcr3 model - -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_top_wrp.v - -## this section is for strobe align circuits - -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_str_align.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_clktree_mimic.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_clktree.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_cmos_nand_x64.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_dll_8ph_intp.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_dll_dlyline64.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_dll_gry2thm64.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_dll_ibkmux.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_dlycell_dll.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_dlycell_dll_c.v - -## other aibcr models -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_scan_iomux.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_2to4dec.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_analog.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_avmm1.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_avmm2.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_buffx1_top.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_buffx1.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_clktree_avmm_mimic.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_clktree_avmm_pcs.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_clktree_avmm.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_clktree_pcs.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_cmos_fine_dly.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_cmos_nand_x1.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_io_ip8phs.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_digital.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_inv_split_align.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_lvshift.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_preclkbuf.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_quadph_code_gen.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_rxanlg.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_rxdatapath_rx.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_rxdig.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_top.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_txanlg.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_txdatapath_tx.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_txdig.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_nd2d0_custom.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/aibcr3_split_align.v -vlog +acc $AIB_LIB/aibcr3_lib/rtl/structured.v - -## NEW for converted RTL (removed logic cells) - -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_ff_r.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_ff_p.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_ff_rp.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_latch.v - - -## NEW REL3.5 - -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_red_custom_dig.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_str_ff.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_sync_ff.v - - -##newly added - -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_top_dummy.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_esd.v - - -##NEW REL4.0 - -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_str_ioload.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_red_custom_dig2.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_red_clkmux2.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_red_clkmux3.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_lvshift_lospeed.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_lvshift_diff.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_triinv_dig.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_interface.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_rambit_buf.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_signal_buf.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_data_buf.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_rxdat_mimic.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_txdat_mimic.v - - -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_dly_rep.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_dly_mimic.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_io_cmos_8ph_interpolator_rep.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_io_cmos_8ph_interpolator.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_io_nand_delay_line_min_rep.v - -##copied models due to io_common_custom ND and CR conflict - -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_io_cmos_nand_x1.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_io_cmos_nand_x128.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_io_nand_delay_line_min.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_io_nand_x128_delay_line.v - -##NEW REL4.5 -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_clkmux2.v - - -##NEW REL4.5 (replacing syncronizer- 3rd party cell issue) - -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_sync_2ff.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_sync_3ff.v - -##custom alias model - -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_aliasv.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_aliasd.v - - -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_ulvt16_dffsdn_cust.v - -## custom esd cells used outside of aibio and aibaux. sits in xcvrcntl -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_opio_esd.v -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_anaio_esd.v - -## update for conformal -vlog +acc -sv $AIB_LIB/aibcr3_lib/rtl/aibcr3_dlycell_dcc_rep.v - -vlog +acc -sv $AIB_LIB/c3lib/rtl/basic/pulse_stretch/cdclib_pulse_stretch.sv - -vlog +acc -sv $AIB_LIB/c3lib/rtl/avmm/c3_avmm_rdl_intf.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/avmm/c3lib_cfgcsr_fastslow_pulse_meta.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/avmm/c3lib_cfgcsr_slowfast_pulse_meta.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/avmm/c3lib_avmm_pulse_cross.sv - -vlog +acc -sv $AIB_LIB/c3lib/rtl/cdc/async_fifo/c3lib_async_fifo.sv - -vlog +acc -sv $AIB_LIB/c3lib/rtl/cdc/bit_synchronizer/c3lib_bitsync.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/cdc/bit_synchronizer/c3lib_sync2_lvt_bitsync.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/cdc/bit_synchronizer/c3lib_sync2_ulvt_bitsync.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/cdc/bit_synchronizer/c3lib_sync3_ulvt_bitsync.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/cdc/gray_code/c3lib_bintogray.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/cdc/gray_code/c3lib_graytobin.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/cdc/level_synchronizer/c3lib_lvlsync.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/cdc/reset_synchronizer/c3lib_rstsync.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/cdc/vector_synchronizer/c3lib_vecsync.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/cdc/vector_synchronizer/c3lib_vecsync_handshake.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/cdc/glitch_free_mux/c3lib_gf_clkmux.sv - -vlog +acc -sv $AIB_LIB/c3lib/rtl/ctn/clock_buf/c3lib_ckinv_ctn.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/ctn/clock_buf/c3lib_ckbuf_ctn.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/ctn/clock_buf/c3lib_ckand2_ctn.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/ctn/clock_gater/c3lib_ckg_async_posedge_ctn.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/ctn/clock_gater/c3lib_ckg_negedge_ctn.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/ctn/clock_gater/c3lib_ckg_posedge_ctn.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/ctn/clock_mux/c3lib_mux2_ctn.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/ctn/clock_mux/c3lib_mux3_ctn.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/ctn/clock_mux/c3lib_mux4_ctn.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/ctn/clock_divider/c3lib_ckdiv2_ctn.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/ctn/clock_divider/c3lib_ckdiv4_ctn.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/ctn/clock_divider/c3lib_ckdiv8_ctn.sv - -vlog +acc -sv $AIB_LIB/c3lib/rtl/lcell/c3lib_and2_lcell.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/lcell/c3lib_buf_lcell.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/lcell/c3lib_mux2_lcell.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/lcell/c3lib_nand2_lcell.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/lcell/c3lib_or2_lcell.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/lcell/c3lib_tie_bus_lcell.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/lcell/c3lib_tieh_lcell.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/lcell/c3lib_tiel_lcell.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/lcell/c3lib_mtieh_lcell.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/lcell/c3lib_mtiel_lcell.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/lcell/c3lib_dff_scan_lcell.sv - -vlog +acc -sv $AIB_LIB/c3lib/rtl/ecc/c3lib_ecc_dec_c39_d32.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/ecc/c3lib_ecc_dec_c88_d80.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/ecc/c3lib_ecc_enc_d32_c39.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/ecc/c3lib_ecc_enc_d80_c88.sv - -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_sync2_reset_lvt_gate.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_sync2_reset_ulvt_gate.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_sync3_reset_ulvt_gate.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_sync2_set_lvt_gate.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_sync2_set_ulvt_gate.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_sync3_set_ulvt_gate.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_tie0_svt_1x.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_tie1_svt_1x.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_mtie0_ds.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_mtie1_ds.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_or2_svt_2x.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_nand2_svt_2x.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_mux2_svt_2x.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_ckmux4_ulvt_gate.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_ckmux4_lvt_gate.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_ckinv_lvt_12x.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_ckinv_svt_8x.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_ckg_lvt_8x.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_ckbuf_lvt_4x.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_buf_svt_4x.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_and2_svt_2x.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_and2_svt_4x.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_dff0_reset_lvt_2x.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_dff0_set_lvt_2x.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_dff0_scan_reset_svt_2x.sv -vlog +acc -sv $AIB_LIB/c3lib/rtl/primitives/c3lib_sync_metastable_behav_gate.sv - -vlog $AIB_LIB/c3dfx/rtl/defines/c3dfx.vh $AIB_LIB/c3dfx/rtl/tcm/c3dfx_tcm_wrap.sv -#vlog $AIB_LIB/c3dfx/rtl/defines/c3dfx.vh $AIB_LIB/c3dfx/rtl/tcm/c3dfx_tcm_wrap.sv +incdir+$AIB_LIB/c3dfx/rtl/defines -vlog +acc -sv $AIB_LIB/c3dfx/rtl/tcm/c3dfx_tcm.sv -vlog $AIB_LIB/c3dfx/rtl/defines/c3dfx.vh $AIB_LIB/c3aibadapt/rtl/c3aibadapt.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1_async.v -vlog $AIB_LIB/c3dfx/rtl/defines/c3dfx.vh $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1clk_ctl.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1_config.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_hwcfg_dec.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_cfg_csr.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_usr_csr.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1_transfer.v -vlog $AIB_LIB/c3dfx/rtl/defines/c3dfx.vh $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2_async.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2clk_ctl.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2_config.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2_transfer.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_async.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_cfg_rdmux.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmmclk_dcg.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmmclk_gate.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_cmdbuilder.sv -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_dec_arb.sv -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_decode.sv -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_rdfifo.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmmrst_ctl.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_usr32_exp.sv -vlog $AIB_LIB/c3dfx/rtl/defines/c3dfx.vh $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_hrdrst_clkctl.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_hrdrst_rstctrl.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_async_capture_bit.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_async_capture_bus.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkand2.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkgate_high.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkgate.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkinv.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkmux2_cell.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkmux2.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_comp_cntr.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_dist_dw.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_dist_pair_dw.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_dist_pair.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_dist.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_dft_clk_ctlr.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_latency_measure.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_occ_clkgate.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_occ_enable_logic.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_occ_gray_cntr.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_occ_test_ctlregs.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_parity_checker.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_parity_gen.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_pulse_stretch.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_dprio_status_sync_regs.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_shadow_status_regs.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_capture.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_direct.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_rsvd_capture.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_rsvd_update.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_update.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxchnl_testbus.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxchnl.v -vlog $AIB_LIB/c3dfx/rtl/defines/c3dfx.vh $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxclk_ctl.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxclk_gate.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_asn.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_async_fifo.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_cp_bond.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_del_sm.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_fifo_ptr.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_fifo_ram.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_fifo.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_map.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rx_dprio.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_rxeq_sm.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_txeq_sm.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_txeq.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxrst_ctl.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_fsr_in.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_fsr_out.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_async_capture_bit.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_async_capture_bus.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_srclk_ctl.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_in_bit.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_out_bit.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_srrst_ctl.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_sm.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_ssr_in.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_ssr_out.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_async_update.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_hip_async_capture.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_hip_async_update.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_capture.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_direct.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_rsvd_capture.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_rsvd_update.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_update.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txchnl_testbus.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txchnl.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txclk_ctl.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txclk_gate.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_async_fifo.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_cp_bond.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_fifo_ptr.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_fifo_ram.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_fifo.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_map.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_tx_dprio.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_word_align.v -vlog +acc -sv $AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txrst_ctl.v - -vlog +acc -sv $AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_redundancy.v -vlog +acc -sv $AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_jtag_bscan.v -vlog +acc -sv $AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_bsr_red_wrap.v - -vlog +acc -sv $AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_half_cycle_code_gen.v -vlog +acc -sv $AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_self_lock_assertion.v -vlog +acc -sv $AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_dll_ctrl.v -vlog +acc -sv $AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_dll_core.v -vlog +acc -sv $AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_dll_pnr.v -vlog +acc -sv $AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_rstsync.sv - -vlog $AIB_LIB/c3dfx/rtl/defines/c3dfx.vh $AIB_LIB/c3dfx/rtl/tcb/c3dfx_aibadaptwrap_tcb.sv -vlog +acc $AIB_LIB/c3dfx/rtl/defines/c3dfx.vh $AIB_LIB/c3aibadapt_wrap/rtl/c3aibadapt_wrap.v - -vlog +acc -sv ./ndaibadapt_wrap.v -vlog +acc -sv ./hdpldadapt.v - -vlog +acc $MODEL_RTL/dll.sv $MODEL_RTL/aib_io_buffer.sv -vlog +acc $MODEL_RTL/aib_dcc.v -vlog +acc $MODEL_RTL/aib_aux_channel.v -vlog +acc $MODEL_RTL/aib_bitsync.v -vlog +acc $MODEL_RTL/aib_bsr_red_wrap.v -vlog +acc $MODEL_RTL/aib_buffx1_top.v -vlog +acc $MODEL_RTL/aib_ioring.v -vlog +acc $MODEL_RTL/aib_jtag_bscan.v -vlog +acc $MODEL_RTL/aib_mux21.v -vlog +acc $MODEL_RTL/aib_osc_clk.sv -vlog +acc $MODEL_RTL/aib_redundancy.v -vlog +acc $MODEL_RTL/aib_rstnsync.v -vlog +acc $MODEL_RTL/aib_sm.v -vlog +acc $MODEL_RTL/aib_sr_ms.v -vlog +acc $MODEL_RTL/aib_sr_sl.v -vlog +acc $MODEL_RTL/aib_channel.v -vlog +acc $MODEL_RTL/aib.v -#vlog +acc -sv ./dut_io.sv -vlog +acc -sv ./hdpldadapt.v -#vlog +acc -sv ./nda_drv.sv -vlog +acc -sv ./ndaibadapt_wrap.v -#vlog +acc -sv ./nda_port.sv -vlog +acc -sv ./ndut_declare.sv -#vlog +acc -sv ./ndut_default.sv -vlog +acc -sv ./ndut_io.sv -vlog +acc -sv ./test.sv -vlog +acc -sv ./dut_io.sv ./top.sv +incdir+$AIB_LIB/c3dfx/rtl/defines +set AIB_LIB ../aib_lib +set MODEL_RTL ../rtl +vlog -mfcu -sv +acc +define+S10_MODEL+ALTR_HPS_INTEL_MACROS_OFF+TIMESCALE_EN ./dut_io.sv ./test.sv ./top.sv \ ++incdir+$AIB_LIB/c3dfx/rtl/defines +incdir+./ \ +$AIB_LIB/c3lib/rtl/defines/c3lib_dv_defines.sv +incdir+$AIB_LIB/c3lib/rtl/defines \ +$AIB_LIB/c3dfx/rtl/defines/c3dfx.vh +incdir+$AIB_LIB/c3dfx/rtl/defines \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_8ph_intp.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_crsdlyline.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_dll.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_dlyline64.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_dlyline.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_dly.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_gry2thm64.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_helper.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_interpolator.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_phasedet.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_top.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dll_custom.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dll_lock_dly.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dlycell_dcc.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_svt16_scdffcdn_cust.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_svt16_scdffsdn_cust.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_ulvt16_2xarstsyncdff1_b2.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_ulvt16_dffcdn_cust.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_io_cmos_nand_x64.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_top_wrp.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_str_align.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_clktree_mimic.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_clktree.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_cmos_nand_x64.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dll_8ph_intp.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dll_dlyline64.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dll_gry2thm64.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dll_ibkmux.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dlycell_dll.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dlycell_dll_c.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_scan_iomux.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_2to4dec.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_analog.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_avmm1.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_avmm2.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_buffx1_top.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_buffx1.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_clktree_avmm_mimic.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_clktree_avmm_pcs.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_clktree_avmm.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_clktree_pcs.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_cmos_fine_dly.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_cmos_nand_x1.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_io_ip8phs.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_digital.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_inv_split_align.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_lvshift.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_preclkbuf.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_quadph_code_gen.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_rxanlg.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_rxdatapath_rx.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_rxdig.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_top.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_txanlg.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_txdatapath_tx.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_txdig.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_nd2d0_custom.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_split_align.v \ +$AIB_LIB/aibcr3_lib/rtl/structured.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_ff_r.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_ff_p.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_ff_rp.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_latch.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_red_custom_dig.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_str_ff.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_sync_ff.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_top_dummy.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_esd.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_str_ioload.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_red_custom_dig2.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_red_clkmux2.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_red_clkmux3.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_lvshift_lospeed.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_lvshift_diff.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_triinv_dig.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_interface.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_rambit_buf.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_signal_buf.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_data_buf.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_rxdat_mimic.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_txdat_mimic.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dcc_dly_rep.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dly_mimic.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_io_cmos_8ph_interpolator_rep.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_io_cmos_8ph_interpolator.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_io_nand_delay_line_min_rep.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_io_cmos_nand_x1.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_io_cmos_nand_x128.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_io_nand_delay_line_min.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_io_nand_x128_delay_line.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_clkmux2.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_sync_2ff.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_sync_3ff.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_aliasv.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_aliasd.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_ulvt16_dffsdn_cust.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_opio_esd.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_anaio_esd.v \ +$AIB_LIB/aibcr3_lib/rtl/aibcr3_dlycell_dcc_rep.v \ +$AIB_LIB/c3lib/rtl/basic/pulse_stretch/cdclib_pulse_stretch.sv \ +$AIB_LIB/c3lib/rtl/avmm/c3_avmm_rdl_intf.sv \ +$AIB_LIB/c3lib/rtl/avmm/c3lib_cfgcsr_fastslow_pulse_meta.sv \ +$AIB_LIB/c3lib/rtl/avmm/c3lib_cfgcsr_slowfast_pulse_meta.sv \ +$AIB_LIB/c3lib/rtl/avmm/c3lib_avmm_pulse_cross.sv \ +$AIB_LIB/c3lib/rtl/cdc/async_fifo/c3lib_async_fifo.sv \ +$AIB_LIB/c3lib/rtl/cdc/bit_synchronizer/c3lib_bitsync.sv \ +$AIB_LIB/c3lib/rtl/cdc/bit_synchronizer/c3lib_sync2_lvt_bitsync.sv \ +$AIB_LIB/c3lib/rtl/cdc/bit_synchronizer/c3lib_sync2_ulvt_bitsync.sv \ +$AIB_LIB/c3lib/rtl/cdc/bit_synchronizer/c3lib_sync3_ulvt_bitsync.sv \ +$AIB_LIB/c3lib/rtl/cdc/gray_code/c3lib_bintogray.sv \ +$AIB_LIB/c3lib/rtl/cdc/gray_code/c3lib_graytobin.sv \ +$AIB_LIB/c3lib/rtl/cdc/level_synchronizer/c3lib_lvlsync.sv \ +$AIB_LIB/c3lib/rtl/cdc/reset_synchronizer/c3lib_rstsync.sv \ +$AIB_LIB/c3lib/rtl/cdc/vector_synchronizer/c3lib_vecsync.sv \ +$AIB_LIB/c3lib/rtl/cdc/vector_synchronizer/c3lib_vecsync_handshake.sv \ +$AIB_LIB/c3lib/rtl/cdc/glitch_free_mux/c3lib_gf_clkmux.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_buf/c3lib_ckinv_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_buf/c3lib_ckbuf_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_buf/c3lib_ckand2_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_gater/c3lib_ckg_async_posedge_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_gater/c3lib_ckg_negedge_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_gater/c3lib_ckg_posedge_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_mux/c3lib_mux2_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_mux/c3lib_mux3_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_mux/c3lib_mux4_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_divider/c3lib_ckdiv2_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_divider/c3lib_ckdiv4_ctn.sv \ +$AIB_LIB/c3lib/rtl/ctn/clock_divider/c3lib_ckdiv8_ctn.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_and2_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_buf_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_mux2_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_nand2_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_or2_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_tie_bus_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_tieh_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_tiel_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_mtieh_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_mtiel_lcell.sv \ +$AIB_LIB/c3lib/rtl/lcell/c3lib_dff_scan_lcell.sv \ +$AIB_LIB/c3lib/rtl/ecc/c3lib_ecc_dec_c39_d32.sv \ +$AIB_LIB/c3lib/rtl/ecc/c3lib_ecc_dec_c88_d80.sv \ +$AIB_LIB/c3lib/rtl/ecc/c3lib_ecc_enc_d32_c39.sv \ +$AIB_LIB/c3lib/rtl/ecc/c3lib_ecc_enc_d80_c88.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_sync2_reset_lvt_gate.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_sync2_reset_ulvt_gate.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_sync3_reset_ulvt_gate.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_sync2_set_lvt_gate.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_sync2_set_ulvt_gate.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_sync3_set_ulvt_gate.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_tie0_svt_1x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_tie1_svt_1x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_mtie0_ds.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_mtie1_ds.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_or2_svt_2x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_nand2_svt_2x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_mux2_svt_2x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_ckmux4_ulvt_gate.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_ckmux4_lvt_gate.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_ckinv_lvt_12x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_ckinv_svt_8x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_ckg_lvt_8x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_ckbuf_lvt_4x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_buf_svt_4x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_and2_svt_2x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_and2_svt_4x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_dff0_reset_lvt_2x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_dff0_set_lvt_2x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_dff0_scan_reset_svt_2x.sv \ +$AIB_LIB/c3lib/rtl/primitives/c3lib_sync_metastable_behav_gate.sv \ +$AIB_LIB/c3dfx/rtl/tcm/c3dfx_tcm_wrap.sv \ +$AIB_LIB/c3dfx/rtl/tcm/c3dfx_tcm.sv \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1_async.v \ +$AIB_LIB/c3dfx/rtl/defines/c3dfx.vh $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1clk_ctl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1_config.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_hwcfg_dec.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_cfg_csr.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_usr_csr.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1_transfer.v \ +$AIB_LIB/c3dfx/rtl/defines/c3dfx.vh $AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2_async.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2clk_ctl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2_config.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2_transfer.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm2.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_async.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_cfg_rdmux.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmmclk_dcg.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmmclk_gate.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_cmdbuilder.sv \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_dec_arb.sv \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_decode.sv \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_rdfifo.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmmrst_ctl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm_usr32_exp.sv \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_hrdrst_clkctl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_hrdrst_rstctrl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_async_capture_bit.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_async_capture_bus.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkand2.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkgate_high.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkgate.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkinv.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkmux2_cell.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_clkmux2.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_comp_cntr.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_dist_dw.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_dist_pair_dw.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_dist_pair.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_cp_dist.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_dft_clk_ctlr.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_latency_measure.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_occ_clkgate.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_occ_enable_logic.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_occ_gray_cntr.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_occ_test_ctlregs.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_parity_checker.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_parity_gen.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_pulse_stretch.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_dprio_status_sync_regs.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_cmn/c3aibadapt_cmn_shadow_status_regs.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_capture.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_direct.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_rsvd_capture.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_rsvd_update.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync_update.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxasync.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxchnl_testbus.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxchnl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxclk_ctl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxclk_gate.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_asn.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_async_fifo.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_cp_bond.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_del_sm.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_fifo_ptr.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_fifo_ram.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_fifo.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_map.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rx_dprio.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_rxeq_sm.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_txeq_sm.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp_txeq.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxdp.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxrst_ctl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_fsr_in.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_fsr_out.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_async_capture_bit.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_async_capture_bus.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_srclk_ctl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_in_bit.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_out_bit.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_srrst_ctl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr_sm.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_sr.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_ssr_in.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_sr/c3aibadapt_ssr_out.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_async_update.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_hip_async_capture.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_hip_async_update.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_capture.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_direct.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_rsvd_capture.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_rsvd_update.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync_update.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txasync.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txchnl_testbus.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txchnl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txclk_ctl.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txclk_gate.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_async_fifo.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_cp_bond.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_fifo_ptr.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_fifo_ram.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_fifo.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_map.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_tx_dprio.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txdp_word_align.v \ +$AIB_LIB/c3aibadapt/rtl/c3aibadapt_txchnl/c3aibadapt_txrst_ctl.v \ +$AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_redundancy.v \ +$AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_jtag_bscan.v \ +$AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_bsr_red_wrap.v \ +$AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_half_cycle_code_gen.v \ +$AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_self_lock_assertion.v \ +$AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_dll_ctrl.v \ +$AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_dll_core.v \ +$AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_dll_pnr.v \ +$AIB_LIB/aibcr3pnr_lib/rtl/aibcr3pnr_rstsync.sv \ +$AIB_LIB/c3dfx/rtl/tcb/c3dfx_aibadaptwrap_tcb.sv \ +$AIB_LIB/c3aibadapt_wrap/rtl/c3aibadapt_wrap.v \ +$AIB_LIB/c3aibadapt_wrap/rtl/c3aib_master.sv \ +$MODEL_RTL/dll.sv $MODEL_RTL/aib_io_buffer.sv \ +$MODEL_RTL/aib_dcc.v \ +$MODEL_RTL/aib_aux_channel.v \ +$MODEL_RTL/aib_bitsync.v \ +$MODEL_RTL/aib_bsr_red_wrap.v \ +$MODEL_RTL/aib_buffx1_top.v \ +$MODEL_RTL/aib_ioring.v \ +$MODEL_RTL/aib_jtag_bscan.v \ +$MODEL_RTL/aib_mux21.v \ +$MODEL_RTL/aib_osc_clk.sv \ +$MODEL_RTL/aib_redundancy.v \ +$MODEL_RTL/aib_rstnsync.v \ +$MODEL_RTL/aib_sm.v \ +$MODEL_RTL/aib_sr_ms.v \ +$MODEL_RTL/aib_sr_sl.v \ +$MODEL_RTL/aib_channel.v \ +$MODEL_RTL/aib.v \ +../maib_rtl/s10aib/rtl/ndaibadapt_wrap.v \ +../maib_rtl/s10aib/rtl/an.v \ +../maib_rtl/s10aib/rtl/s10aib.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1_async.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1_config.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1_dprio_mapping.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1_transfer.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm1.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm2_async.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm2_transfer.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm2.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_async_update.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmmclk_ctl.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_cmdfifo.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_cmn_intf.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_dprio_reg.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_rdfifo.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmmrst_ctl.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_avmm_async.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_hrdrst_rstctrl.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_avmm/hdpldadapt_hrdrst_clkctl.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_fsr_in.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_fsr_out.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_srclk_ctl.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_sr_in_bit.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_sr_out_bit.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_srrst_ctl.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_sr_sm.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_sr.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_ssr_in.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_sr/hdpldadapt_ssr_out.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_async_update.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_reserved_capture.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_reserved_update.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_hip_async_capture.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_hip_async_update.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_capture.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_direct.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async_update.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_async.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_chnl.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_txclk_ctl.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_async_fifo.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_fifo_ram.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_fifo_pointers.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_chnl_testbus.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_cp_bond.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_dv_gen.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_fifo.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_frame_gen.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_word_mark.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_txrst_ctl.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_tx_chnl/hdpldadapt_tx_datapath_pulse_stretch.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_reserved_capture.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_reserved_update.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_capture.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_direct.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async_update.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_async.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_chnl.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rxclk_ctl.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_asn.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_async_fifo.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_cp_bond.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_fifo.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_fifo_ram.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_fifo_pointers.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_insert_sm.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_del_sm.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_word_align.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rxrst_ctl.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_datapath_pulse_stretch.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_rx_chnl/hdpldadapt_rx_chnl_testbus.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_async_capture_bit.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_comp_cntr.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_pair_dw.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_async_capture_bus.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_dw.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_cp_dist_pair.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_latency_measure.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_pulse_stretch.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_parity_gen.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_parity_checker.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkand2.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay_map.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkdelay_cell.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkgate.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkinv.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkmux2_cell.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkmux2.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_clkor2.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_dft_clock_controller.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_clkgate.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_enable_logic.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_gray_code_counter.v \ +../maib_rtl/hdpldadapt/rtl/hdpldadapt_cmn/hdpldadapt_cmn_occ_test_control_register.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_bintogray.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_bintogray_inc8.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_bitsync2.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_sync2_reset_type_l_gate.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_sync2_reset_type_n_gate.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_sync2_reset_type_w_gate.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_sync2_set_type_l_gate.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_sync2_set_type_n_gate.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_sync2_set_type_w_gate.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_bitsync4.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_sync4_reset_type_l_gate.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_sync4_reset_type_w_gate.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_sync4_set_type_l_gate.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_sync4_set_type_w_gate.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_graytobin.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_graytobin_inc2.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_graytobin_inc8.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_rst_n_sync.v \ +../maib_rtl/cdclib/rtl/block_function/cdclib_rst_n_sync_core.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_csr_reg_bit.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_csr_reg_nbits.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_csr_reg_nregs.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_cmn_non_scan_reg.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_readdata_mux.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_interface_top.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_csr_test_mux.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_cmn_clk_mux.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_reg_bit.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_reg_nbits.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_reg_nregs.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_reg_chnl.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_ctrl_stat_reg_top.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_dis_ctrl_cvp.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_readdata_sel.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_status_reg_nbits.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_status_reg_nregs.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_status_sync_regs.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_shadow_status_regs.v \ +../maib_rtl/cfg_shared/rtl/block_function/cfg_dprio_shadow_status_nregs.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_top_wrp.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_top.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dly_rep.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dly_mimic.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_io_dly_interpolator_rep.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_io_nand_delay_line_min_rep.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_latch.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_hgy_latch.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_ff_r.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_ff_rp.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_2ff_scan.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_aliasd.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_aliasv.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_2to4dec.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_analog.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_avmm1.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_avmm2.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_buffx1_top.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_buffx1.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clkbuf.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_avmm.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_avmm_mimic.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_avmm_pcs.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_mimic.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clktree_pcs.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_fine_dly.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x6.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x1.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_d8xsesdd1.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_d8xsesdd2.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_5b_b2tc_x1.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_5b_b2tc.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dll.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_ff.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_fine_dly.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_mux.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_top.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_digital.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dll_phdet.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dll_custom.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_inv_split_align.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_quadph_code_gen.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_preclkbuf.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxdatapath_rx.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxdig.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_align.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_txdatapath_tx.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_txdig.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxanlg.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_txanlg.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_fine_dly_x1.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_fine_dly_x1.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dly_inv.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_fine_dly_inv.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_ff.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_helper.v \ + ../maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_clktree_mimic.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_dcc_dly.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_custom_dig.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_preclkbuf.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_nand_x64_delay_line.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_str_clktree.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_sync_ff.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_cmos_nand_x64.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_signal_buf.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_custom_dig2.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_avmm_rst_sync.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_data_buf.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_interface.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_rambit_buf.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_inv.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_nand2.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_nor2.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_clkmux2.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_red_clkmux3.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_txdat_mimic.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_rxdat_mimic.v \ +../maib_rtl/aibnd_lib/rtl/block_function/aibnd_clkmux2.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_interp_mux.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_ip16phs.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_cmos_16ph_decode.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_interp_misc.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_interp_output.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_interp_latch_in.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_interp_mux_pair.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_interp_pdn.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_min_interp_mux.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_min_ip16phs.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_min_output.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_min_misc.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_min_pdn.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_dly_interpolator.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_dly_interpclk.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_ip8phs_3in.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x1.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x128.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x64_decode.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x128_decode.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x6.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_nand_x128_delay_line.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x64.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_cmos_nand_x4.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_split_align.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_dll_phdet.v \ +../maib_rtl/io_common_custom/rtl/block_function/io_nand_delay_line_min.v \ +../maib_rtl/soc_std_macro/rtl/block_function/i14socnd/soc_simulation_defines.v \ +../maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckinv.v \ +../maib_rtl/soc_std_macro/rtl/block_function/i14socnd/altr_hps_ckmux21.v \ +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_redundancy.v \ +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_jtag_bscan.v \ +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_bsr_red_wrap.v \ +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_half_cycle_code_gen.v \ +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_self_lock_assertion.v \ +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_ctrl.v \ +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_core.v \ +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_pnr.v \ +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkgate_cgc00.v \ +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkgate_cgc01.v \ +../maib_rtl/aibndpnr_lib/rtl/block_function/aibndpnr_dll_atech_clkmux.v diff --git a/rtl/aib.v b/rtl/aib.v index 361c74d..511ec7b 100644 --- a/rtl/aib.v +++ b/rtl/aib.v @@ -43,9 +43,9 @@ inout wire iopad_por_copy, input [DATAWIDTH*2 - 1 :0] data_in, //output data to pad output wire [DATAWIDTH*2 - 1:0] data_out, //input data from pad input m_ns_fwd_clk, //output data clock -output wire m_fs_rvc_clk, +output wire m_fs_rcv_clk, output wire m_fs_fwd_clk, -input m_ns_rvc_clk, +input m_ns_rcv_clk, input ms_ns_adapter_rstn, input sl_ns_adapter_rstn, @@ -129,9 +129,9 @@ aib_channel #(.DATAWIDTH(DATAWIDTH)) aib_channel .iopad_arstni(iopad_fs_adapter_rstn), .tx_launch_clk(m_ns_fwd_clk), //output data clock - .fs_rvc_clk_tomac(m_fs_rvc_clk), + .fs_rvc_clk_tomac(m_fs_rcv_clk), .fs_fwd_clk_tomac(m_fs_fwd_clk), - .ns_rvc_clk_frmac(m_ns_rvc_clk), + .ns_rvc_clk_frmac(m_ns_rcv_clk), .iddren(iddren), .idataselb(idataselb), //output async data selection .itxen(itxen), //data tx enable diff --git a/rtl/aib_channel.v b/rtl/aib_channel.v index c402af9..bb7dc45 100644 --- a/rtl/aib_channel.v +++ b/rtl/aib_channel.v @@ -324,7 +324,7 @@ aib_sm aib_sm .sl_rx_transfer_eni(sl_data_to_core[70]), .sl_osc_transfer_eni(sl_data_to_core[72]), .ms_nsl(ms_nsl), //ms_adapter_rstn & sl_adapter_rstn - .atpg_mode(), + .atpg_mode(1'b0), .reset_n(adpt_rstn) //ms_adapter_rstn & sl_adapter_rstn ); @@ -341,7 +341,7 @@ aib_sr_ms .sr_ms_load_in(srl_in), //master serial data load inupt .sr_ms_clk_in(sr_clk_in), //from input por .ms_nsl(ms_nsl), - .atpg_mode(), + .atpg_mode(1'b0), .reset_n(adpt_rstn) //ms_adapter_rstn & sl_adapter_rstn ); @@ -359,7 +359,7 @@ aib_sr_sl .sr_sl_load_in(srl_in), //slave serial data load inupt .sr_ms_clk_in(sr_clk_in), //input ms clock .ms_nsl(ms_nsl), - .atpg_mode(), + .atpg_mode(1'b0), .reset_n(adpt_rstn) //ms_adapter_rstn & sl_adapter_rstn ); @@ -375,7 +375,7 @@ aib_dcc aib_dcc .sl_dcc_cal_done(sl_tx_dcc_cal_doneint), .clk_out(dcc_clk_out), .ms_nsl(ms_nsl), - .atpg_mode(), + .atpg_mode(1'b0), .reset_n(adpt_rstn) ); @@ -390,7 +390,7 @@ aib_dcc aib_dcc .sl_rx_dll_lock_req(sl_rx_dll_lock_req), .sl_rx_dll_lock(sl_rx_dll_lockint), .ms_nsl(ms_nsl), - .atpg_mode() + .atpg_mode(1'b0) ); endmodule // aib_channel