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dwesterg devicetree: add board name and framebuffer
Rather then modifying the dts in uboot, use the overlay
to modify the board model and frambuffer config.  The
board model should reflect the FPGA configuration being used.

Uboot still modifies the stride, width, and height fields
of the framebuffer config

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Latest commit 138080d Jun 12, 2018

README.md

FPGA hardware design for the Terasic DE10-Nano* kit

Overview

Instructions to build the FPGA design for the Terasic DE10-Nano* Kit.

This repository provides support for building a demonstration FPGA image for the Terasic DE10-Nano kit's development board and is intended to be used in conjunction with the meta-de10-nano layer.

There are 3 FPGA projects created during the build

  • de10-nano-base: A base design with no IP requiring additional licenses
  • de10-nano-fft: An FPGA based FFT example. The FFT IP does require a license
  • de10-nano-mandelbrot: An FPGA implementation of a Mandelbrot. The output of the Mandelbrot is displayed on the HDMI output

Note: Released builds of the FPGA images are available in the release section of the github project.

Note: Only the release builds are tested fully. The master branch is likely to work but is not thoroughly tested.

Build Instructions

A Makefile based build is used for this project which results in the following outputs:

  • Compiled Intel* Quartus* Prime Design Software project
  • Generated Intel* Quartus* QSYS* system
  • Generated and compiled devicetree overlay for the DE10-Nano* Kit
  • Bootloader configuration files

Note: The release build tar file contains all FPGA programing files as well all of the above mentioned files.

Prerequisites:

  • Intel* Quartus* Prime Design Software Version 17.1.2
  • Intel* SoCEDS* Version 17.1

Known Issues:

  • Intel* QSYS* build from tcl source may fail on systems without a full installation of the Intel* Quartus* Prime Design Software. If you encounter this issue, please use a build from one of the released tar.gz files available in the releases section.

Build from a release archive:

The release archive has a complete Intel* Quartus* Prime Design Software project and associtated RTL and SDC scripts. If you are familiar or prefer this flow, please refer to the Intel* Quartus* Prime Design documentation available here.

Release archive contents:

  • de10-nano-base: Intel* Quartus* Prime Design project for the Terasic DE10-Nano kit
    • hps_isw_handoff: prebuilt handoff files for the HPS
    • output_files: prebuild FPGA bitstream files (sof & rbf)
    • preloader: bsp-editor generated files for the HPS bootloader
  • de10-nano-fft: Intel* Quartus* Prime Design project for the Terasic DE10-Nano kit
    • hps_isw_handoff: prebuilt handoff files for the HPS
    • output_files: prebuild FPGA bitstream files (sof & rbf)
    • preloader: bsp-editor generated files for the HPS bootloader
  • de10-nano-mandelbrot: Intel* Quartus* Prime Design project for the Terasic DE10-Nano kit
    • hps_isw_handoff: prebuilt handoff files for the HPS
    • output_files: prebuild FPGA bitstream files (sof & rbf)
    • preloader: bsp-editor generated files for the HPS bootloader
  • devicetrees: devicetree overlay source and devicetree overlay binaries for the kits
  • hdl_src: RTL and SDC source
  • ip: Custom Intel* Quartus* QSYS* components
  • patches: sopc2dts patches to add BASIC support for devicetree overlay generation
  • Makefile: Main Makefile for building the Terasic* DE10-Nano-SoC projects
  • mks: Makefile fragments for various build outputs of the project. These are included in the main Makefile

Build from release archives:

For building the projects from the generated Intel* Quartus* Prime Design project and generated Intel* Quartus* QSYS* system please read the design tools documentation.

Build from GIT:

The build has only been tested on a linux host, although there are no known reasons this will not work in a Cygwin shell.

Please refer to 'make help' for all build targets, to build everything, simple make all.

Preloader and u-Boot generation

This example uses mainline u-Boot for the Intel* Cyclone5* FPGA. The repository for this is available here. The build requires the bsp-editor preloader output created by the Intel* SoCEDS* tools. Please follow the readme available in the repository for generation and creation of the appropriate files should you want to build it yourself. Please note that the linux build for the Terasic* DE10-Nano-SoC does also build the bootloader.

Verify Release Build authenticity

To verify the signature of the release build download please do the following on a linux host:

  • Download the release tgz and sig.tgz from the release section of the github project

  • Extract the sig.tgz file to get only the sig file

  • Save the signing chain as a pem file openssl pkcs7 -print_certs -inform der
    -in de10-nano-build_.sig
    > de10-nano-build.pem

  • Verify the signing certificate openssl x509
    -in de10-nano-build.pem
    -serial -noout

    The result should be: serial=56000003003F7A8C8F5DD497E1000000000300

  • Verify the signature of the file openssl smime -verify
    -in de10-nano-build_.sig
    -inform der
    -content de10-nano-build_.tgz
    -noverify de10-nano-build.pem > /dev/null

Additional Resources