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@Nor7th Nor7th released this Jan 13, 2021

[5.4.0] 2020-12-31

  • Improvement on literal matcher "Fat Teddy" performance, including support for Intel(R) AVX-512 Vector Byte Manipulation Instructions (Intel(R) AVX-512 VBMI).
  • Introduce a new 32-state shuffle-based DFA engine ("Sheng32"). This improves scanning performance by leveraging AVX-512 VBMI.
  • Introduce a new 64-state shuffle-based DFA engine ("Sheng64"). This improves scanning performance by leveraging AVX-512 VBMI.
  • Introduce a new shuffle-based hybrid DFA engine ("McSheng64"). This improves scanning performance by leveraging AVX-512 VBMI.
  • Improvement on exceptional state handling performance for LimEx NFA, including support for AVX-512 VBMI.
  • Improvement on lookaround performance with new models, including support for AVX-512.
  • Improvement on DFA state space efficiency.
  • Optimization on decision of NFA/DFA generation.
  • hsbench: add CSV dump support for hsbench.
  • Bugfix for cmake error on Icelake under release mode.
  • Bugfix in find_vertices_in_cycles() to avoid self-loop checking in SCC.
  • Bugfix for issue #270: fix return value handling in chimera.
  • Bugfix for issue #284: use correct free function in logical combination.
  • Add BUILD_EXAMPLES cmake option to enable example code compilation. (#260)
  • Some typo fixing. (#242, #259)

By using this document, in addition to any agreements you have with Intel, you accept the terms set forth below.

You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined.” Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm.
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*Other names and brands may be claimed as the property of others.
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Assets 2

@Nor7th Nor7th released this May 25, 2020

[5.3.0] 2020-05-15

  • Improvement on literal matcher "Teddy" performance, including support for Intel(R) AVX-512 Vector Byte Manipulation Instructions (Intel(R) AVX-512 VBMI).
  • Improvement on single-byte/two-byte matching performance, including support for Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX-512).
  • hsbench: add hyphen support for -T option.
  • tools/fuzz: add test scripts for synthetic pattern generation.
  • Bugfix for acceleration path analysis in LimEx NFA.
  • Bugfix for duplicate matches for Small-write engine.
  • Bugfix for UTF8 checking problem for hscollider.
  • Bugfix for issue #205: avoid crash of hs_compile_lit_multi() with clang and ASAN.
  • Bugfix for issue #211: fix error in db_check_platform() function.
  • Bugfix for issue #217: fix cmake parsing issue of CPU arch for non-English locale.
  • Bugfix for issue #228: avoid undefined behavior when calling close() after fdopendir() in loadExpressions().
  • Bugfix for issue #239: fix hyperscan compile issue under gcc-10.
  • Add VLAN packets processing capability in pcap analysis script. (#214)
  • Avoid extra convert instruction for "Noodle". (#221)
  • Add Hyperscan version marcro in hs.h. (#222)

By using this document, in addition to any agreements you have with Intel, you accept the terms set forth below.

You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined.” Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm.
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2020, Intel Corporation. All rights reserved.

Assets 2

@Nor7th Nor7th released this Oct 30, 2019

[5.2.1] 2019-10-13

  • Bugfix for issue #186: fix compile issue when BUILD_SHARED_LIBS is on in release mode.
  • Disable redundant move check for older compiler versions.

By using this document, in addition to any agreements you have with Intel, you accept the terms set forth below.

You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined.” Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm.
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2019, Intel Corporation. All rights reserved.

Assets 2

@fatchanghao fatchanghao released this Aug 13, 2019

[5.2.0] 2019-07-12

  • Literal API: add new API hs_compile_lit() and hs_compile_lit_multi() to
    process pure literal rule sets. The 2 literal APIs treat each expression text
    in a literal sense without recognizing any regular grammers.
  • Logical combination: add support for purely negative combinations, which
    report match at EOD in case of no sub-expressions matched.
  • Windows porting: support shared library (DLL) on Windows with available tools
    hscheck, hsbench and hsdump.
  • Bugfix for issue #148: fix uninitialized use of scatter_unit_uX due to
    padding.
  • Bugfix for issue #155: fix numerical result out of range error.
  • Bugfix for issue #165: avoid corruption of pending combination report in
    streaming mode.
  • Bugfix for issue #174: fix scratch free issue when memory allocation fails.

By using this document, in addition to any agreements you have with Intel, you accept the terms set forth below.

You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined.” Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm.
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2019, Intel Corporation. All rights reserved.

Assets 2

@xiangwang1 xiangwang1 released this Apr 10, 2019

[5.1.1] 2019-04-03

Known Issues and Limitations:
There are no known issues with this release.

Resolved Issues:

  • Add extra detection and handling when invalid rose programs are triggered.
  • Bugfix for issue #136: fix CMake parsing of CPU architecture for GCC-9.
  • Bugfix for issue #137: avoid file path impact on fat runtime build.
  • Bugfix for issue #141: fix rose literal programs for multi-pattern
    matching when no pattern ids are provided.
  • Bugfix for issue #144: fix library install path in pkg-config files.

By using this document, in addition to any agreements you have with Intel, you accept the terms set forth below.

You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined.” Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm.
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2019, Intel Corporation. All rights reserved.

Assets 2

@fatchanghao fatchanghao released this Jan 31, 2019

[5.1.0] 2019-01-31

New Features:

  • Improve DFA state compression by wide-state optimization to reduce bytecode
    size.
  • Improve interpreter runtime handling for pure literal patterns to boost the
    performance of pure literal matching.
  • Improve representation of interpreter to boost overall performance.

Known Issues and Limitations:
There are no known issues with this release.

Resolved Issues:

  • Bugfix for logical combinations: fix error reporting combination's match in
    case of sub-expression has EOD match under streaming mode.
  • Bugfix for logical combinations: fix miss reporting combination's match under
    vacuous input.
  • Bugfix for issue #104: fix compile error with Boost 1.68.0.
  • Bugfix for issue #127: avoid pcre error for hscollider with installed PCRE
    package.
  • Update version of PCRE used by testing tools as a syntax and semantic
    reference to PCRE 8.41 or above.
  • Fix github repo address in doc.

By using this document, in addition to any agreements you have with Intel, you accept the terms set forth below.

You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined.” Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm.
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2019, Intel Corporation. All rights reserved.

Assets 2

@xiangwang1 xiangwang1 released this Jul 9, 2018

[5.0.0] 2018-07-09

  • Introduce chimera hybrid engine of Hyperscan and PCRE, to fully support
    PCRE syntax as well as to take advantage of the high performance nature of
    Hyperscan.
  • New API feature: logical combinations (AND, OR and NOT) of patterns in a
    given pattern set.
  • Windows porting: hsbench, hscheck, hscollider and hsdump tools now available
    on Windows 8 or newer.
  • Improve undirected graph implementation to avoid graph copy and reduce
    compile time.
  • Bugfix for issue #86: enable hscollider for installed PCRE package.
Assets 2

@xiangwang1 xiangwang1 released this Jan 23, 2018

[4.7.0] 2018-01-24

  • Introduced hscollider pattern testing tool, for validating Hyperscan match behaviour against PCRE.
  • Introduced hscheck pattern compilation tool.
  • Introduced hsdump development tool for producing information about Hyperscan pattern compilation.
  • New API feature: extended approximate matching support for Hamming distance.
  • Bugfix for issue #69: Force C++ linkage in Xcode.
  • Bugfix for issue #73: More documentation for hs_close_stream().
  • Bugfix for issue #78: Fix for fat runtime initialisation when used as a shared library.
Assets 2

@mdb256 mdb256 released this Sep 22, 2017

[4.6.0] 2017-09-22

  • New API feature: stream state compression. This allows the user to compress and restore state for streams to reduce memory usage.
  • Many improvements to literal matching performance, including more support for Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX-512).
  • Compile time improvements, mainly reducing compiler memory allocation. Also results in reduced compile time for some pattern sets.
  • Bugfix for issue #62: fix error building Hyperscan using older versions of Boost.
  • Small updates to fix warnings identified by Coverity.
Assets 2

@mdb256 mdb256 released this Jul 26, 2017

[4.5.2] 2017-07-26

  • Bugfix for issue #57: Treat characters between \Q..\E as codepoints in
    UTF8 mode.
  • Bugfix for issue #60: Use a portable flag for mktemp for fat runtime builds.
  • Bugfix for fat runtime builds on AVX-512 capable machines with Hyperscan's
    AVX-512 support disabled.
Assets 2