`PYTORCH_OPINFO_SAMPLE_INPUT_INDEX=7 python test/inductor/test_torchinductor_opinfo.py TestInductorOpInfoXPU.test_comprehensive__chunk_cat_xpu_float64` is broken

[anmyachev]

Found in https://github.com/pytorch/pytorch/actions/runs/18906225331/job/53967588385?pr=166436

Error:

FAILED [1.2273s] inductor/test_torchinductor_opinfo.py::TestInductorOpInfoXPU::test_comprehensive__chunk_cat_xpu_float64 - Exception: Tensor-likes are not close!

Mismatched elements: 6 / 1674 (0.4%)
Greatest absolute difference: 5.934405558668234 at index (0, 1, 5) (up to 1e-07 allowed)
Greatest relative difference: 1.0 at index (0, 0, 5) (up to 1e-07 allowed)

[anmyachev]

9c04b522af44727a6df481fe8d4a7d9c420b9411 is the first bad commit
commit 9c04b522af44727a6df481fe8d4a7d9c420b9411
Author: Whitney Tsang <whitney.tsang@intel.com>
Date:   Tue Sep 30 10:14:59 2025 -0400

    [LoadStoreOpToLLVM] Enable predicated load and store (#5215)
    
    This PR enables predicated load and store operations by changing the
    default behavior of the TRITON_INTEL_PREDICATED environment variable
    from false to true.
    
    Benchmark CI:
    https://github.com/intel/intel-xpu-backend-for-triton/actions/runs/18111223923
    (no regression, potential gain)
    
    Signed-off-by: Whitney Tsang <whitney.tsang@intel.com>

 python/test/unit/tools/test_disasm.py                          |  2 +-
 test/TritonIntelGPU/blockptr_load.mlir                         | 10 +++++-----
 test/TritonIntelGPU/blockptr_store.mlir                        |  6 +++---
 .../intel/lib/TritonIntelGPUToLLVM/LoadStoreOpToLLVM.cpp       | 10 ++++++++--
 4 files changed, 17 insertions(+), 11 deletions(-)

[anmyachev]

Problem IR:

; ModuleID = 'LLVMDialectModule'
source_filename = "LLVMDialectModule"
target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
target triple = "spir64-unknown-unknown"

; Function Attrs: mustprogress nounwind willreturn
; Unknown intrinsic
declare !dbg !9 spir_func void @llvm.genx.GenISA.PredicatedStore.p1i32.v1i32(ptr addrspace(1), <1 x i32>, i64, i1) #0

; Function Attrs: mustprogress nounwind willreturn
; Unknown intrinsic
declare !dbg !12 spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1), i64, i1, i32) #0

; Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
declare !dbg !13 spir_func i64 @_Z12get_local_idj(i32) local_unnamed_addr #1

; Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
declare !dbg !14 spir_func i64 @_Z12get_group_idj(i32) local_unnamed_addr #1

; Function Attrs: mustprogress nounwind willreturn
define spir_kernel void @triton_poi_fused__chunk_cat_0(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, ptr addrspace(1) %4, ptr addrspace(1) %5, i32 %6, i32 %7, ptr addrspace(1) readnone captures(none) %8, ptr addrspace(1) readnone captures(none) %9) local_unnamed_addr #0 !dbg !15 !reqd_work_group_size !16 !intel_reqd_sub_group_size !17 {
  %11 = tail call spir_func i64 @_Z12get_group_idj(i32 1) #2, !dbg !18
  %12 = trunc i64 %11 to i32, !dbg !18
  %13 = shl i32 %12, 3, !dbg !19
  %14 = or disjoint i32 %13, 1, !dbg !20
  %15 = or disjoint i32 %13, 2, !dbg !20
  %16 = or disjoint i32 %13, 3, !dbg !20
  %17 = or disjoint i32 %13, 4, !dbg !20
  %18 = or disjoint i32 %13, 5, !dbg !20
  %19 = or disjoint i32 %13, 6, !dbg !20
  %20 = or disjoint i32 %13, 7, !dbg !20
  %21 = icmp slt i32 %13, 6, !dbg !21
  %22 = icmp slt i32 %15, 6, !dbg !21
  %23 = icmp slt i32 %17, 6, !dbg !21
  %24 = icmp slt i32 %13, 0, !dbg !21
  %25 = tail call spir_func i64 @_Z12get_group_idj(i32 0) #2, !dbg !22
  %26 = trunc i64 %25 to i32, !dbg !22
  %27 = shl i32 %26, 7, !dbg !23
  %28 = tail call spir_func i64 @_Z12get_local_idj(i32 0) #2, !dbg !24
  %29 = trunc i64 %28 to i32, !dbg !24
  %30 = and i32 %29, 127, !dbg !24
  %31 = or disjoint i32 %30, %27, !dbg !25
  %32 = icmp slt i32 %31, 279, !dbg !26
  %.frozen = freeze i32 %13, !dbg !27
  %33 = sdiv i32 %.frozen, 3, !dbg !27
  %34 = mul i32 %33, 3, !dbg !28
  %.decomposed = sub i32 %.frozen, %34, !dbg !28
  %.frozen32 = freeze i32 %14, !dbg !27
  %35 = sdiv i32 %.frozen32, 3, !dbg !27
  %36 = mul i32 %35, 3, !dbg !28
  %.decomposed33 = sub i32 %.frozen32, %36, !dbg !28
  %.frozen34 = freeze i32 %15, !dbg !27
  %37 = sdiv i32 %.frozen34, 3, !dbg !27
  %38 = mul i32 %37, 3, !dbg !28
  %.decomposed35 = sub i32 %.frozen34, %38, !dbg !28
  %.frozen36 = freeze i32 %16, !dbg !27
  %39 = sdiv i32 %.frozen36, 3, !dbg !27
  %40 = mul i32 %39, 3, !dbg !28
  %.decomposed37 = sub i32 %.frozen36, %40, !dbg !28
  %.frozen38 = freeze i32 %17, !dbg !27
  %41 = sdiv i32 %.frozen38, 3, !dbg !27
  %42 = mul i32 %41, 3, !dbg !28
  %.decomposed39 = sub i32 %.frozen38, %42, !dbg !28
  %.frozen40 = freeze i32 %18, !dbg !27
  %43 = sdiv i32 %.frozen40, 3, !dbg !27
  %44 = mul i32 %43, 3, !dbg !28
  %.decomposed41 = sub i32 %.frozen40, %44, !dbg !28
  %.frozen42 = freeze i32 %19, !dbg !27
  %45 = sdiv i32 %.frozen42, 3, !dbg !27
  %46 = mul i32 %45, 3, !dbg !28
  %.decomposed43 = sub i32 %.frozen42, %46, !dbg !28
  %.frozen44 = freeze i32 %20, !dbg !27
  %47 = sdiv i32 %.frozen44, 3, !dbg !27
  %48 = mul i32 %47, 3, !dbg !28
  %.decomposed45 = sub i32 %.frozen44, %48, !dbg !28
  %49 = icmp slt i32 %31, 3, !dbg !29
  %50 = mul i32 %31, 3, !dbg !30
  %51 = mul i32 %33, 9, !dbg !31
  %52 = mul i32 %35, 9, !dbg !31
  %53 = mul i32 %37, 9, !dbg !31
  %54 = mul i32 %39, 9, !dbg !31
  %55 = mul i32 %41, 9, !dbg !31
  %56 = mul i32 %43, 9, !dbg !31
  %57 = mul i32 %45, 9, !dbg !31
  %58 = mul i32 %47, 9, !dbg !31
  %59 = add i32 %51, %.decomposed, !dbg !32
  %60 = add i32 %59, %50, !dbg !33
  %61 = add i32 %52, %.decomposed33, !dbg !32
  %62 = add i32 %61, %50, !dbg !33
  %63 = add i32 %53, %.decomposed35, !dbg !32
  %64 = add i32 %63, %50, !dbg !33
  %65 = add i32 %54, %.decomposed37, !dbg !32
  %66 = add i32 %65, %50, !dbg !33
  %67 = add i32 %55, %.decomposed39, !dbg !32
  %68 = add i32 %67, %50, !dbg !33
  %69 = add i32 %56, %.decomposed41, !dbg !32
  %70 = add i32 %69, %50, !dbg !33
  %71 = add i32 %57, %.decomposed43, !dbg !32
  %72 = add i32 %71, %50, !dbg !33
  %73 = add i32 %58, %.decomposed45, !dbg !32
  %74 = add i32 %73, %50, !dbg !33
  %75 = sext i32 %60 to i64, !dbg !34
  %76 = getelementptr float, ptr addrspace(1) %0, i64 %75, !dbg !34
  %77 = sext i32 %62 to i64, !dbg !34
  %78 = getelementptr float, ptr addrspace(1) %0, i64 %77, !dbg !34
  %79 = sext i32 %64 to i64, !dbg !34
  %80 = getelementptr float, ptr addrspace(1) %0, i64 %79, !dbg !34
  %81 = sext i32 %66 to i64, !dbg !34
  %82 = getelementptr float, ptr addrspace(1) %0, i64 %81, !dbg !34
  %83 = sext i32 %68 to i64, !dbg !34
  %84 = getelementptr float, ptr addrspace(1) %0, i64 %83, !dbg !34
  %85 = sext i32 %70 to i64, !dbg !34
  %86 = getelementptr float, ptr addrspace(1) %0, i64 %85, !dbg !34
  %87 = sext i32 %72 to i64, !dbg !34
  %88 = getelementptr float, ptr addrspace(1) %0, i64 %87, !dbg !34
  %89 = sext i32 %74 to i64, !dbg !34
  %90 = getelementptr float, ptr addrspace(1) %0, i64 %89, !dbg !34
  %91 = and i1 %21, %49, !dbg !35
  %92 = and i1 %22, %49, !dbg !35
  %93 = and i1 %23, %49, !dbg !35
  %94 = and i1 %24, %49, !dbg !35
  %95 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %76, i64 4, i1 %91, i32 0) #3
  %96 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %78, i64 4, i1 %91, i32 0) #3
  %97 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %80, i64 4, i1 %92, i32 0) #3
  %98 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %82, i64 4, i1 %92, i32 0) #3
  %99 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %84, i64 4, i1 %93, i32 0) #3
  %100 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %86, i64 4, i1 %93, i32 0) #3
  %101 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %88, i64 4, i1 %94, i32 0) #3
  %102 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %90, i64 4, i1 %94, i32 0) #3
  %103 = add i32 %31, -3, !dbg !36
  %104 = icmp ult i32 %103, 2, !dbg !36
  %105 = shl i32 %12, 4, !dbg !37
  %106 = shl i32 %14, 1, !dbg !37
  %107 = shl i32 %15, 1, !dbg !37
  %108 = shl i32 %16, 1, !dbg !37
  %109 = shl i32 %17, 1, !dbg !37
  %110 = shl i32 %18, 1, !dbg !37
  %111 = shl i32 %19, 1, !dbg !37
  %112 = shl i32 %20, 1, !dbg !37
  %113 = add i32 %103, %105, !dbg !38
  %114 = add i32 %103, %106, !dbg !38
  %115 = add i32 %103, %107, !dbg !38
  %116 = add i32 %103, %108, !dbg !38
  %117 = add i32 %103, %109, !dbg !38
  %118 = add i32 %103, %110, !dbg !38
  %119 = add i32 %103, %111, !dbg !38
  %120 = add i32 %103, %112, !dbg !38
  %121 = sext i32 %113 to i64, !dbg !39
  %122 = getelementptr float, ptr addrspace(1) %1, i64 %121, !dbg !39
  %123 = sext i32 %114 to i64, !dbg !39
  %124 = getelementptr float, ptr addrspace(1) %1, i64 %123, !dbg !39
  %125 = sext i32 %115 to i64, !dbg !39
  %126 = getelementptr float, ptr addrspace(1) %1, i64 %125, !dbg !39
  %127 = sext i32 %116 to i64, !dbg !39
  %128 = getelementptr float, ptr addrspace(1) %1, i64 %127, !dbg !39
  %129 = sext i32 %117 to i64, !dbg !39
  %130 = getelementptr float, ptr addrspace(1) %1, i64 %129, !dbg !39
  %131 = sext i32 %118 to i64, !dbg !39
  %132 = getelementptr float, ptr addrspace(1) %1, i64 %131, !dbg !39
  %133 = sext i32 %119 to i64, !dbg !39
  %134 = getelementptr float, ptr addrspace(1) %1, i64 %133, !dbg !39
  %135 = sext i32 %120 to i64, !dbg !39
  %136 = getelementptr float, ptr addrspace(1) %1, i64 %135, !dbg !39
  %137 = and i1 %21, %104, !dbg !40
  %138 = and i1 %22, %104, !dbg !40
  %139 = and i1 %23, %104, !dbg !40
  %140 = and i1 %24, %104, !dbg !40
  %141 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %122, i64 4, i1 %137, i32 0) #3
  %142 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %124, i64 4, i1 %137, i32 0) #3
  %143 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %126, i64 4, i1 %138, i32 0) #3
  %144 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %128, i64 4, i1 %138, i32 0) #3
  %145 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %130, i64 4, i1 %139, i32 0) #3
  %146 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %132, i64 4, i1 %139, i32 0) #3
  %147 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %134, i64 4, i1 %140, i32 0) #3
  %148 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %136, i64 4, i1 %140, i32 0) #3
  %149 = icmp eq i32 %31, 5, !dbg !41
  %150 = shl nsw i32 %.decomposed, 1, !dbg !42
  %151 = shl nsw i32 %.decomposed33, 1, !dbg !42
  %152 = shl nsw i32 %.decomposed35, 1, !dbg !42
  %153 = shl nsw i32 %.decomposed37, 1, !dbg !42
  %154 = shl nsw i32 %.decomposed39, 1, !dbg !42
  %155 = shl nsw i32 %.decomposed41, 1, !dbg !42
  %156 = shl nsw i32 %.decomposed43, 1, !dbg !42
  %157 = shl nsw i32 %.decomposed45, 1, !dbg !42
  %158 = add nsw i32 %150, %33, !dbg !43
  %159 = add nsw i32 %151, %35, !dbg !43
  %160 = add nsw i32 %152, %37, !dbg !43
  %161 = add nsw i32 %153, %39, !dbg !43
  %162 = add nsw i32 %154, %41, !dbg !43
  %163 = add nsw i32 %155, %43, !dbg !43
  %164 = add nsw i32 %156, %45, !dbg !43
  %165 = add nsw i32 %157, %47, !dbg !43
  %166 = sext i32 %158 to i64, !dbg !44
  %167 = getelementptr float, ptr addrspace(1) %2, i64 %166, !dbg !44
  %168 = sext i32 %159 to i64, !dbg !44
  %169 = getelementptr float, ptr addrspace(1) %2, i64 %168, !dbg !44
  %170 = sext i32 %160 to i64, !dbg !44
  %171 = getelementptr float, ptr addrspace(1) %2, i64 %170, !dbg !44
  %172 = sext i32 %161 to i64, !dbg !44
  %173 = getelementptr float, ptr addrspace(1) %2, i64 %172, !dbg !44
  %174 = sext i32 %162 to i64, !dbg !44
  %175 = getelementptr float, ptr addrspace(1) %2, i64 %174, !dbg !44
  %176 = sext i32 %163 to i64, !dbg !44
  %177 = getelementptr float, ptr addrspace(1) %2, i64 %176, !dbg !44
  %178 = sext i32 %164 to i64, !dbg !44
  %179 = getelementptr float, ptr addrspace(1) %2, i64 %178, !dbg !44
  %180 = sext i32 %165 to i64, !dbg !44
  %181 = getelementptr float, ptr addrspace(1) %2, i64 %180, !dbg !44
  %182 = and i1 %21, %149, !dbg !45
  %183 = and i1 %22, %149, !dbg !45
  %184 = and i1 %23, %149, !dbg !45
  %185 = and i1 %24, %149, !dbg !45
  %186 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %167, i64 4, i1 %182, i32 0) #3
  %187 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %169, i64 4, i1 %182, i32 0) #3
  %188 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %171, i64 4, i1 %183, i32 0) #3
  %189 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %173, i64 4, i1 %183, i32 0) #3
  %190 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %175, i64 4, i1 %184, i32 0) #3
  %191 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %177, i64 4, i1 %184, i32 0) #3
  %192 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %179, i64 4, i1 %185, i32 0) #3
  %193 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %181, i64 4, i1 %185, i32 0) #3
  %194 = and i32 %31, -2, !dbg !46
  %195 = icmp eq i32 %194, 6, !dbg !46
  %196 = add i32 %50, -18, !dbg !47
  %197 = mul i32 %33, 6, !dbg !48
  %198 = mul i32 %35, 6, !dbg !48
  %199 = mul i32 %37, 6, !dbg !48
  %200 = mul i32 %39, 6, !dbg !48
  %201 = mul i32 %41, 6, !dbg !48
  %202 = mul i32 %43, 6, !dbg !48
  %203 = mul i32 %45, 6, !dbg !48
  %204 = mul i32 %47, 6, !dbg !48
  %205 = add i32 %197, %.decomposed, !dbg !49
  %206 = add i32 %205, %196, !dbg !50
  %207 = add i32 %198, %.decomposed33, !dbg !49
  %208 = add i32 %207, %196, !dbg !50
  %209 = add i32 %199, %.decomposed35, !dbg !49
  %210 = add i32 %209, %196, !dbg !50
  %211 = add i32 %200, %.decomposed37, !dbg !49
  %212 = add i32 %211, %196, !dbg !50
  %213 = add i32 %201, %.decomposed39, !dbg !49
  %214 = add i32 %213, %196, !dbg !50
  %215 = add i32 %202, %.decomposed41, !dbg !49
  %216 = add i32 %215, %196, !dbg !50
  %217 = add i32 %203, %.decomposed43, !dbg !49
  %218 = add i32 %217, %196, !dbg !50
  %219 = add i32 %204, %.decomposed45, !dbg !49
  %220 = add i32 %219, %196, !dbg !50
  %221 = sext i32 %206 to i64, !dbg !51
  %222 = getelementptr float, ptr addrspace(1) %3, i64 %221, !dbg !51
  %223 = sext i32 %208 to i64, !dbg !51
  %224 = getelementptr float, ptr addrspace(1) %3, i64 %223, !dbg !51
  %225 = sext i32 %210 to i64, !dbg !51
  %226 = getelementptr float, ptr addrspace(1) %3, i64 %225, !dbg !51
  %227 = sext i32 %212 to i64, !dbg !51
  %228 = getelementptr float, ptr addrspace(1) %3, i64 %227, !dbg !51
  %229 = sext i32 %214 to i64, !dbg !51
  %230 = getelementptr float, ptr addrspace(1) %3, i64 %229, !dbg !51
  %231 = sext i32 %216 to i64, !dbg !51
  %232 = getelementptr float, ptr addrspace(1) %3, i64 %231, !dbg !51
  %233 = sext i32 %218 to i64, !dbg !51
  %234 = getelementptr float, ptr addrspace(1) %3, i64 %233, !dbg !51
  %235 = sext i32 %220 to i64, !dbg !51
  %236 = getelementptr float, ptr addrspace(1) %3, i64 %235, !dbg !51
  %237 = and i1 %21, %195, !dbg !52
  %238 = and i1 %22, %195, !dbg !52
  %239 = and i1 %23, %195, !dbg !52
  %240 = and i1 %24, %195, !dbg !52
  %241 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %222, i64 4, i1 %237, i32 0) #3
  %242 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %224, i64 4, i1 %237, i32 0) #3
  %243 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %226, i64 4, i1 %238, i32 0) #3
  %244 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %228, i64 4, i1 %238, i32 0) #3
  %245 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %230, i64 4, i1 %239, i32 0) #3
  %246 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %232, i64 4, i1 %239, i32 0) #3
  %247 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %234, i64 4, i1 %240, i32 0) #3
  %248 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %236, i64 4, i1 %240, i32 0) #3
  %249 = add i32 %50, -24, !dbg !53
  %250 = mul i32 %33, 813, !dbg !54
  %251 = mul i32 %35, 813, !dbg !54
  %252 = mul i32 %37, 813, !dbg !54
  %253 = mul i32 %39, 813, !dbg !54
  %254 = mul i32 %41, 813, !dbg !54
  %255 = mul i32 %43, 813, !dbg !54
  %256 = mul i32 %45, 813, !dbg !54
  %257 = mul i32 %47, 813, !dbg !54
  %258 = add i32 %250, %.decomposed, !dbg !55
  %259 = add i32 %258, %249, !dbg !56
  %260 = add i32 %251, %.decomposed33, !dbg !55
  %261 = add i32 %260, %249, !dbg !56
  %262 = add i32 %252, %.decomposed35, !dbg !55
  %263 = add i32 %262, %249, !dbg !56
  %264 = add i32 %253, %.decomposed37, !dbg !55
  %265 = add i32 %264, %249, !dbg !56
  %266 = add i32 %254, %.decomposed39, !dbg !55
  %267 = add i32 %266, %249, !dbg !56
  %268 = add i32 %255, %.decomposed41, !dbg !55
  %269 = add i32 %268, %249, !dbg !56
  %270 = add i32 %256, %.decomposed43, !dbg !55
  %271 = add i32 %270, %249, !dbg !56
  %272 = add i32 %257, %.decomposed45, !dbg !55
  %273 = add i32 %272, %249, !dbg !56
  %274 = sext i32 %259 to i64, !dbg !57
  %275 = getelementptr float, ptr addrspace(1) %4, i64 %274, !dbg !57
  %276 = sext i32 %261 to i64, !dbg !57
  %277 = getelementptr float, ptr addrspace(1) %4, i64 %276, !dbg !57
  %278 = sext i32 %263 to i64, !dbg !57
  %279 = getelementptr float, ptr addrspace(1) %4, i64 %278, !dbg !57
  %280 = sext i32 %265 to i64, !dbg !57
  %281 = getelementptr float, ptr addrspace(1) %4, i64 %280, !dbg !57
  %282 = sext i32 %267 to i64, !dbg !57
  %283 = getelementptr float, ptr addrspace(1) %4, i64 %282, !dbg !57
  %284 = sext i32 %269 to i64, !dbg !57
  %285 = getelementptr float, ptr addrspace(1) %4, i64 %284, !dbg !57
  %286 = sext i32 %271 to i64, !dbg !57
  %287 = getelementptr float, ptr addrspace(1) %4, i64 %286, !dbg !57
  %288 = sext i32 %273 to i64, !dbg !57
  %289 = getelementptr float, ptr addrspace(1) %4, i64 %288, !dbg !57
  %290 = add i32 %31, -8, !dbg !58
  %291 = icmp ult i32 %290, 271, !dbg !58
  %292 = and i1 %21, %291, !dbg !59
  %293 = and i1 %22, %291, !dbg !59
  %294 = and i1 %23, %291, !dbg !59
  %295 = and i1 %24, %291, !dbg !59
  %296 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %275, i64 4, i1 %292, i32 0) #3
  %297 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %277, i64 4, i1 %292, i32 0) #3
  %298 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %279, i64 4, i1 %293, i32 0) #3
  %299 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %281, i64 4, i1 %293, i32 0) #3
  %300 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %283, i64 4, i1 %294, i32 0) #3
  %301 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %285, i64 4, i1 %294, i32 0) #3
  %302 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %287, i64 4, i1 %295, i32 0) #3
  %303 = tail call spir_func i32 @llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32(ptr addrspace(1) %289, i64 4, i1 %295, i32 0) #3
  %.v = select i1 %195, i32 %241, i32 %296, !dbg !60
  %.v1 = select i1 %195, i32 %242, i32 %297, !dbg !60
  %.v2 = select i1 %195, i32 %243, i32 %298, !dbg !60
  %.v3 = select i1 %195, i32 %244, i32 %299, !dbg !60
  %.v4 = select i1 %195, i32 %245, i32 %300, !dbg !60
  %.v5 = select i1 %195, i32 %246, i32 %301, !dbg !60
  %.v6 = select i1 %195, i32 %247, i32 %302, !dbg !60
  %.v7 = select i1 %195, i32 %248, i32 %303, !dbg !60
  %.v8 = select i1 %149, i32 %186, i32 %.v, !dbg !61
  %.v9 = select i1 %149, i32 %187, i32 %.v1, !dbg !61
  %.v10 = select i1 %149, i32 %188, i32 %.v2, !dbg !61
  %.v11 = select i1 %149, i32 %189, i32 %.v3, !dbg !61
  %.v12 = select i1 %149, i32 %190, i32 %.v4, !dbg !61
  %.v13 = select i1 %149, i32 %191, i32 %.v5, !dbg !61
  %.v14 = select i1 %149, i32 %192, i32 %.v6, !dbg !61
  %.v15 = select i1 %149, i32 %193, i32 %.v7, !dbg !61
  %.v16 = select i1 %104, i32 %141, i32 %.v8, !dbg !62
  %.v17 = select i1 %104, i32 %142, i32 %.v9, !dbg !62
  %.v18 = select i1 %104, i32 %143, i32 %.v10, !dbg !62
  %.v19 = select i1 %104, i32 %144, i32 %.v11, !dbg !62
  %.v20 = select i1 %104, i32 %145, i32 %.v12, !dbg !62
  %.v21 = select i1 %104, i32 %146, i32 %.v13, !dbg !62
  %.v22 = select i1 %104, i32 %147, i32 %.v14, !dbg !62
  %.v23 = select i1 %104, i32 %148, i32 %.v15, !dbg !62
  %.v24 = select i1 %49, i32 %95, i32 %.v16, !dbg !63
  %.v25 = select i1 %49, i32 %96, i32 %.v17, !dbg !63
  %.v26 = select i1 %49, i32 %97, i32 %.v18, !dbg !63
  %.v27 = select i1 %49, i32 %98, i32 %.v19, !dbg !63
  %.v28 = select i1 %49, i32 %99, i32 %.v20, !dbg !63
  %.v29 = select i1 %49, i32 %100, i32 %.v21, !dbg !63
  %.v30 = select i1 %49, i32 %101, i32 %.v22, !dbg !63
  %.v31 = select i1 %49, i32 %102, i32 %.v23, !dbg !63
  %304 = mul i32 %12, 2232, !dbg !64
  %305 = mul i32 %14, 279, !dbg !64
  %306 = mul i32 %15, 279, !dbg !64
  %307 = mul i32 %16, 279, !dbg !64
  %308 = mul i32 %17, 279, !dbg !64
  %309 = mul i32 %18, 279, !dbg !64
  %310 = mul i32 %19, 279, !dbg !64
  %311 = mul i32 %20, 279, !dbg !64
  %312 = add i32 %31, %304, !dbg !65
  %313 = add i32 %31, %305, !dbg !65
  %314 = add i32 %31, %306, !dbg !65
  %315 = add i32 %31, %307, !dbg !65
  %316 = add i32 %31, %308, !dbg !65
  %317 = add i32 %31, %309, !dbg !65
  %318 = add i32 %31, %310, !dbg !65
  %319 = add i32 %31, %311, !dbg !65
  %320 = sext i32 %312 to i64, !dbg !66
  %321 = getelementptr float, ptr addrspace(1) %5, i64 %320, !dbg !66
  %322 = sext i32 %313 to i64, !dbg !66
  %323 = getelementptr float, ptr addrspace(1) %5, i64 %322, !dbg !66
  %324 = sext i32 %314 to i64, !dbg !66
  %325 = getelementptr float, ptr addrspace(1) %5, i64 %324, !dbg !66
  %326 = sext i32 %315 to i64, !dbg !66
  %327 = getelementptr float, ptr addrspace(1) %5, i64 %326, !dbg !66
  %328 = sext i32 %316 to i64, !dbg !66
  %329 = getelementptr float, ptr addrspace(1) %5, i64 %328, !dbg !66
  %330 = sext i32 %317 to i64, !dbg !66
  %331 = getelementptr float, ptr addrspace(1) %5, i64 %330, !dbg !66
  %332 = sext i32 %318 to i64, !dbg !66
  %333 = getelementptr float, ptr addrspace(1) %5, i64 %332, !dbg !66
  %334 = sext i32 %319 to i64, !dbg !66
  %335 = getelementptr float, ptr addrspace(1) %5, i64 %334, !dbg !66
  %336 = and i1 %21, %32, !dbg !67
  %337 = and i1 %22, %32, !dbg !67
  %338 = and i1 %23, %32, !dbg !67
  %339 = and i1 %24, %32, !dbg !67
  %340 = insertelement <1 x i32> poison, i32 %.v24, i64 0, !dbg !68
  tail call spir_func void @llvm.genx.GenISA.PredicatedStore.p1i32.v1i32(ptr addrspace(1) %321, <1 x i32> %340, i64 4, i1 %336) #3
  %341 = insertelement <1 x i32> poison, i32 %.v25, i64 0, !dbg !68
  tail call spir_func void @llvm.genx.GenISA.PredicatedStore.p1i32.v1i32(ptr addrspace(1) %323, <1 x i32> %341, i64 4, i1 %336) #3
  %342 = insertelement <1 x i32> poison, i32 %.v26, i64 0, !dbg !68
  tail call spir_func void @llvm.genx.GenISA.PredicatedStore.p1i32.v1i32(ptr addrspace(1) %325, <1 x i32> %342, i64 4, i1 %337) #3
  %343 = insertelement <1 x i32> poison, i32 %.v27, i64 0, !dbg !68
  tail call spir_func void @llvm.genx.GenISA.PredicatedStore.p1i32.v1i32(ptr addrspace(1) %327, <1 x i32> %343, i64 4, i1 %337) #3
  %344 = insertelement <1 x i32> poison, i32 %.v28, i64 0, !dbg !68
  tail call spir_func void @llvm.genx.GenISA.PredicatedStore.p1i32.v1i32(ptr addrspace(1) %329, <1 x i32> %344, i64 4, i1 %338) #3
  %345 = insertelement <1 x i32> poison, i32 %.v29, i64 0, !dbg !68
  tail call spir_func void @llvm.genx.GenISA.PredicatedStore.p1i32.v1i32(ptr addrspace(1) %331, <1 x i32> %345, i64 4, i1 %338) #3
  %346 = insertelement <1 x i32> poison, i32 %.v30, i64 0, !dbg !68
  tail call spir_func void @llvm.genx.GenISA.PredicatedStore.p1i32.v1i32(ptr addrspace(1) %333, <1 x i32> %346, i64 4, i1 %339) #3
  %347 = insertelement <1 x i32> poison, i32 %.v31, i64 0, !dbg !68
  tail call spir_func void @llvm.genx.GenISA.PredicatedStore.p1i32.v1i32(ptr addrspace(1) %335, <1 x i32> %347, i64 4, i1 %339) #3
  ret void, !dbg !69
}

attributes #0 = { mustprogress nounwind willreturn }
attributes #1 = { mustprogress nofree nosync nounwind willreturn memory(none) }
attributes #2 = { nounwind willreturn memory(none) }
attributes #3 = { nounwind willreturn }

!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!2, !3, !4, !5}
!opencl.spir.version = !{!6}
!spirv.Source = !{!7}
!llvm.ident = !{!8}

!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
!1 = !DIFile(filename: "c6acuzgpyqbgyurlqujn43umw2asxnbn7e5ww7krqhvmlmly4sx7.py", directory: "/tmp/tmpjja3nz56/6a")
!2 = !{i32 2, !"Debug Info Version", i32 3}
!3 = !{i32 1, !"wchar_size", i32 4}
!4 = !{i32 1, !"sycl-device", i32 1}
!5 = !{i32 7, !"frame-pointer", i32 2}
!6 = !{i32 1, i32 2}
!7 = !{i32 3, i32 100000}
!8 = !{!"Intel(R) oneAPI DPC++/C++ Compiler 2025.2.1 (2025.2.0.20250806)"}
!9 = !DISubprogram(name: "llvm.genx.GenISA.PredicatedStore.p1i32.v1i32", linkageName: "llvm.genx.GenISA.PredicatedStore.p1i32.v1i32", scope: !1, file: !1, line: 18, type: !10, scopeLine: 18, spFlags: DISPFlagOptimized)
!10 = !DISubroutineType(cc: DW_CC_normal, types: !11)
!11 = !{}
!12 = !DISubprogram(name: "llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32", linkageName: "llvm.genx.GenISA.PredicatedLoad.i32.p1i32.i32", scope: !1, file: !1, line: 18, type: !10, scopeLine: 18, spFlags: DISPFlagOptimized)
!13 = !DISubprogram(name: "_Z12get_local_idj", linkageName: "_Z12get_local_idj", scope: !1, file: !1, line: 18, type: !10, scopeLine: 18, spFlags: DISPFlagOptimized)
!14 = !DISubprogram(name: "_Z12get_group_idj", linkageName: "_Z12get_group_idj", scope: !1, file: !1, line: 18, type: !10, scopeLine: 18, spFlags: DISPFlagOptimized)
!15 = distinct !DISubprogram(name: "triton_poi_fused__chunk_cat_0", linkageName: "triton_poi_fused__chunk_cat_0", scope: !1, file: !1, line: 18, type: !10, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0)
!16 = !{i32 128, i32 1, i32 1}
!17 = !{i32 32}
!18 = !DILocation(line: 21, column: 28, scope: !15)
!19 = !DILocation(line: 21, column: 33, scope: !15)
!20 = !DILocation(line: 22, column: 23, scope: !15)
!21 = !DILocation(line: 23, column: 21, scope: !15)
!22 = !DILocation(line: 24, column: 28, scope: !15)
!23 = !DILocation(line: 24, column: 33, scope: !15)
!24 = !DILocation(line: 25, column: 44, scope: !15)
!25 = !DILocation(line: 25, column: 23, scope: !15)
!26 = !DILocation(line: 26, column: 21, scope: !15)
!27 = !DILocation(line: 29, column: 19, scope: !15)
!28 = !DILocation(line: 28, column: 19, scope: !15)
!29 = !DILocation(line: 43, column: 18, scope: !15)
!30 = !DILocation(line: 46, column: 38, scope: !15)
!31 = !DILocation(line: 46, column: 46, scope: !15)
!32 = !DILocation(line: 46, column: 35, scope: !15)
!33 = !DILocation(line: 46, column: 44, scope: !15)
!34 = !DILocation(line: 46, column: 30, scope: !15)
!35 = !DILocation(line: 46, column: 66, scope: !15)
!36 = !DILocation(line: 61, column: 18, scope: !15)
!37 = !DILocation(line: 64, column: 33, scope: !15)
!38 = !DILocation(line: 64, column: 39, scope: !15)
!39 = !DILocation(line: 64, column: 31, scope: !15)
!40 = !DILocation(line: 64, column: 67, scope: !15)
!41 = !DILocation(line: 79, column: 20, scope: !15)
!42 = !DILocation(line: 82, column: 54, scope: !15)
!43 = !DILocation(line: 82, column: 52, scope: !15)
!44 = !DILocation(line: 82, column: 31, scope: !15)
!45 = !DILocation(line: 82, column: 94, scope: !15)
!46 = !DILocation(line: 97, column: 20, scope: !15)
!47 = !DILocation(line: 100, column: 39, scope: !15)
!48 = !DILocation(line: 100, column: 54, scope: !15)
!49 = !DILocation(line: 100, column: 36, scope: !15)
!50 = !DILocation(line: 100, column: 52, scope: !15)
!51 = !DILocation(line: 100, column: 31, scope: !15)
!52 = !DILocation(line: 100, column: 75, scope: !15)
!53 = !DILocation(line: 115, column: 39, scope: !15)
!54 = !DILocation(line: 115, column: 56, scope: !15)
!55 = !DILocation(line: 115, column: 36, scope: !15)
!56 = !DILocation(line: 115, column: 52, scope: !15)
!57 = !DILocation(line: 115, column: 31, scope: !15)
!58 = !DILocation(line: 115, column: 69, scope: !15)
!59 = !DILocation(line: 115, column: 77, scope: !15)
!60 = !DILocation(line: 118, column: 35, scope: !15)
!61 = !DILocation(line: 121, column: 35, scope: !15)
!62 = !DILocation(line: 124, column: 34, scope: !15)
!63 = !DILocation(line: 127, column: 33, scope: !15)
!64 = !DILocation(line: 130, column: 34, scope: !15)
!65 = !DILocation(line: 130, column: 30, scope: !15)
!66 = !DILocation(line: 130, column: 25, scope: !15)
!67 = !DILocation(line: 130, column: 54, scope: !15)
!68 = !DILocation(line: 130, column: 46, scope: !15)
!69 = !DILocation(line: 130, column: 4, scope: !15)

[whitneywhtsang]

Passes with LLVM opt at O0 but fail at O1.
Passes with LLVM opt DivRemPairsPass disabled.

DivRemPairsPass optimization:

  %33 = srem i32 %13, 3

=>

  %.frozen = freeze i32 %13
  %33 = sdiv i32 %.frozen, 3
  %34 = mul i32 %33, 3
  %.decomposed = sub i32 %.frozen, %34

[etiotto]

Passes with LLVM opt at O0 but fail at O1. Passes with LLVM opt DivRemPairsPass disabled.

DivRemPairsPass optimization:

  %33 = srem i32 %13, 3

=>

  %.frozen = freeze i32 %13
  %33 = sdiv i32 %.frozen, 3
  %34 = mul i32 %33, 3
  %.decomposed = sub i32 %.frozen, %34

This code change look correct. It basically replaces the remainder with the division plus multilication:

r = a % b  ==> q = a / b; r = a - q * b

@whitneywhtsang looks like an IGC issue.

[whitneywhtsang]

Internal tracker is created for IGC team.