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[SYCL][NFC] Code clean-up in properties_cache_control test (#20720)
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‎sycl/test/check_device_code/extensions/properties/properties_cache_control.cpp‎

Lines changed: 58 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
// RUN: %clangxx -fsycl-device-only -S -Xclang -emit-llvm %s -o - | \
2-
// RUN: FileCheck %s --check-prefix CHECK-IR
1+
// RUN: %clangxx -fsycl-device-only -fsycl-targets=spir64 -S -emit-llvm %s -o - | \
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// RUN: FileCheck %s
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#include <sycl/sycl.hpp>
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@@ -127,7 +127,7 @@ void cache_control_load_store_func() {
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auto d_h = d_buf_h;
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auto kernel =
130-
[=](nd_item<2> item) [[intel::reqd_sub_group_size(SG_SIZE)]] {
130+
[=](nd_item<2> item) [[sycl::reqd_sub_group_size(SG_SIZE)]] {
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const int global_tid = item.get_global_id(0);
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const int row_st = global_tid * SG_SIZE;
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@@ -170,58 +170,58 @@ SYCL_EXTERNAL void annotated_ptr_func_param_test(float *p) {
170170
*(store_hint{p}) = 42.0f;
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}
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173-
// CHECK-IR: spir_func{{.*}}annotated_ptr_func_param_test
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// CHECK-IR: {{.*}}call ptr addrspace(4) @llvm.ptr.annotation.p4.p1{{.*}}!spirv.Decorations [[WHINT:.*]]
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// CHECK-IR: ret void
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// CHECK-IR: spir_kernel{{.*}}cache_control_read_hint_func
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// CHECK-IR: {{.*}}addrspacecast ptr addrspace(1){{.*}}!spirv.Decorations [[RHINT:.*]]
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// CHECK-IR: ret void
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// CHECK-IR: spir_kernel{{.*}}cache_control_read_assertion_func
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// CHECK-IR: {{.*}}addrspacecast ptr addrspace(1){{.*}}!spirv.Decorations [[RASSERT:.*]]
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// CHECK-IR: ret void
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// CHECK-IR: spir_kernel{{.*}}cache_control_write_hint_func
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// CHECK-IR: {{.*}}addrspacecast ptr addrspace(1){{.*}}!spirv.Decorations [[WHINT]]
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// CHECK-IR: ret void
188-
189-
// CHECK-IR: spir_kernel{{.*}}cache_control_read_write_func
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// CHECK-IR: {{.*}}addrspacecast ptr addrspace(1){{.*}}!spirv.Decorations [[RWHINT:.*]]
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// CHECK-IR: ret void
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// CHECK-IR: spir_kernel{{.*}}cache_control_load_store_func
194-
// CHECK-IR: {{.*}}getelementptr{{.*}}addrspace(4){{.*}}!spirv.Decorations [[LDSTHINT_A:.*]]
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// CHECK-IR: {{.*}}getelementptr{{.*}}addrspace(4){{.*}}!spirv.Decorations [[LDSTHINT_B:.*]]
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// CHECK-IR: ret void
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// CHECK-IR: [[WHINT]] = !{[[WHINT1:.*]], [[WHINT2:.*]], [[WHINT3:.*]], [[WHINT4:.*]]}
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// CHECK-IR: [[WHINT1]] = !{i32 6443, i32 3, i32 3}
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// CHECK-IR: [[WHINT2]] = !{i32 6443, i32 0, i32 1}
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// CHECK-IR: [[WHINT3]] = !{i32 6443, i32 1, i32 2}
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// CHECK-IR: [[WHINT4]] = !{i32 6443, i32 2, i32 2}
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// CHECK-IR: [[RHINT]] = !{[[RHINT1:.*]], [[RHINT2:.*]], [[RHINT3:.*]]}
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// CHECK-IR: [[RHINT1]] = !{i32 6442, i32 1, i32 0}
206-
// CHECK-IR: [[RHINT2]] = !{i32 6442, i32 2, i32 0}
207-
// CHECK-IR: [[RHINT3]] = !{i32 6442, i32 0, i32 1}
208-
209-
// CHECK-IR: [[RASSERT]] = !{[[RASSERT1:.*]], [[RASSERT2:.*]], [[RASSERT3:.*]]}
210-
// CHECK-IR: [[RASSERT1]] = !{i32 6442, i32 1, i32 3}
211-
// CHECK-IR: [[RASSERT2]] = !{i32 6442, i32 2, i32 3}
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// CHECK-IR: [[RASSERT3]] = !{i32 6442, i32 0, i32 4}
213-
214-
// CHECK-IR: [[RWHINT]] = !{[[RWHINT1:.*]], [[RWHINT2:.*]], [[RWHINT3:.*]]}
215-
// CHECK-IR: [[RWHINT1]] = !{i32 6442, i32 2, i32 1}
216-
// CHECK-IR: [[RWHINT2]] = !{i32 6442, i32 3, i32 4}
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// CHECK-IR: [[RWHINT3]] = !{i32 6443, i32 3, i32 1}
218-
219-
// CHECK-IR: [[LDSTHINT_A]] = !{[[RHINT1]], [[RHINT2]], [[RHINT3]], [[LDSTHINT_A1:.*]], [[LDSTHINT_A2:.*]], [[LDSTHINT_A3:.*]]}
220-
// CHECK-IR: [[LDSTHINT_A1]] = !{i32 6443, i32 0, i32 0}
221-
// CHECK-IR: [[LDSTHINT_A2]] = !{i32 6443, i32 1, i32 0}
222-
// CHECK-IR: [[LDSTHINT_A3]] = !{i32 6443, i32 2, i32 0}
223-
224-
// CHECK-IR: [[LDSTHINT_B]] = !{[[LDSTHINT_B1:.*]], [[RWHINT1]], [[LDSTHINT_B2:.*]], [[LDSTHINT_A2]], [[LDSTHINT_A3]], [[LDSTHINT_B3:.*]]}
225-
// CHECK-IR: [[LDSTHINT_B1]] = !{i32 6442, i32 1, i32 1}
226-
// CHECK-IR: [[LDSTHINT_B2]] = !{i32 6442, i32 0, i32 2}
227-
// CHECK-IR: [[LDSTHINT_B3]] = !{i32 6443, i32 0, i32 2}
173+
// CHECK: spir_func{{.*}}annotated_ptr_func_param_test
174+
// CHECK: {{.*}}call ptr addrspace(4) @llvm.ptr.annotation.p4.p1{{.*}}!spirv.Decorations [[WHINT:.*]]
175+
// CHECK: ret void
176+
177+
// CHECK: spir_kernel{{.*}}cache_control_read_hint_func
178+
// CHECK: {{.*}}addrspacecast ptr addrspace(1){{.*}}!spirv.Decorations [[RHINT:.*]]
179+
// CHECK: ret void
180+
181+
// CHECK: spir_kernel{{.*}}cache_control_read_assertion_func
182+
// CHECK: {{.*}}addrspacecast ptr addrspace(1){{.*}}!spirv.Decorations [[RASSERT:.*]]
183+
// CHECK: ret void
184+
185+
// CHECK: spir_kernel{{.*}}cache_control_write_hint_func
186+
// CHECK: {{.*}}addrspacecast ptr addrspace(1){{.*}}!spirv.Decorations [[WHINT]]
187+
// CHECK: ret void
188+
189+
// CHECK: spir_kernel{{.*}}cache_control_read_write_func
190+
// CHECK: {{.*}}addrspacecast ptr addrspace(1){{.*}}!spirv.Decorations [[RWHINT:.*]]
191+
// CHECK: ret void
192+
193+
// CHECK: spir_kernel{{.*}}cache_control_load_store_func
194+
// CHECK: {{.*}}getelementptr{{.*}}addrspace(4){{.*}}!spirv.Decorations [[LDSTHINT_A:.*]]
195+
// CHECK: {{.*}}getelementptr{{.*}}addrspace(4){{.*}}!spirv.Decorations [[LDSTHINT_B:.*]]
196+
// CHECK: ret void
197+
198+
// CHECK: [[WHINT]] = !{[[WHINT1:.*]], [[WHINT2:.*]], [[WHINT3:.*]], [[WHINT4:.*]]}
199+
// CHECK: [[WHINT1]] = !{i32 6443, i32 3, i32 3}
200+
// CHECK: [[WHINT2]] = !{i32 6443, i32 0, i32 1}
201+
// CHECK: [[WHINT3]] = !{i32 6443, i32 1, i32 2}
202+
// CHECK: [[WHINT4]] = !{i32 6443, i32 2, i32 2}
203+
204+
// CHECK: [[RHINT]] = !{[[RHINT1:.*]], [[RHINT2:.*]], [[RHINT3:.*]]}
205+
// CHECK: [[RHINT1]] = !{i32 6442, i32 1, i32 0}
206+
// CHECK: [[RHINT2]] = !{i32 6442, i32 2, i32 0}
207+
// CHECK: [[RHINT3]] = !{i32 6442, i32 0, i32 1}
208+
209+
// CHECK: [[RASSERT]] = !{[[RASSERT1:.*]], [[RASSERT2:.*]], [[RASSERT3:.*]]}
210+
// CHECK: [[RASSERT1]] = !{i32 6442, i32 1, i32 3}
211+
// CHECK: [[RASSERT2]] = !{i32 6442, i32 2, i32 3}
212+
// CHECK: [[RASSERT3]] = !{i32 6442, i32 0, i32 4}
213+
214+
// CHECK: [[RWHINT]] = !{[[RWHINT1:.*]], [[RWHINT2:.*]], [[RWHINT3:.*]]}
215+
// CHECK: [[RWHINT1]] = !{i32 6442, i32 2, i32 1}
216+
// CHECK: [[RWHINT2]] = !{i32 6442, i32 3, i32 4}
217+
// CHECK: [[RWHINT3]] = !{i32 6443, i32 3, i32 1}
218+
219+
// CHECK: [[LDSTHINT_A]] = !{[[RHINT1]], [[RHINT2]], [[RHINT3]], [[LDSTHINT_A1:.*]], [[LDSTHINT_A2:.*]], [[LDSTHINT_A3:.*]]}
220+
// CHECK: [[LDSTHINT_A1]] = !{i32 6443, i32 0, i32 0}
221+
// CHECK: [[LDSTHINT_A2]] = !{i32 6443, i32 1, i32 0}
222+
// CHECK: [[LDSTHINT_A3]] = !{i32 6443, i32 2, i32 0}
223+
224+
// CHECK: [[LDSTHINT_B]] = !{[[LDSTHINT_B1:.*]], [[RWHINT1]], [[LDSTHINT_B2:.*]], [[LDSTHINT_A2]], [[LDSTHINT_A3]], [[LDSTHINT_B3:.*]]}
225+
// CHECK: [[LDSTHINT_B1]] = !{i32 6442, i32 1, i32 1}
226+
// CHECK: [[LDSTHINT_B2]] = !{i32 6442, i32 0, i32 2}
227+
// CHECK: [[LDSTHINT_B3]] = !{i32 6443, i32 0, i32 2}

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