From 78dbb324ab92ae4b27c31d8adab6b98ea973b624 Mon Sep 17 00:00:00 2001 From: Andrei Elovikov Date: Thu, 9 Jan 2025 13:24:54 -0800 Subject: [PATCH] [SYCL][E2E] Pre-compile `fpga_main.cpp` into `.o` file This particular TU has no device code so can be pre-compiled and passed as an object file to final link invocations without affecting the tests' purpose. I'm not touching `fpga-aoc-archive-split-per-kernel.cpp`/ `fpga-aoc-archive2.cpp` as these two are the slowest and would need other changes. --- sycl/test-e2e/AOT/fpga-aoc-archive-early.cpp | 10 ++++++---- sycl/test-e2e/AOT/fpga-aoc-archive-early2.cpp | 10 ++++++---- sycl/test-e2e/AOT/fpga-aoc-archive-image.cpp | 10 ++++++---- sycl/test-e2e/AOT/fpga-aoc-archive.cpp | 6 ++++-- 4 files changed, 22 insertions(+), 14 deletions(-) diff --git a/sycl/test-e2e/AOT/fpga-aoc-archive-early.cpp b/sycl/test-e2e/AOT/fpga-aoc-archive-early.cpp index ef0e34ec42f3b..fcda842266752 100644 --- a/sycl/test-e2e/AOT/fpga-aoc-archive-early.cpp +++ b/sycl/test-e2e/AOT/fpga-aoc-archive-early.cpp @@ -8,6 +8,8 @@ //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// +// RUN: %clangxx -fintelfpga -fsycl %S/Inputs/fpga_main.cpp -c -o %t_main.o + // Build any early archive binaries. // RUN: %clangxx -fintelfpga -fsycl -fsycl-link=early %S/Inputs/fpga_sub.cpp -o %t_early_sub.a // RUN: %clangxx -fintelfpga -fsycl -fsycl-link=early %S/Inputs/fpga_add.cpp -o %t_early_add.a @@ -16,11 +18,11 @@ //////////////////////////////////////////////////////////////////////////////// // Use a variety of archive orders //////////////////////////////////////////////////////////////////////////////// -// RUN: %clangxx -fintelfpga -fsycl %S/Inputs/fpga_main.cpp %t_early_add.a %t_early_sub.a %t_early_add_x.a %t_early_sub_x.a -o %t_early.out +// RUN: %clangxx -fintelfpga -fsycl %t_main.o %t_early_add.a %t_early_sub.a %t_early_add_x.a %t_early_sub_x.a -o %t_early.out // RUN: %{run} %t_early.out -// RUN: %clangxx -fintelfpga -fsycl %S/Inputs/fpga_main.cpp %t_early_sub_x.a %t_early_add.a %t_early_sub.a %t_early_add_x.a -o %t_early.out +// RUN: %clangxx -fintelfpga -fsycl %t_main.o %t_early_sub_x.a %t_early_add.a %t_early_sub.a %t_early_add_x.a -o %t_early.out // RUN: %{run} %t_early.out -// RUN: %clangxx -fintelfpga -fsycl %S/Inputs/fpga_main.cpp %t_early_add_x.a %t_early_sub_x.a %t_early_add.a %t_early_sub.a -o %t_early.out +// RUN: %clangxx -fintelfpga -fsycl %t_main.o %t_early_add_x.a %t_early_sub_x.a %t_early_add.a %t_early_sub.a -o %t_early.out // RUN: %{run} %t_early.out -// RUN: %clangxx -fintelfpga -fsycl %S/Inputs/fpga_main.cpp %t_early_sub.a %t_early_add_x.a %t_early_sub_x.a %t_early_add.a -o %t_early.out +// RUN: %clangxx -fintelfpga -fsycl %t_main.o %t_early_sub.a %t_early_add_x.a %t_early_sub_x.a %t_early_add.a -o %t_early.out // RUN: %{run} %t_early.out diff --git a/sycl/test-e2e/AOT/fpga-aoc-archive-early2.cpp b/sycl/test-e2e/AOT/fpga-aoc-archive-early2.cpp index 08cc0e8199cfd..85c18358590ad 100644 --- a/sycl/test-e2e/AOT/fpga-aoc-archive-early2.cpp +++ b/sycl/test-e2e/AOT/fpga-aoc-archive-early2.cpp @@ -8,6 +8,8 @@ //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// +// RUN: %clangxx -fintelfpga -fsycl %S/Inputs/fpga_main.cpp -c -o %t_main.o + // Build any early archive binaries. // RUN: %clangxx -fintelfpga -fsycl -fsycl-link=early %S/Inputs/fpga_sub.cpp -o %t_early_sub.a // RUN: %clangxx -fintelfpga -fsycl -fsycl-link=early %S/Inputs/fpga_add.cpp -o %t_early_add.a @@ -25,11 +27,11 @@ //////////////////////////////////////////////////////////////////////////////// // Use a variety of archive orders //////////////////////////////////////////////////////////////////////////////// -// RUN: %clangxx -fintelfpga -fsycl %S/Inputs/fpga_main.cpp %t_early_image_add.a %t_early_image_sub.a %t_early_image_add_x.a %t_early_image_sub_x.a -o %t_early_image.out +// RUN: %clangxx -fintelfpga -fsycl %t_main.o %t_early_image_add.a %t_early_image_sub.a %t_early_image_add_x.a %t_early_image_sub_x.a -o %t_early_image.out // RUN: %{run} %t_early_image.out -// RUN: %clangxx -fintelfpga -fsycl %S/Inputs/fpga_main.cpp %t_early_image_sub_x.a %t_early_image_add.a %t_early_image_sub.a %t_early_image_add_x.a -o %t_early_image.out +// RUN: %clangxx -fintelfpga -fsycl %t_main.o %t_early_image_sub_x.a %t_early_image_add.a %t_early_image_sub.a %t_early_image_add_x.a -o %t_early_image.out // RUN: %{run} %t_early_image.out -// RUN: %clangxx -fintelfpga -fsycl %S/Inputs/fpga_main.cpp %t_early_image_add_x.a %t_early_image_sub_x.a %t_early_image_add.a %t_early_image_sub.a -o %t_early_image.out +// RUN: %clangxx -fintelfpga -fsycl %t_main.o %t_early_image_add_x.a %t_early_image_sub_x.a %t_early_image_add.a %t_early_image_sub.a -o %t_early_image.out // RUN: %{run} %t_early_image.out -// RUN: %clangxx -fintelfpga -fsycl %S/Inputs/fpga_main.cpp %t_early_image_sub.a %t_early_image_add_x.a %t_early_image_sub_x.a %t_early_image_add.a -o %t_early_image.out +// RUN: %clangxx -fintelfpga -fsycl %t_main.o %t_early_image_sub.a %t_early_image_add_x.a %t_early_image_sub_x.a %t_early_image_add.a -o %t_early_image.out // RUN: %{run} %t_early_image.out diff --git a/sycl/test-e2e/AOT/fpga-aoc-archive-image.cpp b/sycl/test-e2e/AOT/fpga-aoc-archive-image.cpp index 6ca28d4e20ad9..f659ad6b588b4 100644 --- a/sycl/test-e2e/AOT/fpga-aoc-archive-image.cpp +++ b/sycl/test-e2e/AOT/fpga-aoc-archive-image.cpp @@ -8,6 +8,8 @@ //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// +// RUN: %clangxx -fintelfpga -fsycl %S/Inputs/fpga_main.cpp -c -o %t_main.o + // Build any image archive binaries. // RUN: %clangxx -fintelfpga -fsycl -fsycl-link=image %S/Inputs/fpga_sub.cpp -o %t_image_sub.a // RUN: %clangxx -fintelfpga -fsycl -fsycl-link=image %S/Inputs/fpga_add.cpp -o %t_image_add.a @@ -16,11 +18,11 @@ //////////////////////////////////////////////////////////////////////////////// // Use a variety of archive orders //////////////////////////////////////////////////////////////////////////////// -// RUN: %clangxx -fintelfpga -fsycl %S/Inputs/fpga_main.cpp %t_image_add.a %t_image_sub.a %t_image_add_x.a %t_image_sub_x.a -o %t_image.out +// RUN: %clangxx -fintelfpga -fsycl %t_main.o %t_image_add.a %t_image_sub.a %t_image_add_x.a %t_image_sub_x.a -o %t_image.out // RUN: %{run} %t_image.out -// RUN: %clangxx -fintelfpga -fsycl %S/Inputs/fpga_main.cpp %t_image_sub_x.a %t_image_add.a %t_image_sub.a %t_image_add_x.a -o %t_image.out +// RUN: %clangxx -fintelfpga -fsycl %t_main.o %t_image_sub_x.a %t_image_add.a %t_image_sub.a %t_image_add_x.a -o %t_image.out // RUN: %{run} %t_image.out -// RUN: %clangxx -fintelfpga -fsycl %S/Inputs/fpga_main.cpp %t_image_add_x.a %t_image_sub_x.a %t_image_add.a %t_image_sub.a -o %t_image.out +// RUN: %clangxx -fintelfpga -fsycl %t_main.o %t_image_add_x.a %t_image_sub_x.a %t_image_add.a %t_image_sub.a -o %t_image.out // RUN: %{run} %t_image.out -// RUN: %clangxx -fintelfpga -fsycl %S/Inputs/fpga_main.cpp %t_image_sub.a %t_image_add_x.a %t_image_sub_x.a %t_image_add.a -o %t_image.out +// RUN: %clangxx -fintelfpga -fsycl %t_main.o %t_image_sub.a %t_image_add_x.a %t_image_sub_x.a %t_image_add.a -o %t_image.out // RUN: %{run} %t_image.out diff --git a/sycl/test-e2e/AOT/fpga-aoc-archive.cpp b/sycl/test-e2e/AOT/fpga-aoc-archive.cpp index 43fa561592783..878f1804200eb 100644 --- a/sycl/test-e2e/AOT/fpga-aoc-archive.cpp +++ b/sycl/test-e2e/AOT/fpga-aoc-archive.cpp @@ -9,6 +9,8 @@ //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// +// RUN: %clangxx -fintelfpga -fsycl %S/Inputs/fpga_main.cpp -c -o %t_main.o + // Build any early archive binaries. // RUN: %clangxx -fintelfpga -fsycl -fsycl-link=early %S/Inputs/fpga_sub.cpp -o %t_early_sub.a // RUN: %clangxx -fintelfpga -fsycl -fsycl-link=early %S/Inputs/fpga_add.cpp -o %t_early_add.a @@ -25,7 +27,7 @@ //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Mix early and image archive usage -// RUN: %clangxx -fintelfpga -fsycl %S/Inputs/fpga_main.cpp %t_early_add.a %t_image_sub.a %t_early_add_x.a %t_image_sub_x.a -o %t_mix.out +// RUN: %clangxx -fintelfpga -fsycl %t_main.o %t_early_add.a %t_image_sub.a %t_early_add_x.a %t_image_sub_x.a -o %t_mix.out // RUN: %{run} %t_mix.out -// RUN: %clangxx -fintelfpga -fsycl %S/Inputs/fpga_main.cpp %t_image_add.a %t_early_sub.a %t_image_add_x.a %t_early_sub_x.a -o %t_mix.out +// RUN: %clangxx -fintelfpga -fsycl %t_main.o %t_image_add.a %t_early_sub.a %t_image_add_x.a %t_early_sub_x.a -o %t_mix.out // RUN: %{run} %t_mix.out