From fb4f6981a4979c919a77760d66faa7051ede22b3 Mon Sep 17 00:00:00 2001 From: Dounia Khaldi Date: Tue, 2 Dec 2025 09:04:22 -0600 Subject: [PATCH] [Doc] Add support for WCL in joint matrix --- .../sycl_ext_oneapi_matrix.asciidoc | 44 ++++++++++++------- 1 file changed, 29 insertions(+), 15 deletions(-) diff --git a/sycl/doc/extensions/experimental/sycl_ext_matrix/sycl_ext_oneapi_matrix.asciidoc b/sycl/doc/extensions/experimental/sycl_ext_matrix/sycl_ext_oneapi_matrix.asciidoc index ea1f509eee8bf..5c59c8dcf7bab 100644 --- a/sycl/doc/extensions/experimental/sycl_ext_matrix/sycl_ext_oneapi_matrix.asciidoc +++ b/sycl/doc/extensions/experimental/sycl_ext_matrix/sycl_ext_oneapi_matrix.asciidoc @@ -1110,7 +1110,8 @@ This is currently available in devices with the architecture `architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`, `architecture::intel_gpu_dg2_g10`, `architecture::intel_gpu_dg2_g11`, `architecture::intel_gpu_dg2_g12`, `architecture::intel_gpu_arl_h`, -`architecture::intel_gpu_ptl_h`, and `architecture::intel_gpu_ptl_u`. +`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`, +and `architecture::intel_gpu_wcl`. [frame="none",options="header"] |====================== @@ -1119,7 +1120,8 @@ This is currently available in devices with the architecture `matrix_type::sint32` .2+| `matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32 |`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`, `architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`, -`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u` +`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`, +`architecture::intel_gpu_wcl` |8|`architecture::intel_gpu_dg2_g10, architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`, `architecture::intel_gpu_arl_h` @@ -1127,7 +1129,8 @@ architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`, `matrix_type::sint32` .2+|`matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32 | `architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`, `architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`, -`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u` +`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`, +`architecture::intel_gpu_wcl` |8|`architecture::intel_gpu_dg2_g10, architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`, `architecture::intel_gpu_arl_h` @@ -1135,7 +1138,8 @@ architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`, `matrix_type::sint32` .2+|`matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32 | `architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`, `architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`, -`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u` +`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`, +`architecture::intel_gpu_wcl` |8|`architecture::intel_gpu_dg2_g10, architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`, `architecture::intel_gpu_arl_h` @@ -1143,7 +1147,8 @@ architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`, `matrix_type::sint32` .2+| `matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32 | `architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`, `architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`, -`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u` +`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`, +`architecture::intel_gpu_wcl` |8|`architecture::intel_gpu_dg2_g10, architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`, `architecture::intel_gpu_arl_h` @@ -1151,7 +1156,8 @@ architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`, `matrix_type::fp32` .8+|`matrix_type::fp32` .1+| 16 .1+| 16 | 16 .6+|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`, `architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`, -`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u` +`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`, +`architecture::intel_gpu_wcl` .2+| 1 .2+| 64 | 16 |32 .2+| 32 .2+| 64 | 16 |32 .2+| +<=+ 8 | 16 .2+| 16 @@ -1163,27 +1169,31 @@ architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`, `matrix_type::fp16` .6+|`matrix_type::fp32` .1+| +<=+ 8 | 16 .1+| 16 .6+| `architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`, `architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`, -`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u` +`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`, +`architecture::intel_gpu_wcl` | 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32 .2+| 32 .2+| 64 | 16 | 32 .6+|`matrix_type::fp16` .6+| `matrix_type::fp16` .6+| `matrix_type::fp32` .6+|`matrix_type::fp16` .1+| +<=+ 8 | 16 .1+| 16 .6+|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`, `architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`, -`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u` +`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`, +`architecture::intel_gpu_wcl` | 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32 .2+| 32 .2+| 64 |16 | 32 .6+|`matrix_type::fp16` .6+| `matrix_type::fp16` .6+| `matrix_type::fp16` .6+|`matrix_type::fp16` .1+| +<=+ 8 | 16 .1+| 16 .6+|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`, `architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`, -`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u` +`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`, +`architecture::intel_gpu_wcl` | 16 | 16 | 16 .2+| 1 .2+| 64 | 16 |32 .2+| 32 .2+| 64 | 16 | 32 .8+| `matrix_type::bf16` .8+| `matrix_type::bf16` .8+| `matrix_type::fp32` .8+| `matrix_type::fp32` | 16 | 16 | 16 .6+|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`, `architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`, -`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u` +`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`, +`architecture::intel_gpu_wcl` .2+| 1 .2+| 64 | 16 | 32 .2+| 32 .2+| 64 | 16 |32 .2+| +<=+ 8 | 16 .2+| 16 @@ -1195,34 +1205,38 @@ architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`, `matrix_type::bf16` .6+|`matrix_type::fp32` .1+| +<=+ 8 | 16 .1+| 16 .6+| `architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`, `architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`, -`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u` +`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`, +`architecture::intel_gpu_wcl` | 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32 .2+| 32 .2+| 64 |16 | 32 .6+|`matrix_type::bf16` .6+| `matrix_type::bf16` .6+| `matrix_type::fp32` .6+|`matrix_type::bf16` .1+| +<=+ 8 | 16 .1+| 16 .6+| `architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`, `architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`, -`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u` +`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`, +`architecture::intel_gpu_wcl` | 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32 .2+| 32 .2+| 64 |16 | 32 .6+|`matrix_type::bf16` .6+| `matrix_type::bf16` .6+| `matrix_type::bf16` .6+|`matrix_type::bf16` .1+| +<=+ 8 | 16 .1+| 16 .6+| `architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`, `architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`, -`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u` +`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`, +`architecture::intel_gpu_wcl` | 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32 .2+| 32 .2+| 64 |16 | 32 | `matrix_type::tf32` | `matrix_type::tf32` | `matrix_type::fp32` .2+| `matrix_type::fp32` | +<=+ 8 | 16 | 8 | `architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`, `architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`, -`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u` +`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`, +`architecture::intel_gpu_wcl` |====================== ===== Restrictions on `architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`, `architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`, `architecture::intel_gpu_ptl_h`, -and `architecture::intel_gpu_ptl_u` +`architecture::intel_gpu_ptl_u`, and `architecture::intel_gpu_wcl` - The `stride` parameter to `joint_matrix_load` and `joint_matrix_store` has the following restrictions: