From f620377e69bd04dce696ced5b6596c42fd5cdd1f Mon Sep 17 00:00:00 2001 From: Nick Sarnie Date: Thu, 5 Jan 2023 08:09:49 -0500 Subject: [PATCH 1/2] Translate Intel-specific RegisterAllocMode metadata (#1800) Frontends can use the RegisterAllocMode metadata can be used to configure the register allocation mode. Here we translate into a form that Intel Graphics Compiler can use to actually apply the configuration. This is only a temporary solution, we intend to introduce an extension in the future Signed-off-by: Sarnie, Nick Original commit: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/commit/2439639ed8e572c372d0db8e8c10c5fc80e61c53 --- llvm-spirv/lib/SPIRV/SPIRVWriter.cpp | 25 +++++++ llvm-spirv/lib/SPIRV/SPIRVWriter.h | 2 + .../test/transcoding/registerallocmode.ll | 74 +++++++++++++++++++ 3 files changed, 101 insertions(+) create mode 100644 llvm-spirv/test/transcoding/registerallocmode.ll diff --git a/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp b/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp index 3bdabeddc5dd4..2ba1c87da7587 100644 --- a/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp +++ b/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp @@ -904,6 +904,8 @@ SPIRVFunction *LLVMToSPIRVBase::transFunctionDecl(Function *F) { transFPGAFunctionMetadata(BF, F); + transFunctionMetadataAsUserSemanticDecoration(BF, F); + SPIRVDBG(dbgs() << "[transFunction] " << *F << " => "; spvdbgs() << *BF << '\n';) return BF; @@ -1048,6 +1050,29 @@ void LLVMToSPIRVBase::transFPGAFunctionMetadata(SPIRVFunction *BF, transMetadataDecorations(FDecoMD, BF); } +void LLVMToSPIRVBase::transFunctionMetadataAsUserSemanticDecoration( + SPIRVFunction *BF, Function *F) { + if (auto *RegisterAllocModeMD = F->getMetadata("RegisterAllocMode")) { + // TODO: Once the design for per-kernel register size allocation is + // finalized, we will need to move away from UserSemantic and introduce an + // extension + int RegisterAllocNodeMDOp = getMDOperandAsInt(RegisterAllocModeMD, 0); + // The current RegisterAllocMode metadata format is as follows + // AUTO - 0 + // SMALL - 1 + // LARGE - 2 + // DEFAULT - 3 + // Currently we only support SMALL and LARGE + if (RegisterAllocNodeMDOp == 1 || RegisterAllocNodeMDOp == 2) { + // 4 threads per eu means large grf mode, and 8 threads per eu + // means small grf mode + std::string NumThreads = RegisterAllocNodeMDOp == 2 ? "4" : "8"; + BF->addDecorate(new SPIRVDecorateUserSemanticAttr( + BF, "num-thread-per-eu " + NumThreads)); + } + } +} + SPIRVValue *LLVMToSPIRVBase::transConstantUse(Constant *C) { // Constant expressions expect their pointer types to be i8* in opaque pointer // mode, but the value may have a different "natural" type. If that is the diff --git a/llvm-spirv/lib/SPIRV/SPIRVWriter.h b/llvm-spirv/lib/SPIRV/SPIRVWriter.h index 3c2669a847e97..892d451122c29 100644 --- a/llvm-spirv/lib/SPIRV/SPIRVWriter.h +++ b/llvm-spirv/lib/SPIRV/SPIRVWriter.h @@ -122,6 +122,8 @@ class LLVMToSPIRVBase : protected BuiltinCallHelper { SPIRVFunction *transFunctionDecl(Function *F); void transVectorComputeMetadata(Function *F); void transFPGAFunctionMetadata(SPIRVFunction *BF, Function *F); + void transFunctionMetadataAsUserSemanticDecoration(SPIRVFunction *BF, + Function *F); bool transGlobalVariables(); Op transBoolOpCode(SPIRVValue *Opn, Op OC); diff --git a/llvm-spirv/test/transcoding/registerallocmode.ll b/llvm-spirv/test/transcoding/registerallocmode.ll new file mode 100644 index 0000000000000..d28bf32bf3654 --- /dev/null +++ b/llvm-spirv/test/transcoding/registerallocmode.ll @@ -0,0 +1,74 @@ +; RUN: llvm-as %s -o %t.bc +; RUN: llvm-spirv -spirv-text %t.bc -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llvm-spirv %t.bc -o %t.spv +; RUN: spirv-val %t.spv +; RUN: llvm-spirv -r -emit-opaque-pointers %t.spv -o - | llvm-dis -o - | FileCheck %s --check-prefix=CHECK-LLVM + +; CHECK-SPIRV: 8 Decorate 4 UserSemantic "num-thread-per-eu 4" +; CHECK-SPIRV: 8 Decorate 6 UserSemantic "num-thread-per-eu 8" +; CHECK-SPIRV-NOT: 8 Decorate 8 +; CHECK-SPIRV-NOT: 8 Decorate 10 +; CHECK-SPIRV-NOT: 8 Decorate 12 + +; CHECK-LLVM: @[[FLAG0:[0-9]+]] = private unnamed_addr constant [20 x i8] c"num-thread-per-eu 4\00", section "llvm.metadata" +; CHECK-LLVM: @[[FLAG1:[0-9]+]] = private unnamed_addr constant [20 x i8] c"num-thread-per-eu 8\00", section "llvm.metadata" +; CHECK-LLVM: @[[FLAG2:[0-9]+]] = private unnamed_addr constant [20 x i8] c"num-thread-per-eu 4\00", section "llvm.metadata" +; CHECK-LLVM: @[[FLAG3:[0-9]+]] = private unnamed_addr constant [20 x i8] c"num-thread-per-eu 8\00", section "llvm.metadata" + +; CHECK-LLVM: @llvm.global.annotations = appending global [4 x { ptr, ptr, ptr, i32, ptr }] [{ ptr, ptr, ptr, i32, ptr } { ptr @main_l3, ptr @[[FLAG0]], ptr undef, i32 undef, ptr undef }, { ptr, ptr, ptr, i32, ptr } { ptr @main_l6, ptr @[[FLAG1]], ptr undef, i32 undef, ptr undef }, { ptr, ptr, ptr, i32, ptr } { ptr @main_l3, ptr @[[FLAG2]], ptr undef, i32 undef, ptr undef }, { ptr, ptr, ptr, i32, ptr } { ptr @main_l6, ptr @[[FLAG3]], ptr undef, i32 undef, ptr undef }], section "llvm.metadata" + +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64" +target triple = "spir64" + +; Function Attrs: noinline nounwind optnone +define weak dso_local spir_kernel void @main_l3() #0 !RegisterAllocMode !10 { +newFuncRoot: + ret void +} + +; Function Attrs: noinline nounwind optnone +define weak dso_local spir_kernel void @main_l6() #0 !RegisterAllocMode !11 { +newFuncRoot: + ret void +} + +; Function Attrs: noinline nounwind optnone +define weak dso_local spir_kernel void @main_l9() #0 !RegisterAllocMode !12 { +newFuncRoot: + ret void +} + +; Function Attrs: noinline nounwind optnone +define weak dso_local spir_kernel void @main_l13() #0 !RegisterAllocMode !13 { +newFuncRoot: + ret void +} + +; Function Attrs: noinline nounwind optnone +define weak dso_local spir_kernel void @main_l19() #0 { +newFuncRoot: + ret void +} + +attributes #0 = { noinline nounwind optnone } + + +!opencl.compiler.options = !{!0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0} +!spirv.Source = !{!2, !3, !3, !3, !3, !3, !2, !3, !2, !2, !2, !2, !2, !2, !2, !2, !2, !2, !2, !2, !2, !2} +!llvm.module.flags = !{!4, !5, !6, !7, !8} +!spirv.MemoryModel = !{!9, !9, !9, !9, !9, !9} +!spirv.ExecutionMode = !{} + +!0 = !{} +!2 = !{i32 4, i32 200000} +!3 = !{i32 3, i32 200000} +!4 = !{i32 1, !"wchar_size", i32 4} +!5 = !{i32 7, !"openmp", i32 50} +!6 = !{i32 7, !"openmp-device", i32 50} +!7 = !{i32 8, !"PIC Level", i32 2} +!8 = !{i32 7, !"frame-pointer", i32 2} +!9 = !{i32 2, i32 2} +!10 = !{i32 2} +!11 = !{i32 1} +!12 = !{i32 0} +!13 = !{i32 3} From 1d21b4f95bd4feab50add49b4fddd458eeeceddd Mon Sep 17 00:00:00 2001 From: "Sarnie, Nick" Date: Thu, 5 Jan 2023 10:25:44 -0500 Subject: [PATCH 2/2] fix lit test Signed-off-by: Sarnie, Nick --- llvm-spirv/test/transcoding/registerallocmode.ll | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/llvm-spirv/test/transcoding/registerallocmode.ll b/llvm-spirv/test/transcoding/registerallocmode.ll index d28bf32bf3654..8522cdb1df649 100644 --- a/llvm-spirv/test/transcoding/registerallocmode.ll +++ b/llvm-spirv/test/transcoding/registerallocmode.ll @@ -12,10 +12,8 @@ ; CHECK-LLVM: @[[FLAG0:[0-9]+]] = private unnamed_addr constant [20 x i8] c"num-thread-per-eu 4\00", section "llvm.metadata" ; CHECK-LLVM: @[[FLAG1:[0-9]+]] = private unnamed_addr constant [20 x i8] c"num-thread-per-eu 8\00", section "llvm.metadata" -; CHECK-LLVM: @[[FLAG2:[0-9]+]] = private unnamed_addr constant [20 x i8] c"num-thread-per-eu 4\00", section "llvm.metadata" -; CHECK-LLVM: @[[FLAG3:[0-9]+]] = private unnamed_addr constant [20 x i8] c"num-thread-per-eu 8\00", section "llvm.metadata" -; CHECK-LLVM: @llvm.global.annotations = appending global [4 x { ptr, ptr, ptr, i32, ptr }] [{ ptr, ptr, ptr, i32, ptr } { ptr @main_l3, ptr @[[FLAG0]], ptr undef, i32 undef, ptr undef }, { ptr, ptr, ptr, i32, ptr } { ptr @main_l6, ptr @[[FLAG1]], ptr undef, i32 undef, ptr undef }, { ptr, ptr, ptr, i32, ptr } { ptr @main_l3, ptr @[[FLAG2]], ptr undef, i32 undef, ptr undef }, { ptr, ptr, ptr, i32, ptr } { ptr @main_l6, ptr @[[FLAG3]], ptr undef, i32 undef, ptr undef }], section "llvm.metadata" +; CHECK-LLVM: @llvm.global.annotations = appending global [2 x { ptr, ptr, ptr, i32, ptr }] [{ ptr, ptr, ptr, i32, ptr } { ptr @main_l3, ptr @[[FLAG0]], ptr undef, i32 undef, ptr undef }, { ptr, ptr, ptr, i32, ptr } { ptr @main_l6, ptr @[[FLAG1]], ptr undef, i32 undef, ptr undef }], section "llvm.metadata" target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64" target triple = "spir64"