From e72b2c89cbf949af2ee0d26a571ca6a71e13835d Mon Sep 17 00:00:00 2001
From: Mark Charney <mark.charney@intel.com>
Date: Thu, 9 Aug 2018 18:49:19 -0400
Subject: [PATCH] add CASCADE_LAKE (CLX) to base layer

Change-Id: Ibed00d19d615ab12e9b5cab0e868e9a89ec75e23
(cherry picked from commit c9d8ef48852781e35215aeb1e142721ec81feadc)
---
 datafiles/clx/clx-chips.txt | 25 +++++++++++++++++++++++++
 datafiles/clx/files.cfg     | 20 ++++++++++++++++++++
 xed_mbuild.py               | 21 +++++++++++++++++----
 3 files changed, 62 insertions(+), 4 deletions(-)
 create mode 100644 datafiles/clx/clx-chips.txt
 create mode 100644 datafiles/clx/files.cfg

diff --git a/datafiles/clx/clx-chips.txt b/datafiles/clx/clx-chips.txt
new file mode 100644
index 00000000..491552aa
--- /dev/null
+++ b/datafiles/clx/clx-chips.txt
@@ -0,0 +1,25 @@
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#  
+#END_LEGAL
+
+# Cascade Lake (CLX) based on Coffee Lake CPU.
+#    Coffee Lake has same ISA as SKX.
+
+CASCADE_LAKE: ALL_OF(SKYLAKE_SERVER) \
+         AVX512_VNNI_128 \
+         AVX512_VNNI_256 \
+         AVX512_VNNI_512
diff --git a/datafiles/clx/files.cfg b/datafiles/clx/files.cfg
new file mode 100644
index 00000000..a066ff90
--- /dev/null
+++ b/datafiles/clx/files.cfg
@@ -0,0 +1,20 @@
+#BEGIN_LEGAL
+#
+#Copyright (c) 2018 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#  
+#END_LEGAL
+
+       chip-models: clx-chips.txt
+
diff --git a/xed_mbuild.py b/xed_mbuild.py
index e0f49f1d..56d1947d 100755
--- a/xed_mbuild.py
+++ b/xed_mbuild.py
@@ -543,6 +543,7 @@ def mkenv():
                                  cet=True,
                                  skl=True,
                                  skx=True,
+                                 clx=True,
                                  cnl=True,
                                  icl=True,
                                  future=True,
@@ -714,11 +715,15 @@ def xed_args(env):
     env.parser.add_option("--no-skl",
                           action="store_false", 
                           dest="skl", 
-                          help="Do not include SKL.")
+                          help="Do not include SKL (Skylake Client).")
     env.parser.add_option("--no-skx",
                           action="store_false", 
                           dest="skx", 
-                          help="Do not include SKX.")
+                          help="Do not include SKX (Skylake Server).")
+    env.parser.add_option("--no-clx",
+                          action="store_false", 
+                          dest="clx", 
+                          help="Do not include CLX (Cascade Lake Server).")
     env.parser.add_option("--no-cnl",
                           action="store_false", 
                           dest="cnl", 
@@ -1138,7 +1143,7 @@ def _configure_libxed_extensions(env):
     if env['avx']:
         env.add_define('XED_AVX')
 
-    if _test_chip(env, ['knl','knm', 'skx', 'cnl', 'icl']):
+    if _test_chip(env, ['knl','knm', 'skx', 'clx', 'cnl', 'icl']):
         env.add_define('XED_SUPPORTS_AVX512')
     if env['knc']:
         env.add_define('XED_SUPPORTS_KNC')
@@ -1250,6 +1255,9 @@ def _add_normal_ext(tenv,x , y='files.cfg'):
             _add_normal_ext(env,'skx')
             _add_normal_ext(env,'pku')
             _add_normal_ext(env,'clwb')
+        if env['clx']:
+            _add_normal_ext(env,'clx')
+            _add_normal_ext(env,'vnni')
         if env['knl']:
             _add_normal_ext(env,'knl')
         if env['knm']:
@@ -2211,12 +2219,13 @@ def run_tests(env):
 
 def verify_args(env):
     if not env['avx']:
-        mbuild.warn("No AVX -> Disabling SNB, IVB, HSW, BDW, SKL, SKX, CNL, ICL, KNL, KNM Future\n\n\n")
+        mbuild.warn("No AVX -> Disabling SNB, IVB, HSW, BDW, SKL, SKX, CLX, CNL, ICL, KNL, KNM Future\n\n\n")
         env['ivb'] = False
         env['hsw'] = False
         env['bdw'] = False
         env['skl'] = False
         env['skx'] = False
+        env['clx'] = False
         env['cnl'] = False
         env['icl'] = False
         env['knl'] = False
@@ -2232,12 +2241,14 @@ def verify_args(env):
         
     if not env['avx512']:
         env['skx'] = False
+        env['clx'] = False
         env['cnl'] = False
         env['icl'] = False
         env['knl'] = False
         env['knm'] = False
         env['future'] = False
 
+    # turn off downstream (later) stuff logically
     if not env['ivb']:
         env['hsw'] = False
     if not env['hsw']:
@@ -2248,6 +2259,7 @@ def verify_args(env):
         env['skx'] = False
     if not env['skx']:
         env['cnl'] = False
+        env['clx'] = False
     if not env['cnl']:
         env['icl'] = False
     if not env['icl']:
@@ -2258,6 +2270,7 @@ def verify_args(env):
         env['knl'] = False
         env['knm'] = False
         env['skx'] = False
+        env['clx'] = False
         env['cnl'] = False
         env['icl'] = False
         env['future'] = False