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[realtek] Allow reaction time between writing RTL_CAPR and reading RT…
…L_CR Some older RTL8139 chips seem to not immediately update the RTL_CR.BUFE bit in response to a write to RTL_CAPR. This results in iPXE seeing a spurious zero-length received packet, and thereafter being out of sync with the hardware's RX ring offset. Fix by inserting an extra PCI read cycle after writing to RTL_CAPR, to give the chip time to react before we next read RTL_CR. Reported-by: Gelip <firstname.lastname@example.org> Tested-by: Gelip <email@example.com> Signed-off-by: Michael Brown <firstname.lastname@example.org>
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