[Bug] Fail to read some values in EPYC 7452QS with EPYCD8

[chraac]

As you can see, some values are invalid and some are void.

And there is a popup error on startup:

Log: Debug_Report_26841671.0179896.txt

[irusanov]

Thanks for the report!
I have many debug files from desktop systems, but very few from server parts, which is understandable due to the app being Windows-only.

The second part of the grayed out values I don't know how to fix, but other readings can be adjusted.
The offsets don't match, it seems. Current offsets for your CPU are mostly based on assumption and I've only hit the VDDP i and maybe MCLK it seems :)

Will make the necessary adjustments and will get back to you.
I would be happy if you could make even more tests for me.

Update:
I see what's going on. The command for table version is disabled for Rome, since I'm not sure if it is the same as on Matisse (desktop Zen2).
You can find it experimentally, but it's kind of risky, because that command (0x8) might mean something completely different on Rome.

[chraac]

Thanks for the report!
I have many debug files from desktop systems, but very few from server parts, which is understandable due to the app being Windows-only.

The second part of the grayed out values I don't know how to fix, but other readings can be adjusted.
The offsets don't match, it seems. Current offsets for your CPU are mostly based on assumption and I've only hit the VDDP i and maybe MCLK it seems :)

Will make the necessary adjustments and will get back to you.
I would be happy if you could make even more tests for me.

Update:
I see what's going on. The command for table version is disabled for Rome, since I'm not sure if it is the same as on Matisse (desktop Zen2).
You can find it experimentally, but it's kind of risky, because that command (0x8) might mean something completely different on Rome.

Thanks for quick reply, I'll be happy to test the new software in may computer.

Another words, is the 0x8 a SMU command that will write to CPU?

[irusanov]

Yes, SMU command with ID 0x8 is "get power table version" for Zen2, but I was unsure it is the same on the server parts and left it disabled. It gets sent to the SMU and the result returned is the table version.
There are other commands that apparently work.

0x5 is the command to refresh power table and it is fine, because your debug reports a correct table.
I believe the chance 0x8 also matches is very big, but still there's a risk.

[chraac]

Just curious that is there a detailed doc about these SMU commands, I am working on the Rome ES overclock, there is also some SMU command to control the Frequency/Voltage of ES, so may be we could summarize them if no such doc.

Further thoughts, we know that AMD CPU has a build-in ARM security processor, maybe the SMU is just an another build-in processor or just a service run on the OS of this embedded CPU.

In the group of PSPReverse in github, they did a lot in revere engineering the PSP, there also a emulator can run local compiling code, maybe we could leverage form it.
PSPReverse - Github

[chraac]

After some search, I found that SMU is a special 32bit processor call "Lattice
LM32 microprocessor". There i a tool to dump the SMU fw and I think we could disasm the fw to get more information about the 0x8 command.
smutool - Github

[chraac]

Here is an analysis about SMU fw, though it's for old model (family 16h), I think it's helpful for digging into the fw.

The analysis doc contains almost everything: image structure, first instruction offset, instruction set, toolchain etc.

AMD x86 SMU firmware analysis

[irusanov]

Not much available, just what was discovered about a year ago on another Rome CPU.
I only know 5-6 commands for it, others are unknown.

[chraac]

@irusanov, I'm happy to test if you have any new version

[irusanov]

We can try this one, but I'm still a bit concerned. Some ES chips don't have the protection retails do.
ZenTimings_v1.2.3.148-debug.zip

[chraac]

What kinds of protection? Over-frequency or over-voltage? My 7452 QS is b0 stepping, I tried to overclock it and it runs very well.

[irusanov]

Yes, overvoltage. The command for setting VSOC was blocked some time ago in one of the newer updates, but it is probably active for the ES. It's close to the retails and I have no access to other Rome CPUs, so can't test it myself, but I think it should be fine.
Just have to avoid sending unknown command IDs with random or 0x0 arguments to be on the safer side.

[chraac]

Is there any command known to set the soc voltage? My soc voltage seems always 0.8-0.9v

[irusanov]

There is such command, but it was long time ago and I don't remember the exact id.
It is not recommended at all, because it accepts VID (and not voltage), where 0 is the highest VID, resulting in 1.55V VSOC.
0 is the default argument, so 1.55V will probably damage/kill your CPU.

[chraac]

We can try this one, but I'm still a bit concerned. Some ES chips don't have the protection retails do.
ZenTimings_v1.2.3.148-debug.zip

I run it in my rome es computer for several minutes and it runs well，the clocks looks good. Thks

[chraac]

The SOC voltage seems untouched after running.