Bidirectional counters, also known as Up/Down counters, are capable of counting in either direction through any given count sequence and they can be reversed at any point within their count sequence by using an additional control input as shown in Fig 1.
Note: Circuit requires further optimization to improve performance. Design yet to be modified.
-Fig. 1
Bidirectional counter has various applications
- Up Counter
- Down Counter
- Analog to Digital converter
- Self-reversing counter
- Clock Divider circuit
- Counting the time allotted for special process or event by the scheduler
The digital circuit takes clock, UporDown and reset as input. It operates as 4-bit up counter when UporDown=1 and as 4-bit down counter when UporDown=0. The port description of the Bidirectional counter is shown in Table below.
| PORT NAME | PORT TYPE | DESCRIPTION |
|---|---|---|
| clk | input | Clock Input |
| UporDown | input | Specifies the mode of operation (Up / Down) |
| reset | input | Resets the counter to 0 |
| count[3:0] | output | 4-bit counter output |
Icarus Verilog is an implementation of the Verilog hardware description language.
GTKWave is a fully featured GTK+ v1. 2 based wave viewer for Unix and Win32 which reads Ver Structural Verilog Compiler generated AET files as well as standard Verilog VCD/EVCD files and allows their viewing
Open your terminal and type the following to install iverilog and GTKWave:
$ sudo apt-get install git
$ sudo apt get update
$ sudo apt get install iverilog gtkwave
To clone the Repository and download the Netlist files for Simulation, enter the following commands in your terminal.
$ sudo apt install -y git
$ git clone https://github.com/isahilmahajan/iiitb_4bbc
$ cd iiitb_4bbc
$ iverilog iiitb_4bbc.v iiitb_4bbc_tb.v
$ ./a.out
$ gtkwave updown.vcd
The software used to run gate level synthesis is Yosys. Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the Yosys C++ code base. [^5]
git clone https://github.com/YosysHQ/yosys.git
make
sudo make install make test
The commands to run synthesis in yosys are given below. First create an yosys script yosys_run.sh and paste the below commands.
read_liberty -lib lib/sky130_fd_sc_hd__tt_025C_1v80.lib
read_verilog iiitb_4bbc.v
synth -top iiitb_4bbc
dfflibmap -liberty /home/sahil/iiitb_4bbc/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
abc -liberty /home/sahil/iiitb_4bbc/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
clean
flatten
write_verilog iiitb_4bbc_synth.v
stat
show
Then, open terminal in the folder iiitb_gc and type the below command.
yosys -s yosys_run.sh
On running the yosys script, we get the following output:
GLS stands for gate level simulation. When we write the RTL code, we test it by giving it some stimulus through the testbench and check it for the desired specifications. Similarly, we run the netlist as the design under test (dut) with the same testbench. Gate level simulation is done to verify the logical correctness of the design after synthesis. Also, it ensures the timing of the design.
Commands to run the GLS are given below.
iverilog -DFUNCTIONAL -DUNIT_DELAY=#0 iiitb_4bbc_synth.v iiitb_4bbc_tb.v iiitb_4bbc/verilog_model/primitives.v /iiitb_4bbc/verilog_model/sky130_fd_sc_hd.v -iiitb_4bbc
./iiitb_4bbc
gtkwave iiitb_4bbc.vcd
The layout is generated using OpenLane. To run a custom design on openlane, Navigate to the openlane folder and run the following commands:
$ cd designs
$ mkdir iiitb_4bbc
$ cd iiitb_4bbc
$ mkdir src
$ touch config.json
$ cd src
$ touch iiitb_4bbc.v
The iiitb_freqdiv.v file should contain the verilog RTL code you have used and got the post synthesis simulation for.
Copy sky130_fd_sc_hd__fast.lib, sky130_fd_sc_hd__slow.lib, sky130_fd_sc_hd__typical.lib and sky130_vsdinv.lef files to src folder in your design.
The final src folder should look like this:
The contents of the config.json are as follows. this can be modified specifically for your design as and when required.
As mentioned by kunal sir dont use defined DIE_AREA and FP_SIZING : absolute, use FP_SIZING : relative
{
"DESIGN_NAME": "iiitb_4bbc",
"VERILOG_FILES": "dir::src/iiitb_4bbc.v",
"CLOCK_PORT": "clkin",
"CLOCK_NET": "clkin",
"GLB_RESIZER_TIMING_OPTIMIZATIONS": true,
"CLOCK_PERIOD": 10,
"PL_TARGET_DENSITY": 0.7,
"FP_SIZING" : "relative",
"pdk::sky130*": {
"FP_CORE_UTIL": 30,
"scl::sky130_fd_sc_hd": {
"FP_CORE_UTIL": 20
}
},
"LIB_SYNTH": "dir::src/sky130_fd_sc_hd__typical.lib",
"LIB_FASTEST": "dir::src/sky130_fd_sc_hd__fast.lib",
"LIB_SLOWEST": "dir::src/sky130_fd_sc_hd__slow.lib",
"LIB_TYPICAL": "dir::src/sky130_fd_sc_hd__typical.lib",
"TEST_EXTERNAL_GLOB": "dir::../iiitb_4bbc/src/*"
}
Save all the changes made above and Navigate to the openlane folder in terminal and give the following command :
$ make mount (if this command doesnot go through prefix it with sudo)
After entering the openlane container give the following command:
$ ./flow.tcl -interactive
This command will take you into the tcl console. In the tcl console type the following commands:
% package require openlane 0.9
% prep -design iiitb_freqdiv
The following commands are to merge external the lef files to the merged.nom.lef. In our case sky130_vsdiat is getting merged to the lef file
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
% run_synthesis
% run_floorplan
Navigate to results->floorplan and type the Magic command in terminal to open the floorplan
$ magic -T /home/himanshu/Sahil/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read ../../tmp/merged.nom.lef def read iiitb_4bbc.def &
Floorplan view
% run_placement
Navigate to results->placement and type the Magic command in terminal to open the placement view
$ magic -T /home/himanshu/Sahil/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read ../../tmp/merged.max.lef def read iiitb_4bbc.def &
Placement View
sky130_vsdinv in the placement view :
% run_cts
% run_routing
Navigate to results->routing and type the Magic command in terminal to open the routing view
$ magic -T /home/himanshu/Sahil/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read ../../tmp/merged.nom.lef def read iiitb_4bbc.def &
Routing View
We can also run the whole flow at once instead of step by step process by giving the following command in openlane container
$ ./flow.tcl -design iiitb_4bbc
All the steps will be automated and all the files will be generated.
Gate count = 24
Area = 2486.293 um^2
performance = 1/(clock period-slack = 1/(10-7.16)ps =352.112GHz)
Flop ratio = 6/24 = 0.25
Total Power = 87.6 uW
- Sahil Mahajan
- Kunal Ghosh
- Siddhant Nayak
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.
- Sahil Mahajan, Postgraduate Student, International Institute of Information Technology, Bangalore sahil.mahajan@iiitb.ac.in
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. kunalghosh@gmail.com
-
Verilogcodes : https://verilogcodes.blogspot.com/2015/10/verilog-code-for-updown-counter-using.html
-
FGPA4Student: https://www.fpga4student.com/2017/03/verilog-code-for-counter-with-testbench.html
-
Icarus Verilog - iverilog
-
GTK Wave documentation