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Wait in READ_DONE until we are done transmitting

We want to hold everything until transmission is done
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1 parent 61e86aa commit 6a3dea2a008e730999591d71d6927d177111159e Raul E Rangel committed Feb 23, 2014
Showing with 43 additions and 35 deletions.
  1. +15 −14 MapleBus.qsf
  2. +7 −7 fifo.v
  3. +4 −2 maplebus.v
  4. +17 −12 maplebus.vt
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29 MapleBus.qsf
@@ -95,7 +95,7 @@ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STI
# ==============================
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_TIME_SCALE "10 ps" -section_id eda_simulation
# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------
@@ -115,18 +115,6 @@ set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name WEAK_PULL_UP_RESISTOR OFF
set_global_assignment -name ENABLE_DRC_SETTINGS ON
-set_global_assignment -name VERILOG_FILE frame_pattern_encoder.v
-set_global_assignment -name VERILOG_FILE data_encoder.v
-set_global_assignment -name VERILOG_FILE transmitter.v
-set_global_assignment -name VERILOG_FILE start_frame_decoder.v
-set_global_assignment -name VERILOG_FILE end_frame_decoder.v
-set_global_assignment -name VERILOG_FILE frame_decoder.v
-set_global_assignment -name VERILOG_FILE data_decoder.v
-set_global_assignment -name VERILOG_FILE synchronizer.v
-set_global_assignment -name SDC_FILE MapleBus.sdc
-set_global_assignment -name VERILOG_FILE maplebus.v
-set_global_assignment -name VERILOG_FILE receiver.v
-set_global_assignment -name VERILOG_FILE fifo.v
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH MapleBusTest -section_id eda_simulation
@@ -138,4 +126,17 @@ set_global_assignment -name EDA_TEST_BENCH_FILE maplebus.vt -section_id MapleBus
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sdcka
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sdckb
set_location_assignment PIN_D2 -to txing
-set_location_assignment PIN_D3 -to rxing
+set_location_assignment PIN_D3 -to rxing
+set_global_assignment -name VERILOG_TEST_BENCH_FILE maplebus.vt
+set_global_assignment -name VERILOG_FILE frame_pattern_encoder.v
+set_global_assignment -name VERILOG_FILE data_encoder.v
+set_global_assignment -name VERILOG_FILE transmitter.v
+set_global_assignment -name VERILOG_FILE start_frame_decoder.v
+set_global_assignment -name VERILOG_FILE end_frame_decoder.v
+set_global_assignment -name VERILOG_FILE frame_decoder.v
+set_global_assignment -name VERILOG_FILE data_decoder.v
+set_global_assignment -name VERILOG_FILE synchronizer.v
+set_global_assignment -name SDC_FILE MapleBus.sdc
+set_global_assignment -name VERILOG_FILE maplebus.v
+set_global_assignment -name VERILOG_FILE receiver.v
+set_global_assignment -name VERILOG_FILE fifo.v
View
14 fifo.v
@@ -8,6 +8,7 @@ module fifo(
output reg tx_enable, // The master has data to transmit to the mbus
+ input wire tx_busy, // The transmitter is busy sending
input wire tx_read, // Write next value to mdata_out
output wire [7:0] tx_data, // mbus data in
@@ -147,7 +148,10 @@ begin
next_state = CAN_READ;
end
READ_DONE: begin
- next_state = SELECT_OUT_FIFO;
+ if (tx_busy)
+ next_state = READ_DONE;
+ else
+ next_state = SELECT_OUT_FIFO;
end
default:
@@ -173,10 +177,10 @@ end
always @(posedge clk, negedge reset) begin : READ_DATA_IN
if (reset == 1'b0)
data_in <= 8'd0;
+ else if (next_state == IDLE)
+ data_in <= 8'd0;
else if (next_state == READ_DATA)
data_in <= fdata[7:0];
- else if (next_state == READ_DONE)
- data_in <= 8'd0;
else
data_in <= data_in;
end
@@ -228,8 +232,6 @@ always @(posedge clk, negedge reset) begin : SLAVE_OUTPUT_ENABLE
sloe <= 1'b1;
else
case (next_state)
- IDLE:
- sloe <= 1'b0;
CAN_READ:
sloe <= 1'b0;
READ:
@@ -238,8 +240,6 @@ always @(posedge clk, negedge reset) begin : SLAVE_OUTPUT_ENABLE
sloe <= 1'b0;
READ_DATA:
sloe <= 1'b0;
- READ_DONE:
- sloe <= 1'b0;
default:
sloe <= 1'b1;
endcase
View
6 maplebus.v
@@ -21,8 +21,6 @@ module maplebus(
);
assign clk_out = clk;
- assign txing = transmitting;
- assign rxing = receiving;
//wire menable, mready;
wire [7:0] rx_data;
@@ -51,6 +49,9 @@ module maplebus(
.data(tx_data) // Data from FIFO
);
+ assign txing = transmitting;
+ assign rxing = receiving;
+
assign sdcka_in = transmitting ? 1'b1 : sdcka;
assign sdckb_in = transmitting ? 1'b1 : sdckb;
@@ -66,6 +67,7 @@ module maplebus(
.rx_data(rx_data),
.tx_enable(tx_enable),
+ .tx_busy(transmitting),
.tx_read(tx_read),
.tx_data(tx_data),
View
29 maplebus.vt
@@ -38,9 +38,15 @@ module maplebus_test;
.pkt_end(pkt_end),
.clk_out(clk_out)
);
-
+
+ wire receiving, write;
+
+ wire [7:0] recv_data;
+
+ receiver rec(clk, reset, sdcka, sdckb, receiving, write, recv_data);
+
always begin
- #1 clk = ~clk;
+ #1 clk = ~clk;
end
reg [7:0] data;
@@ -55,22 +61,21 @@ module maplebus_test;
reset = 1'b1;
flagc = 0;
- data = 8'b01100110;
+ data = 8'b00000010;
#4 flagc = 1;
+ @ (negedge slrd);
+ @ (posedge clk_out);
- while (slrd)
- #2 $display ("Waiting for next flag");
+ #1 data = 8'b11111111;
- #2 data = 8'b10011001;
-
- while (slrd)
- #2 $display ("Waiting for 2nd next flag");
-
- flagc = 0;
+ @ (negedge slrd);
+ @ (posedge clk_out);
- #400 $stop;
+ #1 data = 8'bxxxxxxxx;
+ flagc = 0;
+ #200 $stop;
end
endmodule

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