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Disable the constraints

I think they might be off or wrong because they limit us to under 10mhz
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1 parent 8457946 commit ec83e6423c2c6f33a9ebc4b37f00e44339648403 Raul E Rangel committed Feb 18, 2014
Showing with 2 additions and 2 deletions.
  1. +2 −2 MapleBus.sdc
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4 MapleBus.sdc
@@ -42,8 +42,8 @@ derive_pll_clocks -create_base_clocks
#set_input_delay -clock "internal" -max 91.4ns [get_ports {pkt_end}]
#set_input_delay -clock "internal" -min 2.500ns [get_ports {pkt_end}]
-set_input_delay -clock "internal" -max 96.8ns [get_ports {fdata[0] fdata[1] fdata[2] fdata[3] fdata[4] fdata[5] fdata[6] fdata[7]}]
-set_input_delay -clock "internal" -min 4.500ns [get_ports {fdata[0] fdata[1] fdata[2] fdata[3] fdata[4] fdata[5] fdata[6] fdata[7]}]
+#set_input_delay -clock "internal" -max 96.8ns [get_ports {fdata[0] fdata[1] fdata[2] fdata[3] fdata[4] fdata[5] fdata[6] fdata[7]}]
+#set_input_delay -clock "internal" -min 4.500ns [get_ports {fdata[0] fdata[1] fdata[2] fdata[3] fdata[4] fdata[5] fdata[6] fdata[7]}]

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