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  • 3 files changed
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Commits on Feb 19, 2014
@ismell Clean up some data encoding timing
We now make each 150ns -> 200ns which results in a phase pair that is
1200ns long instead of 900 but it's even and clean. So it better work!
99101e1
Commits on Feb 22, 2014
@ismell IT WORKS!!!!
So we need to wait a cycle after we assert SLRD for the fdata to be
correct. We not don't send a duplicated first byte!
61e86aa
Showing with 127 additions and 84 deletions.
  1. +83 −54 data_encoder.v
  2. +29 −22 fifo.v
  3. +15 −8 frame_pattern_encoder.v
View
137 data_encoder.v
@@ -10,21 +10,24 @@ module data_encoder(
input wire [7:0] data
);
- parameter SIZE = 12;
+ parameter SIZE = 15;
// All the hold states are so we can output a 2mhz signal
- parameter IDLE = 12'b000000000001;
- parameter PHASE1_SETUP = 12'b000000000010;
- parameter PHASE1_DATA = 12'b000000000100;
- parameter PHASE1_TICK = 12'b000000001000;
- parameter PHASE1_TICK_HOLD_1 = 12'b000000010000;
- parameter PHASE1_TICK_HOLD_2 = 12'b000000100000;
- parameter PHASE2_SETUP = 12'b000001000000;
- parameter PHASE2_DATA = 12'b000010000000;
- parameter PHASE2_TOCK = 12'b000100000000;
- parameter PHASE2_TOCK_HOLD_1 = 12'b001000000000;
- parameter PHASE2_TOCK_HOLD_2 = 12'b010000000000;
- parameter DONE = 12'b100000000000;
+ parameter IDLE = 15'b1 << 0;
+ parameter PHASE1_SETUP_1 = 15'b1 << 1;
+ parameter PHASE1_SETUP_2 = 15'b1 << 2;
+ parameter PHASE1_DATA_1 = 15'b1 << 3;
+ parameter PHASE1_DATA_2 = 15'b1 << 4;
+ parameter PHASE1_HOLD_1 = 15'b1 << 5;
+ parameter PHASE1_HOLD_2 = 15'b1 << 6;
+ parameter PHASE2_SETUP_1 = 15'b1 << 7;
+ parameter PHASE2_SETUP_2 = 15'b1 << 8;
+ parameter PHASE2_DATA_1 = 15'b1 << 9;
+ parameter PHASE2_DATA_2 = 15'b1 << 10;
+ parameter PHASE2_HOLD_1 = 15'b1 << 11;
+ parameter PHASE2_HOLD_2 = 15'b1 << 12;
+ parameter DONE_1 = 15'b1 << 13;
+ parameter DONE_2 = 15'b1 << 14;
reg [SIZE-1:0] current_state;
reg [SIZE-1:0] next_state;
@@ -58,33 +61,41 @@ module data_encoder(
case(current_state)
IDLE:
if (enable)
- next_state = PHASE1_SETUP;
+ next_state = PHASE1_SETUP_1;
else
next_state = IDLE;
- PHASE1_SETUP:
- next_state = PHASE1_DATA;
- PHASE1_DATA:
- next_state = PHASE1_TICK;
- PHASE1_TICK:
- next_state = PHASE1_TICK_HOLD_1;
- PHASE1_TICK_HOLD_1:
- next_state = PHASE1_TICK_HOLD_2;
- PHASE1_TICK_HOLD_2:
- next_state = PHASE2_SETUP;
-
- PHASE2_SETUP:
- next_state = PHASE2_DATA;
- PHASE2_DATA:
- next_state = PHASE2_TOCK;
- PHASE2_TOCK:
- next_state = PHASE2_TOCK_HOLD_1;
- PHASE2_TOCK_HOLD_1:
- next_state = PHASE2_TOCK_HOLD_2;
- PHASE2_TOCK_HOLD_2:
+ PHASE1_SETUP_1:
+ next_state = PHASE1_SETUP_2;
+ PHASE1_SETUP_2:
+ next_state = PHASE1_DATA_1;
+ PHASE1_DATA_1:
+ next_state = PHASE1_DATA_2;
+ PHASE1_DATA_2:
+ next_state = PHASE1_HOLD_1;
+ PHASE1_HOLD_1:
+ next_state = PHASE1_HOLD_2;
+ PHASE1_HOLD_2:
+ next_state = PHASE2_SETUP_1;
+
+ PHASE2_SETUP_1:
+ next_state = PHASE2_SETUP_2;
+ PHASE2_SETUP_2:
+ next_state = PHASE2_DATA_1;
+ PHASE2_DATA_1:
+ next_state = PHASE2_DATA_2;
+ PHASE2_DATA_2:
+ next_state = PHASE2_HOLD_1;
+ PHASE2_HOLD_1:
+ next_state = PHASE2_HOLD_2;
+ PHASE2_HOLD_2:
if (pointer == 0 && empty)
- next_state = DONE;
+ next_state = DONE_1;
else
- next_state = PHASE1_SETUP;
+ next_state = PHASE1_SETUP_1;
+ DONE_1:
+ next_state = DONE_2;
+ DONE_2:
+ next_state = IDLE;
default:
next_state = IDLE;
endcase
@@ -95,7 +106,7 @@ module data_encoder(
// -----------------------------------------
assign current_bit = buffer[pointer +: 1];
- assign done = (current_state == DONE ? 1'b1 : 1'b0);
+ assign done = (current_state == DONE_2 ? 1'b1 : 1'b0);
// ------------------------------------------
// Register outputs
@@ -110,7 +121,7 @@ module data_encoder(
case (next_state)
IDLE:
buffer <= 0;
- PHASE1_SETUP:
+ PHASE1_SETUP_1:
if (pointer == 0)
buffer <= data;
else
@@ -130,9 +141,9 @@ module data_encoder(
case (next_state)
IDLE:
pointer <= 0;
- PHASE1_TICK:
+ PHASE1_HOLD_1:
pointer <= pointer + 3'b1;
- PHASE2_TOCK:
+ PHASE2_HOLD_1:
pointer <= pointer + 3'b1;
default:
pointer <= pointer;
@@ -147,11 +158,11 @@ module data_encoder(
end
else begin
case (next_state)
- PHASE1_DATA:
+ PHASE1_DATA_1:
if (pointer == 0)
next <= 1;
else
- next <= 0;
+ next <= 0;
default:
next <= 0;
endcase
@@ -167,47 +178,65 @@ module data_encoder(
end
else begin
case (next_state)
- PHASE1_SETUP: begin
+ PHASE1_SETUP_1: begin
+ sdcka <= 1'b1;
+ sdckb <= sdckb;
+ end
+ PHASE1_SETUP_2: begin
sdcka <= 1'b1;
sdckb <= sdckb;
end
- PHASE1_DATA: begin
+ PHASE1_DATA_1: begin
sdcka <= 1'b1;
sdckb <= current_bit;
end
- PHASE1_TICK: begin
- sdcka <= 1'b0;
+ PHASE1_DATA_2: begin
+ sdcka <= 1'b1;
sdckb <= sdckb;
end
- PHASE1_TICK_HOLD_1: begin
+ PHASE1_HOLD_1: begin
sdcka <= 1'b0;
sdckb <= sdckb;
end
- PHASE1_TICK_HOLD_2: begin
+ PHASE1_HOLD_2: begin
sdcka <= 1'b0;
sdckb <= sdckb;
end
- PHASE2_SETUP: begin
+ PHASE2_SETUP_1: begin
+ sdcka <= sdcka;
+ sdckb <= 1'b1;
+ end
+ PHASE2_SETUP_2: begin
sdcka <= sdcka;
sdckb <= 1'b1;
end
- PHASE2_DATA: begin
+ PHASE2_DATA_1: begin
sdcka <= current_bit;
sdckb <= 1'b1;
end
- PHASE2_TOCK: begin
+ PHASE2_DATA_2: begin
sdcka <= sdcka;
- sdckb <= 1'b0;
+ sdckb <= 1'b1;
end
- PHASE2_TOCK_HOLD_1: begin
+ PHASE2_HOLD_1: begin
sdcka <= sdcka;
sdckb <= 1'b0;
end
- PHASE2_TOCK_HOLD_2: begin
+ PHASE2_HOLD_2: begin
sdcka <= sdcka;
sdckb <= 1'b0;
end
+
+ DONE_1: begin
+ sdcka <= 1'b1;
+ sdckb <= 1'b0;
+ end
+ DONE_2: begin
+ sdcka <= 1'b1;
+ sdckb <= 1'b0;
+ end
+
default: begin
sdcka <= 1'b1;
sdckb <= 1'b1;
View
51 fifo.v
@@ -36,20 +36,20 @@ assign fdata[7:0] = sloe ? data_out[7:0] : 8'bz;
parameter SIZE = 14;
-parameter SELECT_OUT_FIFO = 14'b00000000000001;
-parameter IDLE = 14'b00000000000010;
-parameter SELECT_IN_FIFO = 14'b00000000000100;
-parameter IS_FULL = 14'b00000000001000;
-parameter DROP = 14'b00000000010000;
-parameter HAS_DATA = 14'b00000000100000;
-parameter SETUP_DATA = 14'b00000001000000;
-parameter WRITE = 14'b00000010000000;
-parameter PKTEND = 14'b00000100000000;
-parameter CAN_READ = 14'b00001000000000;
-parameter READ_DATA = 14'b00010000000000;
-parameter READ = 14'b00100000000000;
-parameter IS_EMPTY = 14'b01000000000000;
-parameter READ_DONE = 14'b10000000000000;
+parameter SELECT_OUT_FIFO = 14'b1 << 0;
+parameter IDLE = 14'b1 << 1;
+parameter SELECT_IN_FIFO = 14'b1 << 2;
+parameter IS_FULL = 14'b1 << 3;
+parameter DROP = 14'b1 << 4;
+parameter HAS_DATA = 14'b1 << 5;
+parameter SETUP_DATA = 14'b1 << 6;
+parameter WRITE = 14'b1 << 7;
+parameter PKTEND = 14'b1 << 8;
+parameter CAN_READ = 14'b1 << 9;
+parameter READ = 14'b1 << 10;
+parameter READ_HOLD = 14'b1 << 11;
+parameter READ_DATA = 14'b1 << 12;
+parameter READ_DONE = 14'b1 << 13;
reg [SIZE-1:0] current_state;
reg [SIZE-1:0] next_state;
@@ -86,7 +86,7 @@ begin
if (rx_enable) // Maple Bus has something to transmit
next_state = SELECT_IN_FIFO;
else if (empty == 1'b1) // Host has something to transmit on the MapleBus
- next_state = READ_DATA;
+ next_state = READ_HOLD;
else
next_state = IDLE;
end
@@ -128,9 +128,6 @@ begin
end
// Begin reception from host
- READ_DATA: begin
- next_state = CAN_READ;
- end
CAN_READ: begin
if (empty == 1'b0) // We are empty
next_state = READ_DONE;
@@ -141,8 +138,14 @@ begin
next_state = CAN_READ;
end
READ: begin
+ next_state = READ_HOLD;
+ end
+ READ_HOLD: begin
next_state = READ_DATA;
end
+ READ_DATA: begin
+ next_state = CAN_READ;
+ end
READ_DONE: begin
next_state = SELECT_OUT_FIFO;
end
@@ -207,12 +210,14 @@ always @(posedge clk, negedge reset) begin : ENABLE_TRANSMITTER
tx_enable <= 1'b0;
else
case (next_state)
- READ_DATA:
- tx_enable <= 1'b1;
CAN_READ:
tx_enable <= 1'b1;
READ:
tx_enable <= 1'b1;
+ READ_HOLD:
+ tx_enable <= 1'b1;
+ READ_DATA:
+ tx_enable <= 1'b1;
default:
tx_enable <= 1'b0;
endcase
@@ -225,12 +230,14 @@ always @(posedge clk, negedge reset) begin : SLAVE_OUTPUT_ENABLE
case (next_state)
IDLE:
sloe <= 1'b0;
- READ_DATA:
- sloe <= 1'b0;
CAN_READ:
sloe <= 1'b0;
READ:
sloe <= 1'b0;
+ READ_HOLD:
+ sloe <= 1'b0;
+ READ_DATA:
+ sloe <= 1'b0;
READ_DONE:
sloe <= 1'b0;
default:
View
23 frame_pattern_encoder.v
@@ -10,12 +10,15 @@ module frame_pattern_encoder(
//=============Internal Constants======================
parameter TICKS = 0;
- parameter SIZE = 5;
- parameter IDLE = 5'b00001;
- parameter SETUP_1 = 5'b00010;
- parameter SETUP_2 = 5'b00100;
- parameter COUNTING = 5'b01000;
- parameter DONE = 5'b10000;
+ parameter SIZE = 7;
+
+ parameter IDLE = 7'b1 << 0;
+ parameter SETUP_1 = 7'b1 << 1;
+ parameter SETUP_2 = 7'b1 << 2;
+ parameter SETUP_3 = 7'b1 << 3;
+ parameter COUNTING = 7'b1 << 4;
+ parameter END_1 = 7'b1 << 5; // I think we can remove you
+ parameter DONE = 7'b1 << 6;
//=============Internal Variables======================
reg [SIZE-1:0] current_state;
@@ -52,13 +55,17 @@ module frame_pattern_encoder(
SETUP_1:
next_state <= SETUP_2;
SETUP_2:
- next_state <= COUNTING;
+ next_state <= SETUP_3;
+ SETUP_3:
+ next_state = COUNTING;
COUNTING:
if (count == (TICKS * 2) + 1) begin
- next_state = DONE;
+ next_state = END_1;
end else begin
next_state = COUNTING;
end
+ END_1:
+ next_state = DONE;
DONE:
next_state = IDLE;
default:

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