{"payload":{"header_redesign_enabled":false,"results":[{"id":"212624422","archived":false,"color":"#b2b7f8","followers":21,"has_funding_file":false,"hl_name":"ispras/hdl-benchmarks","hl_trunc_description":"Collection of open HDL modules, subsystems and microprocessors (benchmarks) ","language":"Verilog","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":212624422,"name":"hdl-benchmarks","owner_id":1029546,"owner_login":"ispras","updated_at":"2024-03-22T11:21:34.113Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":59,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aispras%252Fhdl-benchmarks%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/ispras/hdl-benchmarks/star":{"post":"Wnjm66LudbJsLytxinps20zbHYfSm9tChP1Iah5jc7-5IpDdH4hRuHgI_cBvLCsAFR9rKVcqpIirvVmDgLJaLA"},"/ispras/hdl-benchmarks/unstar":{"post":"fbC4vZPB6Guj5br3WNC1fy7wadTrH4aGvcTfn87S7ocoLb82IBnEZwboN4F8AH-CJfavZkuc7XyCFGk31hIlYg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"tolsL3XE2Fjj4N8Xmlu7ATFUBFwg64Dc7MAlCn3Zm4o4QF33UApqwi441qv9yKvEi9QelzyrEcOJcs1E2xxqtw"}}},"title":"Repository search results"}