RISC-V Architecture Verification Suite (AVS)
This repository contains an open test suite for RISC-V microprocessors. Each test is a program (in assembly or C) equipped with additional information: a test purpose description, an instruction describing how to generate a program (if applicable), a test coverage report, etc.
The owner is Ivannikov Institute for System Programming of the Russian Academy of Sciences (ISP RAS). The maintainers are members of Microprocessor Verification Group (MVG).
- MicroTESK Framework, a framework for constructing test program generators for microprocessors;
- MicroTESK for RISC-V, a MicroTESK-based test program generator for RISC-V microprocessors.
You may contribute to this repository by submitting pull requests and by commenting on pull requests submitted by other people. A pull request will be merged when a concensus/decision has been reached by the MVG members.
The licensing policy is derived from RISC-V Compliance Task Group:
- code is licensed under the BSD 3-clause license (SPDX license identifier
- documentation is licensed under the Creative Commons Attribution 4.0 International license (SPDX license identifier
For more information, please contact email@example.com.