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RISC-V Architecture Verification Suite (AVS)
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Alexander Kamkin Updated test suite's README.
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README.md

RISC-V Architecture Verification Suite (AVS)

This repository contains an open test suite for RISC-V microprocessors. Each test is a program (in assembly or C) equipped with additional information: a test purpose description, an instruction describing how to generate a program (if applicable), a test coverage report, etc.

Repository Owner

The owner is Ivannikov Institute for System Programming of the Russian Academy of Sciences (ISP RAS). The maintainers are members of Microprocessor Verification Group (MVG).

Related Projects

The repository relates to MicroTESK in general and to the following ISP RAS projects in particular:

Contribution Process

You may contribute to this repository by submitting pull requests and by commenting on pull requests submitted by other people. A pull request will be merged when a concensus/decision has been reached by the MVG members.

Licensing

The licensing policy is derived from RISC-V Compliance Task Group:

  • code is licensed under the BSD 3-clause license (SPDX license identifier BSD-3-Clause); while
  • documentation is licensed under the Creative Commons Attribution 4.0 International license (SPDX license identifier CC-BY-4.0).

The files COPYING.BSD and COPYING.CC in the top level directory contain the complete text of these licenses.

Contacts

For more information, please contact microtesk-support@ispras.ru.

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