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branch: master

Jun 02, 2011

  1. fpgaminer

    Forgot to add the new SOF file.

    authored June 02, 2011
  2. fpgaminer

    Updated the DE2-115 50MHash SOF binary, and fixed a small bug in the …

    …mine.tcl script.
    authored June 02, 2011

Jun 01, 2011

  1. fpgaminer

    A few modifications to udif's patch. Moved testing to a separate test…

    …bench. Created a testbenches folder with the first testbench in it. Tested udif's patch and it works for all LOOP_LOG2 settings from 0 to 5. Added golden_nonce adjustment code so the mining script no longer has to make the adjustments. Mining script updated with TODOs and removed the golden_nonce adjustments.
    authored June 01, 2011
  2. fpgaminer

    Merge remote-tracking branch 'udif/master' into flexible-unrolling

    authored June 01, 2011
  3. fpgaminer

    NIOS code is written and somewhat functional, but SPI communication w…

    …ith the WizNet board is not functioning correctly when reading registers. It fails randomly for as of yet undetermined reasons.
    authored June 01, 2011
  4. Yet another fix for loop rolling code.

    This time the change seems to work:
    1. Install Icarus verilog 0.9.4 (http://iverilog.icarus.com/)
    2. go to source directory.
    3. run icarus:
       iverilog -DSIM sha*.v fpgaminer_top.v
    4. run with:
       a.out
    
    You can use gtkwave.exe (if you are a Windows user,
    it is bundled with the Windows MinGW-based icarus binary
    (http://bleyer.org/icarus/)
    authored June 01, 2011

May 31, 2011

  1. Take SOF files from original location

    The original script took the SOF files only from the script's current directory.
    Given the current project directory structure, the script now looks for SOF files
    in all the project directories, so its no longer required to copy the SOF files
    to the scripts/program directory.
    authored May 31, 2011
  2. Fix last commit

    Last commit was untested and it seems there was a mistake in the loop index code.
    This code is still untested though!
    authored May 31, 2011

May 26, 2011

  1. Reduce design size by slowing throughput

    This change introduces a LOOP_LOG2 parameter that can reduce the design's
    throughput and size by a factor of 2^N.
    A factor of 8 enables it to fit in an EP3C25 (>90% utilization).
    Design not fully verified yet.
    authored May 26, 2011

May 25, 2011

  1. fpgaminer

    Working on a NIOS II core to controller the miner and communicate ove…

    …r a WizNet ethernet board.
    authored May 24, 2011

May 23, 2011

  1. fpgaminer

    Directory structure reorganized to better suit storing multiple varia…

    …tions on the design.
    authored May 23, 2011

May 20, 2011

  1. fpgaminer

    Cleaned up fpgaminer_top.v. old_golden_ticket wasn't necessary for th…

    …is design.
    authored May 20, 2011
  2. Merge pull request #1 from interfect/master

    Clarified Requirements in README.md. DE2-115 is not a normal DE2.
    authored May 20, 2011
  3. interfect

    Made a note that the DE2-115 is distinct from the normal DE2. Origina…

    …l version got my hopes up.
    authored May 19, 2011
  4. fpgaminer

    Fixing README.md so it renders correctly on github.

    authored May 19, 2011
  5. fpgaminer

    Fixing README.md so it renders correctly on github.

    authored May 19, 2011
  6. First commit. Code ported from existing project, cleaned up, and veri…

    …fied to be somewhat user friendly.
    authored May 19, 2011
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