…bench. Created a testbenches folder with the first testbench in it. Tested udif's patch and it works for all LOOP_LOG2 settings from 0 to 5. Added golden_nonce adjustment code so the mining script no longer has to make the adjustments. Mining script updated with TODOs and removed the golden_nonce adjustments.
…ith the WizNet board is not functioning correctly when reading registers. It fails randomly for as of yet undetermined reasons.
This time the change seems to work: 1. Install Icarus verilog 0.9.4 (http://iverilog.icarus.com/) 2. go to source directory. 3. run icarus: iverilog -DSIM sha*.v fpgaminer_top.v 4. run with: a.out You can use gtkwave.exe (if you are a Windows user, it is bundled with the Windows MinGW-based icarus binary (http://bleyer.org/icarus/)
The original script took the SOF files only from the script's current directory. Given the current project directory structure, the script now looks for SOF files in all the project directories, so its no longer required to copy the SOF files to the scripts/program directory.
Last commit was untested and it seems there was a mistake in the loop index code. This code is still untested though!
This change introduces a LOOP_LOG2 parameter that can reduce the design's throughput and size by a factor of 2^N. A factor of 8 enables it to fit in an EP3C25 (>90% utilization). Design not fully verified yet.
…r a WizNet ethernet board.
…tions on the design.
Clarified Requirements in README.md. DE2-115 is not a normal DE2.
…l version got my hopes up.
…fied to be somewhat user friendly.