{"payload":{"header_redesign_enabled":false,"results":[{"id":"165217789","archived":false,"color":"#b2b7f8","followers":11,"has_funding_file":false,"hl_name":"isuckatdrifting/FusionAccel","hl_trunc_description":"RTL-level Convolutional Network Accelerator Implementation on Xilinx Spartan 6. Evaluation for scalability.","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":165217789,"name":"FusionAccel","owner_id":25215492,"owner_login":"isuckatdrifting","updated_at":"2020-01-09T13:53:18.123Z","has_issues":true}},"sponsorable":false,"topics":["fpga","accelerator","verilog"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":58,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aisuckatdrifting%252FFusionAccel%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/isuckatdrifting/FusionAccel/star":{"post":"jfAjKC680v8blyeCHG1Gohe5Wc3D9pn_GsS8MlikXMGjS6g71WRwg8M3L8QdkhaajU4RMQMF7KIQV_hJtLD98A"},"/isuckatdrifting/FusionAccel/unstar":{"post":"kmbYQneIjDvX6poX06javKplFNV3JKLOgj_2dzC9GJ1LInytqGqs19xwwsvc8uQfvPT0QCMeh37VDdbsA-OYBw"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"s09n0Dtt4NuAkCCST9BdgH8HyFzB8Lxu26iNy4tBs4W42LC5oMtGELvPX5ONLRr1365NJKkqFZDKxCp_QmW-3Q"}}},"title":"Repository search results"}