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Added MMU.

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1 parent f9b7ef0 commit 421b2a1767d19afd2735e5156401ab1be1a5a815 @isuru-c-p committed Apr 23, 2012
Showing with 82 additions and 8 deletions.
  1. +50 −0 rtl/vhdl/dcpu16_mmu.vhd
  2. +31 −8 rtl/vhdl/dcpu16_top.vhd
  3. +1 −0 sim/Makefile
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@@ -0,0 +1,50 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.dcpu16_constants.all;
+
+entity dcpu16_mmu is
+port (
+ Clk, Reset : in std_logic;
+ WriteEn_in : in std_logic;
+ Wr_Address_in : in std_logic_vector(MEM_WIDTH-1 downto 0);
+ Rd_Address_in : in std_logic_vector(MEM_WIDTH-1 downto 0);
+ Q_out : out std_logic_vector(MEM_WIDTH-1 downto 0);
+ WriteData : in std_logic_vector(MEM_WIDTH-1 downto 0);
+
+ Mem_WriteEn_out : out std_logic;
+ Mem_Wr_Address_out : out std_logic_vector(MEM_WIDTH-1 downto 0);
+ Mem_Rd_Address_out : out std_logic_vector(MEM_WIDTH-1 downto 0);
+ Mem_Q_in : in std_logic_vector(MEM_WIDTH-1 downto 0);
+ Mem_WriteData_out : out std_logic_vector(MEM_WIDTH-1 downto 0);
+
+ VGA_Controller_WriteEn_out : out std_logic;
+ VGA_Controller_Wr_Address_out : out std_logic_vector(MEM_WIDTH-1 downto 0);
+ VGA_Controller_Rd_Address_out : out std_logic_vector(MEM_WIDTH-1 downto 0);
+ VGA_Controller_Q_in : in std_logic_vector(MEM_WIDTH-1 downto 0);
+ VGA_Controller_WriteData_out : out std_logic_vector(MEM_WIDTH-1 downto 0)
+);
+end entity;
+
+architecture behaviour of dcpu16_mmu is
+begin
+ process(WriteEn_in, Wr_Address_in, Rd_Address_in, WriteData, Mem_Q_in, VGA_Controller_Q_in)
+ begin
+ if (Rd_Address_in >= std_logic_vector(to_unsigned(32768, MEM_WIDTH))) and (Rd_Address_in <= std_logic_vector(to_unsigned(33279, MEM_WIDTH))) then
+ VGA_Controller_WriteEn_out <= WriteEn_in;
+ VGA_Controller_Wr_Address_out <= Wr_Address_in;
+ VGA_Controller_Rd_Address_out <= Rd_Address_in;
+ VGA_Controller_WriteData_out <= WriteData;
+ Q_out <= VGA_Controller_Q_in;
+ else
+ Mem_WriteEn_out <= WriteEn_in;
+ Mem_Wr_Address_out <= Wr_Address_in;
+ Mem_Rd_Address_out <= Rd_Address_in;
+ Mem_WriteData_out <= WriteData;
+ Q_out <= Mem_Q_in;
+ end if;
+ end process;
+
+end architecture;
View
@@ -18,9 +18,9 @@ end entity;
architecture behaviour of dcpu16_top is
-signal mem_write : std_logic;
-signal mem_rd_addr, mem_wr_addr : std_logic_vector(15 downto 0);
-signal mem_data, mem_wr_data : std_logic_vector(15 downto 0);
+signal Mem_WriteEn, mem_write : std_logic;
+signal Mem_Wr_Address, Mem_Rd_Address, mem_rd_addr, mem_wr_addr : std_logic_vector(15 downto 0);
+signal Mem_Q, Mem_WriteData, mem_data, mem_wr_data : std_logic_vector(15 downto 0);
signal opcode : std_logic_vector(OPCODE_WIDTH-1 downto 0);
signal nonbasic_opcode : std_logic_vector(NONBASIC_OPCODE_WIDTH-1 downto 0);
@@ -43,15 +43,38 @@ signal mem_wr_sel : std_logic_vector(MEM_WR_SEL_WIDTH-1 downto 0);
signal rega_write : std_logic;
begin
+ mmu0: entity work.dcpu16_mmu
+ port map(
+ Clk => Clk,
+ Reset => Reset,
+ WriteEn_in => mem_write,
+ Rd_Address_in => mem_rd_addr,
+ Wr_Address_in => mem_wr_addr,
+ WriteData => mem_wr_data,
+ Q_out => mem_data,
+
+ Mem_WriteEn_out => Mem_WriteEn,
+ Mem_Wr_Address_out => Mem_Wr_Address,
+ Mem_Rd_Address_out => Mem_Rd_Address,
+ Mem_Q_in => Mem_Q,
+ Mem_WriteData_out => Mem_WriteData,
+
+ VGA_Controller_WriteEn_out => open,
+ VGA_Controller_Wr_Address_out => open,
+ VGA_Controller_Rd_Address_out => open,
+ VGA_Controller_Q_in => std_logic_vector(to_unsigned(0, 16)),
+ VGA_Controller_WriteData_out => open
+ );
+
memory0: entity work.memory_sim
port map(
Clk => Clk,
Reset => Reset,
- WriteEn => mem_write,
- Rd_Address => mem_rd_addr,
- Wr_Address => mem_wr_addr,
- Q => mem_data,
- DataIn => mem_wr_data
+ WriteEn => Mem_WriteEn,
+ Rd_Address => Mem_Rd_Address,
+ Wr_Address => Mem_Wr_Address,
+ Q => Mem_Q,
+ DataIn => Mem_WriteData
);
datapath0: entity work.dcpu16_datapath
View
@@ -15,6 +15,7 @@ sim:
vcom $(OPTIONS) $(VHDL_DIR)/dcpu16_reg_file.vhd
vcom $(OPTIONS) $(VHDL_DIR)/dcpu16_datapath.vhd
vcom $(OPTIONS) $(VHDL_DIR)/dcpu16_control_unit.vhd
+ vcom $(OPTIONS) $(VHDL_DIR)/dcpu16_mmu.vhd
vcom $(OPTIONS) $(VHDL_DIR)/memory_sim.vhd
vcom $(OPTIONS) $(VHDL_DIR)/dcpu16_top.vhd
vcom $(OPTIONS) $(VHDL_DIR)/sim_testbench.vhd

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