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Simple cache simulator. The Java version is used during the computer architecture course.
Branch: master
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Cache.hs Initial implementation of the simulator
DirectMappedCache.hs
FullyAssociativeCache.hs Initial implementation of the simulator
LRUQueue.hs Initial implementation of the simulator
Main.hs Initial implementation of the simulator
NWayAssociativeCache.hs Initial implementation of the simulator
README.markdown Initial implementation of the simulator
ReplacementQueue.hs Initial implementation of the simulator

README.markdown

CacheSim

This is a simple implementation of a cache simulator. Basically, the simulator processes an address stream and passes it to the chosen cache implementation, so students can see what the hit/missrates are for different cache organisations and configurations.

The simulator provides three implementation at this point, all of which are defined in terms of the n-way set associative cache.

  • DirectMappedCache
  • FullyAssociativeCache
  • NWaySetAssociativeCache
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