The major goal of this project is to implement an elevator controller chip using skywater 130nm Technology. The project is approved for Tapeout in MPW-8 shuttle.
The project below illustrates how an elevator controller can be designed for as many floors as per the requirement. Here, an 8-storey elevator control system has been proposed.
The elevator decides the direction of movement of the elevator based on the request occurring at the instant. It also consists of a sensor which senses the weight of the people inside the elevator. If the weight inside the elevator exceeds the maximum weight then it stops the further movement of the elevator and also indicates that the weight inside elevator has exceeded the safe limit through the Weight Alert signal.
Moreover it also has another sensor which senses the duration of the door being open. Normally the Door Alert signal is low but goes high whenever the door has been open for more than three minutes. Furthermore, a sensor is situated at each floor indicating that the elevator has passed the current floor.
The layout shown below gives a brief idea as how the elevator controller would function keeping in mind the input control signals as well as the inbuilt sensors (flag variables).
To clone the Repository and download the required files for Simulation, enter the following commands in your terminal.
$ sudo apt install -y git
$ git clone https://github.com/itsnishit/iiitb_elc
$ cd iiitb_elc
Icarus Verilog used to compile verilog files To run the verilog files insall Icarus Verilog (simulation and synthesis tool),enter the following commands in your terminal
$ sudo apt install iverilog
GTKWAVE is an analysis tool which is a VCD waveform viewer. It is used to perform debugging on Verilog models To install GTKWAVE, enter the following commands in your terminal
$ sudo apt install gtkwave
GLS is generating the simulation output by running test bench with netlist file generated from synthesis as design under test. Netlist is logically same as RTL code, therefore, same test bench can be used for it.The picture below gives an insight of the procedure. Here while using iverilog, you also include gate level verilog models to generate GLS simulation.
To clone the repository and download the netlist files for simulation, enter the following command in your terminal*
$ git clone https://github.com/itsnishit/iiitb_elc
After cloning the git repository, type the following in "iiitb_elc directory in the terminal for RTL Simulation.
$ iverilog iiitb_elc.v iiitb_elc_tb.v
$ ./a.out
$ gtkwave iiitb_elc.vcd
For synthesis, run "yosys_run.sh" file in the same directory in terminal.
$ yosys -s yosys_run.sh
The above commands create the netlist of iverilog code.
For Gate level syntheses(GLS), type the following in the same directory in terminal
$ iverilog -DFUNCTIONAL -DUNIT_DELAY=#1 ../iiitb_elc/verilog_model/primitives.v ../iiitb_elc/verilog_model/sky130_fd_sc_hd.v iiitb_elc_synth.v iiitb_elcb.v
To generate the simulation, type the following in the same directory in terminal
$ ./a.out
$ gtkwave iiitb_elc.vcd
In electronic design, a netlist is a description of the connectivity of an electronic circuit.In its simplest form, a netlist consists of a list of the electronic components in a circuit and a list of the nodes they are connected to. A network (net) is a collection of two or more interconnected components.
The above picture shows a small portion of the netlist of the project after synthesis.
The layout is generated using OpenLane. To run a custom design on openlane, Navigate to the openlane folder and run the following commands:
$ cd designs
$ mkdir iiitb_elc
$ cd iiitb_elc
$ mkdir src
$ touch config.json
$ cd src
$ touch iiitb_elc.v
The iiitb_elc.v file should contain the verilog RTL code you have used and got the post synthesis simulation for.
Copy sky130_fd_sc_hd__fast.lib, sky130_fd_sc_hd__slow.lib, sky130_fd_sc_hd__typical.lib and sky130_vsdinv.lef files to src folder in your design. The final src folder should contain 5 files
The contents of the config.json are as follows. this can be modified as per requirement for your design as and when required.
NOTE: As mentioned by Kunal sir, remove defined DIE_AREA and FP_SIZING : absolute, use FP_SIZING : relative
{
"DESIGN_NAME": "iiitb_elc",
"VERILOG_FILES": "dir::src/iiitb_elc.v",
"CLOCK_PORT": "clk",
"CLOCK_NET": "clk",
"GLB_RESIZER_TIMING_OPTIMIZATIONS": true,
"CLOCK_PERIOD": 100,
"PL_RANDOM_GLB_PLACEMENT": 1,
"PL_TARGET_DENSITY": 0.9,
"FP_SIZING" : "relative",
"LIB_SYNTH": "dir::src/sky130_fd_sc_hd__typical.lib",
"LIB_FASTEST": "dir::src/sky130_fd_sc_hd__fast.lib",
"LIB_SLOWEST": "dir::src/sky130_fd_sc_hd__slow.lib",
"LIB_TYPICAL": "dir::src/sky130_fd_sc_hd__typical.lib",
"TEST_EXTERNAL_GLOB": "dir::../iiitb_elc/src/*",
"SYNTH_DRIVING_CELL":"sky130_vsdinv",
"pdk::sky130*": {
"FP_CORE_UTIL": 5,
"scl::sky130_fd_sc_hd": {
"FP_CORE_UTIL": 11
}
}
}
After saving the changes, navigate to the Openlane directory in terminal and give the following command :
After entering the openlane container give the following command:
$ ./flow.tcl interactive
This command will take you into the tcl console. In the tcl console type the following commands:
% package require openlane 0.9
% prep -design iiitb_freqdiv
% run_synthesis
Statistics
Setup and Hold Slack after synthesis
% run_floorplan
Die Area
Core Area
Navigate to results->placement and type the Magic command in terminal to open the floorplan
$ magic -T /home/nishit/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merge.nom.lef def read iiitb_elc.def &
Floorplan view
% run_placement
Navigate to results->placement and type the Magic command in terminal to open the floorplan
$ magic -T /home/nishit/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merge.nom.lef def read iiitb_elc.def &
Placement view
sky130_vsdinv in the placement view :
The sky130_vsdinv should also reflect in the netlist after placement
% run_cts
Slack Report post CTS
Clock Skew Report post CTS
Power Report post CTS
% run_routing
Navigate to results->routing and type the Magic command in terminal to open the routing view
$ magic -T /home/nishit/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merge.nom.lef def read iiitb_elc.def &
Routing View
sky130_vsdinv in the routing view :
Gate Count = 83
Area = 14992.319 um^2
To find the performance of the chip, the netlist generated after the clock tree synthesis is considered. The generated netlist is analysed and is found to contain 12 flipflops. Now, reg to reg path for all the flipflops are calculated using OpenSTA tool. Then, the reg to reg path with the worst slack is considered for calculating the performance.
The steps followed are :
$ sta <br>
OpenSTA> read_liberty -max /home/nishit/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib <br>
OpenSTA> read_liberty -min /home/nishit/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib <br>
OpenSTA> read_verilog /home/nishit/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/iiitb_elc.v <br>
OpenSTA> link_design iiitb_elc <br>
OpenSTA> read_sdc /home/nishit/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/iiitb_elc.sdc <br>
OpenSTA> read_spef /home/nishit/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/iiitb_elc.spef <br>
OpenSTA> set_propagated_clock [all_clocks] <br>
OpenSTA> report_checks <br>
Performance = 1/(clock period - slack) = 1/(100 - 98.83)ns = 0.8547 GHz
Flop Ratio = Ratio of total number of flip flops / Total number of cells present in the design = 12/83 = 0.14457
Internal Power = 13.0 uW (65.4%)
Switching Power = 6.91 uW (34.6%)
Leakage Power = 0.637 nW (0.00%)
Total Power = 20 uW (100%)
Nishit Chechani
Kunal Ghosh
Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.
Nishit Dinesh Chechani, Postgraduate Student, International Institute of Information Technology, Bangalore
E-Mail: nishitchechani@gmail.com
Kunal Ghosh, Director, VSD Corp. Pvt. Ltd
E-Mail: kunalghosh@gmail.com