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J-core SOC for ice40 FPGA
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synth
testrom
README
asymmetric_ram.vhd
bus_monitor.vhd
clk_sim.vhd
components_pkg.vhd
conv.c
cpu.vhd
cpu2j0_pkg.vhd
cpu_bulk_sram.vhd
cpu_lattice.vhd
cpu_pure_tb.vhh
cpu_simple_sram.vhd
cpu_sram.vhd
cpu_up5k_42s.vhd
data_bus_pkg.vhd
datapath.vhd
datapath_pkg.vhd
decode.vhd
decode_body.vhd
decode_core.vhd
decode_pkg.vhd
decode_table.vhd
decode_table_reverse.vhd
decode_table_rom.vhd
decode_table_simple.vhd
free42.pcf
ghdl.sh
ghdl_lattice.sh
ghdl_up5k.sh
lattice_ebr.vhd
lattice_spr.vhd
lattice_spr_wrap.vhd
lattice_tb.vhd
monitor_pkg.vhd
mult.vhd
mult_pkg.vhd
nvc.sh
nvc_lattice.sh
nvc_simple.sh
ram.img
ram.sh
ram_init.vhd
reg.gtkw
register_file.vhd
register_file_sync.vhd
simple_ram.vhd
timeout_cnt.vhd
up5k_tb.vhd
upduino2.pcf
verific

README

# J-core j1 for Lattice ice40 FPGA, with GHDL build/test script

This is a stripped-down build of https://j-core.org j2 processor which
is instruction set compatibile with the full j2 but has no I/O devices,
DRAM controller or SMP support.

Install https://github.com/ghdl/ghdl and run ./ghdl_lattice.sh to build and
simulate this CPU running a test rom. (If it prints the C0 line all instruction
tests passed.) See the testrom/ directory for ROM source, for bare metal
elf toolchain build instructions see:
  http://lists.j-core.org/pipermail/j-core/2019-October/000867.html

A working ICE40 UltraPlus5k bitstream was produced from this source via
Lattice's Synplify+IceCube2 toolchain. It's also been tested with GHDL, NVC,
Xilinx WebPack ISE, and Vivado.

We are working to get a fully open source VHDL toolchain (built from
ghdl+ghdlsynth+yosys+abc) creating bitstreams from that (it doesn't yet).
For build instructions for that see:
  http://lists.j-core.org/pipermail/j-core/2019-November/000868.html
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