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- Fixed: Cog RAM declaration now synthesizes correctly to block ram o…

…n Xilinx parts.
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andrewsil1 committed Sep 1, 2017
1 parent e373590 commit e075d9885f6c99a55c4c966dba87af5538d6d634
Showing with 1 addition and 1 deletion.
  1. +1 −1 HDL/cog_ram.v
@@ -36,7 +36,7 @@ output reg [31:0] q

// 512 x 32 ram

reg [511:0] [31:0] r;
reg [31:0] r [511:0];

always @(posedge clk)
begin

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