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Newfixed (#12)

* added revised fixed point library and named types

* build axi source files

* missing require

* filter out failing axi tests

* arbitrary precision fwriteseq

* made writepixels work with arrays

* added cropseq to unit tests

* newfixed unit tests

* fixed array index unit test

* fixed unit test makefile

* added support for bitwidths > 32

* image diff utility

* added ability to lift rigel modules into fixed

* fixed rigel lift bug

* terra harness works on non axi-aligned data. fixed axiverilog regression & reactivated axiverilog test

* added boolean image write out

* fixed boolean and msb/lsb ops

* makefile bug
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jameshegarty committed Apr 1, 2017
1 parent badffbc commit 1c3ca4a997c80b14322f88247ed1d1d5f24532ac
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@@ -34,4 +34,5 @@ env:
- TARGET=verilog
- TARGET=verilator
- TARGET=terra
- TARGET=unit
- TARGET=unit
- TARGET=axiverilog
@@ -82,6 +82,27 @@ C.sum = memoize(function(A,B,outputType,async)
return partial
end)
-----------------------------
C.select = memoize(function(ty)
err(types.isType(ty), "C.select error: input must be type")
local ITYPE = types.tuple{types.bool(),ty,ty}
local sinp = S.parameter("inp",ITYPE)
local sout = S.select(S.index(sinp,0), S.index(sinp,1), S.index(sinp,2))
local selm = RM.lift("C_select", ITYPE, ty, 1, nil, sinp, sout)
return selm
end)
-----------------------------
C.eq = memoize(function(ty)
err(types.isType(ty), "C.select error: input must be type")
local ITYPE = types.tuple{ty,ty}
local sinp = S.parameter("inp",ITYPE)
local sout = S.eq(S.index(sinp,0), S.index(sinp,1))
local selm = RM.lift("C_eq", ITYPE, types.bool(), 1, nil, sinp, sout)
return selm
end)
-------------
-- {{idxType,vType},{idxType,vType}} -> {idxType,vType}
-- async: 0 cycle delay
@@ -921,4 +942,25 @@ end)
function C.plus100(ty) return C.plusConst(ty,100) end
__linearpipelinecnt = 0
-- convert an array of rigel modules into a straight pipeline
-- pipeline starts at index 1, ends at index N
function C.linearPipeline(t,modulename)
err(modulename==nil or type(modulename)=="string","linearPipeline: modulename must be string")
if modulename==nil then
modulename="linearpipeline"..tostring(__linearpipelinecnt)
__linearpipelinecnt = __linearpipelinecnt+1
end
local inp = R.input(t[1].inputType)
local out = inp
for k,v in ipairs(t) do
out = R.apply("linearPipe"..k,v,out)
end
return RM.lambda(modulename,inp,out)
end
return C
@@ -1,5 +1,6 @@
local cstdlib = terralib.includec("stdlib.h")
local rigel = require "rigel"
local types = require "types"
CT={}
@@ -10,7 +11,9 @@ function CT.identity(A)
end
function CT.cast(A,B)
return terra( a : &A:toTerraType(), out : &B:toTerraType() )
err(types.isType(B), "examples common cast, B must be type")
return terra( a : &A:toTerraType(), out : &B:toTerraType() )
@out = [B:toTerraType()](@a)
end
end
@@ -175,7 +178,7 @@ function CT.plusConsttfn(ty,value)
if ty:verilogBits()~=ty:sizeof()*8 then
--print(ty:verilogBits(),ty:sizeof()*8)
--assert(false)
q = quote @[out] = @[out] and ((1<<[ty:verilogBits()])-1) end
q = quote @[out] = @[out] and (([ty:toTerraType()](1)<<[ty:verilogBits()])-1) end
end
return terra( a : ty:toTerraType(true), [out] )
@@ -184,4 +187,4 @@ function CT.plusConsttfn(ty,value)
end
end
return CT
return CT
View
@@ -38,6 +38,7 @@ local function expectedCycles(hsfn,inputCount,outputCount,underflowTest,slackPer
return EC, EC_RAW
end
--[=[
local underoverWrapper=memoize(function( hsfn, infile, inputType, tapInputType, outfileraw, outfile, outputType, id, inputCount, outputCount, frames, underflowTest, earlyOverride, disableCycleCounter, X)
assert(X==nil)
assert(type(inputCount)=="number")
@@ -93,6 +94,7 @@ local underoverWrapper=memoize(function( hsfn, infile, inputType, tapInputType,
local out = R.apply("fwrite", RM.makeHandshake(RM.fwriteSeq(outfile,outputType)), out )
return RM.lambda( "harness"..id..hsfn.systolicModule.name, inpSymb, out )
end)
]=]
local function harnessAxi( hsfn, inputCount, outputCount, underflowTest, inputType, tapType, earlyOverride)
@@ -137,7 +139,7 @@ local H = {}
if terralib~=nil then
harnessWrapperFn = underoverWrapper
--harnessWrapperFn = underoverWrapper
H.terraOnly = require("harnessTerra")
end
@@ -199,52 +201,77 @@ end
local function axiRateWrapper(fn, tapType)
err(tapType==nil or types.isType(tapType),"tapType should be type or nil")
R.expectHandshake(fn.inputType)
local iover = R.extractData(fn.inputType)
if tapType~=nil then
-- taps have tap value packed into argument
assert(iover.list[2]==tapType)
iover = iover.list[1]
end
err(iover:isArray(), "expected input to be array but is "..tostring(iover))
local iover = R.extractData(fn.inputType)
if tapType~=nil then
-- taps have tap value packed into argument
assert(iover.list[2]==tapType)
iover = iover.list[1]
end
R.expectHandshake(fn.outputType)
oover = R.extractData(fn.outputType)
if iover:verilogBits()==64 and oover:verilogBits()==64 then
return fn
end
--err(iover:isArray(), "expected input to be array but is "..tostring(iover))
local inputP
local inputPointwise
if iover:isArray() then
inputP = iover:channels()
iover = iover:arrayOver()
inputPointwise=false
else
inputP = 1 -- just assume pointwise...
inputPointwise=true
end
R.expectHandshake(fn.outputType)
oover = R.extractData(fn.outputType)
assert(oover:isArray())
local outputP
if oover:isArray() then
outputP = oover:channels()
oover = oover:arrayOver()
else
outputP = 1
end
local targetInputP = (64/iover:verilogBits())
err( targetInputP==math.floor(targetInputP), "axiRateWrapper error: input type does not divide evenly into axi bus size ("..tostring(fn.inputType)..") iover:"..tostring(iover).." inputP:"..tostring(inputP).." tapType:"..tostring(tapType))
--iover = types.array2d( iover, inputP )
local inp = R.input( R.Handshake(types.array2d(iover,targetInputP)) )
local out = inp
if fn.inputType:verilogBits()~=64 then
out = R.apply("harnessCR", RM.liftHandshake(RM.changeRate(iover, 1, targetInputP, inputP )), inp)
end
if inputPointwise then out = R.apply("harnessPW",RM.makeHandshake(C.index(types.array2d(iover,1),0)),out) end
out = R.apply("HarnessHSFN",fn,out) --{input=out, toModule=fn}
if inputPointwise then out = R.apply("harnessPW0",RM.makeHandshake(C.arrayop(oover,1)),out) end
local targetOutputP = (64/oover:verilogBits())
err( targetOutputP==math.floor(targetOutputP), "axiRateWrapper error: output type does not divide evenly into axi bus size")
--oover = types.array2d( oover, outputP )
if fn.outputType:verilogBits()~=64 then
out = R.apply("harnessCREnd", RM.liftHandshake(RM.changeRate(oover,1,outputP,targetOutputP)),out)
end
--fn = RS.defineModule{input=inp,output=out}
local outFn = RM.lambda("hsfnAxiRateWrapper",inp,out)
if iover:verilogBits()~=64 or oover:verilogBits()~=64 then
local inputP_orig = inputP
inputP = (64/fn.inputType:verilogBits())*inputP
iover = types.array2d( iover:arrayOver(), inputP )
local inp = R.input( R.Handshake(iover) )
local out
if fn.inputType:verilogBits()~=64 then
--out = RS.connect{input=inp, toModule=RS.HS(RS.modules.changeRate{ type = iover:arrayOver(), H=1, inW=inputP, outW=inputP_orig })}
out = R.apply("harnessCR", RM.liftHandshake(RM.changeRate(iover:arrayOver(), 1, inputP, inputP_orig )), inp)
end
out = R.apply("HarnessHSFN",fn,out) --{input=out, toModule=fn}
local outputP_orig = outputP
outputP = (64/fn.outputType:verilogBits())*outputP
oover = types.array2d( oover:arrayOver(), outputP )
if fn.outputType:verilogBits()~=64 then
--out = RS.connect{input=out, toModule=RS.HS(RS.modules.changeRate{ type = oover:arrayOver(), H=1, inW=outputP_orig, outW=outputP})}
out = R.apply("harnessCREnd", RM.liftHandshake(RM.changeRate(oover:arrayOver(),1,outputP_orig,outputP)),out)
end
--fn = RS.defineModule{input=inp,output=out}
return RM.lambda("hsfn",inp,out)
end
return fn
assert(outFn.inputType:verilogBits()==64)
assert(outFn.outputType:verilogBits()==64)
return outFn
end
-- AXI must have T=8
@@ -268,8 +295,6 @@ function H.axi(filename, hsfn, inputFilename, tapType, tapValue, inputType, inpu
local inputCount = (inputW*inputH)/inputT
local outputCount = (outputW*outputH)/outputT
hsfn = axiRateWrapper(hsfn, tapType)
-- axi runs the sim as well
--H.sim(filename, hsfn,inputFilename, tapType,tapValue, inputType, inputT, inputW, inputH, outputType, outputT, outputW, outputH, underflowTest,earlyOverride)
local inputCount = (inputW*inputH)/inputT
@@ -313,6 +338,10 @@ function harnessTop(t)
err(type(t.inFile)=="string", "expected input filename to be string")
err(type(t.outFile)=="string", "expected output filename to be string")
if(arg[1]=="axi") then
t.fn = axiRateWrapper(t.fn, t.tapType)
end
-- just assume we were given a handshake vector...
R.expectHandshake(t.fn.inputType)
@@ -351,4 +380,4 @@ function harnessTop(t)
end
return harnessTop
return harnessTop
View
@@ -1,6 +1,31 @@
local R = require "rigel"
local RM = require "modules"
local C = require "examplescommon"
local cstdlib = terralib.includec("stdlib.h")
local fixed = require "fixed"
local types = require("types")
local terraWrapper = memoize(function(fn,inputFilename,inputType,tapType,outputFilename,outputType,id)
local fixedTapInputType = tapType
if tapType==nil then fixedTapInputType = types.null() end
local ITYPE = types.tuple{types.null(),fixedTapInputType}
local inpSymb = R.input( R.Handshake(ITYPE) )
local inpdata = R.apply("inpdata", RM.makeHandshake(C.index(types.tuple{types.null(),fixedTapInputType},0)), inpSymb)
local inptaps = R.apply("inptaps", RM.makeHandshake(C.index(types.tuple{types.null(),fixedTapInputType},1)), inpSymb)
local out = R.apply("fread",RM.makeHandshake(RM.freadSeq(inputFilename,inputType)),inpdata)
local hsfninp = out
if tapType~=nil then
hsfninp = R.apply("HFN",RM.packTuple({inputType,tapType}), R.tuple("hsfninp",{out,inptaps},false))
end
local out = R.apply("HARNESS_inner", fn, hsfninp )
local out = R.apply("fwrite", RM.makeHandshake(RM.fwriteSeq(outputFilename,outputType)), out )
return RM.lambda( "harness"..id..fn.systolicModule.name, inpSymb, out )
end)
return function(filename, hsfn, inputFilename, tapType, tapValue, inputType, inputT, inputW, inputH, outputType, outputT, outputW, outputH, underflowTest, earlyOverride, doHalfTest, X)
@@ -15,7 +40,10 @@ if doHalfTest==nil then doHalfTest=true end
for i=1,bound do
local ext=""
if i==2 then ext="_half" end
local f = RM.seqMapHandshake( harnessWrapperFn( hsfn, inputFilename, inputType, tapType, "out/"..filename, "out/"..filename..ext..".terra.raw", outputType, i, inputCount, outputCount, 1, underflowTest, earlyOverride, true ), inputType, tapType, tapValue, inputCount, outputCount, false, i )
--local f = harnessWrapperFn( hsfn, inputFilename, inputType, tapType, "out/"..filename, "out/"..filename..ext..".terra.raw", outputType, i, inputCount, outputCount, 1, underflowTest, earlyOverride, true )
--local f = terraWrapper{fn=hsfn, inputFilename=inputFilename, outputFilename="out/"..filename..ext..".terra.raw",tapType=tapType, inputType=inputType, outputType=outputType,id=i}
local f = terraWrapper(hsfn,inputFilename,inputType,tapType,"out/"..filename..ext..".terra.raw",outputType,i)
f = RM.seqMapHandshake( f, inputType, tapType, tapValue, inputCount, outputCount, false, i )
local Module = f:compile()
if DARKROOM_VERBOSE then print("Call CPU sim, heap size: "..terralib.sizeof(Module)) end
(terra()
View
@@ -93,8 +93,12 @@ SRCS_AXI := $(filter-out lk_tr_handshake_12_1_axi.lua lk_tr_handshake_12_2_axi.l
SRCS_AXI := $(filter-out lk_wide_handshake_12_1_axi_nostall.lua lk_wide_handshake_12_1_axi.lua,$(SRCS_AXI))
SRCS_AXI := $(filter-out pyramid_large_nofifo_taps_4.lua pyramid_large_taps_3.lua pyramid_taps_3.lua pyramid_taps_4.lua pyramid_large_taps_4.lua,$(SRCS_AXI))
AXIBITS = $(patsubst %.lua,out/%.axi.v,$(SRCS_AXI))
AXIBITS += $(patsubst %.lua,out/%.axi.bit,$(SRCS_AXI))
# type size not a factor of axi bus size
SRCS_AXI := $(filter-out 12bpp.lua 18bpp.lua,$(SRCS_AXI))
AXIVERILOG = $(patsubst %.lua,out/%.axi.v,$(SRCS_AXI))
AXIBITS = $(patsubst %.lua,out/%.axi.bit,$(SRCS_AXI))
AXIBITS100 = $(patsubst %.lua,out/%.axi100.bit,$(SRCS_AXI100))
AXIBITS100 += $(patsubst %.lua,out/%.axi100.bit.bin,$(SRCS_AXI100))
@@ -153,6 +157,8 @@ camerabits: $(CAMERABITS)
axi100: $(AXI100)
axiverilog: $(AXIVERILOG)
axibits: $(AXIBITS)
axibits100: $(AXIBITS100)
@@ -170,13 +176,7 @@ out/%.terra.raw out/%_half.terra.raw: %.lua
$(TERRA) $< terrasim
# keep copy for future reference
mkdir -p out/build_$*
- cp out/$*.cycles.txt out/build_$*
out/%.terra.raw out/%_half.terra.raw: %.lua
$(TERRA) $< terrasim
# keep copy for future reference
mkdir -p out/build_$*
- cp out/$*.cycles.txt out/build_$*
#- cp out/$*.cycles.txt out/build_$*
out/%.isim.v out/%_half.isim.v: %.lua
$(LUA) $< isim
View
@@ -62,3 +62,13 @@ void done(){
void writePixel(string id, int w, int h, unsigned short value){
writeBytes(id,w,h,"uint16",1,2,(unsigned char*)&value);
}
void writePixel(string id, int w, int h, float value){
writeBytes(id,w,h,"float",1,4,(unsigned char*)&value);
}
void writePixel(string id, int w, int h, bool value){
unsigned char v = 0;
if(value){v=255;}
writeBytes(id,w,h,"bool",1,1,&v);
}
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