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Bjump (#137)

* Added reference to basejump libraries, and fixed some bugs.
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jameshegarty committed Mar 28, 2019
1 parent 975a22b commit 1eab21f71846e4654c7e60e41307de08541731fa
Showing with 1,374 additions and 434 deletions.
  1. +3 −0 .gitmodules
  2. +18 −8 .travis.yml
  3. +1 −0 examples/gold/soc_15x15.verilatorSOC.cycles.txt
  4. +1 −0 examples/gold/soc_15x15x15.verilatorSOC.cycles.txt
  5. +1 −0 examples/gold/soc_2in.verilatorSOC.cycles.txt
  6. +1 −0 examples/gold/soc_arbiter.verilatorSOC.cycles.txt
  7. +1 −0 examples/gold/soc_bjump_cache.bmp
  8. +1 −0 examples/gold/soc_bjump_cache.regout.lua
  9. +1 −0 examples/gold/soc_bjump_cache.verilatorSOC.cycles.txt
  10. BIN examples/gold/soc_bjump_cache_nocache.bmp
  11. +1 −0 examples/gold/soc_bjump_cache_nocache.regout.lua
  12. +1 −0 examples/gold/soc_bjump_cache_nocache.verilatorSOC.cycles.txt
  13. +1 −0 examples/gold/soc_convgen.verilatorSOC.cycles.txt
  14. +1 −0 examples/gold/soc_convgenTaps.verilatorSOC.cycles.txt
  15. +1 −0 examples/gold/soc_convtest.verilatorSOC.cycles.txt
  16. +1 −0 examples/gold/soc_filterseq.verilatorSOC.cycles.txt
  17. +1 −0 examples/gold/soc_filterseq8.verilatorSOC.cycles.txt
  18. +1 −0 examples/gold/soc_flip.verilatorSOC.cycles.txt
  19. +1 −0 examples/gold/soc_flipWrite.verilatorSOC.cycles.txt
  20. +1 −0 examples/gold/soc_parread.verilatorSOC.cycles.txt
  21. +1 −0 examples/gold/soc_read.verilatorSOC.cycles.txt
  22. +1 −0 examples/gold/soc_readlen.bmp
  23. +1 −0 examples/gold/soc_readlen.regout.lua
  24. +1 −0 examples/gold/soc_readlen.terra.cycles.txt
  25. +1 −0 examples/gold/soc_readlen.verilatorSOC.cycles.txt
  26. +1 −0 examples/gold/soc_redu1024.verilatorSOC.cycles.txt
  27. +1 −0 examples/gold/soc_redu16384.verilatorSOC.cycles.txt
  28. +1 −0 examples/gold/soc_redu2048.verilatorSOC.cycles.txt
  29. +1 −0 examples/gold/soc_redu32768.verilatorSOC.cycles.txt
  30. +1 −0 examples/gold/soc_redu4096.verilatorSOC.cycles.txt
  31. +1 −0 examples/gold/soc_redu8192.verilatorSOC.cycles.txt
  32. +1 −0 examples/gold/soc_regin.verilatorSOC.cycles.txt
  33. +1 −0 examples/gold/soc_regout.verilatorSOC.cycles.txt
  34. +1 −0 examples/gold/soc_simple.verilatorSOC.cycles.txt
  35. +1 −0 examples/gold/soc_simple_uniform.verilatorSOC.cycles.txt
  36. +1 −0 examples/gold/soc_sort.verilatorSOC.cycles.txt
  37. +1 −0 examples/gold/soc_tokencounter.verilatorSOC.cycles.txt
  38. +1 −0 examples/gold/soc_unaligned.verilatorSOC.cycles.txt
  39. +1 −0 examples/gold/soc_underflow.verilatorSOC.cycles.txt
  40. +17 −2 examples/makefile
  41. +61 −0 examples/soc_bjump_cache.lua
  42. +1 −0 examples/soc_bjump_cache_nocache.lua
  43. +52 −0 examples/soc_readlen.lua
  44. +19 −1 misc/extractMetadata.lua
  45. +7 −0 misc/raw2bmp.lua
  46. +10 −7 modules/axi.lua
  47. +248 −0 modules/bjump.lua
  48. +1 −0 modules/bsg_ip_cores
  49. +81 −15 modules/examplescommon.lua
  50. +9 −9 modules/generators.lua
  51. +1 −1 modules/harnessSOC.lua
  52. +12 −7 modules/harnessTerraSOC.t
  53. +126 −56 modules/modules.lua
  54. +6 −4 modules/modulesTerra.t
  55. +71 −58 modules/soc.lua
  56. +19 −1 platform/verilatorSOC/harness.cpp
  57. +5 −0 platform/verilatorSOC/harness.h
  58. +9 −3 platform/verilatorSOC/verilator_wrapper.lua
  59. +24 −14 platform/verilatorSOC/verilator_wrapper.sv
  60. +237 −28 rigel.lua
  61. +7 −0 src/common.lua
  62. +12 −1 src/sdf.lua
  63. +42 −24 src/systolic.lua
  64. +29 −11 src/systolicsugar.lua
  65. +8 −3 src/types.lua
  66. +203 −181 src/uniform.lua
@@ -0,0 +1,3 @@
[submodule "modules/bsg_ip_cores"]
path = modules/bsg_ip_cores
url = https://bitbucket.org/taylor-bsg/bsg_ip_cores.git
@@ -6,19 +6,28 @@ before_install:
# luajit
- sudo apt-get install luajit

# z3
- if [[ $TARGET = "verilatorSOC" ]] || [[ $TARGET = "terra" ]]; then wget https://github.com/Z3Prover/z3/releases/download/z3-4.7.1/z3-4.7.1-x64-ubuntu-14.04.zip; fi
- if [[ $TARGET = "verilatorSOC" ]] || [[ $TARGET = "terra" ]]; then unzip z3-4.7.1-x64-ubuntu-14.04.zip; fi
- if [[ $TARGET = "verilatorSOC" ]] || [[ $TARGET = "terra" ]]; then export PATH=$PATH:$PWD/z3-4.7.1-x64-ubuntu-14.04/bin; fi
- if [[ $TARGET = "verilatorSOC" ]] || [[ $TARGET = "terra" ]]; then z3 --version; fi

# verilator
- sudo apt-get install verilator
- export PKG_CONFIG_PATH=/home/travis/build/jameshegarty/rigel/platform/verilator
- if [[ $TARGET = "verilator" ]] || [[ $TARGET = "verilatorSOC" ]] || [[ $TARGET = "unit" ]]; then sudo apt-get install verilator; fi
- if [[ $TARGET = "verilator" ]] || [[ $TARGET = "verilatorSOC" ]] || [[ $TARGET = "unit" ]]; then export PKG_CONFIG_PATH=/home/travis/build/jameshegarty/rigel/platform/verilator; fi

# bjump requires more recent verilator
- if [[ $TARGET = "bjump" ]]; then wget https://www.veripool.org/ftp/verilator-4.012.tgz; tar xvzf verilator*.t*gz;cd verilator*;./configure;make -j2;sudo make install; cd ..; fi

#terra
- wget https://github.com/zdevito/terra/releases/download/release-2016-03-25/terra-Linux-x86_64-332a506.zip
- unzip terra-Linux-x86_64-332a506.zip
- sudo ln -s /home/travis/build/jameshegarty/rigel/terra-Linux-x86_64-332a506/bin/terra /usr/bin/terra
- if [[ $TARGET = "terra" ]] || [[ $TARGET = "unit" ]]; then wget https://github.com/zdevito/terra/releases/download/release-2016-03-25/terra-Linux-x86_64-332a506.zip; fi
- if [[ $TARGET = "terra" ]] || [[ $TARGET = "unit" ]]; then unzip terra-Linux-x86_64-332a506.zip; fi
- if [[ $TARGET = "terra" ]] || [[ $TARGET = "unit" ]]; then sudo ln -s /home/travis/build/jameshegarty/rigel/terra-Linux-x86_64-332a506/bin/terra /usr/bin/terra; fi

# this installs correct version of glibc for terra binary
- sudo add-apt-repository -y ppa:ubuntu-toolchain-r/test
- sudo apt-get -y update
- sudo apt-get -y install libstdc++6-4.7-dev
- if [[ $TARGET = "terra" ]] || [[ $TARGET = "unit" ]]; then sudo add-apt-repository -y ppa:ubuntu-toolchain-r/test; fi
- if [[ $TARGET = "terra" ]] || [[ $TARGET = "unit" ]]; then sudo apt-get -y update; fi
- if [[ $TARGET = "terra" ]] || [[ $TARGET = "unit" ]]; then sudo apt-get -y install libstdc++6-4.7-dev; fi

#for coveralls
- if [[ $TARGET = "unit" ]] || [[ $TARGET = "coverage" ]]; then sudo apt-get install luarocks; fi
@@ -42,6 +51,7 @@ env:
- TARGET=verilator
- TARGET=verilatorSOC
- TARGET=terra
- TARGET=bjump
- TARGET=unit
- TARGET=coverage
# - TARGET=axiverilog
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return {}
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return {}
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return {regs_readAddress=805339136,regs_len=1024}
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@@ -1,13 +1,24 @@
BUILDDIR ?= out

# soc_flipWrite.lua
SRCS_SOC = soc_simple.lua soc_simple_uniform.lua soc_2in.lua soc_convgen.lua soc_convgenTaps.lua soc_flip.lua soc_15x15.lua soc_15x15x15.lua soc_flipWrite.lua soc_regin.lua soc_regout.lua soc_convtest.lua soc_read.lua soc_redu1024.lua soc_redu2048.lua soc_redu4096.lua soc_redu8192.lua soc_redu16384.lua soc_redu32768.lua soc_sort.lua soc_filterseq.lua soc_filterseq8.lua soc_unaligned.lua soc_underflow.lua soc_parread.lua soc_tokencounter.lua soc_arbiter.lua
SRCS_SOC = soc_simple.lua soc_simple_uniform.lua soc_2in.lua soc_convgen.lua soc_convgenTaps.lua soc_flip.lua soc_15x15.lua soc_15x15x15.lua soc_flipWrite.lua soc_regin.lua soc_regout.lua soc_convtest.lua soc_read.lua soc_redu1024.lua soc_redu2048.lua soc_redu4096.lua soc_redu8192.lua soc_redu16384.lua soc_redu32768.lua soc_sort.lua soc_filterseq.lua soc_filterseq8.lua soc_unaligned.lua soc_underflow.lua soc_parread.lua soc_tokencounter.lua soc_arbiter.lua soc_readlen.lua


VERILATOR_SOC = $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.bit,$(SRCS_SOC))
VERILATOR_SOC += $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.raw,$(SRCS_SOC))
VERILATOR_SOC += $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.bmp,$(SRCS_SOC))
VERILATOR_SOC += $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.correct.txt,$(SRCS_SOC))
VERILATOR_SOC += $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.regcorrect.txt,$(SRCS_SOC))
VERILATOR_SOC += $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.cyclescorrect.txt,$(SRCS_SOC))

SRCS_BJUMP = soc_bjump_cache.lua soc_bjump_cache_nocache.lua

BJUMP = $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.bit,$(SRCS_BJUMP))
BJUMP += $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.raw,$(SRCS_BJUMP))
BJUMP += $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.bmp,$(SRCS_BJUMP))
BJUMP += $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.correct.txt,$(SRCS_BJUMP))
BJUMP += $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.regcorrect.txt,$(SRCS_BJUMP))
BJUMP += $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.cyclescorrect.txt,$(SRCS_BJUMP))

ZU9VIVADOSOCBITS = $(patsubst %.lua,$(BUILDDIR)/%.zu9vivadoSOC.bit,$(SRCS_SOC))

@@ -18,7 +29,7 @@ ZU9VIVADOSOC += $(patsubst %.lua,$(BUILDDIR)/%.zu9vivadoSOC.correct.txt,$(SRCS_S
ZU9VIVADOSOC += $(patsubst %.lua,$(BUILDDIR)/%.zu9vivadoSOC.regcorrect.txt,$(SRCS_SOC))

SRCS = $(wildcard *.lua)
SRCS := $(filter-out pyramid_core.lua harris_core.lua sift_core.lua sift_core_hw.lua campipe_core.lua descriptor_core.lua stereo_core.lua stereo_tr_core.lua lk_core.lua lk_tr_core.lua $(SRCS_SOC),$(SRCS))
SRCS := $(filter-out pyramid_core.lua harris_core.lua sift_core.lua sift_core_hw.lua campipe_core.lua descriptor_core.lua stereo_core.lua stereo_tr_core.lua lk_core.lua lk_tr_core.lua $(SRCS_BJUMP) $(SRCS_SOC),$(SRCS))
METADATA = $(patsubst %.lua,$(BUILDDIR)/%.metadata.lua,$(SRCS))

RIGEL_VERILATOR_INCLUDE ?= $(shell pkg-config --variable=includedir verilator)
@@ -249,6 +260,10 @@ verilatorSOC: $(VERILATOR_SOC)
touch $(BUILDDIR)/verilatorSOC_done.txt
date

bjump: $(BJUMP)
touch $(BUILDDIR)/bjump_done.txt
date

isim: $(ISIM)

stats: $(STATS)
@@ -0,0 +1,61 @@
local R = require "rigel"
local SOC = require "soc"
local C = require "examplescommon"
local harness = require "harnessSOC"
local G = require "generators"
local RM = require "modules"
local J = require "common"
local types = require "types"
types.export()
local SDF = require "sdf"
local Zynq = require "zynq"

local bjump = require "bjump"

-- bjump cache must load 32bit chunks
-- this does a blur in X. we load 32 pixels in X and sum them. We decimate by 4x in X (read every 4 px), 8x in Y.
-- axi bus is artificially slowed by 8x. If cache works, we expect runtime to be approx 128*64*8. If uncached, it should be 128*64*8*8

local NOCACHE = string.find(arg[0],"nocache")

local W,H = 128,64
noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
noc.extern=true
local regs = SOC.axiRegs({},SDF{1,W*H*8*8},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")

local PosToAddr = G.Module{"PosToAddr",ar(u16,2),
function(loc)
local i = G.PosSeq{{8,1},0}() -- inner loop from 0...2
local x = G.Mul(G.Add(loc[0],i[0]),R.constant(4,u16)) -- (x+i.x)*4
return C.cast(u16,u32)(G.Add(G.Mul(loc[1],R.constant(1920*8,u16)),x))
end}

local SlowRead = C.compose("SlowRead",SOC.read("1080p.raw",1920*1080,ar(u8,4),noc.read,false),RM.liftHandshake(RM.reduceThroughput(types.uint(32),8)))
local SlowReadBurst = C.compose("SlowReadBurst",SOC.read("1080p.raw",1920*1080,ar(u8,4*8),noc.read,false),RM.liftHandshake(RM.reduceThroughput(types.uint(32),8)))
local BurstRead = C.compose("BurstRead",G.HS{G.SerSeq{8}},SlowReadBurst)

local CachedReadModule = G.Module{ "CachedReadModule", R.HandshakeTrigger,
function(i)
i = G.TriggerBroadcast{W*H}(i)
local pos = G.HS{G.Pos{{W,H},0}}(i)

local posDup = G.Map{G.HS{G.BroadcastSeq{{8,1},0}}}(pos)
local addr = G.HS{G.Map{PosToAddr}}(posDup) -- mult coords by 8

local stencil
if NOCACHE then
stencil = G.Map{SlowRead}(addr)
else
stencil = G.Map{bjump.AXICachedRead(ar(u(8),4),8,8,BurstRead)}(addr)
end

stencil = G.Map{G.HS{G.Deser{8}}}(stencil)

local shifted = G.HS{G.Map{G.Map{G.Rshift{5}}}}(stencil)
local fin = G.HS{G.Map{G.Reduce{G.Add}}}(shifted)
return G.AXIWriteBurst{"out/soc_bjump_cache"..J.sel(NOCACHE,"_nocache",""),noc.write}(fin)
end}

print(CachedReadModule)

harness({regs.start, CachedReadModule, regs.done},nil,{regs})
@@ -0,0 +1,52 @@
local R = require "rigel"
local G = require "generators"
local SOC = require "soc"
local harness = require "harnessSOC"
require "types".export()
local SDF = require "sdf"
local RM = require "modules"
local Zynq = require "zynq"
local C = require "examplescommon"
local Uniform = require "uniform"


-- this is an example of a simple runtime configurable DMA that loads 64bits/cycle at a configurable address & length

noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
noc.extern=true
local regs = SOC.axiRegs({readAddress={u(32),0x30008000},len={u32,(128*64)/8}},SDF{1,(128/8)*64},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")

local Len = Uniform(regs.len)
Len:addProperty( Len:ge(1) )
Len:addProperty( Len:lt(math.pow(2,16)) )

-- DANGEROUS HACK
regs.module.functions.start.sdfOutput = SDF{1,Len}
regs.module.functions.done.sdfInput = SDF{1,Len}

-- This is the actual DMA
ReadLenDMA = G.Module{ "ReadLenDMA", HandshakeTrigger, SDF{1,Len},
function(trig)
trig = C.triggerUp(regs.len)(trig)
local addrStream = G.HS{RM.counter(u32,regs.len)}(trig)
--addrStream = G.HS{G.Print{"AddrIn"}}(addrStream)
return SOC.read("frame_128.raw",128*64,ar(u8,8),noc.read)(addrStream)
end}

AddAddr = G.Module{"AddAddr",function(i) return R.concat{RM.counter(u32,regs.len)(),i} end}
WriteLenDMA = G.Module{ "WriteLenDMA", Handshake(ar(u8,8)),
function(i)
local addrStream = G.HS{AddAddr}(i)
local bresp = SOC.write("out/soc_readlen",regs.len,1,ar(u8,8),0,true,noc.write)(addrStream)
return RM.triggerCounter(Len)(bresp)
end}

TestDMA = C.linearPipeline({ReadLenDMA,G.HS{G.Map{C.plusConst(u8,200)}},WriteLenDMA},"TestDMA")
print(TestDMA)

-- hack
TestDMA.globalMetadata.MAXI0_write_W = 128
TestDMA.globalMetadata.MAXI0_write_H = 64
TestDMA.globalMetadata.MAXI0_write_bitsPerPixel = 8

harness({regs.start, TestDMA, regs.done},{cycles=1124},{regs})
@@ -52,8 +52,15 @@ elseif arg[2]=="__OUTPUTS" or arg[2]=="__OUTPUTS_ZYNQ" then
if regAddress==nil then print("Could not find register"); assert(false) end
str = str.." reg:0x"..string.format("%x",regAddress).." "
end

local W = v.W
if type(W)=="string" then
local regAddress = metadata.registers[W]
if regAddress==nil then print("Could not find register"); assert(false) end
W = tonumber("0x"..metadata.registerValues[regAddress])
end

str = str.." "..v.W.." "..v.H.." "..v.bitsPerPixel.." "
str = str.." "..W.." "..v.H.." "..v.bitsPerPixel.." "
end
print(str)
elseif arg[2]=="__REGISTERS" then
@@ -80,6 +87,17 @@ elseif arg[2]=="INPUT_FILES" then
i = i + 1
end
print(str)
elseif arg[2]=="cycles" then
if type(metadata.cycles)=="number" then
print(metadata.cycles)
elseif type(metadata.cycles)=="string" then
-- register lookup
local addr = metadata.registers[metadata.cycles]
if addr==nil then print("Could not find register for cycles"); assert(false) end
print(tonumber("0x"..metadata.registerValues[addr]))
else
assert(false)
end
else
if type(metadata[arg[2]])=="table" then
print(table.concat(metadata[arg[2]]," "))
@@ -10,6 +10,13 @@ if type(metadata.outputs)=="table" then
metadata.outputBitsPerPixel = metadata.outputs[1].bitsPerPixel
metadata.outputWidth = metadata.outputs[1].W
metadata.outputHeight = metadata.outputs[1].H

-- value is in a register
if type(metadata.outputWidth)=="string" then
local addr = metadata.registers[metadata.outputWidth]
if addr==nil then print("Could not find register for cycles"); assert(false) end
metadata.outputWidth = tonumber("0x"..metadata.registerValues[addr])
end
end

ffi.cdef[[
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