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Improved regs (#149)

* Improved functionality of register slave - it can now delegate storage to any module with a read/write port.
* perf improvements in compiler so that it works better on large designs
* fixes on terra backend
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jameshegarty committed Oct 18, 2019
1 parent b767ec0 commit 61bbd7e10c486901651378df6d029233d5d8f75f
@@ -0,0 +1 @@
return {}
@@ -0,0 +1 @@
2092813
@@ -0,0 +1 @@
2092815
@@ -1,7 +1,7 @@
BUILDDIR ?= out

# soc_flipWrite.lua
SRCS_SOC = soc_simple.lua soc_simple_uniform.lua soc_2in.lua soc_convgen.lua soc_convgenTaps.lua soc_flip.lua soc_15x15.lua soc_15x15x15.lua soc_flipWrite.lua soc_regin.lua soc_regout.lua soc_convtest.lua soc_read.lua soc_redu1024.lua soc_redu2048.lua soc_redu4096.lua soc_redu8192.lua soc_redu16384.lua soc_redu32768.lua soc_sort.lua soc_filterseq.lua soc_filterseq8.lua soc_unaligned.lua soc_underflow.lua soc_parread.lua soc_tokencounter.lua soc_arbiter.lua soc_readlen.lua
SRCS_SOC = soc_simple.lua soc_simple_uniform.lua soc_2in.lua soc_convgen.lua soc_convgen_0.lua soc_convgenTaps.lua soc_flip.lua soc_15x15.lua soc_15x15x15.lua soc_flipWrite.lua soc_regin.lua soc_regout.lua soc_convtest.lua soc_read.lua soc_redu1024.lua soc_redu2048.lua soc_redu4096.lua soc_redu8192.lua soc_redu16384.lua soc_redu32768.lua soc_sort.lua soc_filterseq.lua soc_filterseq8.lua soc_unaligned.lua soc_underflow.lua soc_parread.lua soc_tokencounter.lua soc_arbiter.lua soc_readlen.lua

VERILATOR_SOC = $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.bit,$(SRCS_SOC))
VERILATOR_SOC += $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.raw,$(SRCS_SOC))
@@ -9,6 +9,7 @@ require "generators.core".export()
local types = require "types"
types.export()
local Zynq = require "generators.zynq"
local J = require "common"

local ConvWidth = 4
local ConvRadius = ConvWidth/2
@@ -35,13 +36,16 @@ function(inp)
return RemoveMSBs{24}(Rshift{8}(res))
end}

local V = string.find(arg[0],"%d+")
if V==nil then V=1 else V=0 end

harness({
regs.start,
AXIReadBurst{"1080p.raw",{1920,1080},u8,1,noc.read},
AXIReadBurst{"1080p.raw",{1920,1080},u8,V,noc.read},
Pad{{8,8,2,1}},
-- RS.HS(C.print(ar(u(8),1))),
Stencil{{-3,0,-3,0}},
conv,
Crop{{9,7,3,0}},
AXIWriteBurst{"out/soc_convgen",noc.write},
AXIWriteBurst{"out/soc_convgen"..J.sel(V==0,"_0",""),noc.write},
regs.done},nil,{regs})
@@ -2,7 +2,7 @@ local R = require "rigel"
R.export()
local SOC = require "generators.soc"
local harness = require "generators.harnessSOC"
local RS = require "rigelSimple"
local RM = require "generators.modules"
local C = require "generators.examplescommon"
require "generators.core".export()
local T = require "types"
@@ -17,11 +17,11 @@ local inSize = { 1920, 1080 }
local padSize = { 1920+16, 1080+3 }

local regs = SOC.axiRegs({
coeffs={ar(u(32),ConvWidth,ConvWidth),
{"coeffs",RM.reg(ar(u(32),ConvWidth,ConvWidth),
{4, 14, 14, 4,
14, 32, 32, 14,
14, 32, 32, 14,
4, 14, 14, 4}}},SDF{1,padSize[1]*padSize[2]}):instantiate("regs")
4, 14, 14, 4})}},SDF{1,padSize[1]*padSize[2]}):instantiate("regs")

local noc = Zynq.SimpleNOC(nil,nil,{{regs.read,regs.write}}):instantiate("ZynqNOC")
noc.extern=true
@@ -10,10 +10,11 @@ local Zynq = require "generators.zynq"
local C = require "generators.examplescommon"
local Uniform = require "uniform"
local AXI = require "generators.axi"
local RM = require "generators.modules"

-- this is an example of a simple runtime configurable DMA that loads 64bits/cycle at a configurable address & length

local Regs = SOC.axiRegs({readAddress={u(32),0x30008000},writeAddress={u(32),0x30008000+(128*64)},len={u32,(128*64)/8}},SDF{1,(128/8)*64})
local Regs = SOC.axiRegs({{"readAddress",RM.reg(u(32),0x30008000)},{"writeAddress",RM.reg(u(32),0x30008000+(128*64))},{"len",RM.reg(u32,(128*64)/8)}},SDF{1,(128/8)*64})
local regs = Regs:instantiate("regs")

local Len = Uniform(regs.len)
@@ -8,8 +8,9 @@ local SDF = require "sdf"
local types = require "types"
require "types".export()
local Zynq = require "generators.zynq"
local RM = require "generators.modules"

local regs = SOC.axiRegs({offset={u(32),200}},SDF{1,1024}):instantiate("regs")
local regs = SOC.axiRegs({{"offset",RM.reg(u(32),200)}},SDF{1,1024}):instantiate("regs")

local noc = Zynq.SimpleNOC(nil,nil,{{regs.read,regs.write}}):instantiate("ZynqNOC")
noc.extern=true
@@ -3,6 +3,7 @@ local SOC = require "generators.soc"
local C = require "generators.examplescommon"
local harness = require "generators.harnessSOC"
local G = require "generators.core"
local RM = require "generators.modules"
local RS = require "rigelSimple"
local types = require "types"
local SDF = require "sdf"
@@ -11,7 +12,7 @@ types.export()

local Zynq = require "generators.zynq"

local regs = SOC.axiRegs({offset={u(8),200},lastPx={u(8),0,"input"}},SDF{1,8192}):instantiate("regs")
local regs = SOC.axiRegs({{"offset",RM.reg(u(8),200)},{"lastPx",RM.reg(u(8),0,true)}},SDF{1,8192}):instantiate("regs")

local noc = Zynq.SimpleNOC(nil,nil,{{regs.read,regs.write}}):instantiate("ZynqNOC")
noc.extern=true
@@ -7,10 +7,11 @@ local RS = require "rigelSimple"
local types = require "types"
local SDF = require "sdf"
local Zynq = require "generators.zynq"
local RM = require "generators.modules"
local Uniform = require "uniform"
types.export()

local regs = SOC.axiRegs({readAddress={u(32),0x30008000},writeAddress={u(32),0x30008000+(128*64)}},SDF{1,128*64}):instantiate("regs")
local regs = SOC.axiRegs({{"readAddress",RM.reg(u(32),0x30008000)},{"writeAddress",RM.reg(u(32),0x30008000+(128*64))}},SDF{1,128*64}):instantiate("regs")

local readAddress = Uniform(regs.readAddress)
readAddress:addProperty(readAddress:ge(0x30008000))
@@ -8,8 +8,9 @@ local types = require "types"
local SDF = require "sdf"
types.export()
local Zynq = require "generators.zynq"
local RM = require "generators.modules"

local regs = SOC.axiRegs({startCnt={u32,0,"input"},endCnt={u32,0,"input"}},SDF{1,8192}):instantiate("regs")
local regs = SOC.axiRegs({{"startCnt",RM.reg(u32,0,true)},{"endCnt",RM.reg(u32,0,true)}},SDF{1,8192}):instantiate("regs")

local noc = Zynq.SimpleNOC(nil,nil,{{regs.read,regs.write}}):instantiate("ZynqNOC")
noc.extern=true
@@ -28,7 +28,7 @@ function(args)
-- going fully sequential is too slow!
local seq = args.rate[1][2]:toNumber()/args.rate[1][1]:toNumber()
local V = (args.size[1]*args.size[2])/seq

V = math.ceil(V)
while (args.size[1]*args.size[2])%V~=0 do
V = V + 1
@@ -145,7 +145,7 @@ end)

generators.AddMSBs = R.FunctionGenerator("core.AddMSBs",{},{"number"}, function(args) return C.addMSBs(args.T,args.number) end,T.rv(T.Par(P.NumberType("T"))),T.rv(T.Par(P.NumberType("T"))))
generators.RemoveMSBs = R.FunctionGenerator("core.RemoveMSBs",{"number"},{}, function(args) return C.removeMSBs(args.T,args.number) end, T.rv(T.Par(P.NumberType("T"))), T.rv(T.Par(P.NumberType("T"))) )
generators.RemoveLSBs = R.FunctionGenerator("core.RemoveLSBs",{"type","rate"},{"number"}, function(args) return C.removeLSBs(args.type,args.number) end)
generators.RemoveLSBs = R.FunctionGenerator("core.RemoveLSBs",{"type","rate"},{"number"}, function(args) return C.removeLSBs(args.T,args.number) end, T.rv(T.Par(P.NumberType("T"))), T.rv(T.Par(P.NumberType("T"))) )

generators.Index = R.FunctionGenerator("core.Index",{},{"number","size"},
function(a)
@@ -436,29 +436,6 @@ P.SumType("opt",
T.rv(T.ParSeq(T.Array2d(P.DataType("out"),P.SizeValue("V")),P.SizeValue("size")))})
)

-- bool is "HandshakeTrigger" option
--[=[generators.HS = R.FunctionGenerator("core.HS",{"rigelFunction","type","rate"},{"bool"},
function(args)
local mod
if R.isFunctionGenerator(args.rigelFunction) and args.type:is("HandshakeFramed") then
-- fill in args from HSF
--mod = args.rigelFunction{args.type.params.A,types.HSFV(args.type),types.HSFSize(args.type)}
mod = args.rigelFunction{ types.StaticFramed( args.type.params.A, args.type.params.mixed, args.type.params.dims ), args.rate }
elseif R.isFunctionGenerator(args.rigelFunction) then
local r
if args.rigelFunction:requiresArg("rate") then r = args.rate end
mod = args.rigelFunction{R.extractData(args.type), r}
else
mod = args.rigelFunction
end
J.err( R.isFunctionGenerator(mod)==false, "generators.HS: input rigel function is a generator, not a module (arguments must be missing)" )
J.err( R.isPlainFunction(mod), "generators.HS: input Rigel function didn't yield a plain Rigel function? (is "..tostring(mod)..")" )
return RS.HS(mod,args.bool)
end)]=]

generators.Linebuffer = R.FunctionGenerator("core.Linebuffer",{"type","size","number","bounds","rate"},{},
function(args)
local itype
@@ -480,37 +457,7 @@ function(args)
return mod
end)

--[=[
generators.Stencil = R.FunctionGenerator("core.Stencil",{"type","bounds","rate"},{},
function(args)
if args.type:is("StaticFramed") then
local pixelType = types.HSFPixelType(args.type)
local size = types.HSFSize(args.type)
local V = types.HSFV(args.type)
for _,v in ipairs(args.bounds) do J.err(v>=0,"Stencil bounds must be >=0") end
local a = C.stencilLinebuffer( pixelType, size[1], size[2], V, -args.bounds[1], args.bounds[2], -args.bounds[3], args.bounds[4], true )
local b = C.unpackStencil( pixelType, args.bounds[1]+1,args.bounds[3]+1, V, nil, true, size[1], size[2] )
local mod = C.compose("generators_Linebuffer_"..a.name.."_"..b.name,b,a)
if args.number==0 then
mod = C.linearPipeline({C.arrayop(itype,1,1),mod,C.index(mod.outputType,0)},"generators_Linebuffer_0wrap_"..mod.name)
end
return mod
elseif types.isBasic(args.type) then
-- fully parallel
assert(false)
else
err(false,"generators.Stencil: unsupported input type: "..tostring(args.type))
end
end)]=]

generators.Stencil = R.FunctionGenerator("core.Stencil",{"bounds"},{},
--function(args)
-- return R.FunctionGenerator("core.Stencil",{},{},
function(a)
if a.opt==0 then
assert(a.V[2]==1)
@@ -523,19 +470,27 @@ function(a)
end,
P.SumType("opt",{types.rv(types.ParSeq(types.array2d(P.DataType("T"),P.SizeValue("V")),P.SizeValue("size"))),
types.rv(types.Seq(types.Par(P.DataType("T")),P.SizeValue("size")))}),
P.SumType("opt",{--types.rv(types.ParSeq(types.array2d(types.array2d(P.DataType("T"),args.bounds[2]-args.bounds[1]+1,args.bounds[4]-args.bounds[3]+1),P.SizeValue("V")),P.SizeValue("size"))),
P.SumType("opt",{
types.rv(types.ParSeq(types.array2d(types.array2d(P.DataType("T"),P.SizeValue("stSize")),P.SizeValue("V")),P.SizeValue("size"))),
types.rv(types.Seq(types.Par(types.array2d(P.DataType("T"),P.SizeValue("stSize"))),P.SizeValue("size")))})
)

generators.Pad = R.FunctionGenerator("core.Pad",{"bounds"},{},
function(a)
J.err(a.V[2]==1,"Pad NYI - Vh >1")
--local A = args.type:arrayOver()
return RM.padSeq(a.T,a.size[1],a.size[2],a.V[1],a.bounds[1],a.bounds[2],a.bounds[3],a.bounds[4],0,true)
if a.opt==0 then
assert(a.V[2]==1)
return RM.padSeq(a.T,a.size[1],a.size[2],a.V[1],a.bounds[1],a.bounds[2],a.bounds[3],a.bounds[4],0,true)
else
return RM.padSeq(a.T,a.size[1],a.size[2],0,a.bounds[1],a.bounds[2],a.bounds[3],a.bounds[4],0,true)
end
end,
types.rV( T.ParSeq(T.array2d(P.DataType("T"),P.SizeValue("V")),P.SizeValue("size")) ),
types.rRV( T.ParSeq(T.array2d(P.DataType("T"),P.SizeValue("V")),P.SizeValue("sizeOut")) ))
P.SumType("opt",
{types.rV( T.ParSeq(T.array2d(P.DataType("T"),P.SizeValue("V")),P.SizeValue("size")) ),
T.rV(T.Seq(T.Par(P.DataType("T")),P.SizeValue("size")))}),
P.SumType("opt",{
types.rRV( T.ParSeq(T.array2d(P.DataType("T"),P.SizeValue("V")),P.SizeValue("sizeOut"))),
T.rRV(T.Seq(T.Par(P.DataType("T")),P.SizeValue("sizeOut")))})
)


generators.CropSeq = R.FunctionGenerator("core.CropSeq",{"type","size","number","bounds","rate"},{},
@@ -857,10 +812,10 @@ end,
P.SumType("opt",{types.rV(types.Seq(types.Par(P.DataType("T")),P.SizeValue("totalSize")))}),
P.SumType("opt",{types.rRV(types.Par(types.array2d(P.DataType("T"),P.SizeValue("totalSize"))))}))

generators.Fwrite = R.FunctionGenerator("core.Fwrite",{"string"},{},
generators.Fwrite = R.FunctionGenerator("core.Fwrite",{"string"},{"filenameVerilog"},
function(args)
--return RS.modules.fwriteSeq({type=args.type,filename=args.string})
return RM.fwriteSeq(args.string,args.T,args.string..".verilatorSOC.raw",true)
return RM.fwriteSeq(args.string,args.T,args.filenameVerilog,true)
end,
T.rv(T.Par(P.DataType("T"))),
T.rv(T.Par(P.DataType("T"))))
@@ -1073,11 +1028,6 @@ end,
T.array2d(T.RV(P.ScheduleType("sched")),P.SizeValue("size")),
T.RV(P.ScheduleType("sched")))

--generators.StripFramed = R.FunctionGenerator("core.StripFramed",{"type","rate"},{},
--function(args)
-- return C.stripFramed(args.type)
--end)

function generators.export(t)
if t==nil then t=_G end
for k,v in pairs(generators) do rawset(t,k,v) end

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