diff --git a/examples/harness.lua b/examples/harness.lua
index e42cf45..0f2374b 100644
--- a/examples/harness.lua
+++ b/examples/harness.lua
@@ -348,12 +348,7 @@ function harnessTop(t)
     H.sim( t.outFile, fn, t.inFile, t.tapType, t.tapValue, iover, inputP, t.inSize[1], t.inSize[2], oover, outputP, t.outSize[1], t.outSize[2], t.underflowTest, t.earlyOverride )
   elseif backend=="terra" then
     H.terraOnly( t.outFile, fn, t.inFile, t.tapType, t.tapValue, iover, inputP, t.inSize[1], t.inSize[2], oover, outputP, t.outSize[1], t.outSize[2], t.underflowTest, t.earlyOverride,  t.doHalfTest, t.simCycles, t.harness, t.ramFile )
-  else
-    print("unknown build target "..arg[1])
-    assert(false)
-  end
-
-  if backend=="verilog" or backend=="terra" or backend=="axi" or backend=="verilator" then
+  elseif backend=="metadata" then
     local tapValueString = "x"
     local tapBits = 0
     if t.tapType~=nil then
@@ -368,7 +363,10 @@ function harnessTop(t)
     local MD = {inputBitsPerPixel=R.extractData(iover):verilogBits()/(inputP), inputWidth=t.inSize[1], inputHeight=t.inSize[2], outputBitsPerPixel=oover:verilogBits()/(outputP), outputWidth=t.outSize[1], outputHeight=t.outSize[2], inputImage=t.inFile, topModule= fn.name, inputP=inputP, outputP=outputP, simCycles=t.simCycles, tapBits=tapBits, tapValue=tapValueString, harness=harnessOption, ramFile=t.ramFile}
     if t.ramType~=nil then MD.ramBits = t.ramType:verilogBits() end
     
-    writeMetadata("out/"..t.outFile.."."..backend..".metadata.lua", MD)
+    writeMetadata("out/"..t.outFile..".metadata.lua", MD)
+  else
+    print("unknown build target "..arg[1])
+    assert(false)
   end
 
 end
diff --git a/examples/makefile b/examples/makefile
index 21b8fac..694944d 100644
--- a/examples/makefile
+++ b/examples/makefile
@@ -1,6 +1,7 @@
 SRCS = $(wildcard *.lua)
 SRCS := $(filter-out harness.lua examplescommon.lua pyramid_core.lua harris_core.lua sift_core.lua sift_core_hw.lua campipe_core.lua descriptor_core.lua  stereo_core.lua stereo_tr_core.lua  lk_core.lua lk_tr_core.lua,$(SRCS))
 
+METADATA = $(patsubst %.lua,out/%.metadata.lua,$(SRCS))
 
 RIGEL_VERILATOR_INCLUDE ?= $(shell pkg-config --variable=includedir verilator)
 RIGEL_VERILATOR_CFLAGS ?= $(shell pkg-config --cflags verilator)
@@ -175,6 +176,8 @@ all: $(RES)
 
 dups: $(DUPS)
 
+metadata: $(METADATA)
+
 verilog: $(VERILOG)
 	touch out/verilog_done.txt
 
@@ -208,13 +211,19 @@ asic: $(ASIC)
 clean:
 	rm -Rf out/*
 
-out/%.v out/%.verilator.metadata.lua: %.lua
+out/%.metadata.lua: %.lua
+	$(LUA) $< metadata
+	# keep copy for future reference
+	mkdir -p out/build_$*
+	- cp out/$*.metadata.lua out/build_$*
+
+out/%.v: %.lua
 	$(LUA) $< verilator
 	# keep copy for future reference
 	mkdir -p out/build_$*
 	- cp out/$*.v out/build_$*
 
-out/%.terra.raw out/%_half.terra.raw out/%.terra.metadata.lua: %.lua
+out/%.terra.raw out/%_half.terra.raw: %.lua
 	$(TERRA) $< terra
 	# keep copy for future reference
 	mkdir -p out/build_$*
@@ -226,7 +235,7 @@ out/%.isim.v out/%_half.isim.v: %.lua
 	mkdir -p out/build_$*
 	- cp out/$*.isim.v out/build_$*
 
-out/%.axi.v out/%.axi.metadata.lua: %.lua
+out/%.axi.v: %.lua
 	$(LUA) $< axi
 	# keep copy for future reference
 	mkdir -p out/build_$*
@@ -236,29 +245,29 @@ out/%.axi.v out/%.axi.metadata.lua: %.lua
 
 #/opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims
 #	verilator -cc -Mdir out/$*_verilator  /opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims/RAMB16_S36_S36.v out/$*.verilator.v
-out/%.verilator: out/%.v out/%.verilator.metadata.lua ../platform/verilator/harness.cpp
-	../platform/verilator/compile out/$*.v out/$*.verilator.metadata.lua out/$*_verilator $@
+out/%.verilator: out/%.v out/%.metadata.lua ../platform/verilator/harness.cpp
+	../platform/verilator/compile out/$*.v out/$*.metadata.lua out/$*_verilator $@
 
 out/%.verilator.raw: out/%.verilator
-	$(eval $@_INPUT := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua inputImage))
-	$(eval $@_OUTW := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua outputWidth))
-	$(eval $@_OUTH := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua outputHeight))
-	$(eval $@_OUTBPP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua outputBitsPerPixel))
-	$(eval $@_OUTP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua outputP))
-	$(eval $@_INW := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua inputWidth))
-	$(eval $@_INH := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua inputHeight))
-	$(eval $@_INBPP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua inputBitsPerPixel))
-	$(eval $@_INP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua inputP))
-	$(eval $@_TAPBITS := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua tapBits))
-	$(eval $@_TAPVALUE := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua tapValue))
+	$(eval $@_INPUT := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua inputImage))
+	$(eval $@_OUTW := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua outputWidth))
+	$(eval $@_OUTH := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua outputHeight))
+	$(eval $@_OUTBPP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua outputBitsPerPixel))
+	$(eval $@_OUTP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua outputP))
+	$(eval $@_INW := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua inputWidth))
+	$(eval $@_INH := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua inputHeight))
+	$(eval $@_INBPP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua inputBitsPerPixel))
+	$(eval $@_INP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua inputP))
+	$(eval $@_TAPBITS := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua tapBits))
+	$(eval $@_TAPVALUE := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua tapValue))
 	./out/$*.verilator $($@_INPUT) $@ $($@_INW) $($@_INH)  $($@_INBPP) $($@_INP) $($@_OUTW) $($@_OUTH) $($@_OUTBPP) $($@_OUTP) $($@_TAPBITS) $($@_TAPVALUE)
 
 out/%.hz.txt: out/%.axi.bit
 	$(eval $@_HZl := $(shell grep Maximum out/build_$*/OUT_trce.txt  | grep -P -o "[0-9.]+" | tail -1 | tr -d '\n' | awk '{print $$1" * 1000000"}' | bc -l | xargs printf "%d"))
 	echo $($@_HZl) > out/$*.hz.txt
 
-out/%_half.terra.bmp: out/%_half.terra.raw out/%.terra.metadata.lua
-	$(LUA) ../misc/raw2bmp.lua out/$*_half.terra.raw out/$*_half.terra.bmp out/$*.terra.metadata.lua 0
+out/%_half.terra.bmp: out/%_half.terra.raw out/%.metadata.lua
+	$(LUA) ../misc/raw2bmp.lua out/$*_half.terra.raw out/$*_half.terra.bmp out/$*.metadata.lua 0
 	# keep copy for future reference
 	mkdir -p out/build_$*
 	cp out/$*_half.terra.bmp out/build_$*
@@ -299,11 +308,11 @@ out/%.$(1).correct.txt : out/%.$(1).bmp
 	diff out/$$*.$(1).bmp gold/$$*.bmp > out/$$*.$(1).diff
 	test ! -s out/$$*.$(1).diff && touch $$@
 
-out/%.$(1).raw: out/%.$(1).bit
-	../platform/$(1)/run $(shell pwd)/out/$$*.$(1).bit $(shell pwd)/out/$$*.metadata.lua $(shell pwd)/out/$$*.$(1).raw
+out/%.$(1).raw: out/%.$(1).bit out/%.metadata.lua
+	../platform/$(1)/run $(shell pwd)/out/$$*.$(1).bit $(shell pwd)/out/$$*.metadata.lua $(shell pwd)/out/$$*.$(1).raw $(shell pwd)/out/$$*.$(!)
 
-out/%.$(1).bmp: out/%.$(1).raw out/%.$(1).metadata.lua
-	$(LUA) ../misc/raw2bmp.lua out/$$*.$(1).raw out/$$*.$(1).bmp out/$$*.$(1).metadata.lua 0
+out/%.$(1).bmp: out/%.$(1).raw out/%.metadata.lua
+	$(LUA) ../misc/raw2bmp.lua out/$$*.$(1).raw out/$$*.$(1).bmp out/$$*.metadata.lua 0
 	# keep copy for future reference
 	mkdir -p out/$$*_$(1)
 	cp out/$$*.$(1).bmp out/$$*_$(1)
diff --git a/platform/zynq10ise/run b/platform/zynq10ise/run
new file mode 100755
index 0000000..3e9cc1a
--- /dev/null
+++ b/platform/zynq10ise/run
@@ -0,0 +1,41 @@
+#!/bin/bash -x
+# -x shows all commands
+
+ZYNQ_WRITE_PATH=/tmp
+ZYNQ_ADDR=192.168.1.10
+
+BITFILE=$1
+BITFILE_BASE=$(basename $1)
+METAFILE=$2
+OUTFILE=$3
+OUTPATH=$4
+
+
+LUA=../rigelLuajit
+
+#out/%.axi.raw: out/%.axi.bit out/%.hz.txt out/%.axi.metadata.lua
+IMG=$($LUA ../misc/extractMetadata.lua $METAFILE inputImage)
+INW=$($LUA ../misc/extractMetadata.lua $METAFILE inputWidth)
+INH=$($LUA ../misc/extractMetadata.lua $METAFILE inputHeight)
+BPP_IN=$($LUA ../misc/extractMetadata.lua $METAFILE inputBitsPerPixel)
+BPP_OUT=$($LUA ../misc/extractMetadata.lua $METAFILE outputBitsPerPixel)
+OUTW=$($LUA ../misc/extractMetadata.lua $METAFILE outputWidth)
+OUTH=$($LUA ../misc/extractMetadata.lua $METAFILE outputHeight)
+###### SET THE CLOCK	
+#HZ=$(cat $OUTPATH.hz.txt)
+#lockfile /tmp/zynq10lock
+# (* second time around we can't write to fclk_export, so surpress error)
+#sshpass -p 'root' ssh root@$ZYNQ_ADDR "if [[ ! -a /sys/devices/amba.0/f8007000.ps7-dev-cfg/fclk/fclk0 ]]; then echo 'fclk0' > /sys/devices/amba.0/f8007000.ps7-dev-cfg/fclk_export; fi"
+#	sshpass -p 'root' ssh root@$ZYNQ_ADDR "echo '$($@_HZ)' > /sys/class/fclk/fclk0/set_rate"
+#	sshpass -p 'root' ssh root@$ZYNQ_ADDR "cat /sys/class/fclk/fclk0/set_rate" > out/$*.realhz.txt
+###### CLOCK STUFF END
+
+sshpass -p 'root' scp ../platform/axi/processimage $BITFILE $IMG root@$ZYNQ_ADDR:$ZYNQ_WRITE_PATH
+sshpass -p 'root' ssh root@$ZYNQ_ADDR "cat $ZYNQ_WRITE_PATH/$BITFILE_BASE > /dev/xdevcfg"
+sshpass -p 'root' ssh root@$ZYNQ_ADDR "$ZYNQ_WRITE_PATH/processimage 805339136 $ZYNQ_WRITE_PATH/$IMG $ZYNQ_WRITE_PATH/out.raw $INW $INH $BPP_IN $OUTW $OUTH $BPP_OUT "
+sshpass -p 'root' scp root@$ZYNQ_ADDR:$ZYNQ_WRITE_PATH/out.raw $OUTFILE
+sshpass -p 'root' ssh root@$ZYNQ_ADDR "rm $ZYNQ_WRITE_PATH/processimage $ZYNQ_WRITE_PATH/$IMG $ZYNQ_WRITE_PATH/out.raw $ZYNQ_WRITE_PATH/$BITFILE_BASE"
+#rm -f /tmp/zynq10lock
+#	$(TERRA) ../misc/extractCycles.t out/$*.axi.raw > out/$*.axi.cycles.txt
+#	# keep copy for future reference
+#	cp out/$*.axi.cycles.txt out/build_$*
diff --git a/platform/zynq10ise/system.ucf b/platform/zynq10ise/system.ucf
index bd7a437..2facced 100644
--- a/platform/zynq10ise/system.ucf
+++ b/platform/zynq10ise/system.ucf
@@ -26,6 +26,13 @@ NET "LED<1>"        LOC=M15 | IOSTANDARD=LVCMOS33; #IO_L23N_T3_35
 NET "LED<2>"        LOC=G14 | IOSTANDARD=LVCMOS33; #IO_0_35
 NET "LED<3>"        LOC=D18 | IOSTANDARD=LVCMOS33; #IO_L3N_T0_DQS_AD1N_35
 
+# HACK: zybo doesn't have 8 LEDs, instead, emulate that by putting some of the LEDs on PMOD JA
+NET "LED<4>"       LOC=N16 | IOSTANDARD=LVCMOS33; #IO_L21N_T3_DQS_AD14N_35
+NET "LED<5>"       LOC=N15 | IOSTANDARD=LVCMOS33; #IO_L21P_T3_DQS_AD14P_35
+NET "LED<6>"       LOC=L15 | IOSTANDARD=LVCMOS33; #IO_L22N_T3_AD7N_35
+NET "LED<7>"       LOC=L14 | IOSTANDARD=LVCMOS33; #IO_L22P_T3_AD7P_35
+
+
 ## I2S Audio Codec
 #NET "ac_bclk"       LOC=K18 | IOSTANDARD=LVCMOS33; #IO_L12N_T1_MRCC_35
 #NET "ac_mclk"       LOC=T19 | IOSTANDARD=LVCMOS33; #IO_25_34
diff --git a/platform/zynq10vivado/compile b/platform/zynq10vivado/compile
new file mode 100755
index 0000000..628ce98
--- /dev/null
+++ b/platform/zynq10vivado/compile
@@ -0,0 +1,23 @@
+#!/bin/bash
+
+VERILOG_FILE=$1
+METADATA_FILE=$2
+BUILDDIR=$3
+OUTFILE=$4
+
+mkdir -p $BUILDDIR
+cd $BUILDDIR
+echo "read_verilog $VERILOG_FILE" > system.tcl
+echo "read_xdc ../../../platform/zynq10vivado/zybo.xdc" >> system.tcl
+echo "read_xdc ../../../platform/vivado/ps7_constraints.xdc" >> system.tcl
+echo "synth_design -top stage -part xc7z010clg400-1" >> system.tcl
+echo "opt_design" >> system.tcl
+echo "place_design" >> system.tcl
+echo "phys_opt_design" >> system.tcl
+echo "route_design" >> system.tcl
+echo "write_bitstream system.bit" >> system.tcl
+echo "report_timing" >> system.tcl
+echo "report_timing_summary" >> system.tcl
+vivado -mode batch -source 'system.tcl' -nojournal -log 'vivado.log' > /dev/null
+cp system.bit $OUTFILE
+                                          
diff --git a/platform/zynq10vivado/run b/platform/zynq10vivado/run
new file mode 120000
index 0000000..f06cdb7
--- /dev/null
+++ b/platform/zynq10vivado/run
@@ -0,0 +1 @@
+../zynq10ise/run
\ No newline at end of file
diff --git a/platform/zynq10vivado/zybo.xdc b/platform/zynq10vivado/zybo.xdc
new file mode 100644
index 0000000..764085f
--- /dev/null
+++ b/platform/zynq10vivado/zybo.xdc
@@ -0,0 +1,153 @@
+## This file is a general .xdc for the ZYBO Rev B board
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used signals according to the project
+
+
+##Clock signal
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L11P_T1_SRCC_35 Sch=sysclk
+#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];
+
+create_clock -add -name FCLK -period 5.00 -waveform {0 4} [get_ports { FCLK }];
+
+##Switches
+#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=SW0
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }];  #IO_L24P_T3_34 Sch=SW1
+#set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=SW2
+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=SW3
+
+
+##Buttons
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L20N_T3_34 Sch=BTN0
+#set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=BTN1
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L18P_T2_34 Sch=BTN2
+#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=BTN3
+
+
+##LEDs
+set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L23P_T3_35 Sch=LED0
+set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L23N_T3_35 Sch=LED1
+set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_0_35=Sch=LED2
+set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3
+
+# HACK: zybo doesn't have 8 LEDs, instead, emulate that by putting some of the LEDs on PMOD JA
+
+set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
+set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
+set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
+set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
+
+##I2S Audio Codec
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports ac_bclk]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK
+#set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports ac_mclk]; #IO_25_34 Sch=AC_MCLK
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports ac_muten]; #IO_L23N_T3_34 Sch=AC_MUTEN
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports ac_pbdat]; #IO_L8P_T1_AD10P_35 Sch=AC_PBDAT
+#set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports ac_pblrc]; #IO_L11N_T1_SRCC_35 Sch=AC_PBLRC
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports ac_recdat]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports ac_reclrc]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC
+
+
+##Audio Codec/external EEPROM IIC bus
+#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports ac_scl]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports ac_sda]; #IO_L23P_T3_34 Sch=AC_SDA
+
+
+##Additional Ethernet signals
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports eth_int_b]; #IO_L6P_T0_35 Sch=ETH_INT_B
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports eth_rst_b]; #IO_L3P_T0_DQS_AD1P_35 Sch=ETH_RST_B
+
+
+##HDMI Signals
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD TMDS_33 } [get_ports hdmi_clk_n]; #IO_L13N_T2_MRCC_35 Sch=HDMI_CLK_N
+#set_property -dict { PACKAGE_PIN H16   IOSTANDARD TMDS_33 } [get_ports hdmi_clk_p]; #IO_L13P_T2_MRCC_35 Sch=HDMI_CLK_P
+#set_property -dict { PACKAGE_PIN D20   IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[0] }]; #IO_L4N_T0_35 Sch=HDMI_D0_N
+#set_property -dict { PACKAGE_PIN D19   IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[0] }]; #IO_L4P_T0_35 Sch=HDMI_D0_P
+#set_property -dict { PACKAGE_PIN B20   IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=HDMI_D1_N
+#set_property -dict { PACKAGE_PIN C20   IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=HDMI_D1_P
+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=HDMI_D2_N
+#set_property -dict { PACKAGE_PIN B19   IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=HDMI_D2_P
+#set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports hdmi_cec]; #IO_L5N_T0_AD9N_35 Sch=HDMI_CEC
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports hdmi_hpd]; #IO_L5P_T0_AD9P_35 Sch=HDMI_HPD
+#set_property -dict { PACKAGE_PIN F17   IOSTANDARD LVCMOS33 } [get_ports hdmi_out_en]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports hdmi_scl]; #IO_L16P_T2_35 Sch=HDMI_SCL
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports hdmi_sda]; #IO_L16N_T2_35 Sch=HDMI_SDA
+
+
+##Pmod Header JA (XADC)
+#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { ja_p[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
+#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { ja_n[0] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
+#set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
+#set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
+
+
+##Pmod Header JB
+#set_property -dict { PACKAGE_PIN T20   IOSTANDARD LVCMOS33 } [get_ports { jb_p[0] }]; #IO_L15P_T2_DQS_34 Sch=JB1_p
+#set_property -dict { PACKAGE_PIN U20   IOSTANDARD LVCMOS33 } [get_ports { jb_n[0] }]; #IO_L15N_T2_DQS_34 Sch=JB1_N
+#set_property -dict { PACKAGE_PIN V20   IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L16P_T2_34 Sch=JB2_P
+#set_property -dict { PACKAGE_PIN W20   IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L16N_T2_34 Sch=JB2_N
+#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L17P_T2_34 Sch=JB3_P
+#set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L17N_T2_34 Sch=JB3_N
+#set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L22P_T3_34 Sch=JB4_P
+#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L22N_T3_34 Sch=JB4_N
+
+
+##Pmod Header JC
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { jc_p[0] }]; #IO_L10P_T1_34 Sch=JC1_P
+#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports { jc_n[0] }]; #IO_L10N_T1_34 Sch=JC1_N
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { jc_p[1] }]; #IO_L1P_T0_34 Sch=JC2_P
+#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { jc_n[1] }]; #IO_L1N_T0_34 Sch=JC2_N
+#set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports { jc_p[2] }]; #IO_L8P_T1_34 Sch=JC3_P
+#set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33 } [get_ports { jc_n[2] }]; #IO_L8N_T1_34 Sch=JC3_N
+#set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33 } [get_ports { jc_p[3] }]; #IO_L2P_T0_34 Sch=JC4_P
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { jc_n[3] }]; #IO_L2N_T0_34 Sch=JC4_N
+
+
+##Pmod Header JD
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { jd_p[0] }]; #IO_L5P_T0_34 Sch=JD1_P
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { jd_n[0] }]; #IO_L5N_T0_34 Sch=JD1_N
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { jd_p[1] }]; #IO_L6P_T0_34 Sch=JD2_P
+#set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33 } [get_ports { jd_n[1] }]; #IO_L6N_T0_VREF_34 Sch=JD2_N
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { jd_p[2] }]; #IO_L11P_T1_SRCC_34 Sch=JD3_P
+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { jd_n[2] }]; #IO_L11N_T1_SRCC_34 Sch=JD3_N
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { jd_p[3] }]; #IO_L21P_T3_DQS_34 Sch=JD4_P
+#set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33 } [get_ports { jd_n[3] }]; #IO_L21N_T3_DQS_34 Sch=JD4_N
+
+
+##Pmod Header JE
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=JE1
+#set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=JE2
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=JE3
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=JE4
+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8
+#set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=JE9
+#set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=JE10
+
+
+##USB-OTG overcurrent detect pin
+#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports otg_oc]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=OTG_OC
+
+
+##VGA Connector
+#set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L7P_T1_AD2P_35 Sch=VGA_R1
+#set_property -dict { PACKAGE_PIN L20   IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=VGA_R2
+#set_property -dict { PACKAGE_PIN J20   IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L17P_T2_AD5P_35 Sch=VGA_R3
+#set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L18N_T2_AD13N_35 Sch=VGA_R4
+#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_AD12P_35 Sch=VGA_R5
+#set_property -dict { PACKAGE_PIN H18   IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=VGA_G0
+#set_property -dict { PACKAGE_PIN N20   IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L14P_T2_SRCC_34 Sch=VGA_G1
+#set_property -dict { PACKAGE_PIN L19   IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=VGA_G2
+#set_property -dict { PACKAGE_PIN J19   IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L10N_T1_AD11N_35 Sch=VGA_G3
+#set_property -dict { PACKAGE_PIN H20   IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L17N_T2_AD5N_35 Sch=VGA_G4
+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L15N_T2_DQS_AD12N_35 Sch=VGA=G5
+#set_property -dict { PACKAGE_PIN P20   IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L14N_T2_SRCC_34 Sch=VGA_B1
+#set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L7N_T1_AD2N_35 Sch=VGA_B2
+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L10P_T1_AD11P_35 Sch=VGA_B3
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=VGA_B4
+#set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L18P_T2_AD13P_35 Sch=VGA_B5
+#set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports vga_hs]; #IO_L13N_T2_MRCC_34 Sch=VGA_HS
+#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports vga_vs]; #IO_0_34 Sch=VGA_VS
diff --git a/src/common.lua b/src/common.lua
index ac5c01c..101d0b6 100644
--- a/src/common.lua
+++ b/src/common.lua
@@ -8,14 +8,14 @@ function common.table_print (tt, indent, done)
     local first = true
     for key, value in pairs (tt) do
       table.insert(sb, string.rep (" ", indent)) -- indent it
-      if type (value) == "table" and not done [value] then
+      if type (value) == "table" then
         done [value] = true
 	table.insert(sb, key);
 	table.insert(sb, "=");
 --        table.insert(sb, "{"..tostring(value).."\n");
 --        if first then comma="";first=false end
         table.insert(sb, "{\n");
-        table.insert(sb, table_print (value, indent + 2, done))
+        table.insert(sb, common.table_print (value, indent + 2, done))
         table.insert(sb, string.rep (" ", indent)) -- indent it
         local comma = ","
         table.insert(sb, "}");
@@ -38,7 +38,7 @@ function common.to_string( tbl )
     if  "nil"       == type( tbl ) then
         return tostring(nil)
     elseif  "table" == type( tbl ) then
-        return tostring(tbl).." "..table_print(tbl)
+        return common.table_print(tbl)
     elseif  "string" == type( tbl ) then
         return tbl
     else
@@ -610,7 +610,7 @@ function common.verilogCheckReserved(k)
   end
 end
 
-function common.verilogSanitize(s)
+function common.verilogSanitizeInner(s)
   --local s = s:gsub('%W','_')
   local s = s:gsub("%[","_OB_")
   s = s:gsub("%]","_CB_")
@@ -625,6 +625,18 @@ function common.verilogSanitize(s)
 
   return s
 end
+
+-- hack: running only one round of sanitize may leave unsanitized stuff
+function common.verilogSanitize(s)
+  local a = common.verilogSanitizeInner(s)
+
+  while(true) do
+    local b = common.verilogSanitizeInner(a)
+    if(a==b) then return b end
+    a=b
+  end
+end
+
 common.sanitize = common.verilogSanitize
 
 function common.fileExists(name)
@@ -632,4 +644,20 @@ function common.fileExists(name)
    if f~=nil then io.close(f) return true else return false end
 end
 
+-- uniquify a table
+local __uniqCache = {}
+function common.uniq(t)
+  if type(t)=="number" or type(t)=="string" then
+    return t
+  elseif type(t)=="table" then
+    local out = {}
+    assert(#t==common.keycount(t))
+    for _,v in ipairs(t) do table.insert(out,common.uniq(v)) end
+    if __uniqCache[#t]==nil then __uniqCache[#t]={} end
+    return common.deepsetweak(__uniqCache[#t],out,out)
+  else
+    assert(false)
+  end
+end
+
 return common
diff --git a/src/modules.lua b/src/modules.lua
index 4feee5f..da0c583 100644
--- a/src/modules.lua
+++ b/src/modules.lua
@@ -3299,7 +3299,7 @@ function modules.lift( name, inputType, outputType, delay, makeSystolic, makeTer
   return res
 end
 
-modules.constSeq = memoize(function( value, A, w, h, T, X )
+modules.constSeqInner = memoize(function( value, A, w, h, T, X )
   err( type(value)=="table", "constSeq: value should be a lua array of values to shift through")
   err( J.keycount(value)==#value, "constSeq: value should be a lua array of values to shift through")
   err( #value==w*h, "constSeq: value array has wrong number of values")
@@ -3321,7 +3321,13 @@ modules.constSeq = memoize(function( value, A, w, h, T, X )
   res.stateful = false
   --if T==1 then res.stateful=false end
   res.sdfInput, res.sdfOutput = {}, {{1,1}}  -- well, technically this produces 1 output for every (nil) input
-  res.name = "constSeq_"..verilogSanitize(tostring(value)).."_T"..tostring(1/T).."_w"..tostring(w).."_h"..tostring(h)
+
+  -- TODO: FIX: replace this with an actual hash function... it seems likely this can lead to collisions
+  local vh = J.to_string(value)
+  if #vh>100 then vh = string.sub(vh,0,100) end
+  
+  -- some different types can have the same lua array representation (i.e. different array shapes), so we need to include both
+  res.name = verilogSanitize("constSeq_"..tostring(A).."_"..vh.."_T"..tostring(1/T).."_w"..tostring(w).."_h"..tostring(h))
   res.delay = 0
 
   if terralib~=nil then res.terraModule = MT.constSeq(res, value, A, w, h, T,W ) end
@@ -3357,6 +3363,13 @@ modules.constSeq = memoize(function( value, A, w, h, T, X )
   return rigel.newFunction( res )
 end)
 
+function modules.constSeq(value,A,w,h,T,X)
+  err( type(value)=="table", "constSeq: value should be a lua array of values to shift through")
+  local UV = J.uniq(value)
+  local I = modules.constSeqInner(UV,A,w,h,T,X)
+  return I
+end
+
 modules.freadSeq = memoize(function( filename, ty )
   err( type(filename)=="string", "filename must be a string")
   err( types.isType(ty), "type must be a type")
diff --git a/unittests/fixedtest.lua b/unittests/fixedtest.lua
index 0578c60..6d0efd4 100644
--- a/unittests/fixedtest.lua
+++ b/unittests/fixedtest.lua
@@ -42,7 +42,7 @@ for k,v in pairs(configs) do
   local inputImageSize={64,32}
   local outputImageSize={64,32}
 
-  local targets = {"verilog","terra"}
+  local targets = {"verilog","terra","metadata"}
   
   for _,bk in pairs(targets) do
     R.harness{ outFile="fixed_test"..k, fn=mod, inFile="../examples/frame_64.raw", inSize=inputImageSize, outSize=outputImageSize, backend=bk }
diff --git a/unittests/makefile b/unittests/makefile
index d4fdc90..8a6b03e 100644
--- a/unittests/makefile
+++ b/unittests/makefile
@@ -52,7 +52,8 @@ out/fixedtest.correct.txt: out/verilogcorrect.txt
 ###################
 out/fwriteseq.compiles.txt: fwriteseq.lua
 	../rigelTerra fwriteseq.lua terra
-	../rigelLuajit fwriteseq.lua
+	../rigelLuajit fwriteseq.lua verilog
+	../rigelLuajit fwriteseq.lua metadata
 
 out/fwriteseq.correct.txt: out/verilogcorrect.txt
 	diff out/fwriteseqtest.raw out/fwriteseqtestVerilog.raw > out/fwriteseqtest.diff
@@ -60,7 +61,8 @@ out/fwriteseq.correct.txt: out/verilogcorrect.txt
 ###################
 out/fwriteseq16.compiles.txt: fwriteseq16.lua
 	../rigelTerra fwriteseq16.lua terra
-	../rigelLuajit fwriteseq16.lua
+	../rigelLuajit fwriteseq16.lua verilog
+	../rigelLuajit fwriteseq16.lua metadata
 
 out/fwriteseq16.correct.txt: out/verilogcorrect.txt
 	diff out/fwriteseq16test.raw out/fwriteseq16testVerilog.raw > out/fwriteseq16test.diff
@@ -68,7 +70,8 @@ out/fwriteseq16.correct.txt: out/verilogcorrect.txt
 ###################
 out/fwriteseq12.compiles.txt: fwriteseq12.lua
 	../rigelTerra fwriteseq12.lua terra
-	../rigelLuajit fwriteseq12.lua
+	../rigelLuajit fwriteseq12.lua verilog
+	../rigelLuajit fwriteseq12.lua metadata
 
 out/fwriteseq12.correct.txt: out/verilogcorrect.txt
 	diff out/fwriteseq16test.raw out/dbg_terra_fwriteseq12.raw > out/fwriteseq12test.diff
@@ -77,7 +80,8 @@ out/fwriteseq12.correct.txt: out/verilogcorrect.txt
 ###################
 out/fwriteseq18.compiles.txt: fwriteseq18.lua
 	../rigelTerra fwriteseq18.lua terra
-	../rigelLuajit fwriteseq18.lua
+	../rigelLuajit fwriteseq18.lua verilog
+	../rigelLuajit fwriteseq18.lua metadata
 
 out/fwriteseq18.correct.txt: out/verilogcorrect.txt
 	diff out/dbg_terra_fwriteseq18.raw out/dbg_verilog_fwriteseq18.raw > out/fwriteseq18test.diff
@@ -85,7 +89,8 @@ out/fwriteseq18.correct.txt: out/verilogcorrect.txt
 ###################
 out/fwriteseq24.compiles.txt: fwriteseq24.lua
 	../rigelTerra fwriteseq24.lua terra
-	../rigelLuajit fwriteseq24.lua
+	../rigelLuajit fwriteseq24.lua verilog
+	../rigelLuajit fwriteseq24.lua metadata
 
 out/fwriteseq24.correct.txt: out/verilogcorrect.txt
 	diff out/dbg_terra_fwriteseq24.raw out/dbg_verilog_fwriteseq24.raw > out/fwriteseq24test.diff
@@ -95,7 +100,8 @@ out/fwriteseq24.correct.txt: out/verilogcorrect.txt
 ###################
 out/fwriteseq37.compiles.txt: fwriteseq37.lua
 	../rigelTerra fwriteseq37.lua terra
-	../rigelLuajit fwriteseq37.lua
+	../rigelLuajit fwriteseq37.lua verilog
+	../rigelLuajit fwriteseq37.lua metadata
 
 out/fwriteseq37.correct.txt: out/verilogcorrect.txt
 	diff out/dbg_terra_fwriteseq37.raw out/dbg_verilog_fwriteseq37.raw > out/fwriteseq37test.diff
diff --git a/unittests/makefile.compileverilog b/unittests/makefile.compileverilog
index 35a7b8f..441d10a 100644
--- a/unittests/makefile.compileverilog
+++ b/unittests/makefile.compileverilog
@@ -15,36 +15,36 @@ LUA = ../rigelLuajit
 all: $(TARGETS)
 	touch out/verilogcorrect.txt
 
-out/%.terra.bmp: out/%.terra.raw out/%.terra.metadata.lua
-	$(LUA) ../misc/raw2bmp.lua out/$*.terra.raw out/$*.terra.bmp out/$*.terra.metadata.lua 0
+out/%.terra.bmp: out/%.terra.raw out/%.metadata.lua
+	$(LUA) ../misc/raw2bmp.lua out/$*.terra.raw out/$*.terra.bmp out/$*.metadata.lua 0
 	# keep copy for future reference
 	mkdir -p out/build_$*
 	cp out/$*.terra.bmp out/build_$*
 
-out/%.verilator: out/%.v out/%.verilog.metadata.lua
-	$(eval $@_TOP := $(shell luajit ../misc/extractMetadata.lua out/$*.verilog.metadata.lua topModule))
-	$(eval $@_HARNESS := $(shell luajit ../misc/extractMetadata.lua out/$*.verilog.metadata.lua harness))
-	$(eval $@_INBPP := $(shell luajit ../misc/extractMetadata.lua out/$*.verilog.metadata.lua inputBitsPerPixel))
+out/%.verilator: out/%.v out/%.metadata.lua
+	$(eval $@_TOP := $(shell luajit ../misc/extractMetadata.lua out/$*.metadata.lua topModule))
+	$(eval $@_HARNESS := $(shell luajit ../misc/extractMetadata.lua out/$*.metadata.lua harness))
+	$(eval $@_INBPP := $(shell luajit ../misc/extractMetadata.lua out/$*.metadata.lua inputBitsPerPixel))
 	verilator -cc -Mdir out/$*_verilator out/$*.v ../platform/verilator/RAM128X1D.v ../platform/verilator/RAMB16_S36_S36.v ../platform/verilator/RAMB16_S18_S18.v ../platform/verilator/RAMB16_S9_S9.v ../platform/verilator/RAMB16_RIGEL.v --top-module "$($@_TOP)"
-#	$(LUA) ../platform/verilator/makeHarness.lua out/$*.verilog.metadata.lua $* > out/$*.verilator.cpp
+#	$(LUA) ../platform/verilator/makeHarness.lua out/$*.metadata.lua $* > out/$*.verilator.cpp
 	g++ ${RIGEL_VERILATOR_CFLAGS} -I. -DHARNESS=$($@_HARNESS) -DINBPP=$($@_INBPP) -DVERILATORCLASS="V$($@_TOP)" -DVERILATORFILE="\"out/$*_verilator/V$($@_TOP).h\"" out/$*_verilator/V$($@_TOP).cpp out/$*_verilator/V$($@_TOP)__Syms.cpp ${RIGEL_VERILATOR_INCLUDE}/verilated.cpp ../platform/verilator/harness.cpp -o $@
 
-out/%.verilator.raw: out/%.verilator out/%.verilog.metadata.lua
-	$(eval $@_INPUT := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilog.metadata.lua inputImage))
-	$(eval $@_OUTW := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilog.metadata.lua outputWidth))
-	$(eval $@_OUTH := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilog.metadata.lua outputHeight))
-	$(eval $@_OUTBPP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilog.metadata.lua outputBitsPerPixel))
-	$(eval $@_OUTP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilog.metadata.lua outputP))
-	$(eval $@_INW := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilog.metadata.lua inputWidth))
-	$(eval $@_INH := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilog.metadata.lua inputHeight))
-	$(eval $@_INBPP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilog.metadata.lua inputBitsPerPixel))
-	$(eval $@_INP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilog.metadata.lua inputP))
-	$(eval $@_TAPBITS := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilog.metadata.lua tapBits))
-	$(eval $@_TAPVALUE := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilog.metadata.lua tapValue))
+out/%.verilator.raw: out/%.verilator out/%.metadata.lua
+	$(eval $@_INPUT := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua inputImage))
+	$(eval $@_OUTW := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua outputWidth))
+	$(eval $@_OUTH := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua outputHeight))
+	$(eval $@_OUTBPP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua outputBitsPerPixel))
+	$(eval $@_OUTP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua outputP))
+	$(eval $@_INW := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua inputWidth))
+	$(eval $@_INH := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua inputHeight))
+	$(eval $@_INBPP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua inputBitsPerPixel))
+	$(eval $@_INP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua inputP))
+	$(eval $@_TAPBITS := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua tapBits))
+	$(eval $@_TAPVALUE := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua tapValue))
 	./out/$*.verilator $($@_INPUT) $@ $($@_INW) $($@_INH)  $($@_INBPP) $($@_INP) $($@_OUTW) $($@_OUTH) $($@_OUTBPP) $($@_OUTP) $($@_TAPBITS) $($@_TAPVALUE)
 
-out/%.verilator.bmp: out/%.verilator.raw out/%.verilog.metadata.lua
-	$(LUA) ../misc/raw2bmp.lua out/$*.verilator.raw out/$*.verilator.bmp out/$*.verilog.metadata.lua 0
+out/%.verilator.bmp: out/%.verilator.raw out/%.metadata.lua
+	$(LUA) ../misc/raw2bmp.lua out/$*.verilator.raw out/$*.verilator.bmp out/$*.metadata.lua 0
 	# keep copy for future reference
 	mkdir -p out/build_$*
 	cp out/$*.verilator.bmp out/build_$*
diff --git a/unittests/moduleparams.lua b/unittests/moduleparams.lua
index cc608f4..21f8f1e 100644
--- a/unittests/moduleparams.lua
+++ b/unittests/moduleparams.lua
@@ -119,7 +119,7 @@ for k,v in pairs(configs) do
     -- TODO: hack to get around axi burst nonsense
     local valid = true
     
-    local targets = {"verilog"}
+    local targets = {"verilog","metadata"}
     if valid then 
       table.insert(targets,"terra") 
     else