Zynq10 (#83)

ISE and vivado scripts for zynq7010

examples/harness.lua

@@ -348,12 +348,7 @@ function harnessTop(t)
     H.sim( t.outFile, fn, t.inFile, t.tapType, t.tapValue, iover, inputP, t.inSize[1], t.inSize[2], oover, outputP, t.outSize[1], t.outSize[2], t.underflowTest, t.earlyOverride )
   elseif backend=="terra" then
     H.terraOnly( t.outFile, fn, t.inFile, t.tapType, t.tapValue, iover, inputP, t.inSize[1], t.inSize[2], oover, outputP, t.outSize[1], t.outSize[2], t.underflowTest, t.earlyOverride,  t.doHalfTest, t.simCycles, t.harness, t.ramFile )
-  else
-    print("unknown build target "..arg[1])
-    assert(false)
-  end
-
-  if backend=="verilog" or backend=="terra" or backend=="axi" or backend=="verilator" then
+  elseif backend=="metadata" then
     local tapValueString = "x"
     local tapBits = 0
     if t.tapType~=nil then
@@ -368,7 +363,10 @@ function harnessTop(t)
     local MD = {inputBitsPerPixel=R.extractData(iover):verilogBits()/(inputP), inputWidth=t.inSize[1], inputHeight=t.inSize[2], outputBitsPerPixel=oover:verilogBits()/(outputP), outputWidth=t.outSize[1], outputHeight=t.outSize[2], inputImage=t.inFile, topModule= fn.name, inputP=inputP, outputP=outputP, simCycles=t.simCycles, tapBits=tapBits, tapValue=tapValueString, harness=harnessOption, ramFile=t.ramFile}
     if t.ramType~=nil then MD.ramBits = t.ramType:verilogBits() end
 
-    writeMetadata("out/"..t.outFile.."."..backend..".metadata.lua", MD)
+    writeMetadata("out/"..t.outFile..".metadata.lua", MD)
+  else
+    print("unknown build target "..arg[1])
+    assert(false)
   end
 
 end

examples/makefile

@@ -1,6 +1,7 @@
 SRCS = $(wildcard *.lua)
 SRCS := $(filter-out harness.lua examplescommon.lua pyramid_core.lua harris_core.lua sift_core.lua sift_core_hw.lua campipe_core.lua descriptor_core.lua  stereo_core.lua stereo_tr_core.lua  lk_core.lua lk_tr_core.lua,$(SRCS))
 
+METADATA = $(patsubst %.lua,out/%.metadata.lua,$(SRCS))
 
 RIGEL_VERILATOR_INCLUDE ?= $(shell pkg-config --variable=includedir verilator)
 RIGEL_VERILATOR_CFLAGS ?= $(shell pkg-config --cflags verilator)
@@ -175,6 +176,8 @@ all: $(RES)
 
 dups: $(DUPS)
 
+metadata: $(METADATA)
+
 verilog: $(VERILOG)
 	touch out/verilog_done.txt
 
@@ -208,13 +211,19 @@ asic: $(ASIC)
 clean:
 	rm -Rf out/*
 
-out/%.v out/%.verilator.metadata.lua: %.lua
+out/%.metadata.lua: %.lua
+	$(LUA) $< metadata
+	# keep copy for future reference
+	mkdir -p out/build_$*
+	- cp out/$*.metadata.lua out/build_$*
+
+out/%.v: %.lua
 	$(LUA) $< verilator
 	# keep copy for future reference
 	mkdir -p out/build_$*
 	- cp out/$*.v out/build_$*
 
-out/%.terra.raw out/%_half.terra.raw out/%.terra.metadata.lua: %.lua
+out/%.terra.raw out/%_half.terra.raw: %.lua
 	$(TERRA) $< terra
 	# keep copy for future reference
 	mkdir -p out/build_$*
@@ -226,7 +235,7 @@ out/%.isim.v out/%_half.isim.v: %.lua
 	mkdir -p out/build_$*
 	- cp out/$*.isim.v out/build_$*
 
-out/%.axi.v out/%.axi.metadata.lua: %.lua
+out/%.axi.v: %.lua
 	$(LUA) $< axi
 	# keep copy for future reference
 	mkdir -p out/build_$*
@@ -236,29 +245,29 @@ out/%.axi.v out/%.axi.metadata.lua: %.lua
 
 #/opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims
 #	verilator -cc -Mdir out/$*_verilator  /opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims/RAMB16_S36_S36.v out/$*.verilator.v
-out/%.verilator: out/%.v out/%.verilator.metadata.lua ../platform/verilator/harness.cpp
-	../platform/verilator/compile out/$*.v out/$*.verilator.metadata.lua out/$*_verilator $@
+out/%.verilator: out/%.v out/%.metadata.lua ../platform/verilator/harness.cpp
+	../platform/verilator/compile out/$*.v out/$*.metadata.lua out/$*_verilator $@
 
 out/%.verilator.raw: out/%.verilator
-	$(eval $@_INPUT := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua inputImage))
-	$(eval $@_OUTW := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua outputWidth))
-	$(eval $@_OUTH := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua outputHeight))
-	$(eval $@_OUTBPP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua outputBitsPerPixel))
-	$(eval $@_OUTP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua outputP))
-	$(eval $@_INW := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua inputWidth))
-	$(eval $@_INH := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua inputHeight))
-	$(eval $@_INBPP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua inputBitsPerPixel))
-	$(eval $@_INP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua inputP))
-	$(eval $@_TAPBITS := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua tapBits))
-	$(eval $@_TAPVALUE := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.verilator.metadata.lua tapValue))
+	$(eval $@_INPUT := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua inputImage))
+	$(eval $@_OUTW := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua outputWidth))
+	$(eval $@_OUTH := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua outputHeight))
+	$(eval $@_OUTBPP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua outputBitsPerPixel))
+	$(eval $@_OUTP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua outputP))
+	$(eval $@_INW := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua inputWidth))
+	$(eval $@_INH := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua inputHeight))
+	$(eval $@_INBPP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua inputBitsPerPixel))
+	$(eval $@_INP := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua inputP))
+	$(eval $@_TAPBITS := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua tapBits))
+	$(eval $@_TAPVALUE := $(shell $(LUA) ../misc/extractMetadata.lua out/$*.metadata.lua tapValue))
 	./out/$*.verilator $($@_INPUT) $@ $($@_INW) $($@_INH)  $($@_INBPP) $($@_INP) $($@_OUTW) $($@_OUTH) $($@_OUTBPP) $($@_OUTP) $($@_TAPBITS) $($@_TAPVALUE)
 
 out/%.hz.txt: out/%.axi.bit
 	$(eval $@_HZl := $(shell grep Maximum out/build_$*/OUT_trce.txt  | grep -P -o "[0-9.]+" | tail -1 | tr -d '\n' | awk '{print $$1" * 1000000"}' | bc -l | xargs printf "%d"))
 	echo $($@_HZl) > out/$*.hz.txt
 
-out/%_half.terra.bmp: out/%_half.terra.raw out/%.terra.metadata.lua
-	$(LUA) ../misc/raw2bmp.lua out/$*_half.terra.raw out/$*_half.terra.bmp out/$*.terra.metadata.lua 0
+out/%_half.terra.bmp: out/%_half.terra.raw out/%.metadata.lua
+	$(LUA) ../misc/raw2bmp.lua out/$*_half.terra.raw out/$*_half.terra.bmp out/$*.metadata.lua 0
 	# keep copy for future reference
 	mkdir -p out/build_$*
 	cp out/$*_half.terra.bmp out/build_$*
@@ -299,11 +308,11 @@ out/%.$(1).correct.txt : out/%.$(1).bmp
 	diff out/$$*.$(1).bmp gold/$$*.bmp > out/$$*.$(1).diff
 	test ! -s out/$$*.$(1).diff && touch $$@
 
-out/%.$(1).raw: out/%.$(1).bit
-	../platform/$(1)/run $(shell pwd)/out/$$*.$(1).bit $(shell pwd)/out/$$*.metadata.lua $(shell pwd)/out/$$*.$(1).raw
+out/%.$(1).raw: out/%.$(1).bit out/%.metadata.lua
+	../platform/$(1)/run $(shell pwd)/out/$$*.$(1).bit $(shell pwd)/out/$$*.metadata.lua $(shell pwd)/out/$$*.$(1).raw $(shell pwd)/out/$$*.$(!)
 
-out/%.$(1).bmp: out/%.$(1).raw out/%.$(1).metadata.lua
-	$(LUA) ../misc/raw2bmp.lua out/$$*.$(1).raw out/$$*.$(1).bmp out/$$*.$(1).metadata.lua 0
+out/%.$(1).bmp: out/%.$(1).raw out/%.metadata.lua
+	$(LUA) ../misc/raw2bmp.lua out/$$*.$(1).raw out/$$*.$(1).bmp out/$$*.metadata.lua 0
 	# keep copy for future reference
 	mkdir -p out/$$*_$(1)
 	cp out/$$*.$(1).bmp out/$$*_$(1)

platform/zynq10ise/run

@@ -0,0 +1,41 @@
+#!/bin/bash -x
+# -x shows all commands
+
+ZYNQ_WRITE_PATH=/tmp
+ZYNQ_ADDR=192.168.1.10
+
+BITFILE=$1
+BITFILE_BASE=$(basename $1)
+METAFILE=$2
+OUTFILE=$3
+OUTPATH=$4
+
+
+LUA=../rigelLuajit
+
+#out/%.axi.raw: out/%.axi.bit out/%.hz.txt out/%.axi.metadata.lua
+IMG=$($LUA ../misc/extractMetadata.lua $METAFILE inputImage)
+INW=$($LUA ../misc/extractMetadata.lua $METAFILE inputWidth)
+INH=$($LUA ../misc/extractMetadata.lua $METAFILE inputHeight)
+BPP_IN=$($LUA ../misc/extractMetadata.lua $METAFILE inputBitsPerPixel)
+BPP_OUT=$($LUA ../misc/extractMetadata.lua $METAFILE outputBitsPerPixel)
+OUTW=$($LUA ../misc/extractMetadata.lua $METAFILE outputWidth)
+OUTH=$($LUA ../misc/extractMetadata.lua $METAFILE outputHeight)
+###### SET THE CLOCK	
+#HZ=$(cat $OUTPATH.hz.txt)
+#lockfile /tmp/zynq10lock
+# (* second time around we can't write to fclk_export, so surpress error)
+#sshpass -p 'root' ssh root@$ZYNQ_ADDR "if [[ ! -a /sys/devices/amba.0/f8007000.ps7-dev-cfg/fclk/fclk0 ]]; then echo 'fclk0' > /sys/devices/amba.0/f8007000.ps7-dev-cfg/fclk_export; fi"
+#	sshpass -p 'root' ssh root@$ZYNQ_ADDR "echo '$($@_HZ)' > /sys/class/fclk/fclk0/set_rate"
+#	sshpass -p 'root' ssh root@$ZYNQ_ADDR "cat /sys/class/fclk/fclk0/set_rate" > out/$*.realhz.txt
+###### CLOCK STUFF END
+
+sshpass -p 'root' scp ../platform/axi/processimage $BITFILE $IMG root@$ZYNQ_ADDR:$ZYNQ_WRITE_PATH
+sshpass -p 'root' ssh root@$ZYNQ_ADDR "cat $ZYNQ_WRITE_PATH/$BITFILE_BASE > /dev/xdevcfg"
+sshpass -p 'root' ssh root@$ZYNQ_ADDR "$ZYNQ_WRITE_PATH/processimage 805339136 $ZYNQ_WRITE_PATH/$IMG $ZYNQ_WRITE_PATH/out.raw $INW $INH $BPP_IN $OUTW $OUTH $BPP_OUT "
+sshpass -p 'root' scp root@$ZYNQ_ADDR:$ZYNQ_WRITE_PATH/out.raw $OUTFILE
+sshpass -p 'root' ssh root@$ZYNQ_ADDR "rm $ZYNQ_WRITE_PATH/processimage $ZYNQ_WRITE_PATH/$IMG $ZYNQ_WRITE_PATH/out.raw $ZYNQ_WRITE_PATH/$BITFILE_BASE"
+#rm -f /tmp/zynq10lock
+#	$(TERRA) ../misc/extractCycles.t out/$*.axi.raw > out/$*.axi.cycles.txt
+#	# keep copy for future reference
+#	cp out/$*.axi.cycles.txt out/build_$*

platform/zynq10ise/system.ucf

@@ -26,6 +26,13 @@ NET "LED<1>"        LOC=M15 | IOSTANDARD=LVCMOS33; #IO_L23N_T3_35
 NET "LED<2>"        LOC=G14 | IOSTANDARD=LVCMOS33; #IO_0_35
 NET "LED<3>"        LOC=D18 | IOSTANDARD=LVCMOS33; #IO_L3N_T0_DQS_AD1N_35
 
+# HACK: zybo doesn't have 8 LEDs, instead, emulate that by putting some of the LEDs on PMOD JA
+NET "LED<4>"       LOC=N16 | IOSTANDARD=LVCMOS33; #IO_L21N_T3_DQS_AD14N_35
+NET "LED<5>"       LOC=N15 | IOSTANDARD=LVCMOS33; #IO_L21P_T3_DQS_AD14P_35
+NET "LED<6>"       LOC=L15 | IOSTANDARD=LVCMOS33; #IO_L22N_T3_AD7N_35
+NET "LED<7>"       LOC=L14 | IOSTANDARD=LVCMOS33; #IO_L22P_T3_AD7P_35
+
+
 ## I2S Audio Codec
 #NET "ac_bclk"       LOC=K18 | IOSTANDARD=LVCMOS33; #IO_L12N_T1_MRCC_35
 #NET "ac_mclk"       LOC=T19 | IOSTANDARD=LVCMOS33; #IO_25_34

platform/zynq10vivado/compile

@@ -0,0 +1,23 @@
+#!/bin/bash
+
+VERILOG_FILE=$1
+METADATA_FILE=$2
+BUILDDIR=$3
+OUTFILE=$4
+
+mkdir -p $BUILDDIR
+cd $BUILDDIR
+echo "read_verilog $VERILOG_FILE" > system.tcl
+echo "read_xdc ../../../platform/zynq10vivado/zybo.xdc" >> system.tcl
+echo "read_xdc ../../../platform/vivado/ps7_constraints.xdc" >> system.tcl
+echo "synth_design -top stage -part xc7z010clg400-1" >> system.tcl
+echo "opt_design" >> system.tcl
+echo "place_design" >> system.tcl
+echo "phys_opt_design" >> system.tcl
+echo "route_design" >> system.tcl
+echo "write_bitstream system.bit" >> system.tcl
+echo "report_timing" >> system.tcl
+echo "report_timing_summary" >> system.tcl
+vivado -mode batch -source 'system.tcl' -nojournal -log 'vivado.log' > /dev/null
+cp system.bit $OUTFILE
+

platform/zynq10vivado/run

@@ -0,0 +1 @@
+../zynq10ise/run