verilator fixes

examples/makefile

@@ -145,9 +145,10 @@ out/%.raw out/%_half.raw out/%.sim.v out/%_half.sim.v out/%.axi.v out/%.verilato
 #/opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims
 #	verilator -cc -Mdir out/$*_verilator  /opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims/RAMB16_S36_S36.v out/$*.verilator.v
 out/%.verilator: out/%.verilator.v
-	verilator -cc -Mdir out/$*_verilator out/$*.verilator.v ../platform/verilator/RAMB16_S36_S36.v
+	$(eval $@_TOP := $(shell terra ../misc/extractMetadata.t out/$*.metadata.lua topModule))
+	verilator -cc -Mdir out/$*_verilator out/$*.verilator.v ../platform/verilator/RAMB16_S36_S36.v ../platform/verilator/RAMB16_S9_S9.v --top-module $($@_TOP)
 	terra ../platform/verilator/makeHarness.lua out/$*.metadata.lua $* > out/$*.verilator.cpp
-	g++ -I${VERPATH} out/$*_verilator/V$*.cpp out/$*_verilator/V$*__Syms.cpp ${VERPATH}verilated.cpp out/$*.verilator.cpp -o $@
+	g++ -I${VERPATH} out/$*_verilator/V$($@_TOP).cpp out/$*_verilator/V$($@_TOP)__Syms.cpp ${VERPATH}verilated.cpp out/$*.verilator.cpp -o $@
 
 out/%.verilator.raw: out/%.verilator
 	./out/$*.verilator

platform/verilator/RAMB16_S9_S9.v

@@ -0,0 +1,72 @@
+module RAMB16_S9_S9(
+  input WEA,
+  input ENA,
+  input SSRA,
+  input CLKA,
+  input [10:0] ADDRA,
+  input [7:0] DIA,
+  input DIPA,
+//  output [3:0] DOPA,
+  output [7:0] DOA,
+  input WEB,
+  input ENB,
+  input SSRB,
+  input CLKB,
+  input [10:0] ADDRB,
+  input [7:0] DIB,
+  input DIPB,
+//  output [3:0] DOPB,
+  output [7:0] DOB);
+  parameter WRITE_MODE_A = "write_first";
+  parameter WRITE_MODE_B = "write_first";
+
+  reg [7:0] ram [1024:0];
+  reg [7:0] bufferA;
+  reg [7:0] bufferB;
+
+  assign DOA = bufferA;
+  assign DOB = bufferB;
+
+//  assign DOPA = 4'b0;
+//  assign DOPB = 4'b0;
+
+  always @(posedge CLKA or posedge CLKB) begin
+
+    if( CLKA && CLKB && ENA && ENB && WEA && WEB ) begin
+      if(ADDRA==ADDRB) begin
+        $display("ERROR: write to some address on both ports");
+      end else begin
+        // different address: OK
+        bufferA <= ram[ADDRA];
+        bufferB <= ram[ADDRB];
+        ram[ADDRA] <= DIA;
+        ram[ADDRB] <= DIB;
+      end
+    end else begin
+      // not writing on both ports: can treat A/B differently
+
+      if (CLKA && ENA) begin
+        if (WEA) begin
+          ram[ADDRA] <= DIA;
+          bufferA <= ram[ADDRA];
+        end else begin
+          bufferA <= ram[ADDRA];
+        end
+      end
+
+      if (CLKB && ENB) begin
+        if (WEB) begin
+          ram[ADDRB] <= DIB;
+          bufferB <= ram[ADDRB];
+        end else begin
+          bufferB <= ram[ADDRB];
+        end
+      end
+
+    end
+
+  end
+
+
+
+endmodule

platform/verilator/makeHarness.lua

@@ -6,14 +6,14 @@ local outpackets = outbytes/8 -- axi bus
 
 print([=[#include <verilated.h>
 #include <iostream>
-#include "]=]..outmodule..[=[_verilator/V]=]..outmodule..[=[.h"
+#include "]=]..outmodule..[=[_verilator/V]=]..metadata.topModule..[=[.h"
 
 int main(int argc, char** argv) {
   //printf("START\n");
   Verilated::commandArgs(argc, argv); 
 
   //printf("alloc\n");
-  V]=]..outmodule..[=[* top = new V]=]..outmodule..[=[;
+  V]=]..metadata.topModule..[=[* top = new V]=]..metadata.topModule..[=[;
 
   //vluint64_t cycle = 0;
   bool CLK = false;