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Luacov (#92)

* Added luacov
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jameshegarty committed Dec 15, 2017
1 parent 4d242ad commit db3acc00020e46eb4083de628dc63a2d03b36570
Showing with 43 additions and 24 deletions.
  1. +6 −0 .luacov
  2. +10 −12 .travis.yml
  3. +1 −0 examples/.luacov
  4. +11 −0 examples/makefile
  5. +1 −0 unittests/.luacov
  6. +14 −12 unittests/makefile
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@@ -0,0 +1,6 @@
return {
include = {
"/home/travis/build/jameshegarty/rigel/src/.+$",
"/home/travis/build/jameshegarty/rigel/examples/examplescommon.lua"
}
}
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@@ -5,17 +5,12 @@ before_install:
# luajit
- sudo apt-get install luajit
#- sudo ln -s /usr/bin/luajit-2.0.0-beta9 /usr/bin/luajit
# verilator
- sudo apt-get install verilator
- export PKG_CONFIG_PATH=/home/travis/build/jameshegarty/rigel/platform/verilator
#terra
# - wget https://github.com/zdevito/terra/releases/download/release-2016-02-26/terra-Linux-x86_64-2fa8d0a.zip
# - unzip terra-Linux-x86_64-2fa8d0a.zip
# - sudo ln -s /home/travis/build/jameshegarty/rigel/terra-Linux-x86_64-2fa8d0a/bin/terra /usr/bin/terra
- wget https://github.com/zdevito/terra/releases/download/release-2016-03-25/terra-Linux-x86_64-332a506.zip
- unzip terra-Linux-x86_64-332a506.zip
- sudo ln -s /home/travis/build/jameshegarty/rigel/terra-Linux-x86_64-332a506/bin/terra /usr/bin/terra
@@ -25,23 +20,26 @@ before_install:
- sudo apt-get -y update
- sudo apt-get -y install libstdc++6-4.7-dev
# - cd examples
# - make out/pointwise_wide_handshake.terra.correct.txt
# - make out/pointwise_wide_handshake.verilator.correct.txt
#for coveralls
- if [[ $TARGET = "unit" ]] || [[ $TARGET = "coverage" ]]; then sudo apt-get install luarocks; fi
- if [[ $TARGET = "unit" ]] || [[ $TARGET = "coverage" ]]; then sudo luarocks install luacov-coveralls; fi
- if [[ $TARGET = "unit" ]] || [[ $TARGET = "coverage" ]]; then eval `luarocks path --bin`; fi
script:
# early out on errors
# early out on errors
- set -e
- if [[ $TARGET = "unit" ]]; then export LUA="../rigelLuajit -lluacov"; fi
- if [[ $TARGET = "unit" ]]; then cd unittests; make; else cd examples; make -j2 $TARGET; fi
# check that make actually 100% completed, just to be really sure (?)
# check that make actually 100% completed, just to be really sure (?)
- pwd
- echo out/${TARGET}_done.txt
# - test -e out/{$TARGET}_done.txt
- if [[ $TARGET != "unit" ]]; then test -e out/${TARGET}_done.txt || exit; fi
- if [[ $TARGET = "unit" ]]; then luacov-coveralls -v; fi
env:
- TARGET=verilog
- TARGET=verilator
- TARGET=terra
- TARGET=unit
- TARGET=axiverilog
- TARGET=coverage
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@@ -159,6 +159,9 @@ SRCS_ASIC = $(SRCS_VERILATOR)
ASIC = $(patsubst %.lua, out/%.32nm.txt, $(SRCS_ASIC))
COVERAGE_SRCS = pointwise_wide_handshake.lua convpadcrop_wide_handshake_4_1.lua conv_tr_handshake_4_4.lua campipe_128.lua downsamplex_wide_handshake_2.lua filterseq.lua downsampley_wide_handshake.lua padcrop_wide_handshake.lua shifty_wide_handshake.lua reduceseq_handshake.lua tmux_wide_handshake.lua upsample_wide_handshake_2.lua 4bpp.lua 12bpp.lua fifo_wide_handshake_2.lua fifo_wide_handshake_2_noloop.lua pad_wide_handshake.lua fifo_wide_handshake_bram.lua pyramid_tr_1.lua stereo_wide_handshake_tiny.lua
COVERAGE = $(patsubst %.lua,out/%.coverage.txt,$(COVERAGE_SRCS))
RES = $(TERRAOUT)
RES += $(VERILATOR)
RES += $(ISIM)
@@ -208,6 +211,9 @@ zynq100bits: $(AXIBITS100)
asic: $(ASIC)
coverage: $(COVERAGE)
touch out/coverage_done.txt
clean:
rm -Rf out/*
@@ -223,6 +229,11 @@ out/%.v: %.lua
mkdir -p out/build_$*
- cp out/$*.v out/build_$*
out/%.coverage.txt: %.lua
$(LUA) -lluacov $< verilator
luacov-coveralls -v
touch $@
out/%.terra.raw out/%_half.terra.raw: %.lua
$(TERRA) $< terra
# keep copy for future reference
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@@ -13,6 +13,8 @@ TARGETS += $(patsubst %.lua,out/%.correct.txt,$(SRCS))
CORES ?= 2
LUA ?= ../rigelLuajit
all: $(TARGETS)
# build all .v files
@@ -52,26 +54,26 @@ out/fixedtest.correct.txt: out/verilogcorrect.txt
###################
out/fwriteseq.compiles.txt: fwriteseq.lua
../rigelTerra fwriteseq.lua terra
../rigelLuajit fwriteseq.lua verilog
../rigelLuajit fwriteseq.lua metadata
$(LUA) fwriteseq.lua verilog
$(LUA) fwriteseq.lua metadata
out/fwriteseq.correct.txt: out/verilogcorrect.txt
diff out/fwriteseqtest.raw out/fwriteseqtestVerilog.raw > out/fwriteseqtest.diff
test ! -s out/$*.fwriteseqtest.diff && touch $@
###################
out/fwriteseq16.compiles.txt: fwriteseq16.lua
../rigelTerra fwriteseq16.lua terra
../rigelLuajit fwriteseq16.lua verilog
../rigelLuajit fwriteseq16.lua metadata
$(LUA) fwriteseq16.lua verilog
$(LUA) fwriteseq16.lua metadata
out/fwriteseq16.correct.txt: out/verilogcorrect.txt
diff out/fwriteseq16test.raw out/fwriteseq16testVerilog.raw > out/fwriteseq16test.diff
test ! -s out/$*.fwriteseq16test.diff && touch $@
###################
out/fwriteseq12.compiles.txt: fwriteseq12.lua
../rigelTerra fwriteseq12.lua terra
../rigelLuajit fwriteseq12.lua verilog
../rigelLuajit fwriteseq12.lua metadata
$(LUA) fwriteseq12.lua verilog
$(LUA) fwriteseq12.lua metadata
out/fwriteseq12.correct.txt: out/verilogcorrect.txt
diff out/fwriteseq16test.raw out/dbg_terra_fwriteseq12.raw > out/fwriteseq12test.diff
@@ -80,17 +82,17 @@ out/fwriteseq12.correct.txt: out/verilogcorrect.txt
###################
out/fwriteseq18.compiles.txt: fwriteseq18.lua
../rigelTerra fwriteseq18.lua terra
../rigelLuajit fwriteseq18.lua verilog
../rigelLuajit fwriteseq18.lua metadata
$(LUA) fwriteseq18.lua verilog
$(LUA) fwriteseq18.lua metadata
out/fwriteseq18.correct.txt: out/verilogcorrect.txt
diff out/dbg_terra_fwriteseq18.raw out/dbg_verilog_fwriteseq18.raw > out/fwriteseq18test.diff
test ! -s out/$*.fwriteseq18test.diff && touch $@
###################
out/fwriteseq24.compiles.txt: fwriteseq24.lua
../rigelTerra fwriteseq24.lua terra
../rigelLuajit fwriteseq24.lua verilog
../rigelLuajit fwriteseq24.lua metadata
$(LUA) fwriteseq24.lua verilog
$(LUA) fwriteseq24.lua metadata
out/fwriteseq24.correct.txt: out/verilogcorrect.txt
diff out/dbg_terra_fwriteseq24.raw out/dbg_verilog_fwriteseq24.raw > out/fwriteseq24test.diff
@@ -100,8 +102,8 @@ out/fwriteseq24.correct.txt: out/verilogcorrect.txt
###################
out/fwriteseq37.compiles.txt: fwriteseq37.lua
../rigelTerra fwriteseq37.lua terra
../rigelLuajit fwriteseq37.lua verilog
../rigelLuajit fwriteseq37.lua metadata
$(LUA) fwriteseq37.lua verilog
$(LUA) fwriteseq37.lua metadata
out/fwriteseq37.correct.txt: out/verilogcorrect.txt
diff out/dbg_terra_fwriteseq37.raw out/dbg_verilog_fwriteseq37.raw > out/fwriteseq37test.diff

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