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Harnessrefactor (#93)

* Fully factored out axi harness into a script.
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jameshegarty committed Dec 16, 2017
1 parent db3acc0 commit f72b37aa43b592bcb50ccf6590bf4fe9de4984f6
Showing with 239 additions and 154 deletions.
  1. +2 −2 .travis.yml
  2. +19 −143 examples/harness.lua
  3. +4 −2 examples/makefile
  4. +172 −7 platform/axi/wrapper.lua
  5. +42 −0 src/modules.lua
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@@ -41,5 +41,5 @@ env:
- TARGET=verilator
- TARGET=terra
- TARGET=unit
- TARGET=axiverilog
- TARGET=coverage
- TARGET=coverage
# - TARGET=axiverilog
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@@ -40,81 +40,6 @@ local function expectedCycles(hsfn,inputCount,outputCount,underflowTest,slackPer
return EC, EC_RAW
end
local function harnessAxi( hsfn, inputCount, outputCount, underflowTest, inputType, tapType, earlyOverride)
local outputBytes = J.upToNearest(128,outputCount*8) -- round to axi burst
local inputBytes = J.upToNearest(128,inputCount*8) -- round to axi burst
err(outputBytes==outputCount*8, "NYI - non-burst-aligned output counts")
err(inputBytes==inputCount*8, "NYI - non-burst-aligned input counts")
local ITYPE = inputType
--if tapType~=nil then ITYPE = types.tuple{inputType,tapType} end
local inpSymb = R.input( R.Handshake(ITYPE) )
local inpdata
local inptaps
-- if tapType==nil then
inpdata = inpSymb
-- else
-- inpdata = R.apply("inpdata", RM.makeHandshake(C.index(ITYPE,0)), inpSymb)
-- inptaps = R.apply("inptaps", RM.makeHandshake(C.index(ITYPE,1)), inpSymb)
-- end
local EC
if type(earlyOverride)=="number" then
EC=earlyOverride
else
EC = expectedCycles(hsfn,inputCount,outputCount,underflowTest,1.85)
end
local inpdata = R.apply("underflow_US", RM.underflow( R.extractData(inputType), inputBytes/8, EC, true ), inpdata)
local hsfninp
-- if tapType==nil then
hsfninp = inpdata
-- else
-- hsfninp = R.apply("HFN",RM.packTuple({inputType,tapType}), R.concat("hsfninp",{inpdata,inptaps}))
-- end
-- add a FIFO to all pipelines. Some user's pipeline may not have any FIFOs in them.
-- you would think it would be OK to have no FIFOs, but for some reason, sometimes wiring the AXI read port and write port
-- directly won't work. The write port ready seizes up (& the underflow_US is needed to prevent deadlock, but then the image is incorrect).
-- The problem is intermittent.
local regs, out
local stats = {}
local EXTRA_FIFO = false
if EXTRA_FIFO then
regs = {R.instantiateRegistered("f1",RM.fifo(R.extractData(hsfn.inputType),256))}
stats[2] = R.applyMethod("s1",regs[1],"store",hsfninp)
hsfninp = R.applyMethod("l1",regs[1],"load")
end
local pipelineOut = R.apply("hsfna",hsfn,hsfninp)
if EXTRA_FIFO then
regs[2] = R.instantiateRegistered("f2",RM.fifo(R.extractData(hsfn.outputType),256))
out = R.applyMethod("l2",regs[2],"load")
stats[3] = R.applyMethod("s2",regs[2],"store",pipelineOut)
else
out = pipelineOut
end
out = R.apply("overflow", RM.liftHandshake(RM.liftDecimate(RM.overflow(R.extractData(hsfn.outputType), outputCount))), out)
out = R.apply("underflow", RM.underflow(R.extractData(hsfn.outputType), outputBytes/8, EC, false ), out)
out = R.apply("cycleCounter", RM.cycleCounter(R.extractData(hsfn.outputType), outputBytes/8 ), out)
if EXTRA_FIFO then
stats[1] = out
out = R.statements(stats)
end
return RM.lambda( "harnessaxi", inpSymb, out, regs )
end
local H = {}
@@ -178,71 +103,6 @@ function H.verilogOnly(filename, hsfn, inputFilename, tapType, tapValue, inputTy
end
local function axiRateWrapper(fn)
--err(tapType==nil or types.isType(tapType),"tapType should be type or nil")
R.expectHandshake(fn.inputType)
local iover = R.extractData(fn.inputType)
-- if tapType~=nil then
-- -- taps have tap value packed into argument
-- assert(iover.list[2]==tapType)
-- iover = iover.list[1]
-- end
R.expectHandshake(fn.outputType)
oover = R.extractData(fn.outputType)
if iover:verilogBits()==64 and oover:verilogBits()==64 then
return fn
end
local inputP
if iover:isArray() then
inputP = iover:channels()
iover = iover:arrayOver()
else
inputP = 1 -- just assume pointwise...
end
local outputP
if oover:isArray() then
outputP = oover:channels()
oover = oover:arrayOver()
else
outputP = 1
end
local targetInputP = (64/iover:verilogBits())
err( targetInputP==math.floor(targetInputP), "axiRateWrapper error: input type does not divide evenly into axi bus size ("..tostring(fn.inputType)..") iover:"..tostring(iover).." inputP:"..tostring(inputP))
local inp = R.input( R.Handshake(types.array2d(iover,targetInputP)) )
local out = inp
if fn.inputType:verilogBits()~=64 then
out = R.apply("harnessCR", RM.liftHandshake(RM.changeRate(iover, 1, targetInputP, inputP )), inp)
end
if R.extractData(fn.inputType):isArray()==false then out = R.apply("harnessPW",RM.makeHandshake(C.index(types.array2d(iover,1),0)),out) end
out = R.apply("HarnessHSFN",fn,out) --{input=out, toModule=fn}
if R.extractData(fn.outputType):isArray()==false then out = R.apply("harnessPW0",RM.makeHandshake(C.arrayop(oover,1)),out) end
local targetOutputP = (64/oover:verilogBits())
err( targetOutputP==math.floor(targetOutputP), "axiRateWrapper error: output type does not divide evenly into axi bus size")
if fn.outputType:verilogBits()~=64 then
out = R.apply("harnessCREnd", RM.liftHandshake(RM.changeRate(oover,1,outputP,targetOutputP)),out)
end
local outFn = RM.lambda("hsfnAxiRateWrapper",inp,out)
err( R.extractData(outFn.inputType):verilogBits()==64, "axi rate wrapper: failed to make input type 64 bit (originally "..tostring(fn.inputType)..")")
err( R.extractData(outFn.outputType):verilogBits()==64, "axi rate wrapper: failed to make output type 64 bit")
return outFn
end
-- AXI must have T=8
function H.axi(filename, hsfn, inputFilename, tapType, tapValue, inputType, inputT, inputW, inputH, outputType, outputT, outputW, outputH,underflowTest,earlyOverride,X)
@@ -312,9 +172,9 @@ function harnessTop(t)
if backend==nil then backend = arg[1] end
if backend==nil then backend = "verilog" end
if(backend=="axi") then
t.fn = axiRateWrapper(t.fn, t.tapType)
end
-- if(backend=="axi") then
-- t.fn = axiRateWrapper(t.fn, t.tapType)
-- end
-- if user explicitly passes us the the info, just trust them...
local iover, inputP, oover, outputP, fn = t.inType, t.inP, t.outType, t.outP, t.fn
@@ -366,6 +226,22 @@ function harnessTop(t)
if harnessOption==nil then harnessOption=1 end
local MD = {inputBitsPerPixel=R.extractData(iover):verilogBits()/(inputP), inputWidth=t.inSize[1], inputHeight=t.inSize[2], outputBitsPerPixel=oover:verilogBits()/(outputP), outputWidth=t.outSize[1], outputHeight=t.outSize[2], inputImage=t.inFile, topModule= fn.name, inputP=inputP, outputP=outputP, simCycles=t.simCycles, tapBits=tapBits, tapValue=tapValueString, harness=harnessOption, ramFile=t.ramFile}
if fn.sdfInput~=nil then
assert(#fn.sdfInput==1)
MD.sdfInputN = fn.sdfInput[1][1]
MD.sdfInputD = fn.sdfInput[1][2]
end
if fn.sdfOutput~=nil then
assert(#fn.sdfOutput==1)
MD.sdfOutputN = fn.sdfOutput[1][1]
MD.sdfOutputD = fn.sdfOutput[1][2]
end
MD.earlyOverride=t.earlyOverride
MD.underflowTest = t.underflowTest
if t.ramType~=nil then MD.ramBits = t.ramType:verilogBits() end
writeMetadata("out/"..t.outFile..".metadata.lua", MD)
View
@@ -53,6 +53,8 @@ SRCS_VERILATOR := $(filter-out stereo_wide_handshake_medi.lua stereo_wide_handsh
# NYI
SRCS_VERILATOR := $(filter-out pad.lua crop.lua stencil.lua downsample_2.lua downsample_4.lua upsample_2.lua upsample_4.lua, $(SRCS_VERILATOR))
SRCS_VERILATOR := $(filter-out readmemory.lua readmemory_flip.lua, $(SRCS_VERILATOR))
VERILATOR = $(patsubst %.lua,out/%.verilator,$(SRCS_VERILATOR))
VERILATOR = $(patsubst %.lua,out/%.verilator.raw,$(SRCS_VERILATOR))
#VERILATOR += $(patsubst %.lua,out/%_half.raw,$(SRCS_VERILATOR))
@@ -312,8 +314,8 @@ PLATFORMDIRS = $(wildcard ../platform/*)
AA = $(patsubst ../platform/%,%,$(PLATFORMDIRS))
define MyRule
out/%.$(1).bit: out/%.axi.v out/%.metadata.lua
../platform/$(1)/compile $(shell pwd)/out/$$*.axi.v out/$$*.metadata.lua $(shell pwd)/out/$$*_$(1) $(shell pwd)/out/$$*.$(1).bit
out/%.$(1).bit: out/%.v out/%.metadata.lua
../platform/$(1)/compile $(shell pwd)/out/$$*.v out/$$*.metadata.lua $(shell pwd)/out/$$*_$(1) $(shell pwd)/out/$$*.$(1).bit
out/%.$(1).correct.txt : out/%.$(1).bmp
diff out/$$*.$(1).bmp gold/$$*.bmp > out/$$*.$(1).diff
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