Permalink
Commits on Aug 10, 2018
  1. AxiByteWriter (#122)

    jameshegarty committed Aug 10, 2018
    * Implemented Axi byte writer and performed harness changes to better obey handshaking rules.
Commits on Jul 25, 2018
  1. Nonalignedrw (#121)

    jameshegarty committed Jul 25, 2018
    * support non-aligned read/write sizes in DMA
Commits on Jul 18, 2018
  1. Non128 (#120)

    jameshegarty committed Jul 18, 2018
    allowed non-128 byte aligned reads/writes
Commits on Jul 17, 2018
  1. quick fix

    jameshegarty committed Jul 17, 2018
  2. Regsimpl (#119)

    jameshegarty committed Jul 17, 2018
    * initial
    
    * progress
    
    * convgenTaps works
    
    * included convgenTaps
    
    * registers work on zu9/terra
    
    * printf
    
    * fix
Commits on Jul 12, 2018
  1. More bram options (#118)

    jameshegarty committed Jul 12, 2018
    * initial
    
    * minor fix
Commits on Jul 9, 2018
  1. Improvepipelining (#117)

    jameshegarty committed Jul 9, 2018
    * initial
    
    * commended out print
    
    * quick fixes
    
    * testbench fix
    
    * approx cleanup
    
    * cost updates
Commits on Jul 6, 2018
  1. missing file

    jameshegarty committed Jul 6, 2018
  2. Cyclecheck (#116)

    jameshegarty committed Jul 6, 2018
    * added cycle checking. minor fixes. shift chain linebuffer. fixed verilog for some platforms which was no longer compiling due to additional sanity checking option
    
    * zu9 perf checking
Commits on Jun 21, 2018
  1. Donebit (#115)

    jameshegarty committed Jun 21, 2018
    * Added done bit & done bit checking
Commits on Jun 15, 2018
  1. Generators + Terra SOC Harness + Register slave (#114)

    jameshegarty committed Jun 15, 2018
Commits on Apr 19, 2018
  1. varnames (#113)

    jameshegarty committed Apr 19, 2018
    used lua debug interface to pull var names into rigel
Commits on Apr 10, 2018
  1. Soc travis (#112)

    jameshegarty committed Apr 10, 2018
    * SOC backend (incl 2x DMA) working in verilator and zu9
Commits on Apr 5, 2018
  1. verilator soc backend

    jameshegarty committed Apr 5, 2018
  2. disabled some tests to make cron test work

    jameshegarty committed Apr 5, 2018
Commits on Apr 3, 2018
  1. fix script

    jameshegarty committed Apr 3, 2018
  2. change to bash

    jameshegarty committed Apr 3, 2018
  3. script fixes (#111)

    jameshegarty committed Apr 3, 2018
    * added padding to dma so that non-burst sized outputs work better
    * stopped cycles from being written into file stream
    * updated cron script
  4. wrapper verilog fixes (#110)

    jameshegarty committed Apr 3, 2018
    fixed syntax errors in wrapper.
Commits on Mar 29, 2018
  1. changed default timeout to something reasonable

    jameshegarty committed Mar 29, 2018
  2. Soc (#108)

    jameshegarty committed Mar 29, 2018
    * Initial work on allowing Rigel to generate full AXI interfaces
    * removed const nonsense
Commits on Mar 24, 2018
  1. wrapper refactor

    jameshegarty committed Mar 24, 2018
Commits on Mar 23, 2018
  1. changed canaries to be unique

    jameshegarty committed Mar 23, 2018
Commits on Mar 22, 2018
  1. improved zu9 script

    jameshegarty committed Mar 22, 2018
Commits on Mar 16, 2018
  1. script fix

    James Hegarty
    James Hegarty committed Mar 16, 2018
  2. script tweak

    James Hegarty
    James Hegarty committed Mar 16, 2018
Commits on Mar 15, 2018
  1. Wrapperfix (#105)

    jameshegarty committed Mar 15, 2018
    Tweaked wrapper so that it can support non-burst aligned read/writes, sort of.
Commits on Mar 14, 2018
  1. slight tweak to wrapper

    jameshegarty committed Mar 14, 2018
  2. Runtimegpio (#104)

    jameshegarty committed Mar 14, 2018
    Plumbed code through so that N bits of GPIO registers could be reconfigured at runtime
Commits on Mar 10, 2018
  1. fix to problem with memoize (#103)

    jameshegarty committed Mar 10, 2018
Commits on Feb 28, 2018
  1. new terra fix (#102)

    jameshegarty committed Feb 28, 2018
    Minor fix of bug due to switch to new version of terra.
  2. Codesize optimization (#101)

    jameshegarty committed Feb 28, 2018
    Optimized map/reduce/SoAtoAoS to write log(n) sized verilog code instead of n.
Commits on Feb 26, 2018
  1. Verilator file name fix (#100)

    jameshegarty committed Feb 26, 2018
    * initial
    
    * minor fixes
    
    * minor fixes
    
    * code cleanup to support different output dirs
    
    * minor fix
    
    * initial
  2. Platform.mk and cleanup (#99)

    jameshegarty committed Feb 26, 2018
    * Move common makefile stuff into platform/platform.mk
    * fixed broken 2 ram config
    * allow for different output dirs than out/
Commits on Jan 30, 2018
  1. Zu9 board support (#98)

    jameshegarty committed Jan 30, 2018
    * Fixed scripts to work on zu9 MPSoC boards. Documented script interface.