diff --git a/LICENSE b/LICENSE
index 63b4b68..a46a1e0 100644
--- a/LICENSE
+++ b/LICENSE
@@ -1,6 +1,6 @@
MIT License
-Copyright (c) [year] [fullname]
+Copyright (c) 2018 James Jiang
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
diff --git a/README.rst b/README.rst
index b1092da..838c6f3 100644
--- a/README.rst
+++ b/README.rst
@@ -46,7 +46,7 @@ Interacting with it in a Python session::
In [2]: b.value = 0
- In [3]: sum.value
+ In [3]: sum_.value
Out[3]: 0
In [4]: carry_out.value
@@ -54,7 +54,7 @@ Interacting with it in a Python session::
In [5]: a.value = 1
- In [6]: sum.value
+ In [6]: sum_.value
Out[6]: 1
In [7]: carry_out.value
@@ -62,7 +62,7 @@ Interacting with it in a Python session::
In [8]: b.value = 1
- In [9]: sum.value
+ In [9]: sum_.value
Out[9]: 0
In [10]: carry_out.value
diff --git a/bitwise/signal/__init__.py b/bitwise/signal/__init__.py
index 7170fe7..140db94 100644
--- a/bitwise/signal/__init__.py
+++ b/bitwise/signal/__init__.py
@@ -3,6 +3,4 @@
from .ENC import *
from .MUX import *
from .INV_CTRL import *
-from .PISO import *
-from .SIPO import *
from .SSD import *
diff --git a/bitwise/storage/FLOP.py b/bitwise/storage/FLOP.py
index 180d511..38a3567 100644
--- a/bitwise/storage/FLOP.py
+++ b/bitwise/storage/FLOP.py
@@ -1,9 +1,4 @@
"""
-This module defines classes that simulate primitive storage elements, namely
-1-bit latches and 1-bit flip-flops. Latches are level-sensitive, changing their
-value according to the value of a clock input, while flip-flops are edge-
-sensitive, changing their value according to edges of a clock input.
-
The following classes are defined:
SRLatch
GatedSRLatch
@@ -24,16 +19,15 @@
class SRLatch:
- """
- This class simulates an SR latch, which has two inputs and two outputs:
- ________
- set ----| |---- output
- reset ----|________|---- output_not
-
- If set is 1 and reset is 0, output and output_not are 1 and 0,
- respectively. If set is 0 and reset is 1, output and output_not are 0 and
- 1, respectively. If both set and reset are 0, output and output_not hold
- their current values. The input where both set and reset are 1 is not used.
+ """Construct a new SR latch.
+
+ Args:
+ set_: An object of type Wire. The set input to the latch.
+ reset: An object of type Wire. The reset input to the latch.
+ output: An object of type Wire. The output of the latch. Takes on the
+ value of 1 if the value of set is 1 and the value of 0 if the value
+ of reset is 1.
+ output_not: An object of type Wire. The complemented form of output.
"""
def __init__(self, set_, reset, output, output_not):
gate.NORGate2(set_, output, output_not)
@@ -41,21 +35,16 @@ def __init__(self, set_, reset, output, output_not):
class GatedSRLatch:
- """
- This class simulates a gated SR latch, which has three inputs, including a
- clock, and two outputs:
- ________
- set ----| |---- output
- reset ----| |---- output_not
- clock ----|________|
-
- If clock is 0, output and output_not hold their current values, regardless
- of the set and reset inputs. If clock is 1 and set and reset are 1 and 0,
- respectively, output and output_not are 1 and 0, respectively. If clock is
- 1 and set and reset are 1 and 0, respectively, output and output_not are 0
- and 1, respectively. If clock is 1 and both set and reset are 0, output and
- output_not hold their current values. The input where both set and reset
- are 1 is not used.
+ """Construct a new gated SR latch.
+
+ Args:
+ set_: An object of type Wire. The set input to the latch.
+ reset: An object of type Wire. The reset input to the latch.
+ clock: An object of type Wire. The clock input to the latch.
+ output: An object of type Wire. The output of the latch. When the value
+ of clock is 1, takes on the value of 1 if the value of set is 1 and
+ the value of 0 if the value of reset is 1.
+ output_not: An object of type Wire. The complemented form of output.
"""
def __init__(self, set_, reset, clock, output, output_not):
wire_1 = Wire()
@@ -67,16 +56,14 @@ def __init__(self, set_, reset, clock, output, output_not):
class GatedDLatch:
- """
- This class simulates a gated D latch, which has two inputs, including a
- clock, and two outputs:
- ________
- data ----| |---- output
- clock ----|________|---- output_not
-
- If clock is 0, output and output_not hold their current values, regardless
- of the data input. If clock is 1, output takes on the value of data and
- output_not takes on the opposite value.
+ """Construct a new gated D latch.
+
+ Args:
+ data: An object of type Wire. The data input to the latch.
+ clock: An object of type Wire. The clock input to the latch.
+ output: An object of type Wire. The output of the latch. Takes on the
+ value of data if the value of clock is 1.
+ output_not: An object of type Wire. The complemented form of output.
"""
def __init__(self, data, clock, output, output_not):
wire_1 = Wire()
@@ -86,17 +73,14 @@ def __init__(self, data, clock, output, output_not):
class DFlipFlop:
- """
- This class simulates a D flip-flop, which has two inputs, including a
- clock, and two outputs:
- ________
- data ----| |---- output
- clock ----|________|---- output_not
-
- On the positive edge of clock (i.e. on the clock transition from a 0 value
- to a 1 value), output takes on the value of data and output_not takes on
- the opposite value. Otherwise, output and output_not hold their current
- values.
+ """Construct a new positive edge-triggered D flip-flop.
+
+ Args:
+ data: An object of type Wire. The data input to the flip-flop.
+ clock: An object of type Wire. The clock input to the flip-flop.
+ output: An object of type Wire. The output of the flip-flop. Takes on
+ the value of data on the positive edges of clock.
+ output_not: An object of type Wire. The complemented form of output.
"""
def __init__(self, data, clock, output, output_not):
q_1 = Wire()
@@ -109,24 +93,19 @@ def __init__(self, data, clock, output, output_not):
class DFlipFlopPresetClear:
- """
- This class simulates a D flip-flop, with additional inputs for presetting
- and clearing the flip_flop. It has four inputs, including a clock, and two
- outputs:
- ________
- data ----| |---- output
- preset_n ----| |---- output_not
- clear_n ----| |
- clock ----|________|
-
- On the positive edge of clock (i.e. on the clock transition from a 0 value
- to a 1 value), output takes on the value of data and output_not takes on
- the opposite value. Otherwise, output and output_not hold their current
- values.
-
- Inputs preset_n and clear_n are, respectively, an active low
- asynchronous preset (setting output to 1 and output_not to 0) and an active
- low asynchronous clear (setting output to 0 and output_not to 1).
+ """Construct a new positive edge-triggered D flip-flop with preset/clear
+ capabilities.
+
+ Args:
+ data: An object of type Wire. The data input to the flip-flop.
+ preset_n: An object of type Wire. Presets output to 1 and output_not to
+ 0 if its value is 0.
+ clear_n: An object of type Wire. Clears output to 0 and output_not to 1
+ if its value is 0.
+ clock: An object of type Wire. The clock input to the flip-flop.
+ output: An object of type Wire. The output of the flip-flop. Takes on
+ the value of data on the positive edges of clock.
+ output_not: An object of type Wire. The complemented form of output.
"""
def __init__(self, data, preset_n, clear_n, clock, output, output_not):
not_clock = Wire()
@@ -151,17 +130,15 @@ def __init__(self, data, preset_n, clear_n, clock, output, output_not):
class TFlipFlop:
- """
- This class simulates a T flip-flop, which has two inputs, including a
- clock, and two outputs:
- ________
- toggle ----| |---- output
- clock ----|________|---- output_not
-
- On the positive edge of clock (i.e. on the clock transition from a 0 value
- to a 1 value), if toggle has the value 1, both output and output_not toggle
- their current values. If toggle has the value 0, both output and output_not
- are unchanged.
+ """Construct a new positive edge-triggered T flip-flop.
+
+ Args:
+ toggle: An object of type Wire. The toggle input to the flip-flop.
+ clock: An object of type Wire. The clock input to the flip-flop.
+ output: An object of type Wire. The output of the flip-flop. Toggles
+ its value on the positive edges of clock if the value of toggle is
+ 1.
+ output_not: An object of type Wire. The complemented form of output.
"""
def __init__(self, toggle, clock, output, output_not):
mux_output = Wire()
@@ -173,24 +150,20 @@ def __init__(self, toggle, clock, output, output_not):
class TFlipFlopPresetClear:
- """
- This class simulates a T flip-flop, with additional inputs for presetting
- and clearing the flip_flop. It has four inputs, including a clock, and two
- outputs:
- ________
- toggle ----| |---- output
- preset_n ----| |---- output_not
- clear_n ----| |
- clock ----|________|
-
- On the positive edge of clock (i.e. on the clock transition from a 0 value
- to a 1 value), if toggle has the value 1, both output and output_not toggle
- their current values. If toggle has the value 0, both output and output_not
- are unchanged.
-
- Inputs preset_n and clear_n are, respectively, an active low
- asynchronous preset (setting output to 1 and output_not to 0) and an active
- low asynchronous clear (setting output to 0 and output_not to 1).
+ """Construct a new positive edge-triggered T flip-flop with preset/clear
+ capabilities.
+
+ Args:
+ toggle: An object of type Wire. The toggle input to the flip-flop.
+ preset_n: An object of type Wire. Presets output to 1 and output_not to
+ 0 if its value is 0.
+ clear_n: An object of type Wire. Clears output to 0 and output_not to 1
+ if its value is 0.
+ clock: An object of type Wire. The clock input to the flip-flop.
+ output: An object of type Wire. The output of the flip-flop. Toggles
+ its value on the positive edges of clock if the value of toggle is
+ 1.
+ output_not: An object of type Wire. The complemented form of output.
"""
def __init__(self, toggle, preset_n, clear_n, clock, output, output_not):
mux_output = Wire()
@@ -209,20 +182,17 @@ def __init__(self, toggle, preset_n, clear_n, clock, output, output_not):
class JKFlipFlop:
- """
- This class simulates a JK flip-flop, which has three inputs, including a
- clock, and two outputs:
- ________
- J ----| |---- output
- K ----| |---- output_not
- clock ----|________|
-
- On the positive edge of clock (i.e. on the clock transition from a 0 value
- to a 1 value), if J is 1 and K is 0, output and output_not are 1 and 0,
- respectively. If J is 0 and K is 1, output and output_not are 0 and 1,
- respectively. If J and K are both 0, both output and output_not hold their
- current values. If J and K are both 1, both output and output_not toggle
- their current values.
+ """Construct a new positive edge-triggered JK flip-flop.
+
+ Args:
+ J: An object of type Wire. The J input to the flip-flop.
+ K: An object of type Wire. The K input to the flip-flop.
+ clock: An object of type Wire. The clock input to the flip-flop.
+ output: An object of type Wire. The output of the flip-flop. On the
+ positive edges of clock, takes on the value of 1 if the value of J
+ is 1, takes on the value of 0 if the value of K is 1, and toggles
+ its value if both J and K have value 1.
+ output_not: An object of type Wire. The complemented form of output.
"""
def __init__(self, j, k, clock, output, output_not):
and_1 = Wire()
@@ -238,27 +208,22 @@ def __init__(self, j, k, clock, output, output_not):
class JKFlipFlopPresetClear:
- """
- This class simulates a JK flip-flop, with additional inputs for presetting
- and clearing the flip_flop. It has five inputs, including a clock, and two
- outputs:
- ________
- J ----| |---- output
- K ----| |---- output_not
- preset_n ----| |
- clear_n ----| |
- clock ----|________|
-
- On the positive edge of clock (i.e. on the clock transition from a 0 value
- to a 1 value), if J is 1 and K is 0, output and output_not are 1 and 0,
- respectively. If J is 0 and K is 1, output and output_not are 0 and 1,
- respectively. If J and K are both 0, both output and output_not hold their
- current values. If J and K are both 1, both output and output_not toggle
- their current values.
-
- Inputs preset_n and clear_n are, respectively, an active low
- asynchronous preset (setting output to 1 and output_not to 0) and an active
- low asynchronous clear (setting output to 0 and output_not to 1).
+ """Construct a new positive edge-triggered JK flip-flop with preset/clear
+ capabilities.
+
+ Args:
+ J: An object of type Wire. The J input to the flip-flop.
+ K: An object of type Wire. The K input to the flip-flop.
+ preset_n: An object of type Wire. Presets output to 1 and output_not to
+ 0 if its value is 0.
+ clear_n: An object of type Wire. Clears output to 0 and output_not to 1
+ if its value is 0.
+ clock: An object of type Wire. The clock input to the flip-flop.
+ output: An object of type Wire. The output of the flip-flop. On the
+ positive edges of clock, takes on the value of 1 if the value of J
+ is 1, takes on the value of 0 if the value of K is 1, and toggles
+ its value if both J and K have value 1.
+ output_not: An object of type Wire. The complemented form of output.
"""
def __init__(self, j, k, preset_n, clear_n, clock, output, output_not):
and_1 = Wire()
diff --git a/bitwise/signal/PISO.py b/bitwise/storage/PISO.py
similarity index 52%
rename from bitwise/signal/PISO.py
rename to bitwise/storage/PISO.py
index 7702196..3ed651e 100644
--- a/bitwise/signal/PISO.py
+++ b/bitwise/storage/PISO.py
@@ -15,8 +15,23 @@
class ParallelToSerialConverter4To1:
- """
-
+ """Construct a new 4-bit-parallel-to-serial converter.
+
+ Args:
+ enable: An object of type Wire. Enables the converter.
+ clear_n: An object of type Wire. Clears all 4 internal registers to 0
+ if its value is 0.
+ load_n: An object of type Wire. The mode select. A value of 0 indicates
+ a parallel load operation, where the values of data_bus are loaded
+ into the internal registers. A value of 1 indicates a shift-right
+ operation.
+ data_bus: An object of type Bus4. The parallel data input.
+ clock: An object of type Wire or Clock. The clock input.
+ output: An object of type Wire. The serial output of the converter.
+ data_bus[3] is outputted first, and data_bus[0] is outputted last.
+
+ Raises:
+ TypeError: If data_bus is not a bus of width 4.
"""
def __init__(
self,
@@ -27,10 +42,10 @@ def __init__(
clock,
output
):
- if len(data_bus.wires) != 4:
+ if len(data_bus) != 4:
raise TypeError(
"Expected bus of width 4, received bus of width {0}.".format(
- len(data_bus.wires)
+ len(data_bus)
)
)
@@ -59,8 +74,23 @@ def __init__(
class ParallelToSerialConverter8To1:
- """
-
+ """Construct a new 8-bit-parallel-to-serial converter.
+
+ Args:
+ enable: An object of type Wire. Enables the converter.
+ clear_n: An object of type Wire. Clears all 8 internal registers to 0
+ if its value is 0.
+ load_n: An object of type Wire. The mode select. A value of 0 indicates
+ a parallel load operation, where the values of data_bus are loaded
+ into the internal registers. A value of 1 indicates a shift-right
+ operation.
+ data_bus: An object of type Bus8. The parallel data input.
+ clock: An object of type Wire or Clock. The clock input.
+ output: An object of type Wire. The serial output of the converter.
+ data_bus[7] is outputted first, and data_bus[0] is outputted last.
+
+ Raises:
+ TypeError: If data_bus is not a bus of width 8.
"""
def __init__(
self,
@@ -71,10 +101,10 @@ def __init__(
clock,
output
):
- if len(data_bus.wires) != 8:
+ if len(data_bus) != 8:
raise TypeError(
"Expected bus of width 8, received bus of width {0}.".format(
- len(data_bus.wires)
+ len(data_bus)
)
)
@@ -107,8 +137,23 @@ def __init__(
class ParallelToSerialConverter16To1:
- """
-
+ """Construct a new 16-bit-parallel-to-serial converter.
+
+ Args:
+ enable: An object of type Wire. Enables the converter.
+ clear_n: An object of type Wire. Clears all 16 internal registers to 0
+ if its value is 0.
+ load_n: An object of type Wire. The mode select. A value of 0 indicates
+ a parallel load operation, where the values of data_bus are loaded
+ into the internal registers. A value of 1 indicates a shift-right
+ operation.
+ data_bus: An object of type Bus16. The parallel data input.
+ clock: An object of type Wire or Clock. The clock input.
+ output: An object of type Wire. The serial output of the converter.
+ data_bus[15] is outputted first, and data_bus[0] is outputted last.
+
+ Raises:
+ TypeError: If data_bus is not a bus of width 16.
"""
def __init__(
self,
@@ -119,10 +164,10 @@ def __init__(
clock,
output
):
- if len(data_bus.wires) != 16:
+ if len(data_bus) != 16:
raise TypeError(
"Expected bus of width 16, received bus of width {0}.".format(
- len(data_bus.wires)
+ len(data_bus)
)
)
diff --git a/bitwise/storage/REG.py b/bitwise/storage/REG.py
index 4437693..8c80f93 100644
--- a/bitwise/storage/REG.py
+++ b/bitwise/storage/REG.py
@@ -1,8 +1,4 @@
"""
-This module defines classes that simulate storage registers. These registers
-are simply arrays of single-bit flip-flops, and they serve the same purpose as
-flip-flops as well, being used for storing data.
-
The following classes are defined:
Register4
Register8
@@ -16,33 +12,30 @@
class Register4:
- """
- This register has four inputs in a single 4-bit bus, a clock input, and
- four outputs in a single 4-bit bus:
- ________
- input_1 ----| |---- output_1
- input_2 ----| |---- output_2
- input_3 ----| |---- output_3
- input_4 ----| |---- output_4
- clock ----|________|
-
- On the positive edge of clock (i.e. on the clock transition from a 0 value
- to a 1 value), the outputs takes on the value of the inputs, with output_1
- corresponding to input_1, output_2, corresponding to input_2, and so on.
- Otherwise, the outputs hold their current values.
+ """Construct a new 4-bit storage register.
+
+ Args:
+ data_bus: An object of type Bus4. The data input to the register.
+ clock: An object of type Wire or Clock. The clock input to the
+ register.
+ output_bus: An object of type Bus4. The output of the register. Takes
+ on the value of data_bus on the positive edges of clock.
+
+ Raises:
+ TypeError: If either data_bus or output_bus is not a bus of width 4.
"""
def __init__(self, input_bus, clock, output_bus):
- if len(input_bus.wires) != 4:
+ if len(input_bus) != 4:
raise TypeError(
"Expected bus of width 4, received bus of width {0}.".format(
- len(input_bus.wires)
+ len(input_bus)
)
)
- if len(output_bus.wires) != 4:
+ if len(output_bus) != 4:
raise TypeError(
"Expected bus of width 4, received bus of width {0}.".format(
- len(output_bus.wires)
+ len(output_bus)
)
)
@@ -51,44 +44,37 @@ def __init__(self, input_bus, clock, output_bus):
not_3 = Wire()
not_4 = Wire()
- FLOP.DFlipFlop(input_bus.wires[0], clock, output_bus.wires[0], not_1)
- FLOP.DFlipFlop(input_bus.wires[1], clock, output_bus.wires[1], not_2)
- FLOP.DFlipFlop(input_bus.wires[2], clock, output_bus.wires[2], not_3)
- FLOP.DFlipFlop(input_bus.wires[3], clock, output_bus.wires[3], not_4)
+ FLOP.DFlipFlop(input_bus[0], clock, output_bus[0], not_1)
+ FLOP.DFlipFlop(input_bus[1], clock, output_bus[1], not_2)
+ FLOP.DFlipFlop(input_bus[2], clock, output_bus[2], not_3)
+ FLOP.DFlipFlop(input_bus[3], clock, output_bus[3], not_4)
class Register8:
- """
- This register has eight inputs in a single 8-bit bus, a clock input, and
- eight outputs in a single 8-bit bus:
- ________
- input_1 ----| |---- output_1
- input_2 ----| |---- output_2
- input_3 ----| |---- output_3
- input_4 ----| |---- output_4
- input_5 ----| |---- output_5
- input_6 ----| |---- output_6
- input_7 ----| |---- output_7
- input_8 ----| |---- output_8
- clock ----|________|
-
- On the positive edge of clock (i.e. on the clock transition from a 0 value
- to a 1 value), the outputs takes on the value of the inputs, with output_1
- corresponding to input_1, output_2, corresponding to input_2, and so on.
- Otherwise, the outputs hold their current values.
+ """Construct a new 8-bit storage register.
+
+ Args:
+ data_bus: An object of type Bus8. The data input to the register.
+ clock: An object of type Wire or Clock. The clock input to the
+ register.
+ output_bus: An object of type Bus8. The output of the register. Takes
+ on the value of data_bus on the positive edges of clock.
+
+ Raises:
+ TypeError: If either data_bus or output_bus is not a bus of width 8.
"""
def __init__(self, input_bus, clock, output_bus):
- if len(input_bus.wires) != 8:
+ if len(input_bus) != 8:
raise TypeError(
"Expected bus of width 8, received bus of width {0}.".format(
- len(input_bus.wires)
+ len(input_bus)
)
)
- if len(output_bus.wires) != 8:
+ if len(output_bus) != 8:
raise TypeError(
"Expected bus of width 8, received bus of width {0}.".format(
- len(output_bus.wires)
+ len(output_bus)
)
)
@@ -101,56 +87,41 @@ def __init__(self, input_bus, clock, output_bus):
not_7 = Wire()
not_8 = Wire()
- FLOP.DFlipFlop(input_bus.wires[0], clock, output_bus.wires[0], not_1)
- FLOP.DFlipFlop(input_bus.wires[1], clock, output_bus.wires[1], not_2)
- FLOP.DFlipFlop(input_bus.wires[2], clock, output_bus.wires[2], not_3)
- FLOP.DFlipFlop(input_bus.wires[3], clock, output_bus.wires[3], not_4)
- FLOP.DFlipFlop(input_bus.wires[4], clock, output_bus.wires[4], not_5)
- FLOP.DFlipFlop(input_bus.wires[5], clock, output_bus.wires[5], not_6)
- FLOP.DFlipFlop(input_bus.wires[6], clock, output_bus.wires[6], not_7)
- FLOP.DFlipFlop(input_bus.wires[7], clock, output_bus.wires[7], not_8)
+ FLOP.DFlipFlop(input_bus[0], clock, output_bus[0], not_1)
+ FLOP.DFlipFlop(input_bus[1], clock, output_bus[1], not_2)
+ FLOP.DFlipFlop(input_bus[2], clock, output_bus[2], not_3)
+ FLOP.DFlipFlop(input_bus[3], clock, output_bus[3], not_4)
+ FLOP.DFlipFlop(input_bus[4], clock, output_bus[4], not_5)
+ FLOP.DFlipFlop(input_bus[5], clock, output_bus[5], not_6)
+ FLOP.DFlipFlop(input_bus[6], clock, output_bus[6], not_7)
+ FLOP.DFlipFlop(input_bus[7], clock, output_bus[7], not_8)
class Register16:
- """
- This register has sixteen inputs in a single 16-bit bus, a clock input, and
- sixteen outputs in a single 16-bit bus:
- ________
- input_1 ----| |---- output_1
- input_2 ----| |---- output_2
- input_3 ----| |---- output_3
- input_4 ----| |---- output_4
- input_5 ----| |---- output_5
- input_6 ----| |---- output_6
- input_7 ----| |---- output_7
- input_8 ----| |---- output_8
- input_9 ----| |---- output_9
- input_10 ----| |---- output_10
- input_11 ----| |---- output_11
- input_12 ----| |---- output_12
- input_13 ----| |---- output_13
- input_14 ----| |---- output_14
- input_15 ----| |---- output_15
- input_16 ----| |---- output_16
- clock ----|________|
-
- On the positive edge of clock (i.e. on the clock transition from a 0 value
- to a 1 value), the outputs takes on the value of the inputs, with output_1
- corresponding to input_1, output_2, corresponding to input_2, and so on.
- Otherwise, the outputs hold their current values.
+ """Construct a new 16-bit storage register.
+
+ Args:
+ data_bus: An object of type Bus16. The data input to the register.
+ clock: An object of type Wire or Clock. The clock input to the
+ register.
+ output_bus: An object of type Bus16. The output of the register. Takes
+ on the value of data_bus on the positive edges of clock.
+
+ Raises:
+ TypeError: If either data_bus or output_bus is not a bus of width 16.
"""
def __init__(self, input_bus, clock, output_bus):
- if len(input_bus.wires) != 16:
+ if len(input_bus) != 16:
raise TypeError(
"Expected bus of width 16, received bus of width {0}.".format(
- len(input_bus.wires)
+ len(input_bus)
)
)
- if len(output_bus.wires) != 16:
+ if len(output_bus) != 16:
raise TypeError(
"Expected bus of width 16, received bus of width {0}.".format(
- len(output_bus.wires)
+ len(output_bus)
)
)
@@ -171,21 +142,19 @@ def __init__(self, input_bus, clock, output_bus):
not_15 = Wire()
not_16 = Wire()
- output = output_bus.wires
-
- FLOP.DFlipFlop(input_bus.wires[0], clock, output[0], not_1)
- FLOP.DFlipFlop(input_bus.wires[1], clock, output[1], not_2)
- FLOP.DFlipFlop(input_bus.wires[2], clock, output[2], not_3)
- FLOP.DFlipFlop(input_bus.wires[3], clock, output[3], not_4)
- FLOP.DFlipFlop(input_bus.wires[4], clock, output[4], not_5)
- FLOP.DFlipFlop(input_bus.wires[5], clock, output[5], not_6)
- FLOP.DFlipFlop(input_bus.wires[6], clock, output[6], not_7)
- FLOP.DFlipFlop(input_bus.wires[7], clock, output[7], not_8)
- FLOP.DFlipFlop(input_bus.wires[8], clock, output[8], not_9)
- FLOP.DFlipFlop(input_bus.wires[9], clock, output[9], not_10)
- FLOP.DFlipFlop(input_bus.wires[10], clock, output[10], not_11)
- FLOP.DFlipFlop(input_bus.wires[11], clock, output[11], not_12)
- FLOP.DFlipFlop(input_bus.wires[12], clock, output[12], not_13)
- FLOP.DFlipFlop(input_bus.wires[13], clock, output[13], not_14)
- FLOP.DFlipFlop(input_bus.wires[14], clock, output[14], not_15)
- FLOP.DFlipFlop(input_bus.wires[15], clock, output[15], not_16)
+ FLOP.DFlipFlop(input_bus[0], clock, output_bus[0], not_1)
+ FLOP.DFlipFlop(input_bus[1], clock, output_bus[1], not_2)
+ FLOP.DFlipFlop(input_bus[2], clock, output_bus[2], not_3)
+ FLOP.DFlipFlop(input_bus[3], clock, output_bus[3], not_4)
+ FLOP.DFlipFlop(input_bus[4], clock, output_bus[4], not_5)
+ FLOP.DFlipFlop(input_bus[5], clock, output_bus[5], not_6)
+ FLOP.DFlipFlop(input_bus[6], clock, output_bus[6], not_7)
+ FLOP.DFlipFlop(input_bus[7], clock, output_bus[7], not_8)
+ FLOP.DFlipFlop(input_bus[8], clock, output_bus[8], not_9)
+ FLOP.DFlipFlop(input_bus[9], clock, output_bus[9], not_10)
+ FLOP.DFlipFlop(input_bus[10], clock, output_bus[10], not_11)
+ FLOP.DFlipFlop(input_bus[11], clock, output_bus[11], not_12)
+ FLOP.DFlipFlop(input_bus[12], clock, output_bus[12], not_13)
+ FLOP.DFlipFlop(input_bus[13], clock, output_bus[13], not_14)
+ FLOP.DFlipFlop(input_bus[14], clock, output_bus[14], not_15)
+ FLOP.DFlipFlop(input_bus[15], clock, output_bus[15], not_16)
diff --git a/bitwise/storage/SHIFT.py b/bitwise/storage/SHIFT.py
index 0720e05..17dc9b2 100644
--- a/bitwise/storage/SHIFT.py
+++ b/bitwise/storage/SHIFT.py
@@ -17,8 +17,28 @@
class ShiftRegister4:
- """
+ """Construct a new 4-bit shift register.
+
+ Args:
+ enable: An object of type Wire. Enables the shift register.
+ clear_n: An object of type Wire. Clears output_bus and output_serial to
+ 0 if its value is 1.
+ shift_load: An object of type Wire. The mode select. A value of 0
+ indicates a parallel load operation, where output_bus takes on the
+ value of data_bus. A value of 1 indicates a shift-right operation,
+ where output_bus[3] takes on the value of output_bus[2],
+ output_bus[2] takes on the value of output_bus[1], and so on;
+ output_bus[0] takes on the value of data_serial.
+ data_bus: An object of type Bus4. The parallel data input.
+ data_serial. An object of type Wire. The serial data input.
+ clock. An object of type Wire or Clock. The clock input to the shift
+ register.
+ output_bus. An object of type Bus4. The parallel data output.
+ output_serial. An object of type Wire. The serial data output.
+ Identical to output_bus[3].
+ Raises:
+ TypeError: If either data_bus or output_bus is not a bus of width 4.
"""
def __init__(
self,
@@ -31,17 +51,17 @@ def __init__(
output_bus,
output_s
):
- if len(data_bus.wires) != 4:
+ if len(data_bus) != 4:
raise TypeError(
"Expected bus of width 4, received bus of width {0}.".format(
- len(data_bus.wires)
+ len(data_bus)
)
)
- if len(output_bus.wires) != 4:
+ if len(output_bus) != 4:
raise TypeError(
"Expected bus of width 4, received bus of width {0}.".format(
- len(output_bus.wires)
+ len(output_bus)
)
)
@@ -126,8 +146,28 @@ def __init__(
class ShiftRegister8:
- """
+ """Construct a new 8-bit shift register.
+ Args:
+ enable: An object of type Wire. Enables the shift register.
+ clear_n: An object of type Wire. Clears output_bus and output_serial to
+ 0 if its value is 1.
+ shift_load: An object of type Wire. The mode select. A value of 0
+ indicates a parallel load operation, where output_bus takes on the
+ value of data_bus. A value of 1 indicates a shift-right operation,
+ where output_bus[7] takes on the value of output_bus[6],
+ output_bus[6] takes on the value of output_bus[5], and so on;
+ output_bus[0] takes on the value of data_serial.
+ data_bus: An object of type Bus8. The parallel data input.
+ data_serial. An object of type Wire. The serial data input.
+ clock. An object of type Wire or Clock. The clock input to the shift
+ register.
+ output_bus. An object of type Bus8. The parallel data output.
+ output_serial. An object of type Wire. The serial data output.
+ Identical to output_bus[7].
+
+ Raises:
+ TypeError: If either data_bus or output_bus is not a bus of width 8.
"""
def __init__(
self,
@@ -140,17 +180,17 @@ def __init__(
output_bus,
output_s
):
- if len(data_bus.wires) != 8:
+ if len(data_bus) != 8:
raise TypeError(
"Expected bus of width 8, received bus of width {0}.".format(
- len(data_bus.wires)
+ len(data_bus)
)
)
- if len(output_bus.wires) != 8:
+ if len(output_bus) != 8:
raise TypeError(
"Expected bus of width 8, received bus of width {0}.".format(
- len(output_bus.wires)
+ len(output_bus)
)
)
@@ -302,8 +342,28 @@ def __init__(
class ShiftRegister16:
- """
+ """Construct a new 16-bit shift register.
+
+ Args:
+ enable: An object of type Wire. Enables the shift register.
+ clear_n: An object of type Wire. Clears output_bus and output_serial to
+ 0 if its value is 1.
+ shift_load: An object of type Wire. The mode select. A value of 0
+ indicates a parallel load operation, where output_bus takes on the
+ value of data_bus. A value of 1 indicates a shift-right operation,
+ where output_bus[15] takes on the value of output_bus[14],
+ output_bus[14] takes on the value of output_bus[13], and so on;
+ output_bus[0] takes on the value of data_serial.
+ data_bus: An object of type Bus16. The parallel data input.
+ data_serial. An object of type Wire. The serial data input.
+ clock. An object of type Wire or Clock. The clock input to the shift
+ register.
+ output_bus. An object of type Bus16. The parallel data output.
+ output_serial. An object of type Wire. The serial data output.
+ Identical to output_bus[15].
+ Raises:
+ TypeError: If either data_bus or output_bus is not a bus of width 16.
"""
def __init__(
self,
@@ -316,17 +376,17 @@ def __init__(
output_bus,
output_s
):
- if len(data_bus.wires) != 16:
+ if len(data_bus) != 16:
raise TypeError(
"Expected bus of width 16, received bus of width {0}.".format(
- len(data_bus.wires)
+ len(data_bus)
)
)
- if len(output_bus.wires) != 16:
+ if len(output_bus) != 16:
raise TypeError(
"Expected bus of width 16, received bus of width {0}.".format(
- len(output_bus.wires)
+ len(output_bus)
)
)
diff --git a/bitwise/signal/SIPO.py b/bitwise/storage/SIPO.py
similarity index 57%
rename from bitwise/signal/SIPO.py
rename to bitwise/storage/SIPO.py
index ff9d0e5..b0ba305 100644
--- a/bitwise/signal/SIPO.py
+++ b/bitwise/storage/SIPO.py
@@ -15,14 +15,26 @@
class SerialToParallelConverter1To4:
- """
-
+ """Construct a new serial-to-4-bit-parallel converter.
+
+ Args:
+ enable: An object of type Wire. Enables the converter.
+ clear_n: An object of type Wire. Clears all 4 internal registers to 0
+ if its value is 0.
+ data: An object of type Wire. The serial data input.
+ clock: An object of type Wire or Clock. The clock input.
+ output_bus: An object of type Bus4. The parallel output of the
+ converter. output[0] corresponds to the most recent serial data
+ input.
+
+ Raises:
+ TypeError: If output_bus is not a bus of width 4.
"""
def __init__(self, enable, reset_n, data, clock, output_bus):
- if len(output_bus.wires) != 4:
+ if len(output_bus) != 4:
raise TypeError(
"Expected bus of width 4, received bus of width {0}.".format(
- len(output_bus.wires)
+ len(output_bus)
)
)
@@ -51,14 +63,26 @@ def __init__(self, enable, reset_n, data, clock, output_bus):
class SerialToParallelConverter1To8:
- """
-
+ """Construct a new serial-to-8-bit-parallel converter.
+
+ Args:
+ enable: An object of type Wire. Enables the converter.
+ clear_n: An object of type Wire. Clears all 8 internal registers to 0
+ if its value is 0.
+ data: An object of type Wire. The serial data input.
+ clock: An object of type Wire or Clock. The clock input.
+ output_bus: An object of type Bus8. The parallel output of the
+ converter. output[0] corresponds to the most recent serial data
+ input.
+
+ Raises:
+ TypeError: If output_bus is not a bus of width 8.
"""
def __init__(self, enable, reset_n, data, clock, output_bus):
- if len(output_bus.wires) != 8:
+ if len(output_bus) != 8:
raise TypeError(
"Expected bus of width 8, received bus of width {0}.".format(
- len(output_bus.wires)
+ len(output_bus)
)
)
@@ -91,14 +115,26 @@ def __init__(self, enable, reset_n, data, clock, output_bus):
class SerialToParallelConverter1To16:
- """
-
+ """Construct a new serial-to-16-bit-parallel converter.
+
+ Args:
+ enable: An object of type Wire. Enables the converter.
+ clear_n: An object of type Wire. Clears all 16 internal registers to 0
+ if its value is 0.
+ data: An object of type Wire. The serial data input.
+ clock: An object of type Wire or Clock. The clock input.
+ output_bus: An object of type Bus16. The parallel output of the
+ converter. output[0] corresponds to the most recent serial data
+ input.
+
+ Raises:
+ TypeError: If output_bus is not a bus of width 16.
"""
def __init__(self, enable, reset_n, data, clock, output_bus):
- if len(output_bus.wires) != 16:
+ if len(output_bus) != 16:
raise TypeError(
"Expected bus of width 16, received bus of width {0}.".format(
- len(output_bus.wires)
+ len(output_bus)
)
)
diff --git a/bitwise/storage/__init__.py b/bitwise/storage/__init__.py
index dec80fd..79a024e 100644
--- a/bitwise/storage/__init__.py
+++ b/bitwise/storage/__init__.py
@@ -1,3 +1,5 @@
from .FLOP import *
+from .PISO import *
from .REG import *
from .SHIFT import *
+from .SIPO import *
diff --git a/docs/_build/doctrees/api.doctree b/docs/_build/doctrees/api.doctree
index b8330a2..2f76a4e 100644
Binary files a/docs/_build/doctrees/api.doctree and b/docs/_build/doctrees/api.doctree differ
diff --git a/docs/_build/doctrees/changelog.doctree b/docs/_build/doctrees/changelog.doctree
new file mode 100644
index 0000000..839b536
Binary files /dev/null and b/docs/_build/doctrees/changelog.doctree differ
diff --git a/docs/_build/doctrees/environment.pickle b/docs/_build/doctrees/environment.pickle
index 580ba48..679f51b 100644
Binary files a/docs/_build/doctrees/environment.pickle and b/docs/_build/doctrees/environment.pickle differ
diff --git a/docs/_build/doctrees/index.doctree b/docs/_build/doctrees/index.doctree
index 38d0d84..24ddbb2 100644
Binary files a/docs/_build/doctrees/index.doctree and b/docs/_build/doctrees/index.doctree differ
diff --git a/docs/_build/doctrees/signal.doctree b/docs/_build/doctrees/signal.doctree
index f1ae094..e6acddd 100644
Binary files a/docs/_build/doctrees/signal.doctree and b/docs/_build/doctrees/signal.doctree differ
diff --git a/docs/_build/doctrees/storage.doctree b/docs/_build/doctrees/storage.doctree
index 8690209..17424c7 100644
Binary files a/docs/_build/doctrees/storage.doctree and b/docs/_build/doctrees/storage.doctree differ
diff --git a/docs/_build/html/.buildinfo b/docs/_build/html/.buildinfo
index 91bce97..715c16b 100644
--- a/docs/_build/html/.buildinfo
+++ b/docs/_build/html/.buildinfo
@@ -1,4 +1,4 @@
# Sphinx build info version 1
# This file hashes the configuration used when building these files. When it is not found, a full rebuild will be done.
-config: 40b3bb7ac50d6bdd9837b581875ce877
+config: a2f2ebb05638847ca43a223a4bebb03f
tags: 645f666f9bcd5a90fca523b33c5a78b7
diff --git a/docs/_build/html/_images/DFlipFlop.svg b/docs/_build/html/_images/DFlipFlop.svg
new file mode 100644
index 0000000..05bd7cc
--- /dev/null
+++ b/docs/_build/html/_images/DFlipFlop.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/DFlipFlopPresetClear.svg b/docs/_build/html/_images/DFlipFlopPresetClear.svg
new file mode 100644
index 0000000..ffa23ae
--- /dev/null
+++ b/docs/_build/html/_images/DFlipFlopPresetClear.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/GatedDLatch.svg b/docs/_build/html/_images/GatedDLatch.svg
new file mode 100644
index 0000000..db90007
--- /dev/null
+++ b/docs/_build/html/_images/GatedDLatch.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/GatedSRLatch.svg b/docs/_build/html/_images/GatedSRLatch.svg
new file mode 100644
index 0000000..41e48e4
--- /dev/null
+++ b/docs/_build/html/_images/GatedSRLatch.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/JKFlipFlop.svg b/docs/_build/html/_images/JKFlipFlop.svg
new file mode 100644
index 0000000..37bef4c
--- /dev/null
+++ b/docs/_build/html/_images/JKFlipFlop.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/JKFlipFlopPresetClear.svg b/docs/_build/html/_images/JKFlipFlopPresetClear.svg
new file mode 100644
index 0000000..455776a
--- /dev/null
+++ b/docs/_build/html/_images/JKFlipFlopPresetClear.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/ParallelToSerialConverter16To1.svg b/docs/_build/html/_images/ParallelToSerialConverter16To1.svg
new file mode 100644
index 0000000..5211248
--- /dev/null
+++ b/docs/_build/html/_images/ParallelToSerialConverter16To1.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/ParallelToSerialConverter4To1.svg b/docs/_build/html/_images/ParallelToSerialConverter4To1.svg
new file mode 100644
index 0000000..15639e8
--- /dev/null
+++ b/docs/_build/html/_images/ParallelToSerialConverter4To1.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/ParallelToSerialConverter8To1.svg b/docs/_build/html/_images/ParallelToSerialConverter8To1.svg
new file mode 100644
index 0000000..ed18105
--- /dev/null
+++ b/docs/_build/html/_images/ParallelToSerialConverter8To1.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/Register16.svg b/docs/_build/html/_images/Register16.svg
new file mode 100644
index 0000000..932632a
--- /dev/null
+++ b/docs/_build/html/_images/Register16.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/Register4.svg b/docs/_build/html/_images/Register4.svg
new file mode 100644
index 0000000..4386d80
--- /dev/null
+++ b/docs/_build/html/_images/Register4.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/Register8.svg b/docs/_build/html/_images/Register8.svg
new file mode 100644
index 0000000..23757db
--- /dev/null
+++ b/docs/_build/html/_images/Register8.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/SRLatch.svg b/docs/_build/html/_images/SRLatch.svg
new file mode 100644
index 0000000..6221399
--- /dev/null
+++ b/docs/_build/html/_images/SRLatch.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/SerialToParallelConverter1To16.svg b/docs/_build/html/_images/SerialToParallelConverter1To16.svg
new file mode 100644
index 0000000..0576e1e
--- /dev/null
+++ b/docs/_build/html/_images/SerialToParallelConverter1To16.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/SerialToParallelConverter1To4.svg b/docs/_build/html/_images/SerialToParallelConverter1To4.svg
new file mode 100644
index 0000000..542fdc9
--- /dev/null
+++ b/docs/_build/html/_images/SerialToParallelConverter1To4.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/SerialToParallelConverter1To8.svg b/docs/_build/html/_images/SerialToParallelConverter1To8.svg
new file mode 100644
index 0000000..ea70b6a
--- /dev/null
+++ b/docs/_build/html/_images/SerialToParallelConverter1To8.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/ShiftRegister16.svg b/docs/_build/html/_images/ShiftRegister16.svg
new file mode 100644
index 0000000..fa9f6bb
--- /dev/null
+++ b/docs/_build/html/_images/ShiftRegister16.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/ShiftRegister4.svg b/docs/_build/html/_images/ShiftRegister4.svg
new file mode 100644
index 0000000..a22837a
--- /dev/null
+++ b/docs/_build/html/_images/ShiftRegister4.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/ShiftRegister8.svg b/docs/_build/html/_images/ShiftRegister8.svg
new file mode 100644
index 0000000..13ae06e
--- /dev/null
+++ b/docs/_build/html/_images/ShiftRegister8.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/TFlipFlop.svg b/docs/_build/html/_images/TFlipFlop.svg
new file mode 100644
index 0000000..d499c37
--- /dev/null
+++ b/docs/_build/html/_images/TFlipFlop.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_images/TFlipFlopPresetClear.svg b/docs/_build/html/_images/TFlipFlopPresetClear.svg
new file mode 100644
index 0000000..8b56ef5
--- /dev/null
+++ b/docs/_build/html/_images/TFlipFlopPresetClear.svg
@@ -0,0 +1,2 @@
+
+
\ No newline at end of file
diff --git a/docs/_build/html/_sources/api.rst.txt b/docs/_build/html/_sources/api.rst.txt
index 16bf3bc..024fc36 100644
--- a/docs/_build/html/_sources/api.rst.txt
+++ b/docs/_build/html/_sources/api.rst.txt
@@ -69,6 +69,27 @@ API Documentation
:doc:`storage`
==============
+* :ref:`DFlipFlop`
+* :ref:`DFlipFlopPresetClear`
+* :ref:`GatedDLatch`
+* :ref:`GatedSRLatch`
+* :ref:`JKFlipFlop`
+* :ref:`JKFlipFlopPresetClear`
+* :ref:`ParallelToSerialConverter4To1`
+* :ref:`ParallelToSerialConverter8To1`
+* :ref:`ParallelToSerialConverter16To1`
+* :ref:`SerialToParallelConverter1To4`
+* :ref:`SerialToParallelConverter1To8`
+* :ref:`SerialToParallelConverter1To16`
+* :ref:`Register4`
+* :ref:`Register8`
+* :ref:`Register16`
+* :ref:`ShiftRegister4`
+* :ref:`ShiftRegister8`
+* :ref:`ShiftRegister16`
+* :ref:`SRLatch`
+* :ref:`TFlipFlop`
+* :ref:`TFlipFlopPresetClear`
:doc:`wire`
===========
diff --git a/docs/_build/html/_sources/changelog.rst.txt b/docs/_build/html/_sources/changelog.rst.txt
new file mode 100644
index 0000000..0281a3a
--- /dev/null
+++ b/docs/_build/html/_sources/changelog.rst.txt
@@ -0,0 +1,49 @@
+:tocdepth: 2
+
+=========
+Changelog
+=========
+
+
+Unreleased
+==========
+
+Added
+-----
+* Shift register classes to storage subpackage
+ * ``ShiftRegister4``
+ * ``ShiftRegister8``
+ * ``ShiftRegister16``
+
+* Parallel-to-serial converter classes to signal subpackage
+ * ``ParallelToSerialConverter4To1``
+ * ``ParallelToSerialConverter8To1``
+ * ``ParallelToSerialConverter16To1``
+
+* Serial-to-parallel converter classes to signal subpackage
+ * ``SerialToParallelConverter1To4``
+ * ``SerialToParallelConverter1To8``
+ * ``SerialToParallelConverter1To16``
+
+* Buffer class to gate subpackage
+* ``__getitem__()`` and ``__len__()`` methods to ``Bus4``, ``Bus8``, ``Bus16``, and ``BusSevenSegmentDisplay`` classes
+
+Changed
+-------
+* Rewrote docstrings for all classes
+* Misc improvements
+
+
+v0.1.1 - 2018-10-17
+===================
+
+Added
+-----
+* Storage register classes to storage subpackage
+ * ``Register4``
+ * ``Register8``
+ * ``Register16``
+
+Changed
+-------
+* Misc improvements
diff --git a/docs/_build/html/_sources/index.rst.txt b/docs/_build/html/_sources/index.rst.txt
index c377826..4d8ccee 100644
--- a/docs/_build/html/_sources/index.rst.txt
+++ b/docs/_build/html/_sources/index.rst.txt
@@ -1,3 +1,17 @@
+.. toctree::
+ :hidden:
+
+ api
+ arithmetic
+ changelog
+ gate
+ install
+ logic
+ signal
+ storage
+ wire
+
+
=============
About Bitwise
=============
@@ -40,7 +54,7 @@ Interacting with it in a Python session::
In [2]: b.value = 0
- In [3]: sum.value
+ In [3]: sum_.value
Out[3]: 0
In [4]: carry_out.value
@@ -48,7 +62,7 @@ Interacting with it in a Python session::
In [5]: a.value = 1
- In [6]: sum.value
+ In [6]: sum_.value
Out[6]: 1
In [7]: carry_out.value
@@ -56,7 +70,7 @@ Interacting with it in a Python session::
In [8]: b.value = 1
- In [9]: sum.value
+ In [9]: sum_.value
Out[9]: 0
In [10]: carry_out.value
diff --git a/docs/_build/html/_sources/signal.rst.txt b/docs/_build/html/_sources/signal.rst.txt
index 7664be0..5184dde 100644
--- a/docs/_build/html/_sources/signal.rst.txt
+++ b/docs/_build/html/_sources/signal.rst.txt
@@ -578,7 +578,7 @@ Args:
* ``select``: An object of type ``Wire``. The select input.
* ``input_1``: An object of type ``Wire``. The first data input to the multiplexer.
* ``input_2``: An object of type ``Wire``. The second data input to the multiplexer.
-* ``output``: An object of type ``Wire``. The output of the multiplexer, which takes on the value of ``input_1`` for a 1 select and ``input_2`` for a 0 select.
+* ``output``: An object of type ``Wire``. The output of the multiplexer. Takes on the value of ``input_1`` for a 1 select and ``input_2`` for a 0 select.
.. _Multiplexer4To1:
@@ -617,7 +617,7 @@ Args:
* ``select_1``: An object of type ``Wire``. The most significant bit of the select input.
* ``select_2``: An object of type ``Wire``. The least significant bit of the select input.
* ``input_bus``: An object of type ``Bus4``. The data input to the multiplexer.
-* ``output``: An object of type ``Wire``. The output of the multiplexer, which takes on the value of ``input_bus[0]`` for a (1, 1) select and ``input_bus[3]`` for a (0, 0) select.
+* ``output``: An object of type ``Wire``. The output of the multiplexer. Takes on the value of ``input_bus[0]`` for a (1, 1) select and ``input_bus[3]`` for a (0, 0) select.
Raises:
~~~~~~~
@@ -662,7 +662,7 @@ Args:
* ``select_2``: An object of type ``Wire``.
* ``select_3``: An object of type ``Wire``. The least significant bit of the select input.
* ``input_bus``: An object of type ``Bus8``. The data input to the multiplexer.
-* ``output``: An object of type ``Wire``. The output of the multiplexer, which takes on the value of ``input_bus[0]`` for a (1, 1, 1) select and ``input_bus[7]`` for a (0, 0, 0) select.
+* ``output``: An object of type ``Wire``. The output of the multiplexer. Takes on the value of ``input_bus[0]`` for a (1, 1, 1) select and ``input_bus[7]`` for a (0, 0, 0) select.
Raises:
~~~~~~~
@@ -703,7 +703,7 @@ Args:
* ``enable``: An object of type ``Wire``. Enables the multiplexer.
* ``select_bus``: An object of type ``Bus4``. ``select_bus[0]`` and ``select_bus[3]`` are the most and least significant bit, respectively.
* ``input_bus``: An object of type ``Bus16``. The data input to the multiplexer.
-* ``output``: An object of type ``Wire``. The output of the multiplexer, which takes on the value of ``input_bus[0]`` for a (1, 1, 1, 1) select and ``input_bus[15]`` for a (0, 0, 0, 0) select.
+* ``output``: An object of type ``Wire``. The output of the multiplexer. Takes on the value of ``input_bus[0]`` for a (1, 1, 1, 1) select and ``input_bus[15]`` for a (0, 0, 0, 0) select.
Raises:
~~~~~~~
diff --git a/docs/_build/html/_sources/storage.rst.txt b/docs/_build/html/_sources/storage.rst.txt
index e318e4e..cdcb1ff 100644
--- a/docs/_build/html/_sources/storage.rst.txt
+++ b/docs/_build/html/_sources/storage.rst.txt
@@ -3,3 +3,882 @@
=======
Storage
=======
+
+
+.. _DFlipFlop:
+
+DFlipFlop
+=========
+
+Class ``bw.storage.DFlipFlop``
+------------------------------
+
+.. image:: images/schematics/storage/DFlipFlop.svg
+ :width: 360px
+
+Defined in `bitwise/storage/FLOP.py `_.
+
+Positive edge-triggered `D flip-flop `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ data,
+ clock,
+ output,
+ output_not
+ )
+
+Construct a new positive edge-triggered D flip-flop.
+
+Args:
+~~~~~
+* ``data``: An object of type ``Wire``. The data input to the flip-flop.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the flip-flop.
+* ``output``: An object of type ``Wire``. The output of the flip-flop. Takes on the value of ``data`` on the positive edges of ``clock``.
+* ``output_not``: An object of type ``Wire``. The complemented form of ``output``.
+
+
+.. _DFlipFlopPresetClear:
+
+DFlipFlopPresetClear
+====================
+
+Class ``bw.storage.DFlipFlopPresetClear``
+-----------------------------------------
+
+.. image:: images/schematics/storage/DFlipFlopPresetClear.svg
+ :width: 360px
+
+Defined in `bitwise/storage/FLOP.py `_.
+
+Positive edge-triggered `D flip-flop `_ with asynchronous active low preset and clear.
+
+__init__
+--------
+
+::
+
+ __init__(
+ data,
+ preset_n,
+ clear_n,
+ clock,
+ output,
+ output_not
+ )
+
+Construct a new positive edge-triggered D flip-flop with preset/clear capabilities.
+
+Args:
+~~~~~
+* ``data``: An object of type ``Wire``. The data input to the flip-flop.
+* ``preset_n``: An object of type ``Wire``. Presets ``output`` to 1 and ``output_not`` to 0 if its value is 0.
+* ``clear_n``: An object of type ``Wire``. Clears ``output`` to 0 and ``output_not`` to 1 if its value is 0.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the flip-flop.
+* ``output``: An object of type ``Wire``. The output of the flip-flop. Takes on the value of ``data`` on the positive edges of ``clock``.
+* ``output_not``: An object of type ``Wire``. The complemented form of ``output``.
+
+
+.. _GatedDLatch:
+
+GatedDLatch
+===========
+
+Class ``bw.storage.GatedDLatch``
+--------------------------------
+
+.. image:: images/schematics/storage/GatedDLatch.svg
+ :width: 360px
+
+Defined in `bitwise/storage/FLOP.py `_.
+
+`Gated D latch `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ data,
+ clock,
+ output,
+ output_not
+ )
+
+Construct a new gated D latch.
+
+Args:
+~~~~~
+* ``data``: An object of type ``Wire``. The data input to the latch.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the latch.
+* ``output``: An object of type ``Wire``. The output of the latch. Takes on the value of ``data`` if the value of ``clock`` is 1.
+* ``output_not``: An object of type ``Wire``. The complemented form of ``output``.
+
+
+.. _GatedSRLatch:
+
+GatedSRLatch
+============
+
+Class ``bw.storage.GatedSRLatch``
+---------------------------------
+
+.. image:: images/schematics/storage/GatedSRLatch.svg
+ :width: 360px
+
+Defined in `bitwise/storage/FLOP.py `_.
+
+`Gated SR latch `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ set_,
+ reset,
+ clock,
+ output,
+ output_not
+ )
+
+Construct a new gated SR latch.
+
+Args:
+~~~~~
+* ``set_``: An object of type ``Wire``. The set input to the latch.
+* ``reset``: An object of type ``Wire``. The reset input to the latch.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the latch.
+* ``output``: An object of type ``Wire``. The output of the latch. When the value of ``clock`` is 1, takes on the value of 1 if the value of ``set`` is 1 and the value of 0 if the value of ``reset`` is 1.
+* ``output_not``: An object of type ``Wire``. The complemented form of ``output``.
+
+
+.. _JKFlipFlop:
+
+JKFlipFlop
+==========
+
+Class ``bw.storage.JKFlipFlop``
+-------------------------------
+
+.. image:: images/schematics/storage/JKFlipFlop.svg
+ :width: 360px
+
+Defined in `bitwise/storage/FLOP.py `_.
+
+Positive edge-triggered `JK flip-flop `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ J,
+ K,
+ clock,
+ output,
+ output_not
+ )
+
+Construct a new positive edge-triggered JK flip-flop.
+
+Args:
+~~~~~
+* ``J``: An object of type ``Wire``. The J input to the flip-flop.
+* ``K``: An object of type ``Wire``. The K input to the flip-flop.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the flip-flop.
+* ``output``: An object of type ``Wire``. The output of the flip-flop. On the positive edges of ``clock``, takes on the value of 1 if the value of ``J`` is 1, takes on the value of 0 if the value of ``K`` is 1, and toggles its value if both ``J`` and ``K`` have value 1.
+* ``output_not``: An object of type ``Wire``. The complemented form of ``output``.
+
+
+.. _JKFlipFlopPresetClear:
+
+JKFlipFlopPresetClear
+=====================
+
+Class ``bw.storage.JKFlipFlopPresetClear``
+------------------------------------------
+
+.. image:: images/schematics/storage/JKFlipFlopPresetClear.svg
+ :width: 360px
+
+Defined in `bitwise/storage/FLOP.py `_.
+
+Positive edge-triggered `JK flip-flop `_ with asynchronous active low preset and clear.
+
+__init__
+--------
+
+::
+
+ __init__(
+ J,
+ K,
+ preset_n,
+ clear_n,
+ clock,
+ output,
+ output_not
+ )
+
+Construct a new positive edge-triggered JK flip-flop with preset/clear capabilities.
+
+Args:
+~~~~~
+* ``J``: An object of type ``Wire``. The J input to the flip-flop.
+* ``K``: An object of type ``Wire``. The K input to the flip-flop.
+* ``preset_n``: An object of type ``Wire``. Presets ``output`` to 1 and ``output_not`` to 0 if its value is 0.
+* ``clear_n``: An object of type ``Wire``. Clears ``output`` to 0 and ``output_not`` to 1 if its value is 0.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the flip-flop.
+* ``output``: An object of type ``Wire``. The output of the flip-flop. On the positive edges of ``clock``, takes on the value of 1 if the value of ``J`` is 1, takes on the value of 0 if the value of ``K`` is 1, and toggles its value if both ``J`` and ``K`` have value 1.
+* ``output_not``: An object of type ``Wire``. The complemented form of ``output``.
+
+
+.. _ParallelToSerialConverter4To1:
+
+ParallelToSerialConverter4To1
+=============================
+
+Class ``bw.signal.ParallelToSerialConverter4To1``
+-------------------------------------------------
+
+.. image:: images/schematics/storage/ParallelToSerialConverter4To1.svg
+ :width: 600px
+
+Defined in `bitwise/storage/PISO.py `_.
+
+`4-bit-parallel-to-serial converter `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ enable,
+ clear_n,
+ load_n,
+ data_bus,
+ clock,
+ output
+ )
+
+Construct a new 4-bit-parallel-to-serial converter.
+
+Args:
+~~~~~
+* ``enable``: An object of type ``Wire``. Enables the converter.
+* ``clear_n``: An object of type ``Wire``. Clears all 4 internal registers to 0 if its value is 0.
+* ``load_n``: An object of type ``Wire``. The mode select. A value of 0 indicates a parallel load operation, where the values of ``data_bus`` are loaded into the internal registers. A value of 1 indicates a shift-right operation.
+* ``data_bus``: An object of type ``Bus4``. The parallel data input.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input.
+* ``output``: An object of type ``Wire``. The serial output of the converter. ``data_bus[3]`` is outputted first, and ``data_bus[0]`` is outputted last.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If ``data_bus`` is not a bus of width 4.
+
+
+.. _ParallelToSerialConverter8To1:
+
+ParallelToSerialConverter8To1
+=============================
+
+Class ``bw.signal.ParallelToSerialConverter8To1``
+-------------------------------------------------
+
+.. image:: images/schematics/storage/ParallelToSerialConverter8To1.svg
+ :width: 600px
+
+Defined in `bitwise/storage/PISO.py `_.
+
+`8-bit-parallel-to-serial converter `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ enable,
+ clear_n,
+ load_n,
+ data_bus,
+ clock,
+ output
+ )
+
+Construct a new 8-bit-parallel-to-serial converter.
+
+Args:
+~~~~~
+* ``enable``: An object of type ``Wire``. Enables the converter.
+* ``clear_n``: An object of type ``Wire``. Clears all 8 internal registers to 0 if its value is 0.
+* ``load_n``: An object of type ``Wire``. The mode select. A value of 0 indicates a parallel load operation, where the values of ``data_bus`` are loaded into the internal registers. A value of 1 indicates a shift-right operation.
+* ``data_bus``: An object of type ``Bus8``. The parallel data input.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input.
+* ``output``: An object of type ``Wire``. The serial output of the converter. ``data_bus[7]`` is outputted first, and ``data_bus[0]`` is outputted last.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If ``data_bus`` is not a bus of width 8.
+
+
+.. _ParallelToSerialConverter16To1:
+
+ParallelToSerialConverter16To1
+==============================
+
+Class ``bw.signal.ParallelToSerialConverter16To1``
+--------------------------------------------------
+
+.. image:: images/schematics/storage/ParallelToSerialConverter16To1.svg
+ :width: 600px
+
+Defined in `bitwise/storage/PISO.py `_.
+
+`16-bit-parallel-to-serial converter `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ enable,
+ clear_n,
+ load_n,
+ data_bus,
+ clock,
+ output
+ )
+
+Construct a new 16-bit-parallel-to-serial converter.
+
+Args:
+~~~~~
+* ``enable``: An object of type ``Wire``. Enables the converter.
+* ``clear_n``: An object of type ``Wire``. Clears all 16 internal registers to 0 if its value is 0.
+* ``load_n``: An object of type ``Wire``. The mode select. A value of 0 indicates a parallel load operation, where the values of ``data_bus`` are loaded into the internal registers. A value of 1 indicates a shift-right operation.
+* ``data_bus``: An object of type ``Bus16``. The parallel data input.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input.
+* ``output``: An object of type ``Wire``. The serial output of the converter. ``data_bus[15]`` is outputted first, and ``data_bus[0]`` is outputted last.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If ``data_bus`` is not a bus of width 16.
+
+
+.. _Register4:
+
+Register4
+=========
+
+Class ``bw.storage.Register4``
+------------------------------
+
+.. image:: images/schematics/storage/Register4.svg
+ :width: 800px
+
+Defined in `bitwise/storage/REG.py `_.
+
+`4-bit storage register `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ data_bus,
+ clock,
+ output_bus
+ )
+
+Construct a new 4-bit storage register.
+
+Args:
+~~~~~
+* ``data_bus``: An object of type ``Bus4``. The data input to the register.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the register.
+* ``output_bus``: An object of type ``Bus4``. The output of the register. Takes on the value of ``data_bus`` on the positive edges of ``clock``.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If either ``data_bus`` or ``output_bus`` is not a bus of width 4.
+
+
+.. _Register8:
+
+Register8
+=========
+
+Class ``bw.storage.Register8``
+------------------------------
+
+.. image:: images/schematics/storage/Register8.svg
+ :width: 800px
+
+Defined in `bitwise/storage/REG.py `_.
+
+`8-bit storage register `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ data_bus,
+ clock,
+ output_bus
+ )
+
+Construct a new 8-bit storage register.
+
+Args:
+~~~~~
+* ``data_bus``: An object of type ``Bus8``. The data input to the register.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the register.
+* ``output_bus``: An object of type ``Bus8``. The output of the register. Takes on the value of ``data_bus`` on the positive edges of ``clock``.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If either ``data_bus`` or ``output_bus`` is not a bus of width 8.
+
+
+.. _Register16:
+
+Register16
+==========
+
+Class ``bw.storage.Register16``
+-------------------------------
+
+.. image:: images/schematics/storage/Register16.svg
+ :width: 800px
+
+Defined in `bitwise/storage/REG.py `_.
+
+`16-bit storage register `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ data_bus,
+ clock,
+ output_bus
+ )
+
+Construct a new 16-bit storage register.
+
+Args:
+~~~~~
+* ``data_bus``: An object of type ``Bus16``. The data input to the register.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the register.
+* ``output_bus``: An object of type ``Bus16``. The output of the register. Takes on the value of ``data_bus`` on the positive edges of ``clock``.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If either ``data_bus`` or ``output_bus`` is not a bus of width 16.
+
+
+.. _SerialToParallelConverter1To4:
+
+SerialToParallelConverter1To4
+=============================
+
+Class ``bw.storage.SerialToParallelConverter1To4``
+--------------------------------------------------
+
+.. image:: images/schematics/storage/SerialToParallelConverter1To4.svg
+ :width: 600px
+
+Defined in `bitwise/storage/SIPO.py `_.
+
+`Serial-to-4-bit-parallel converter `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ enable,
+ clear_n,
+ data,
+ clock,
+ output_bus
+ )
+
+Construct a new serial-to-4-bit-parallel converter.
+
+Args:
+~~~~~
+* ``enable``: An object of type ``Wire``. Enables the converter.
+* ``clear_n``: An object of type ``Wire``. Clears all 4 internal registers to 0 if its value is 0.
+* ``data``: An object of type ``Wire``. The serial data input.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input.
+* ``output_bus``: An object of type ``Bus4``. The parallel output of the converter. ``output[0]`` corresponds to the most recent serial data input.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If ``output_bus`` is not a bus of width 4.
+
+
+.. _SerialToParallelConverter1To8:
+
+SerialToParallelConverter1To8
+=============================
+
+Class ``bw.storage.SerialToParallelConverter1To8``
+--------------------------------------------------
+
+.. image:: images/schematics/storage/SerialToParallelConverter1To8.svg
+ :width: 600px
+
+Defined in `bitwise/storage/SIPO.py `_.
+
+`Serial-to-8-bit-parallel converter `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ enable,
+ clear_n,
+ data,
+ clock,
+ output_bus
+ )
+
+Construct a new serial-to-8-bit-parallel converter.
+
+Args:
+~~~~~
+* ``enable``: An object of type ``Wire``. Enables the converter.
+* ``clear_n``: An object of type ``Wire``. Clears all 8 internal registers to 0 if its value is 0.
+* ``data``: An object of type ``Wire``. The serial data input.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input.
+* ``output_bus``: An object of type ``Bus8``. The parallel output of the converter. ``output[0]`` corresponds to the most recent serial data input.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If ``output_bus`` is not a bus of width 8.
+
+
+.. _SerialToParallelConverter1To16:
+
+SerialToParallelConverter1To16
+==============================
+
+Class ``bw.storage.SerialToParallelConverter1To16``
+---------------------------------------------------
+
+.. image:: images/schematics/storage/SerialToParallelConverter1To16.svg
+ :width: 600px
+
+Defined in `bitwise/storage/SIPO.py `_.
+
+`Serial-to-16-bit-parallel converter `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ enable,
+ clear_n,
+ data,
+ clock,
+ output_bus
+ )
+
+Construct a new serial-to-16-bit-parallel converter.
+
+Args:
+~~~~~
+* ``enable``: An object of type ``Wire``. Enables the converter.
+* ``clear_n``: An object of type ``Wire``. Clears all 16 internal registers to 0 if its value is 0.
+* ``data``: An object of type ``Wire``. The serial data input.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input.
+* ``output_bus``: An object of type ``Bus16``. The parallel output of the converter. ``output[0]`` corresponds to the most recent serial data input.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If ``output_bus`` is not a bus of width 16.
+
+
+.. _ShiftRegister4:
+
+ShiftRegister4
+==============
+
+Class ``bw.storage.ShiftRegister4``
+-----------------------------------
+
+.. image:: images/schematics/storage/ShiftRegister4.svg
+ :width: 800px
+
+Defined in `bitwise/storage/SHIFT.py `_.
+
+`4-bit shift register `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ enable,
+ clear_n,
+ shift_load,
+ data_bus,
+ data_serial,
+ clock,
+ output_bus,
+ output_serial
+ )
+
+Construct a new 4-bit shift register.
+
+Args:
+~~~~~
+* ``enable``: An object of type ``Wire``. Enables the shift register.
+* ``clear_n``: An object of type ``Wire``. Clears ``output_bus`` and ``output_serial`` to 0 if its value is 1.
+* ``shift_load``: An object of type ``Wire``. The mode select. A value of 0 indicates a parallel load operation, where ``output_bus`` takes on the value of ``data_bus``. A value of 1 indicates a shift-right operation, where ``output_bus[3]`` takes on the value of ``output_bus[2]``, ``output_bus[2]`` takes on the value of ``output_bus[1]``, and so on; ``output_bus[0]`` takes on the value of ``data_serial``.
+* ``data_bus``: An object of type ``Bus4``. The parallel data input.
+* ``data_serial``. An object of type ``Wire``. The serial data input.
+* ``clock``. An object of type ``Wire`` or ``Clock``. The clock input to the shift register.
+* ``output_bus``. An object of type ``Bus4``. The parallel data output.
+* ``output_serial``. An object of type ``Wire``. The serial data output. Identical to ``output_bus[3]``.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If either ``data_bus`` or ``output_bus`` is not a bus of width 4.
+
+
+.. _ShiftRegister8:
+
+ShiftRegister8
+==============
+
+Class ``bw.storage.ShiftRegister8``
+-----------------------------------
+
+.. image:: images/schematics/storage/ShiftRegister8.svg
+ :width: 800px
+
+Defined in `bitwise/storage/SHIFT.py `_.
+
+`8-bit shift register `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ enable,
+ clear_n,
+ shift_load,
+ data_bus,
+ data_serial,
+ clock,
+ output_bus,
+ output_serial
+ )
+
+Construct a new 8-bit shift register.
+
+Args:
+~~~~~
+* ``enable``: An object of type ``Wire``. Enables the shift register.
+* ``clear_n``: An object of type ``Wire``. Clears ``output_bus`` and ``output_serial`` to 0 if its value is 1.
+* ``shift_load``: An object of type ``Wire``. The mode select. A value of 0 indicates a parallel load operation, where ``output_bus`` takes on the value of ``data_bus``. A value of 1 indicates a shift-right operation, where ``output_bus[7]`` takes on the value of ``output_bus[6]``, ``output_bus[6]`` takes on the value of ``output_bus[5]``, and so on; ``output_bus[0]`` takes on the value of ``data_serial``.
+* ``data_bus``: An object of type ``Bus8``. The parallel data input.
+* ``data_serial``. An object of type ``Wire``. The serial data input.
+* ``clock``. An object of type ``Wire`` or ``Clock``. The clock input to the shift register.
+* ``output_bus``. An object of type ``Bus8``. The parallel data output.
+* ``output_serial``. An object of type ``Wire``. The serial data output. Identical to ``output_bus[7]``.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If either ``data_bus`` or ``output_bus`` is not a bus of width 8.
+
+
+.. _ShiftRegister16:
+
+ShiftRegister16
+===============
+
+Class ``bw.storage.ShiftRegister16``
+------------------------------------
+
+.. image:: images/schematics/storage/ShiftRegister16.svg
+ :width: 800px
+
+Defined in `bitwise/storage/SHIFT.py `_.
+
+`16-bit shift register `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ enable,
+ clear_n,
+ shift_load,
+ data_bus,
+ data_serial,
+ clock,
+ output_bus,
+ output_serial
+ )
+
+Construct a new 16-bit shift register.
+
+Args:
+~~~~~
+* ``enable``: An object of type ``Wire``. Enables the shift register.
+* ``clear_n``: An object of type ``Wire``. Clears ``output_bus`` and ``output_serial`` to 0 if its value is 1.
+* ``shift_load``: An object of type ``Wire``. The mode select. A value of 0 indicates a parallel load operation, where ``output_bus`` takes on the value of ``data_bus``. A value of 1 indicates a shift-right operation, where ``output_bus[15]`` takes on the value of ``output_bus[14]``, ``output_bus[14]`` takes on the value of ``output_bus[13]``, and so on; ``output_bus[0]`` takes on the value of ``data_serial``.
+* ``data_bus``: An object of type ``Bus16``. The parallel data input.
+* ``data_serial``. An object of type ``Wire``. The serial data input.
+* ``clock``. An object of type ``Wire`` or ``Clock``. The clock input to the shift register.
+* ``output_bus``. An object of type ``Bus16``. The parallel data output.
+* ``output_serial``. An object of type ``Wire``. The serial data output. Identical to ``output_bus[15]``.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If either ``data_bus`` or ``output_bus`` is not a bus of width 16.
+
+
+.. _SRLatch:
+
+SRLatch
+=======
+
+Class ``bw.storage.SRLatch``
+----------------------------
+
+.. image:: images/schematics/storage/SRLatch.svg
+ :width: 360px
+
+Defined in `bitwise/storage/FLOP.py `_.
+
+`SR latch `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ set_,
+ reset,
+ output,
+ output_not
+ )
+
+Construct a new SR latch.
+
+Args:
+~~~~~
+* ``set_``: An object of type ``Wire``. The set input to the latch.
+* ``reset``: An object of type ``Wire``. The reset input to the latch.
+* ``output``: An object of type ``Wire``. The output of the latch. Takes on the value of 1 if the value of ``set`` is 1 and the value of 0 if the value of ``reset`` is 1.
+* ``output_not``: An object of type ``Wire``. The complemented form of ``output``.
+
+
+.. _TFlipFlop:
+
+TFlipFlop
+=========
+
+Class ``bw.storage.TFlipFlop``
+------------------------------
+
+.. image:: images/schematics/storage/TFlipFlop.svg
+ :width: 360px
+
+Defined in `bitwise/storage/FLOP.py `_.
+
+Positive edge-triggered `T flip-flop `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ toggle,
+ clock,
+ output,
+ output_not
+ )
+
+Construct a new positive edge-triggered T flip-flop.
+
+Args:
+~~~~~
+* ``toggle``: An object of type ``Wire``. The toggle input to the flip-flop.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the flip-flop.
+* ``output``: An object of type ``Wire``. The output of the flip-flop. Toggles its value on the positive edges of ``clock`` if the value of ``toggle`` is 1.
+* ``output_not``: An object of type ``Wire``. The complemented form of ``output``.
+
+
+.. _TFlipFlopPresetClear:
+
+TFlipFlopPresetClear
+====================
+
+Class ``bw.storage.TFlipFlopPresetClear``
+-----------------------------------------
+
+.. image:: images/schematics/storage/TFlipFlopPresetClear.svg
+ :width: 360px
+
+Defined in `bitwise/storage/FLOP.py `_.
+
+Positive edge-triggered `T flip-flop `_ with asynchronous active low preset and clear.
+
+__init__
+--------
+
+::
+
+ __init__(
+ toggle,
+ preset_n,
+ clear_n,
+ clock,
+ output,
+ output_not
+ )
+
+Construct a new positive edge-triggered T flip-flop with preset/clear capabilities.
+
+Args:
+~~~~~
+* ``toggle``: An object of type ``Wire``. The toggle input to the flip-flop.
+* ``preset_n``: An object of type ``Wire``. Presets ``output`` to 1 and ``output_not`` to 0 if its value is 0.
+* ``clear_n``: An object of type ``Wire``. Clears ``output`` to 0 and ``output_not`` to 1 if its value is 0.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the flip-flop.
+* ``output``: An object of type ``Wire``. The output of the flip-flop. Toggles its value on the positive edges of ``clock`` if the value of ``toggle`` is 1.
+* ``output_not``: An object of type ``Wire``. The complemented form of ``output``.
diff --git a/docs/_build/html/_static/alabaster.css b/docs/_build/html/_static/alabaster.css
index 4966909..900083d 100644
--- a/docs/_build/html/_static/alabaster.css
+++ b/docs/_build/html/_static/alabaster.css
@@ -75,11 +75,11 @@ div.documentwrapper {
}
div.bodywrapper {
- margin: 0 0 0 220px;
+ margin: 0 0 0 240px;
}
div.sphinxsidebar {
- width: 220px;
+ width: 240px;
font-size: 14px;
line-height: 1.5;
}
diff --git a/docs/_build/html/_static/custom.css b/docs/_build/html/_static/custom.css
index 3a79c64..1a0230e 100644
--- a/docs/_build/html/_static/custom.css
+++ b/docs/_build/html/_static/custom.css
@@ -1,10 +1,40 @@
@import url('https://fonts.googleapis.com/css?family=Sorts+Mill+Goudy');
+@import url('https://fonts.googleapis.com/css?family=EB+Garamond');
body {
font-family: 'Sorts Mill Goudy', serif;
}
+/*
+div.sphinxsidebar {
+ width: 240px;
+ font-size: 14px;
+ line-height: 1.5;
+ overflow-y: scroll;
+ top: 40px;
+ bottom: 0;
+}
+
+div.sphinxsidebarwrapper {
+ padding: 18px 10px;
+}
+*/
+div.sphinxsidebar input {
+ font-family: 'Sorts Mill Goudy', serif;
+}
a:hover, a:visited, a:link, a:active {
/* text-decoration: none !important; */
border-bottom: none !important;
}
+
+div.body h1,
+div.body h2,
+div.body h3,
+div.body h4,
+div.body h5,
+div.body h6 {
+ font-family: 'Garamond', 'Georgia', serif;
+ font-weight: normal;
+ margin: 30px 0px 10px 0px;
+ padding: 0;
+}
diff --git a/docs/_build/html/api.html b/docs/_build/html/api.html
index ed7d68d..f617b91 100644
--- a/docs/_build/html/api.html
+++ b/docs/_build/html/api.html
@@ -24,6 +24,8 @@
+
+
@@ -64,6 +66,8 @@
Bitwise is a Python library intended to make hardware design and simulation more accessible
for software engineers. While it can never replace a true hardware description language,
@@ -127,7 +132,7 @@
input_1: An object of type Wire. The first data input to the multiplexer.
input_2: An object of type Wire. The second data input to the multiplexer.
-
output: An object of type Wire. The output of the multiplexer, which takes on the value of input_1 for a 1 select and input_2 for a 0 select.
+
output: An object of type Wire. The output of the multiplexer. Takes on the value of input_1 for a 1 select and input_2 for a 0 select.
@@ -625,7 +629,7 @@
Args:
select_1: An object of type Wire. The most significant bit of the select input.
select_2: An object of type Wire. The least significant bit of the select input.
input_bus: An object of type Bus4. The data input to the multiplexer.
-
output: An object of type Wire. The output of the multiplexer, which takes on the value of input_bus[0] for a (1, 1) select and input_bus[3] for a (0, 0) select.
+
output: An object of type Wire. The output of the multiplexer. Takes on the value of input_bus[0] for a (1, 1) select and input_bus[3] for a (0, 0) select.
@@ -664,7 +668,7 @@
Args:
select_2: An object of type Wire.
select_3: An object of type Wire. The least significant bit of the select input.
input_bus: An object of type Bus8. The data input to the multiplexer.
-
output: An object of type Wire. The output of the multiplexer, which takes on the value of input_bus[0] for a (1, 1, 1) select and input_bus[7] for a (0, 0, 0) select.
+
output: An object of type Wire. The output of the multiplexer. Takes on the value of input_bus[0] for a (1, 1, 1) select and input_bus[7] for a (0, 0, 0) select.
@@ -699,7 +703,7 @@
Args:
enable: An object of type Wire. Enables the multiplexer.
select_bus: An object of type Bus4. select_bus[0] and select_bus[3] are the most and least significant bit, respectively.
input_bus: An object of type Bus16. The data input to the multiplexer.
-
output: An object of type Wire. The output of the multiplexer, which takes on the value of input_bus[0] for a (1, 1, 1, 1) select and input_bus[15] for a (0, 0, 0, 0) select.
+
output: An object of type Wire. The output of the multiplexer. Takes on the value of input_bus[0] for a (1, 1, 1, 1) select and input_bus[15] for a (0, 0, 0, 0) select.
set_: An object of type Wire. The set input to the latch.
+
reset: An object of type Wire. The reset input to the latch.
+
clock: An object of type Wire or Clock. The clock input to the latch.
+
output: An object of type Wire. The output of the latch. When the value of clock is 1, takes on the value of 1 if the value of set is 1 and the value of 0 if the value of reset is 1.
+
output_not: An object of type Wire. The complemented form of output.
Construct a new positive edge-triggered JK flip-flop.
+
+
Args:
+
+
J: An object of type Wire. The J input to the flip-flop.
+
K: An object of type Wire. The K input to the flip-flop.
+
clock: An object of type Wire or Clock. The clock input to the flip-flop.
+
output: An object of type Wire. The output of the flip-flop. On the positive edges of clock, takes on the value of 1 if the value of J is 1, takes on the value of 0 if the value of K is 1, and toggles its value if both J and K have value 1.
+
output_not: An object of type Wire. The complemented form of output.
Construct a new positive edge-triggered JK flip-flop with preset/clear capabilities.
+
+
Args:
+
+
J: An object of type Wire. The J input to the flip-flop.
+
K: An object of type Wire. The K input to the flip-flop.
+
preset_n: An object of type Wire. Presets output to 1 and output_not to 0 if its value is 0.
+
clear_n: An object of type Wire. Clears output to 0 and output_not to 1 if its value is 0.
+
clock: An object of type Wire or Clock. The clock input to the flip-flop.
+
output: An object of type Wire. The output of the flip-flop. On the positive edges of clock, takes on the value of 1 if the value of J is 1, takes on the value of 0 if the value of K is 1, and toggles its value if both J and K have value 1.
+
output_not: An object of type Wire. The complemented form of output.
Construct a new 4-bit-parallel-to-serial converter.
+
+
Args:
+
+
enable: An object of type Wire. Enables the converter.
+
clear_n: An object of type Wire. Clears all 4 internal registers to 0 if its value is 0.
+
load_n: An object of type Wire. The mode select. A value of 0 indicates a parallel load operation, where the values of data_bus are loaded into the internal registers. A value of 1 indicates a shift-right operation.
+
data_bus: An object of type Bus4. The parallel data input.
+
clock: An object of type Wire or Clock. The clock input.
+
output: An object of type Wire. The serial output of the converter. data_bus[3] is outputted first, and data_bus[0] is outputted last.
Construct a new 8-bit-parallel-to-serial converter.
+
+
Args:
+
+
enable: An object of type Wire. Enables the converter.
+
clear_n: An object of type Wire. Clears all 8 internal registers to 0 if its value is 0.
+
load_n: An object of type Wire. The mode select. A value of 0 indicates a parallel load operation, where the values of data_bus are loaded into the internal registers. A value of 1 indicates a shift-right operation.
+
data_bus: An object of type Bus8. The parallel data input.
+
clock: An object of type Wire or Clock. The clock input.
+
output: An object of type Wire. The serial output of the converter. data_bus[7] is outputted first, and data_bus[0] is outputted last.
Construct a new 16-bit-parallel-to-serial converter.
+
+
Args:
+
+
enable: An object of type Wire. Enables the converter.
+
clear_n: An object of type Wire. Clears all 16 internal registers to 0 if its value is 0.
+
load_n: An object of type Wire. The mode select. A value of 0 indicates a parallel load operation, where the values of data_bus are loaded into the internal registers. A value of 1 indicates a shift-right operation.
+
data_bus: An object of type Bus16. The parallel data input.
+
clock: An object of type Wire or Clock. The clock input.
+
output: An object of type Wire. The serial output of the converter. data_bus[15] is outputted first, and data_bus[0] is outputted last.
enable: An object of type Wire. Enables the shift register.
+
clear_n: An object of type Wire. Clears output_bus and output_serial to 0 if its value is 1.
+
shift_load: An object of type Wire. The mode select. A value of 0 indicates a parallel load operation, where output_bus takes on the value of data_bus. A value of 1 indicates a shift-right operation, where output_bus[3] takes on the value of output_bus[2], output_bus[2] takes on the value of output_bus[1], and so on; output_bus[0] takes on the value of data_serial.
+
data_bus: An object of type Bus4. The parallel data input.
+
data_serial. An object of type Wire. The serial data input.
+
clock. An object of type Wire or Clock. The clock input to the shift register.
+
output_bus. An object of type Bus4. The parallel data output.
+
output_serial. An object of type Wire. The serial data output. Identical to output_bus[3].
+
+
+
+
Raises:
+
+
TypeError: If either data_bus or output_bus is not a bus of width 4.
enable: An object of type Wire. Enables the shift register.
+
clear_n: An object of type Wire. Clears output_bus and output_serial to 0 if its value is 1.
+
shift_load: An object of type Wire. The mode select. A value of 0 indicates a parallel load operation, where output_bus takes on the value of data_bus. A value of 1 indicates a shift-right operation, where output_bus[7] takes on the value of output_bus[6], output_bus[6] takes on the value of output_bus[5], and so on; output_bus[0] takes on the value of data_serial.
+
data_bus: An object of type Bus8. The parallel data input.
+
data_serial. An object of type Wire. The serial data input.
+
clock. An object of type Wire or Clock. The clock input to the shift register.
+
output_bus. An object of type Bus8. The parallel data output.
+
output_serial. An object of type Wire. The serial data output. Identical to output_bus[7].
+
+
+
+
Raises:
+
+
TypeError: If either data_bus or output_bus is not a bus of width 8.
enable: An object of type Wire. Enables the shift register.
+
clear_n: An object of type Wire. Clears output_bus and output_serial to 0 if its value is 1.
+
shift_load: An object of type Wire. The mode select. A value of 0 indicates a parallel load operation, where output_bus takes on the value of data_bus. A value of 1 indicates a shift-right operation, where output_bus[15] takes on the value of output_bus[14], output_bus[14] takes on the value of output_bus[13], and so on; output_bus[0] takes on the value of data_serial.
+
data_bus: An object of type Bus16. The parallel data input.
+
data_serial. An object of type Wire. The serial data input.
+
clock. An object of type Wire or Clock. The clock input to the shift register.
+
output_bus. An object of type Bus16. The parallel data output.
+
output_serial. An object of type Wire. The serial data output. Identical to output_bus[15].
+
+
+
+
Raises:
+
+
TypeError: If either data_bus or output_bus is not a bus of width 16.
set_: An object of type Wire. The set input to the latch.
+
reset: An object of type Wire. The reset input to the latch.
+
output: An object of type Wire. The output of the latch. Takes on the value of 1 if the value of set is 1 and the value of 0 if the value of reset is 1.
+
output_not: An object of type Wire. The complemented form of output.
diff --git a/docs/_static/custom.css b/docs/_static/custom.css
index 3a79c64..1a0230e 100644
--- a/docs/_static/custom.css
+++ b/docs/_static/custom.css
@@ -1,10 +1,40 @@
@import url('https://fonts.googleapis.com/css?family=Sorts+Mill+Goudy');
+@import url('https://fonts.googleapis.com/css?family=EB+Garamond');
body {
font-family: 'Sorts Mill Goudy', serif;
}
+/*
+div.sphinxsidebar {
+ width: 240px;
+ font-size: 14px;
+ line-height: 1.5;
+ overflow-y: scroll;
+ top: 40px;
+ bottom: 0;
+}
+
+div.sphinxsidebarwrapper {
+ padding: 18px 10px;
+}
+*/
+div.sphinxsidebar input {
+ font-family: 'Sorts Mill Goudy', serif;
+}
a:hover, a:visited, a:link, a:active {
/* text-decoration: none !important; */
border-bottom: none !important;
}
+
+div.body h1,
+div.body h2,
+div.body h3,
+div.body h4,
+div.body h5,
+div.body h6 {
+ font-family: 'Garamond', 'Georgia', serif;
+ font-weight: normal;
+ margin: 30px 0px 10px 0px;
+ padding: 0;
+}
diff --git a/docs/api.rst b/docs/api.rst
index 16bf3bc..024fc36 100644
--- a/docs/api.rst
+++ b/docs/api.rst
@@ -69,6 +69,27 @@ API Documentation
:doc:`storage`
==============
+* :ref:`DFlipFlop`
+* :ref:`DFlipFlopPresetClear`
+* :ref:`GatedDLatch`
+* :ref:`GatedSRLatch`
+* :ref:`JKFlipFlop`
+* :ref:`JKFlipFlopPresetClear`
+* :ref:`ParallelToSerialConverter4To1`
+* :ref:`ParallelToSerialConverter8To1`
+* :ref:`ParallelToSerialConverter16To1`
+* :ref:`SerialToParallelConverter1To4`
+* :ref:`SerialToParallelConverter1To8`
+* :ref:`SerialToParallelConverter1To16`
+* :ref:`Register4`
+* :ref:`Register8`
+* :ref:`Register16`
+* :ref:`ShiftRegister4`
+* :ref:`ShiftRegister8`
+* :ref:`ShiftRegister16`
+* :ref:`SRLatch`
+* :ref:`TFlipFlop`
+* :ref:`TFlipFlopPresetClear`
:doc:`wire`
===========
diff --git a/docs/changelog.rst b/docs/changelog.rst
new file mode 100644
index 0000000..0281a3a
--- /dev/null
+++ b/docs/changelog.rst
@@ -0,0 +1,49 @@
+:tocdepth: 2
+
+=========
+Changelog
+=========
+
+
+Unreleased
+==========
+
+Added
+-----
+* Shift register classes to storage subpackage
+ * ``ShiftRegister4``
+ * ``ShiftRegister8``
+ * ``ShiftRegister16``
+
+* Parallel-to-serial converter classes to signal subpackage
+ * ``ParallelToSerialConverter4To1``
+ * ``ParallelToSerialConverter8To1``
+ * ``ParallelToSerialConverter16To1``
+
+* Serial-to-parallel converter classes to signal subpackage
+ * ``SerialToParallelConverter1To4``
+ * ``SerialToParallelConverter1To8``
+ * ``SerialToParallelConverter1To16``
+
+* Buffer class to gate subpackage
+* ``__getitem__()`` and ``__len__()`` methods to ``Bus4``, ``Bus8``, ``Bus16``, and ``BusSevenSegmentDisplay`` classes
+
+Changed
+-------
+* Rewrote docstrings for all classes
+* Misc improvements
+
+
+v0.1.1 - 2018-10-17
+===================
+
+Added
+-----
+* Storage register classes to storage subpackage
+ * ``Register4``
+ * ``Register8``
+ * ``Register16``
+
+Changed
+-------
+* Misc improvements
diff --git a/docs/conf.py b/docs/conf.py
index 7bd5951..d17a5f4 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -20,6 +20,7 @@
nav_links["Home"] = "index.html"
nav_links["Getting Started"] = "install.html"
nav_links["API Documentation"] = "api.html"
+nav_links["Changelog"] = "changelog.html"
html_theme = "alabaster"
highlight_language="python3"
@@ -30,6 +31,7 @@
"logo": "logo.png",
"logo_name": False,
"page_width": "70%",
+ "sidebar_width": "240px",
"sidebar_collapse": True,
"sidebar_includehidden": False,
"show_powered_by": False,
diff --git a/docs/images/schematics/signal/signal.xml b/docs/images/schematics/signal/signal.xml
index 909f12b..3c212b0 100644
--- a/docs/images/schematics/signal/signal.xml
+++ b/docs/images/schematics/signal/signal.xml
@@ -1 +1 @@
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NGSfOqe8eBk5MSe3uEeVV2nePh/9QsmV6CClj5j859d3D8B/Kvnu9gNliOfXdw/AfSmVbr1wtIX33+q1srSQsJaHvXq98LiF993rlcwHt8jj23etz1CCK7LvXc2s7JL/vHsI7BWXfvXJ027yDVUDfvbJQQpWMvntlYdVSIvrulQU3AZz8vnsYByChAq4suPG15Pfdw3ABQsJWWXAjbMnvu4fhApR99woBM92MKulnHcgF5yml9GUhYKhbr/6zyn8IHwfLIkfQzIM30TqsxbyHCxif1mmkr4p0QrlqOf6svCMd6xk3ojSuNDkibp6lsJ5xI4rjSpMj4uZZCusZN6I8rjQCSFBG+zOvOz4JWbylQcTrojmQ0jBXOVBJedMyEhrEa7+ZdQ5EWsBLwAp1QsW6I4yQyFsaAVihUSXKugxECTYbBQtfUZc294uMx4UsTY59/j1LYcG63kKIlhqXzttSWLCctxCmpRSWG34/LFjOWwjRUmWOnH2vLwYWES4mgFoi9mBFocDMvmChV5VcKTCELWvKMsdSxW9igxWsEYvKKsdSxbMUFmc/JlegyrFU8SyFxdmP+dZbWWYH4CxZK5cDECJmRDsAK25igHnCZzY+QKkGqLipAebforPxAUo5QJVj9wavbyDWoR0TCaq49Vmdf3bLJloplRuVYkwbqF9eiR2R+lXl+Grl5VUsgCHmq1WlUNCGVyvPUhEBhvG78zkBtdX4FUwniXYC1oh9TXF8QNu4XMGctHg+wA2+mucPZeMDhNhFBfandXb64/ClP/tf1Ux8UVvcHO/vDzePT+Penz4vZjfAQ2wrfwPOfeVf74A3tDVoC0AUd03h4m/NeVu5limhz8tee/94z8sVJrQajfGYEeHxJVcEEx4JNR8ViMo6O/32K0ObsvJ+ErBHFsh2532LkO0ogEpu+c9viRmW/vyOmPGyH0WTWe52wuKrxTylKKBEbnaSN7K0AoFElGriy+fr+0XVRANVE+cyYfzg58PN8f3pp7rlg/nPDycVETQ76PzZ99/lQrnh1yXoBcjN4LrDd9i/AqE+XTkOpDrcP93E0htGFVKRusOofPeAbpooFSkm7hrrQpNTuzCECw2hgKtiB9nKZxoFeICH1lEmEAt4QOq1pnsnwGpYEu/Ruqoh5GqNnfhbxevcjDYx1F8J0zLsqHqaQ8FTNF4O5da3Vz77C8EDAGA4ngdwIwDKZz8geABAfojnAYrZ4SlMI2KrNQX5j7ud2uDKyrWUvxKmrSjof9xtZbCImt5CiJYaA5YVRvnqQFSc8uSgLk7Z+edjG+t8bAQMPc+pVxkCUEnYqqxqLOA+qR8F3nxUrE5TUY+CrUCVREtJHORXNdyAK/l0bYRLKzR1M9qtteGGXMlna2O4AOUDUMMNupI/dw7DBSjx6waxD6zOnUNzAUoAu1FYzIoY6ls1Coqd0iMaggkshWitMYbzthZWVwBvIUxLUbRI424pCW0Hq9YCltIeoXuXK5SvrS23Fmnyu+QhuAAp87nlhl4l0CUPwwcosYuWG3yVQJc8DB+gBC/aHEWNEpsQV61SpE75Ee3mCiyFaS1FhGTMTKhaRYRkdB6sxqX51CvKFL+C+4RGq1c6bpK7BDrlYfgAJXzRWW4+oNSLK7hTXjwf4AZhJdApD8MHKPGLbkE/qeQrNwmdiKsuxxZXnqXCFbmeraJKcjvFhGRMTqg6ASOoZ+tjlQW4sgCIwBpNF9DliFJ5ugCs3oMx2ebdVpSKsV3GRBl8PHrDcGOejuNNN2FLBDP5vIiIePb100jQfqLJl4NvV83k3rdDp6EPgUKyBrUYzsbGbpt+JtidUbHG34EK6hzvBUrQHthpUGR7SGDWh18Od8O2/sNurwvlSpBfPHZxPBH2tqvtAnAFvVn3mj35NpljwG6iSBFGAWScd2HvcmDsB+aSU8OKAzc5RisNaksBYDC3UmgJ180vg2klCkILNytdvqosrrWbSyth2kpOr+5PX+8ebz/fHb5BHbvhgiGoWTfFHQP8zubXY7WqHhLbXZx/OaDNxZlWzOOfOngE3etkPb6ESrmMGb2MrbqMAS/d0S5jJTfWk3yxRkAysU4HMEKuQ11awANSL5adCjeUTdzNL4NYJpcU3Zu4Wcm90oSLy12Dx9SW1yU7BZzmVFLtU13mCOa50RrezNaN1pjNbOuSW58l+dR/hGglZP7XpcKF1vZo0eqvhBmtiHChNvTHilZCjUZd4vOVuMfmBnpvd2klxNgcf+ucLBOs73YNE/HRsuLIZ0q6CXxASq0cQBng98RjOElh9zyR4BRNXuZY05V0NDQZ7FydeiXtlL+hevdufhnE82BJBwlqQmMJtteGCI04nlpNY3S8Up4SGl97LEtCY7UA7cMnNK7Yk5UMBqRdIaHKjbvA8yzgT2isSLAv3lbiT2isKNR03KwklNBYTTO3lNBIT2jsVtVDcgmN3MuBMSmwAqHSJTSud4cdCY11TIBSCY27X8YoCY21xTt+ldAYmkz2JDTWJFQ5ZsWyOEJjTQIVM7OSUEJjza6du+ZUWkJjnSOYJ5TQWHObGpgAoXF7tFISGmuFC8UQGmtEuFAJjVjRSkloHL0NkzbHPDaFEBqbraMH5VkmfNCg92YZ7+7Y2MmcqYTG3UG/CUKjKfycGo/RmON9RRwRbWa+OUvcv1Tcf1kK2IN6muOdx+3wHHp4u0VVzLM7ZmMb5ZrvG/DAtSlawJNMcOcW8N5FKvwm5SWPqFcpcIr7njCH/MFKCDAHSLqPFrDQrS27gMVjMQJLYQYstzFY8qdgYQQsJZECnOSeXcDivdEDS2EGLLdH+kYD9mRzyoDNEfXyAhbvmR5YCjNgub3TtxqwJ5vTBWyzpPdibCWuO1TuPFXu1QY00A6ULjIclLMwR29HgHwX8M0SmzT34pTBk+YocV9wbLez0+ji24A9skBYgXIbpLCiuGyft4FLKeDkMqzxexH1t+C06dzsFMpWd+0Uka5OMhGam528ybV4Y4ZjFtbgTGhV4G56WdugwDXNqscxsRJcAUXBdKvb/XhTyWpwQwpp9zJKCB5xnfj95iI2K6bUi5h7EaPsggRO/FbhLbEHVKVTaFFmkK2deSXWyO5dJpR16d5lItIuN88Zl2gn9y4T/qzn3mWivurNzCJX6e1uWZXyUe88HD3naA1/03OjNeqTXs+NNCNfeosQrZTS215xwi3SWzdao0pve26MGfnSW4RopZTe9lsJM/JiM5ww3lwU8WLG5ta+tPIsU4Y+g7mG8RbCtMs0yrMfhJy09DYgpdYujAy0+owmve0VBdqgxPPYjPGkeM24NGvEf/YGo4i/i/gTKvCaYmt7jCQiHYtkFHECWFNYwFLcIn329qOR7kY6pN2LF+o50tS8q9OGtkVu1oh5eWoKCIRSse3OwAal2LYpKCaQsw9YPMJiVLFtU3CbQS5fbIsRsITkiaagGMTEPmDxXuWjim2bghvZSb7YFiNgCd/lmyJHnMsLWLyH+ahi22asvdgErHyxLUbAUoptDX43VzbhuXGSoYtFxRtl2BibvBW29Pi53C4I0xY5ojoegIulPvQWwrQUIqKDCeB6b79u10RIuKbI7gVkl1C20RgFik5UFrwyNiZlrTHcgKJOy9iTzSnLWAWK7BYamxuwUXlsjeEGFPUasJZUWNsYBYosZu+IqM0jmvGHsQlYozrWJ6MTRqzdihQlEbF4bzFRJZLNaBw+EasaySejU0ZsjkiWF7F4jzFRZZKN5cZPMqqTvHrVCpUkYhV3sphKyahSycZyw52MaiWfjE4ZsQo8DdcQPOAJWAozYrkBT0ZJwE9Gp4xYRZ5ODc3xIjYq8jR6Cp+IVRbwk9EJI7acbve0n7z6lUprV3n13g7idGYjEFM3S2amUQ+IaCFgB9oBjxATFhJMqS9PTJcc50O0yyNm//kQTbkAZ8CfD7F+jxa3gkaKKopRUedtYFIaypsP0ZQkl27mduI/H6IpoasWx5kDf7u/Ob5PddpA9evRXvjloK8ncdgA+xNm/GmsrjLpDhsIqMr2GzbQVIhtjQPT5cWi3uHdQAlQi/oX96EkrVckz/3MqyL+neabGjoD1tiJsVXkSO7qCMJHZlYwWGbwFsK0g2YtIZ0R62iYI155YrU8WVOeUDZGrEm4TdwDXUJjxBqR1xTrcSGrvojbA520L2IzPUJgP5DjxXnSe65d4R87PNc2Ob6q4E0Y8LXUEek2TY4vK66tQq9NrqUi3poaiMiYm51kTKtrmulXsPe3v4Mn2umc+eH5yDgdaU+nxuVnLPJDdfhKw9dc/7Y0fPb01ZM9Zqd6IhC+JozneYJu90zINOp5ywmblJ43/Y6ViOdZ9bzFnkeoeG2XNPimZob2FtgA8LLl1othwafMUFbgzYtPimCGtnswQwP2aDFvBymqKDCM8zYwuW8JZIa2FPgFdzsJYIa2iEJMZYaGftvu12MZUMkKZIYKOGGmUaL9rjvJMkNDqrIdmaHjcw1n6kVOzFCEop6SGdpRtG7jXhUJYIZ2dqOdGFtFDjO028pI5G8FvKtcxLtcByFZuWUtEczQbprww6Y8yYkZilCeUDJDOwXXhDBDOwheY/a4kBMzFCHQSZmh3TTstx/IkTAzdI1/uOmDghraUfRi45b5hVJDx4oga1sJoIb2OYI9QqmhvZ08D6UzpbKihgbUYXtSQ3sI4UrD7XKjhiJ4HiU1tJ9mpyXieVY9jyM1tOmjYZR40MVsa2GFLnYdCdsrSCmko0gfDaTEe42o9DViVaQDNUq8SKfQVrKPdAkD4Psc4UPPUljEFm8hPEu1IzzDOSc3mpNX5WRCWUpb5Ahq+voLNAFGxEifhjTZ3LNavWetinRCMkhbUPQD5Bbp7vMF3szSmCNL2yJ5NC9EHpMrmkc4KLVtoHrS2WhioXcFFUQNtAOVe/yGJUoBXKyshN5nn5Qg9G6LBSgHvtB7/R4tluEhRRUJpDD+/kzKD3lC79YsOACStxN/oXdr9p9pQS/0Rv7VTPPrsQr4NRacuOhHayT5Nvtzw0zDHvtdYtKVbwfUWvvJt1szzbdig35nJd/eXqoTUg9aQyKEZF7r8Jdvt2brhAPGVhEj327NVqIOfyuUWMHgLYRpB5JWXFwsI1i+3Zr9m3GpfBu3PKF8sTMKmcmQb7fj0pyfDLKSb28PdEr5dmunwbz9QI6U5dsr/MOl9hDIt9sx0WeV+WXKt1tLwqthbqvQBxPXUhEfTGyOYI9Q/pOd1pRJ5z/lJd9eX4ftKN9u7fR8Thy3o2bZgS8QEx6XpXdRzlCx07wyyd61gIqWq3dREjdtNKxRZdh7QRCUb6FWwUYZMux2TDKcXxWykmEjRDqhDLstSSR/3CNdgAy7LXOEAUXKsEsBRLSsZNgIOZlSNFLmCE6KlGGXAtpdZSXDRoh0SlJHSdLuilmku88QPdozhL8SZqynidhZReymEDsgE0RD7MrpwYRsTpJeT5I1JwnU8jXaSTI6ZlYniVczChi41Vb7azUvRnqnt8NVkU5JD6wUB7J4EpmYGpkqRzKYZyksbDUmHayabrHEJicb1Y6uS8qUD6bVVlFiEqGOBc7HlI9W07QuNhctox2d1oU6JTpfSegIpvqeVQ5UkhbwJJ3PmZ8VJdbzjrcQ5lkRDZRDLAtVs7vurKB83xkXzjvUsVA5byHEUK+VBzVsMBaq4i2EaSkrICkr5XFVUi4pn0pqheWGHceC5byFMEM9GiyHeNVSHcO6UKeE5eocYTlPOo+onY8qnq/TVFwuwGJyZdhAfVWiUWzqra3S5IV+aD3f0DUSrLeiYfKsEiwsc80SU1hWT2Nf7zjkVW23fHJQp91y56fTWG2JOrDNmbPT1MNhGqAvEzgcxhMFBJ0oTTQoQofDhETQi0+KGA7TLAAi0IfDBOzR4ib/SFFFIX86bwOTGkHgcJiG4nLN3U4ChsM00RgvyBNYfjn8frj/5fDx0+Hp6Nk+IWbqvAs+bZ3vsXrjfjreP6Xdh1Xlq9iBMgLOmmkyz363nGQHyoTUZzsOlGkEdGzPiRSMUN5TPj40FE2UuNdHAgbKjBkGEYFkYxU5A2XarQQc/lYwVRX6EOe3FPOWwrQFhGvllrlEDJVpBbQayomgilCiUPJTW4XahAyVaQV0GspJdIIQ6KRDZdppEHA/oCPhoTJr/IP+8bZtKTRI3BI/FjvGZcXFvBXliCG4dqrR+Iv+Soi26qYbu0imL6Y6MCLgBHfpi4BqIRoY3UF3cvnelerACATvohxH0lPI37ifM0LmYfVpZoJUG1EiZALC0TFdoRWnlJa03QggJJYJUhXMIGQCwpa0nUn4RW4i7kORYFeYEQ8I7gx0+qdtleChH55eJh6LoDPTL3H7AaxJ62UC0qmrlwHSaTS9jMnxrU2qFrkzsYcO71NaVVpacdAid4Zi8Af7ZFDiJQN/KcxkkObojwWdS7JNBoTQfmf0MXZYAO+VD1gKMxlMC+MlJ4NGk8FkMiB8ienGKyonWX0HlEagrN5rBhbWWQCCOJhx3bKS1XerQ2hHWX1nd5HVr9+jxVJHpKgiwR86XlWGPFl9Z0lk9cztxF9W31mV1bOT1f/89fpuFdItV1rP/7xRaT3zGm0/aX1nVVov3n32k9Z3loSkxLxG4i+t70YgBZOswMUqYqT1XRmByMPMChIm/3YlhGvllrUkyOq7UmX1qZUnhLL6rlSoTYasvitVVp9aoFPK6rtSZfW0r7kr/MNNHxQkz3LrjAmJmV+err4rSSg3zO0kQ1fflQkSbv5hUlbWrz/Ed1TWd+PCyflXstr67f5FyeiqSLT1zM8aGdr6roIguhRyQbLq+u25gFJdX1HMnuWeC4So6ysIxUshFySrr9+eCyj19dVWop+8yBegr6+2KvPkWUWEvr7iSCd7k1iVVHa1r8K+UlBPkMK+ShXWS1Zjv728ItXYjwGWdzqQorGvE+ye+5QOklXZI6QDSpi/hqC97NKBFJV9Pc3Ak50OktXZI6QDyleZehrdY8P8WnB0KPNr3n+iMb9qlekOC2CpH7yFMI+S/YW6FyO9UjL3qkgHCsd4kZ4jp8+LdCxFvrcQZqTnCAB6lsLSBcZE8+tp8I9NTm40J6/KyZQ9fsafnXWkWywpnbcQYqQ307gem3tWq/esVZFOqaVrbIaR7vMmAiPdBe2iRrpy2+wpOLAAVmApTGulyG6zqqqYBVgp6W1Ngh30nxxMZRWTDkbaQ6oh6aHP/bzBe98HlsI8bxLsof+UDlRZMZ0OKN/3mxzBPy8d4L3vxxX1Nimy/6yKK2bTAeX7/ohGZsTjL0NfY10ev7cQYuC303ggCx6/vRy8OfL4odiNRuRvFfOzmJLpuJrpNkWqnlUi/+xRTimabiGoMrt0gKeajiubblPF/ZTIP50OKIHlVnG/oUTHe2cClsJMB6nifkrkn0wHJeEzQN8toGcSD8yrz9S5SwPzGpdjF5QRO+i+xIxjk9PAvBefFDEwr9tjYF7AHi0eYIQUVRTXjvM2MKkzBA7M6yiUONztJGBgXre/DkcH5jkD8/776/X7VYC32IF5As4bjh2Okh2YF1Kj7Tgwr9OBeeLdZ8eBeR3FwDzuNZKAgXkjjorIWmBjFTkD83r8gXncrFBiBYO3EKYdIFwrt6wlYmBerwPzUitPKEV+vUJtwJw7jgPzeh2Yl1qgkw7M63VgHulr7hr/cDXCFFTPnqK5DrfML3BgXk+hruFuJyED8/oUtTUpD8wLOMR3HJjXj1GRnH+lquxG8C9C6VZfUAzM437WyBiY1xcQRJdCLkhV1o2QCwi1H31B0VSIey6QMTCvL1JsKZTywDyEXEAo/OgL/IF53COf/8C8vsAfmMfdKhIG5vUFRzpZ4gPzAhLqjgPz+kJBPTkD8/oiVVgvVZ09QnlFOTCvH39W3ulAyMC83ujAvPzSASXMbyBoL7t0IGRgXm9S7MKT8sA8jHRA+SpjptE9NsyvnAbmYTC/CCUovVGZroyBeb3ZX6h7MdJzGpiHEemEA/N6kyOnT+LAvN7kCABKHJjXGx2Yl1xOJuzx04+LZB3pEgbm9XYa12Nzz8ppYB5GpBNq6foxsLOKdIkD83qr3DY5A/N6myK7LeWBeRgAKyW9zabaOFtlFdONsynf9y1F42z2542QgXm9TbVxtiorptMB5fu+zRH8kzowr7cpsv9SHpiHkQ4o3/fHn50Rj1/CwLy+1IF5EjC/PQfm9aVifnIG5vVlilS9lAfmYRzllKLpEoIqs0sHQgbm9WWquJ8S+afTASWwXCruJ2dgXl+mivspkZ/HwLxScb9hx0PpmV4yiEjPLHOc2uBZCu9aByyFaK0xYJNK3KUSBGYTNyVCW6Wo+C2VIDDrYJS4QaUw4ulRH++8iYobVCnCiKUSBGbTASVuUCmMOPw7Hm4ALIWZDlKEEUslCMylg4oSN6jya/RXh8oIXIKAtxBm4DNv9FcqQeDJBdrLsRuNIFAp5nfKnnhHeVTqb5Ui169UgsDsUU5J/R0DLO90gEf9BZZCTAd1qrifEgSm0wElsFwr7jf8O947E7AUZjpIFfdTgsB0OqB8BqgV9xuWDR294I36izh7oc6xp55nKbxrHbAUprWm++rJTdyVEgTmEndNidDWKVIHKyUIzDoYKW6gMOKwLOIY4Li4QYowYqUEgdl0QIkbjNTXvNMBHm4ALIWYDpoUYcRKCQKz6YASN2i2wojygr8JlRG4BAFvIczAVzzn1JwFL01HpXU2KfK4Kn38nU3TlLTORuWgQ77Fo3UCS2Gmg1QxHX38nUwHDSVo2CimM+w43hsCsBRmOkgV09HH3+l0QAnxjhdGzuMHeh0/MOc/7vgBqKtotPEDLYQypX6ceINGQskD3qCRiOSBFoJrmI0U6nSk0KpIBwrHeJGe4/gKL9KxBjp6C2FGeo4AoGcprIF83kKYlpoG/9jkZFNoUl6VlCmn7LY5gnteqGNNdPQWwgz1aWCPzUXLLCBeaai/8hfKkY4tBNxxc6AFb/PqQC8OBDUCjOdAObaXc8+KEmsmqLcQ4lkxHkOsy0KrZeGqs4JyKGinqNwQoVionLcQZqhbtVT4YBbPUhFRlW5ah8knKVealFfVX5RPJZ3CchsaMXuhHhGW66LBcohXrQWEGg31V/5CCct109LPdzwYGNqj68rv0QXR56P16OoWELE+Dl/688S3ssXN8f7+cPN4/W7864W/KxeCpH+7AbZo/B2ooC0wbqUVsgcliGmtORIhN+h4HYDujPHgRgPthYXwDsByBqzenr/wT0S7/RyUnPfGILqc9/5869oEBLMSVKU6O/v2K0KbsLoKXr4n397m+Vd7ci4h8BMfkZSSVyqs3cMmLBG6kzfjpUFQQpmZlUKhGbf9aUQr2Qyt5JYVwQjaBXNj2ml/AK2Bagivsvn5cHN8f/qpbvVg/vNDBZcKs4jbgqoEvdS4GTx3+Ao71hr7nKsQxrb3xftw/3RF09LzCmSsRis9Z6S1HG8xRm8xqzKLeXtyAVB+Gc2zpvG9HeC8Sy3Z0D0gjnBqtQNYF+KlzC0QQpJ60enUiqFPOe38Mpg4VowZJrxs4uGL4cpWF2CMKGwtMSlOKBl0lvqaSwalBAZBjtKeHjDbZi4XDyBsIFWC3Kc9PWCWvZyLBxD2pilBokXqVZR7YgczYi6UY4indQ9Fam52Cm/86FoqZt/HsqfR6fK2lQmm+dcXFsK0FEew8tWBqCjTFdA6iJIitODtnJwiBEK44BaglAj9VqAF8oKedfKyocnLvcF7C2Emr2k5Ikdw3V7IZomD62MiYUkR6vehCC3fk5VPmSi7cj53ItdxvFKhNIpQVdBQhFhbiT1FqCpo7q+8rCSPIlQVKVCEuswpQtzPVY637oQpQqtLT0KKUFUoRShlVyJkhFSFcoIYnCU7coKqgoYTxKvKlMYJqooYmkNeNpHJCaqK6Wb3ygnaLYMSIoHVWPqx8YAUOEGbPYCQE1QZbqywFDhBmz2AkBNUGcXqJHCCKkPDM+FtJxmcoMrQtJ7ibSsJnKDKxASklBOEczy6nKCzQxCQgioTs7cUPmRZKmS5zLf2KLYVsAqeHdDOL4N4JJRaEG9om+Ud3hHJICXi8zXK5XV2BnMul1dD+aBYTr8u7+MCs21Cs3EBymegErF7LIoLzM5azcYFKHHskttbcKsuMPxtytq6zLG29qo2LM6htxBm1UYzEZ25pWo0JBNYCtNaC8QC6VsreOKda6uIE+/GRyNW6rUOKAPOo5ze9KNzQd6QU6CWBdZlDdWd3ZWjRqoC5XbOzuJrpFbsydp2jxjhVS1Rjm0/DMZdYHIYSNNI1TRKNt5WYq+RqmmUbMyshMeU9CqriEVwDerZeOqkPn29e7z9fHf4Bqml4IIhSClF8TgOfmfz69GuqofkSruYlwP1jHxwP/JEutKu9RUz4UtMHVXnh3n1+nK4Gy65evda5UmEDzp1VJHgRnj/kiIwsjtEQfrXHzMe0k/pHVt7DEusm6WpvmqTI1Lg3m5KtNuNvxKircaw5Jhv15X6ueTbeKfx8K8Px5MhXpxp+Fa//f34/nD6G/8P
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cceKc+u5h4MSU1O4eUV6lffd4+A8lW6aHkDJm/pNT3z0M/6Hsu9cLmC2WU989DP+hVLb1ytUS0nev38rWSsJSEvru9crnEtJ3r1c+F9Auj2PfvT5HDaLIvns9t7ZD8vvuIbxTUPbdK0e3zTtYBfTdKwslVMnou1cWVi0lou9eWXATwMnvu4dxABIq4MqCG19Lft89DBcgJGyVBTfClvy+exguQNl3rxAw082okn7WgVxwnlJKXxYChrr16j+r/IfwcbAscgTNPHgTrcNazHu4gPFpnUb6qkgnlKuW48/KO9KxnnEjSuNKkyPi5lkK6xk3ojiuNDkibp6lsJ5xI8rjSiOABGW0P/O645OQxVsaRLwumgMpDXOVA5WUNy0joUG89ptZ50CkBbwErFAnVKw7wgiJvKURgBUaVaKsy0CUYLNRsPANdWlzv8h4XMjS5Njn37MUFqzrLYRoqXHpvC2FBct5C2FaSmG54ffDguW8hRAtVebI2ff6YmAR4WICqCViD1YUCszsCxZ6VcmVAkPYsqYscyxV/CY2WMEasaiscixVPEthcfZjcgWqHEsVz1JYnP2Yb72VZXYAzpK1cjkAIWJGtAOw4iYGmCd8ZuMDlGqAipsaYP4tOhsfoJQDVDl2b/D6BmId2jGRoIpbn9X5Z7dsopVSuVEpxrSB+uWV2BGpX1WOr1ZeXsUCGGK+WlUKBW14tfIsFRFgGL87nxNQW41fwXSSaCdgjdjXFMcHtI3LFcxJi+cD3OCref5QNj5AiF1UYH9aZ6c/DF/6k/9VzcQXtcXN8eHhcPP0PO79+fNidgM8xLbyN+DcV/7tDnhDW4O2AERx1xQu/tact5VrmRL6vOy194/3vFxhQqvRGI8ZER5fc0Uw4ZFQ81GBqKyz0++/MrQpK+8nAXtkgWx33rcI2Y4CqOSW//yWmGHpz++IGS/7UTSZ5W4nLL5azFOKAkrkZid5I0srEEhEqSY+f7p+WFRNNFA1cS4Txg9+ONwcb08/1S0fzN9/OamIoNlB58++/S4Xyg2/LkEvQG4G1x2+w/4VCPXpynEg1eHh+SaW3jCqkIrUHUbluwd000SpSDFx11gXmpzahSFcaAgFXBU7yFY+0yjAAzy0jjKBWMADUq813TsBVsOSeI/WVQ0hV2vsxN8qXudmtImh/kqYlmFH1dMcCp6i8XIot7698tlfCB4AAMPxPIAbAVA++wHBAwDyQzwPUMwOT2EaEVutKch/3O3UBldWrqX8lTBtRUH/424rg0XU9BZCtNQYsKwwyjcHouKUJwd1ccrOPx/bWOdjI2DoeU69yhCASsJWZVVjAfdJ/Sjw5qNidZqKehRsBaokWkriIL+q4QZcyadrI1xaoamb0W6tDTfkSj5bG8MFKB+AGm7Qlfy5cxguQIlfN4h9YHXuHJoLUALYjcJiVsRQ36pRUOyUHtEQTGApRGuNMZy3tbC6AngLYVqKokUad0tJaDtYtRawlPYI3btcoXxtbbm1SJPfJQ/BBUiZzy039CqBLnkYPkCJXbTc4KsEuuRh+AAleNHmKGqU2IS4apUidcqPaDdXYClMaykiJGNmQtUqIiSj82A1Ls2nXlGm+BXcJzRavdJxk9wl0CkPwwco4YvOcvMBpV5cwZ3y4vkANwgrgU55GD5AiV90C/pJJV+5SehEXHU5trjyLBWuyPVsFVWS2ykmJGNyQtUJGEE9Wx+rLMCVBUAE1mi6gC5HlMrTBWD1HozJNu+2olSM7TImyuDj0RuGG/N0HG+6CVsimMnnRUTEs6+fRoL2E02+Hny7aib3vh06DX0IFJI1qMVwNjZ22/Qzwe6MijX+DlRQ53gvUIL2wE6DIttDArM+/Hy4H7b1n3Z7XShXgvzqsYvjibC3XW0XgCvozbrX7MnXyRwDdhNFijAKIOO8C3uXA2M/MJecGlYcuMkxWmlQWwoAg7mVQku4bn4ZTCtREFq4WenyVWVxrd1cWgnTVnJ6dX/8cv909+n+8BXq2A0XDEHNuinuGOB3Nj8dq1X1kNju4vzLAW0uzrRiHv/UwSPoXifr8SVUymXM6GVs1WUMeOmOdhkrubGe5Is1ApKJdTqAEXId6tICHpB6sexUuKFs4m5+GcQyuaTo3sTNSu6VJlxc7ho8pra8Ltkp4DSnkmqf6jJHMM+N1vBmtm60xmxmW5fc+izJp/4jRCsh878uFS60tkeLVn8lzGhFhAu1oT9WtBJqNOoSn6/EPTY30Hu7Syshxub4W+dkmWB9t2uYiI+WFUc+U9JN4ANSauUAygC/Jx7DSQq755kEp2jyMsearqSjoclg5+rUK2mn/A3Vu3fzyyCeB0s6SFATGkuwvTZEaMTx1Goao+OV8pTQ+NZjWRIaqwVoHz6hccWerGQwIO0KCVVu3AWeZwF/QmNFgn3xthJ/QmNFoabjZiWhhMZqmrmlhEZ6QmO3qh6SS2jkXg6MSYEVCJUuoXG9O+xIaKxjApRKaNz9MkZJaKwt3vGrhMbQZLInobEmocoxK5bFERprEqiYmZWEEhprdu3cNafSEhrrHME8oYTGmtvUwAQIjdujlZLQWCtcKIbQWCPChUpoxIpWSkLj6G2YtDnmsSmE0NhsHT0ozzLhgwa9N8t4d8fGTuZMJTTuDvpNEBpN4efUeIzGHO8r4ohoM/PNWeL+peL+y1LAHtTTHO88bofn0MPbLapint0xG9so13zfgAeuTdECnmSCO7eA9y5S4TcpL3lEvUqBU9z3hDnkD1ZCgDlA0n20gIVubdkFLB6LEVgKM2C5jcGSPwULI2ApiRTgJPfsAhbvjR5YCjNguT3SNxqwJ5tTBmyOqJcXsHjP9MBSmAHL7Z2+1YA92ZwuYJslvRdjK3HdoXLnqXJvNqCBdqB0keGgnIU5ejsC5LuAb5bYpLlXpwyeNEeJ+4Jju52dRhffBuyRBcIKlNsghRXFZfu8DVxKASeXYY3fi6i/BadN52anULa6a6eIdHWSidDc7ORNrsUbMxyzsAZnQqsCd9PL2gYFrmlWPY6JleAKKAqmW93ux5tKVoMbUki7l1FC8IjrxO93F7FZMaVexNyLGGUXJHDitwpviT2gKp1CizKDbO3MK7FGdu8yoaxL9y4TkXa5ec64RDu5d5nwZz33LhP1VW9mFrlKb3fLqpSPeufh6DlHa/ibnhutUZ/0em6kGfnSW4RopZTe9ooTbpHeutEaVXrbc2PMyJfeIkQrpfS230qYkReb4YTx5qKIFzM2t/allWeZMvQZzDWMtxCmXaZRnv0g5KSltwEptXZhZKDVZzTpba8o0AYlnsdmjCfFa8alWSP+szcYRfxdxJ9QgdcUW9tjJBHpWCSjiBPAmsICluIW6bO3H410N9Ih7V68UM+RpuZdnTa0LXKzRszLU1NAIJSKbXcGNijFtk1BMYGcfcDiERajim2bgtsMcvliW4yAJSRPNAXFICb2AYv3Kh9VbNsU3MhO8sW2GAFL+C7fFDniXF7A4j3MRxXbNmPtxSZg5YttMQKWUmxr8Lu5sgnPjZMMXSwq3ijDxtjkrbClx8/ldkGYtsgR1fEAXCz1obcQpqUQER1MANd7+3W7JkLCNUV2LyC7hLKNxihQdKKy4JWxMSlrjeEGFHVaxp5sTlnGKlBkt9DY3ICNymNrDDegqNeAtaTC2sYoUGQxe0dEbR7RjD+MTcAa1bE+G50wYu1WpCiJiMV7i4kqkWxG4/CJWNVIPhudMmJzRLK8iMV7jIkqk2wsN36SUZ3k1ZtWqCQRq7iTxVRKRpVKNpYb7mRUK/lsdMqIVeBpuIbgAU/AUpgRyw14MkoCfjY6ZcQq8nRqaI4XsVGRp9FT+ESssoCfjU4YseV0u6f95NVvVFq7yqv3dhCnMxuBmLpZMjONekBECwE70A54hJiwkGBKfXlmuuQ4H6JdHjH7z4doygU4A/58iPV7tLgVNFJUUYyKOm8Dk9JQ3nyIpiS5dDO3E//5EE0JXbU4zhz468PN8TbVaQPVT0d74ZeDvp7EYQPsT5jxp7G6yqQ7bCCgKttv2EBTIbY1DkyXF4t6h3cDJUAt6l/dh5K0XpE89zOvivh3mm9q6AxYYyfGVpEjuasjCB+ZWcFgmcFbCNMOmrWEdEaso2GOeOWJ1fJkTXlC2RixJuE2cQ90CY0Ra0ReU6zHhaz6Im4PdNK+iM30CIH9QI5X50nvuXaFf+zwXNvk+KqCN2HA11JHpNs0Ob6suLYKvTa5lop4a2ogImNudpIxra5ppl/Bbu9+A0+00znzp5cj43SkPZ8al5+xyA/V4SsNX3P929Lw2fNXT/aYneqJQPiaMJ7nCbrdCyHTqOctJ2xSet70O1YinmfV8xZ7HqHitV3S4JuaGdpbYAPAy5ZbL4YFnzJDWYE3rz4pghna7sEMDdijxbwdpKiiwDDO28DkviWQGdpS4Bfc7SSAGdoiCjGVGRr6bbufjmVAJSuQGSrghJlGifa77iTLDA2pynZkho7PNZypFzkxQxGKekpmaEfRuo17VSSAGdrZjXZibBU5zNBuKyORvxXwrnIR73IdhGTllrVEMEO7acIPm/IkJ2YoQnlCyQztFFwTwgztIHiN2eNCTsxQhEAnZYZ207DffiBHwszQNf7hpg8KamhH0YuNW+YXSg0dK4KsbSWAGtrnCPYIpYb2dvI8lM6UyooaGlCH7UkN7SGEKw23y40aiuB5lNTQfpqdlojnWfU8jtTQpo+GUeJBF7OthRW62HUkbK8gpZCOIn00kBLvNaLS14hVkQ7UKPEinUJbyT7SJQyA73OEDz1LYRFbvIXwLNWO8AznnNxoTl6VkwllKW2RI6jp6y/QBBgRI30a0mRzz2r1nrUq0gnJIG1B0Q+QW6S7zxd4M0tjjixti+TRvBB5TK5oHuGg1LaB6klno4mF3hVUEDXQDlTu8RuWKAVwsbISep99UoLQuy0WoBz4Qu/1e7RYhocUVSSQwvj7Myk/5Am9W7PgAEjeTvyF3q3Zf6YFvdAb+Vc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+7V1dc9u4kv01ftwtEQA/9DhJ7tyt+7F1a7JV+5hSZNpWjSL5ysoks79+KVmkJQCkSbC72SAwLzOjJHCE7gYap0+fvpMfv/3862H1/PTP/X25vROL+5938tOdEIkSWfWv0yd/vn5S5Or1g8fD5v7ym94++Lz5v/Ly4eLy6ffNffly8xuP+/32uHm+/XC93+3K9fHms9XhsP9x+9se9tvbn/q8eiyNDz6vV1vz0//d3B+fLt8iXbx9/l/l5vGp/snJ4vIrX1fr3x8P+++7y8+7E/Lh/M/rL39b1Wtdfv/L0+p+/+PqI/mXO/nxsN8fX//r28+P5fa0t/W2vf65X1t+tfl7H8rdsdcfkK9/4o/V9ntZ/5XPf7Hjn/VmnL7Ps7nw5Wf9UR6O5U+bVVZf6xXevlnlMeX+W3k8/Fn9vsufkpe9+PPWB368bbzILp89XW+6uny4uhj7sVn57QtX/3H5zvbv3+Prn61Znn7/4k5++PG0OZafn1fr06/+qLy/+uzp+K1a/1NS/efL8bD/vfGZ6kt/sGycbNm51h3KzC1JJNaWqPe3pNzd/3KKsur/dvtd6b4F5f1NHJobcPWNU8sXrj87lNvVcfPHbfTaNuHyE/6131R/lWZ/1a0HCm0XX/bfD+vy8meug0lbJute5rg6PJZHY5mzPZqv3MtEafAmSoBsZKwDZ6QsPCMlS5hAau4A9EjKLUbKttWufHjYn/9GD68nffXpv7+fLuUPH6vvsCkP1S/9d/nj7eOTYes0pv4suf7l7PHy7/PqX28cof5dp5/5H6/L/FL9hiR7/mku8fm3f6yO66d6peobftVXrz57/evXH2t+V107R5uzfdxv94c3Z3zYbLfaR6vt5nFX/e+6csFqE+SH0yW2qRKnXy6/8G1zf3/6MdaL8vYq9e5mLFqdxbCAg/e86w0Lmze8lMdWq9scBNwTDq+bPJkjtGeNNj/QTxIXN1giuoH1jzu6xqF83zm+Ht49O4LyIkI3qn8Uq+Nk//34/H3iE2VbPkzpCnUOIrRM0fQMheUZicUzAksdnRN8PXdEzPATwTaCv+z2MYptUUwYxtbHhbbP1NiaJV/GA9eSHjgFOLrW7DrPN0RCAQvUe8DkbPcNXkt6BO7MbdQUNMbia/o6gFayPcdnbiX/ALak/bXMFmH76+pY3UjGC3nGwBvzS7N2T1aJ9jyRtwGeQI+8CdvDOEJvs3CjJaEb8X23z+/NPvxqmRB568MHmXtO6QPyZiWp8IjgeSJvAFFMGcYUBBlmYewfQcbKkOGYza23+/XvMZvjWki18jK0jUXH2fMpgXYrJUHbAXigvWjZPB6YQb0w7h1QcL4D2APtkqLQzdtGHtzT0vZcnrmV/APape3p6ifQ/mm+ODvzO5Pjs/p+dVzNMafu7wr0QLu0PaDj02webkTpR5hP/Ii0j71cJkTaJQnHhndS6QPSLjk2vcwaaR8fxYRhnPZ4wRNzXKU0vz4e9FavQQq9pW17x+MZoShgnXoPmJztvkFvigLU4W0jD6A3RcFHYGYl/6A31Q6bjHwcvzyvdr3SJCu8ZiRqn37dbp5/3e6f38HWXn9srzfz9eMaPL/CAeG4356Y2EsE4VxdgR6EU5EfMV83ovSjdpGTqZ/w83u+D79cJgThFEULFfP00gcQTmFKjkQQDiWKKUG4HhjU8bBZ7R5bN+Rq/y1bDZlDN/uTmjm1LaWG2J8eWAcxSKkKSpAynULmstl1ns+s1PZoB7/7BKu7zzeQMqXg8fO2kQcgZUohacHMSv6BlCmg1CUqSPk/EaT04PbkSAs47h9PGe4M8aX+zkAPU6a+6GFGmHK4GxH6UX1+sTpSZgtTDr5eJoQpMxI+Ce8E0weYMhMWO/GI4JnClOOjmDKMe6BQ0DClcxY9AUyZc+hjvv36GSmXMptCLzTn3ZKVUYArOS+evG8wZUbRy8DbRh7AlBlFsZuZlfyDKTNAvVBUmPJvf484Jf/rs5ZlYfUk+dsMsaUBfkAPUea+6IYGD1E6uBGlH/EFOOYHbgy/WSaEKHOKRh3myaUPEGU9h5phBM8TogSIYsow7oFAAUOU7gn0FBBlRKM8mIySc2z4+HvMVu9IVe6XPURBqWVRabUZao41aT2h2XaegEhBUUuv94DnCc6+nlDYnplh2ciDekJB8eRjZiX/6gmFt9oMbzjfv27GCb19/nFbrg5BVx+4X7ZRyoEsFx/gCvQFiCJKOczXjSj9iOPLfq4FiOGXy4QFiIKC3cI8G/WhAFFEKQfvopgwjGuPJixAuOfQExQglpTw1evxcfksZXX0aXBJ5njwZd3LwB17SxukNfWx93x+V3/ZxTT2yjEpKhOUyNlNELMe2VjABLG+DGAQcyRPrE8gWIzh86/mhDHcR5plu908v/TIU1Yvz+X69Jd72Pw8bcjNVt8J+XD+Byh7SW/DJSVMXijYE/WGvIZ9TF4gzr0+/T0++HpO6OuUeMSNr8c7foyvN9AHJ9oIrVpesujxyATnjbxtPM9aVrKwPeGgI7rZBZ7hy546kiwo3lbMreQBeSRZ2N5Sc7eTf/SRZNFewufFHzFk8yJ/5P0nNv9Ll+MAzdnq7A1xB3oSSbLArP5HFsnEjkTqSRzlO+fKI3G4ZCYkkiSLHn0js89MfaCSNCcGwyieJ5cEIpIpQznpAWQBs0lGZNQT0EmShBTUuq5FJ0nG6gT0rSiTJDaka+rTb8aUEoeclpBTkiSkgNptJLNuWOdfcko4tsnMl1fiEMiExJLmXpy62u6QyUxHLUkSCg3SZkuuC+4xkRl7/PWhSnjh8IT8kiQhhSluHT7e96McXvWoUVNTTGiVzpP6G9NSTJqNZ1rtEiTkhXoXeIYvf4qJIHlp8baSDxQTQTE9k5udPKSYiPYaPy+KiSl5HjkmPZ7b7G9djqICc9RIH+IJE9BLBCYpINJLJnYkUk/iK3Iww6L08PtlSnpJ7XRBZ6Ve0Esk5tSMSC/BiWTSUO4BYkHTS9yT6SnoJZIU0LopSsvYBznu9OModjBnesnwnJayKi1JwbTbSOaluubfPIREcuyimTHBZHgoE85FaG7Gyevtw3OZCevtkkLQodmSm3p7TGVGHn99qBJeOPyS0OFrM0/h8PHGH+nyikInkhvK5B3zTdkAhKnzsjkOqnLIyCi5+9apjNrOYhPCNCAtXy7/07xsMhuWlugR4nbdoAlNjCu2ncZFfPn6/eUu/SDu0k/jy26eREzjk71zlUQ/OG0eZDv+QWJIobFIwPwnif4zxH8Urf/0eBXDM1KH71KT5Vy/AaxEXZhjmYRmXm8Dk0RSvwxl44mD65XqvZUA08n62wdlK7W43WHn15kySAF4iX/aXlrmRXn8rXzcvBzLg7Jn/6FQGNkf02l7MziX7GcRs58h2Y8gzX7S9movNbWlh7eAOwEKm2W4DyipZQvmGVKgeQBJgZdZ8qAneilYomeuBJk+jBXSZ2yZhqYEZgrLUpC2IGk852KdlrjJwYxlrgRpK5IaLnNbLcFsZa4Eaat2Dj2XjFbGjHZIRluQZrT1D5/zHQl3RWJGcsaRR9+E8fxY9AMi1UhWrxw3R4tMEeAtrMOUeueqK0qprwMZtyTkfeZ2ciWR6HZCZJFkPdgDs7eTKwtRtxMiDTEDZDiAYGyd9ejZ3XUtGJuF54OGsWWAHAUQD+hktITiAZY2GjwPaNeamMYDOt+woXiApfsCzwPGYlD+3c3OWlHvSINB3s1jaS7+WcVdwus9LTBAu9RnMyvs4OoAnSFVevhxmupakuZxigYm5CSNDsxC2VA9cEUTDBwQEU7IxfuWglZLGMHbqXdEErZc5WgsnrbDElGBysYUi+WQa88yj0msaojooxZN3GGytLy7rP0lBsbpFlv8+wNC6i9588gR/SVk8ZPkgO/22F3CwXsUpff0ePOD95Y47FFv0jLQkUzRW9JsA9Pcve51H99ZcrsOYOZeY2FB2UmHS9xpU3qJCZU2VfjWWVJ0vRdm31nC/5AubM92XplPSJ0lAJmPIMx8CkBEI/aVuHqAXu+y9hahVbwKCn4Kt/TB7CyBSfP0dSBTh7EdQIyt0lQQgYByYyFIO4zt7plDvORA8aKvA2knis4f7nZaAtlJXwfSTu1zPbhksCF1kgBksAVlBgvPDGET0033B0wM6+sAxnDN0GLFA5lvD8mQGNXlUihYH0sK1gebMG1BJN1ViXREElWVaGkDkEKzlbuwgG4rVGGBJUXLD3dbuTez67ZCbWZf2mCV2E4yMbRmFS1Eg9aW3FqK/G8oAfABq/Apng9wayryv6UEwAesYgd4PjAWivLvlnYXPzD6F1Bvafh2H+6WcQbZzX4fPJC9xhtZAQqzbixxOFT1xpLaaAQQQ+N7QT2FdHTfWMK5XqYvBBfKVTC9byngxpIxtJ16R5LMcGasxhKxsGEwsbFkHqekwe9JEsOz0BpLFvyFh7NYXBviPgkhM14sAEEsJPdJo/sMch9CeqFYUIgWc0/SErD6LV4BVyz4t9+pGOiDAn1BGeiRayXe5mKODnS8ZiGxoNBYZm8pKLqvsRCkpWL73VUT4mhL4TFNGwyA8eWZx8tz0OVJ2Lze4AFBBbpRL4JSCDUWggx0ARfoILXczpwYPFqZ1nKT+vwlKOVWuVkMVndtOiNY8bTpRBJiX5thKSghc0TpsSqLjpYyBw06WwpPy7wpirG5ADvR32AuQMJBdNVDipkLdNaPgnEBQp30KsVm5gKdr9tgXIBQKF3KHoAvsWBhklliAE+xUFipg7xQn5AUC99cckxtlHAEmujgOHJxoJBECyEcaEHpQLIPBxJct9Bhm2glsWQfwuHo52SzDUyek36OEZVW5uPcbWU8/V0Z+cbTH4+RL/GYhMDKhZ+fNg9H83aqBQ3V1TVl8FTv5i5o6MHpzZ9yGJKgIUBWRDpYWFo5h1HSkNgHdHCCEKGUVi7j3HMKC+sUbPo0ZgemHE0dZGybN+4RmC0wNSskCTmQjXXaaZxg1sJU7pEkBEH21nKX7rGQORGt5QFJMCSZQwi0zyomg5bYjqYJMg7u0dJOpq4sZiiL1lA2EIWodkgaqmbKSiBGIElIgWyCtQXFhGKa4RHNJAklkLudoHhmeDQzSUII5G4nKEI8Hh9esqMD+q9xCIC1EVLBJDs2oP8KhwAeQMkEY0cG9F/fEMADlpQeMBaH8u9udu1/MSX00O7meumArOLclmRITmLapX0C5HTgwayVDR2OU13ZMDOPUzQwoY7ToB4/prKhYyibyoaIodwD9gFWNhzD32n050xkDEvZUAo0Nk/bYRmVDScriAhLIzZaOUSEiBEZxyTUKYl4SDJVFjPOkXJ3bjzqZofGmuh7HRCEJwCF6Bj3E8C16qKfAIhVF8G0Uc44AdbbcnX4sotHwKgjwEL1xDsCIgXKvaCnHwGIBb3aJ9gfAS+n5pEv2/3qPp4Co04BSxEK7RSQseFPuI91IZydLqXw5Bw4s6leysNmtY0HwbgXgaUUhXcSADYpgvnSBVx38CZwJ2FaraQUMJIyksD80IWTMsRGLpXoseE+71ZbCrWT36pmohmLWhFoaRl6blUEkjAnC39Bl6AUgRqX9EQRSNauydiBglIEAnAgWkUg1eMlDK8INHybemtKwBzMyvbsBE8k6m1gkkh4qgikSHppmNnKRzV8qdC4HbSKQMU7b/KZKwLxP70BFV2iIhCHrIhWEUhx61KagSLQcB+YUhFIkTBFmOUU3ioCqbEqNIxtU9fYoGr2mEV7ZYOzgosaX9SA6u8ftrV8UQNK27uAuOS0QakBASB9tGpAqZj9JemJGlDazjkw0ISoBkQaqvpELIr2vZSEXsAlVP3VAkpJ+oeY28kDLaCUhATC3E4eaAGl3JRgZqAFNB5lo9QCSrkpwcxAC2i8B1BqAaWABKg4GBDKA0gHA9aZwBzfpf6KAWUI2sHsrQJmFkS72FCcqbGDeYsBDT9PdTGgxMIqRoMTshDpUDqsL6F624yFIGO5B/ADrQY0grtTn25LQjWgDI3J03ZaRjWgyQoiNg1KtHJIFiJK5KEaUAaIEkU1IO5HAKUaUEYyu4r5CeCBGlDGtEnOOAGiGhDEEUCpBlQ/woI+AjxQA8qZkp+MIyCqAQGdApRqQLkNUwvtFHCuGBtvAcSScY42Uj6qATE9CGzlSLyTALBBMaoBkdUrbc9GtHplHmlgI9T2dX4RJnSUhwjx6RI+wr2JyxAWQmVF50yBvqsGhyw2OAy6uinRvJypZvSV+6TRfYa4D6kOZB5bF0eIiBitcIhvwHppxoGuYqAPCnTKJ15BIv3MPNC9kH4uRLQUYIke8aFVRMqZgCulYtZSC0CAC+ny7GTgx8vTeGRR1ksLQDpeHN3s6gI6/GkVx0LDP4sgUTUN/3SXxtQBUFRpzCJEGStDGnMEAvq+IhaktUIkpBnWGqFe/74SE6S1uLUudqIOodyFdvlstMuwhijZOEEnxhyME1hF+PGcIN6yV++S0ac2Io9wyU1woLOiGEy4EmpOpIse+C/x1BnrG946dUbpdRWXLVDWLeAFAoU0debNJT2ZOqMWgr0DhTR1BsKBSKfOqEWPggH41BmHbeo9twDoYO7RED46kWy2gUki6efUGbWgoIFys5We9Eso2UZjIUhLAU5zmHLqTJJd3VM28ve8x854cHzzZ7CGNHYGIC0iHTujFtzQCf/Hzjj4wIRjZ9SCgoXKLanwdexM0x4BqJHHxja1rAMU/cxYCNIOFJRONpbxfOyMSmzgUXDW8mTsjEqYdlwHOnYGAuojHTujkrGYFuPg9mrsjErayZsGmhDHzpCGqs78JtCJVQkFj5NNqHo7dkYlFOwS7nbiP3ZGJRTsTe524j92RiXceJv+j50BQNkIKUCNr7HxAP/HzgB4AOHMESVsiNGkZ4D/vF0IqJ0Sa6+v5zk+TL2dO6PE2FZi/6wiXZNb3SzGQpB2aW8cng48mPXcGYfz1Jg7U5jnKRqeIEIkRBly6lBiysZCkLHcA/kBnjszhrxT70hKN3dGCTQqT9tpGefOTFYRUYRi00qECBP5N3dGCUCYKM6d4X4EECpVNo/eoE8A/nNnlGTaJmecAHHuDMQRQKijpORY7GkORwD/uTNKMmU/GUdAnDsDdApQPgVkbPerdgEsE8BMBdDG0Ma5M0wPAkWaDwC2KMa5M3T1SsqatYw8sCv199ENx4gMIxkixKcPi5HurGhjKdR+FMkU6At07gzA1U2K5tVZJ2P3CWnuDAQWTDh3RqnYu+jH3BmlBPtAD2nuDESgE86dUYpiRgb3QPdh7oxSEZbzY+6MUpFy5sfcGaXQNLji3JmJHlmU+KgCpOPFuTOuLjDp3BmlgkTVvJw7o1SIOla+zp1p6K9hW8uTuTMq5da76P/cGYC7kHbujEoFMyeI/at31HNnVBoipOTj3BmVtndPxrkz04UrpehEypRCdj0zI6pDd/qPAYFQFgpT/gjaMrrPIPehLD+lIbLHDKgcquUAs+cgBVSBRwr0Igb6oECnbCpIQ4TejECHIpRgCtHVXhK0pSQUI8BYCNJSkaRVbTAUI8BYCNJSgv3lmcTRhINuT0nJ5s2YNnxe+09k+Q3zn3xBqXefAUJ9WB4UJyYM86CU1oMiq+08EBJqqIJlKciMgz8ul8Rp2sPiXdLGe4TmztqlYPFuLgUZ7yHS0AxrFXDWMpeCtFZEw84lcyhrWZYCtFZdEOF8l8ZmymF36ZL0Li0Aq+wgRIvOrgJwL+BKtKDUySjiXKsRHbUGKwqxAFKEmPiaMxmALIXZElmEmPQalnItgBiWQiyAFNymW3VyBYK5AC1MMbQLcAmYRYO4QCcvLBQXsInS4LkAtx6RbmppMD5A2x+wFPHWPr1Aofq6LEsB3tzL2M1xosrBWctcCtJatjJvcNYaofGnWwt19PmSGyzUTQIK5j5UtPchA5XdWy+Ig19Pts1ovSCiTiNot4aOLiLqtATshICJ1yj7cmdve8OL1hALuEa0QiGPiNTrtP4784nWKExxZ6dPY0VruuiBODxWX/q55VuJxXq/25Xr43mk3fnzhbkr3RugF7CaD642oJmcfL0DSr/KXLag+SKMOQxh0QFFi6/1pjDUHCIC/oIQtgDi5T1hta+M9h5F6T09IMTbr/zObOd+ydPgPWpYZdejnDO8I5kGq7ssyiSHNCiby9sVnPma2jpwGaQgmiDPy05+KjwK6wx5kIvq5Xm163VRZb2mWP1WPm5ejuUhya7uoq+W++n15w6ekwZ+ka0rV612afqbjPqUBtT4RUp9wtJHGp36CMrUhxtWOAfCw2APMKFCQmS/8beg8gc9z0uB8jx9HcDcoXYSZzsxtkrTMuycxhkJNyaPQViH3IcWMzlQzOjrQNpJRDuJJZCd9HUg7cRfQCQs9YfRWWxBmMWOngjPOKYbKjxMDOvrQMZwO1vMAA7IHhdNAHdH7i24Mbt3RtNQaAZljhaUNA2FTMK0jYIABktikqgF0ZB03raC41DjPj1omgp52wqOQY1JoBaQQ9JhyD0RXiOmTwvISecgPjAH9vRoHyAlTwvruPI4iHFiHyAdxCisg9Bn8khtk9NwvqUz49mKeEuPnjHun2Wk60gH3TDGQpB2scE6UwMKV8fopJACF9wvzbVIpcQYiCaZ84pli6qgWyxbNAXxYrkHGnQ8bFa7x1bnvTKbJS5AnNnYkdxMEBKLZRMQZ0Zj8rSdlo5H4Hq7X/8+6PSL5RGLvLrhWWj1EesMcF7Vtc7JitF9dPdJKPnx1rHkvNwnLHnR8e5DyTEkmpPOO0lLwAq4iBVcyBnpSIEe1hSX8YG+oAx0YXGf4AIdqmPIWAgy0GlEs5hbCorzaywEaanYhHeFKY22FCLV1INJ5Z2q6vHyNC5PyhZ266DyuQe6j/rrwjoTfMpi7hwEWwYHq6EVTSjYIqzDxoMLVih5JWMhyGANsbnNsJSCspS+EKCliOZ6M7eUa13esBRiXd4613vKC7AT/Q3mApSEFyDkwHAQF+isHwXjAimlCwC27MWZYWAuQDgzTPgwtDuKj3T6jyE+YrlF0DAP68huXv7TOYQnuo/hPpZXOJ77hAiZ6di48yA8HRtHHIQnrLO6eQV658C1GOgGNm5RM8cL9BDhNiPQXeE2I9AR4TaiweHMLeUKtxmWQoTbrEPDg7OUK9xmWAoRbsv5s7K65zLF29NIky1ADdrtmQv+/hNpfYP8xzadAs9/+GtzdU8Yiv5jSsxS+k+ksIk3EHZ0poHIbMn543Hds/9ipBuRTtlnlkdAbsSMQKP5FBGQy0MU/DIsBYWoIM6HE3nEvk4Cn1CWwkRU+LdJJrFPctDtKSmroXViF1SkG7PRoQhwmIhcwY0A11m8Ao9WrtQXwgG7ohAWFwguWKHGYWPWnosQex0NS0Fx9TGLh0WIQJFhKSiuPmbxsAAEikAuwE6aVigXoI18hXcBAk4yhJE2jqPD7uz8TTwf4NYJ2V2HDsYHKNsAihDxKUNOVS3A5jyYS0Fe3OwE6aMa+d25SkMpRV0/lIOO2Wp7oWLWshRgzC5DnDVonLALuBPWXArSWiJa61QQA7OWuRSktbg1MXYzmYK5D5e09yFgHyOMF0RJl7szy5HUC7iBWt3V2mC8QCJ6QfW/h/3JAm8XSPXFnv65vy9Pv+P/AQ==
\ No newline at end of file
diff --git a/docs/index.rst b/docs/index.rst
index c377826..4d8ccee 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -1,3 +1,17 @@
+.. toctree::
+ :hidden:
+
+ api
+ arithmetic
+ changelog
+ gate
+ install
+ logic
+ signal
+ storage
+ wire
+
+
=============
About Bitwise
=============
@@ -40,7 +54,7 @@ Interacting with it in a Python session::
In [2]: b.value = 0
- In [3]: sum.value
+ In [3]: sum_.value
Out[3]: 0
In [4]: carry_out.value
@@ -48,7 +62,7 @@ Interacting with it in a Python session::
In [5]: a.value = 1
- In [6]: sum.value
+ In [6]: sum_.value
Out[6]: 1
In [7]: carry_out.value
@@ -56,7 +70,7 @@ Interacting with it in a Python session::
In [8]: b.value = 1
- In [9]: sum.value
+ In [9]: sum_.value
Out[9]: 0
In [10]: carry_out.value
diff --git a/docs/signal.rst b/docs/signal.rst
index 7664be0..5184dde 100644
--- a/docs/signal.rst
+++ b/docs/signal.rst
@@ -578,7 +578,7 @@ Args:
* ``select``: An object of type ``Wire``. The select input.
* ``input_1``: An object of type ``Wire``. The first data input to the multiplexer.
* ``input_2``: An object of type ``Wire``. The second data input to the multiplexer.
-* ``output``: An object of type ``Wire``. The output of the multiplexer, which takes on the value of ``input_1`` for a 1 select and ``input_2`` for a 0 select.
+* ``output``: An object of type ``Wire``. The output of the multiplexer. Takes on the value of ``input_1`` for a 1 select and ``input_2`` for a 0 select.
.. _Multiplexer4To1:
@@ -617,7 +617,7 @@ Args:
* ``select_1``: An object of type ``Wire``. The most significant bit of the select input.
* ``select_2``: An object of type ``Wire``. The least significant bit of the select input.
* ``input_bus``: An object of type ``Bus4``. The data input to the multiplexer.
-* ``output``: An object of type ``Wire``. The output of the multiplexer, which takes on the value of ``input_bus[0]`` for a (1, 1) select and ``input_bus[3]`` for a (0, 0) select.
+* ``output``: An object of type ``Wire``. The output of the multiplexer. Takes on the value of ``input_bus[0]`` for a (1, 1) select and ``input_bus[3]`` for a (0, 0) select.
Raises:
~~~~~~~
@@ -662,7 +662,7 @@ Args:
* ``select_2``: An object of type ``Wire``.
* ``select_3``: An object of type ``Wire``. The least significant bit of the select input.
* ``input_bus``: An object of type ``Bus8``. The data input to the multiplexer.
-* ``output``: An object of type ``Wire``. The output of the multiplexer, which takes on the value of ``input_bus[0]`` for a (1, 1, 1) select and ``input_bus[7]`` for a (0, 0, 0) select.
+* ``output``: An object of type ``Wire``. The output of the multiplexer. Takes on the value of ``input_bus[0]`` for a (1, 1, 1) select and ``input_bus[7]`` for a (0, 0, 0) select.
Raises:
~~~~~~~
@@ -703,7 +703,7 @@ Args:
* ``enable``: An object of type ``Wire``. Enables the multiplexer.
* ``select_bus``: An object of type ``Bus4``. ``select_bus[0]`` and ``select_bus[3]`` are the most and least significant bit, respectively.
* ``input_bus``: An object of type ``Bus16``. The data input to the multiplexer.
-* ``output``: An object of type ``Wire``. The output of the multiplexer, which takes on the value of ``input_bus[0]`` for a (1, 1, 1, 1) select and ``input_bus[15]`` for a (0, 0, 0, 0) select.
+* ``output``: An object of type ``Wire``. The output of the multiplexer. Takes on the value of ``input_bus[0]`` for a (1, 1, 1, 1) select and ``input_bus[15]`` for a (0, 0, 0, 0) select.
Raises:
~~~~~~~
diff --git a/docs/storage.rst b/docs/storage.rst
index e318e4e..cdcb1ff 100644
--- a/docs/storage.rst
+++ b/docs/storage.rst
@@ -3,3 +3,882 @@
=======
Storage
=======
+
+
+.. _DFlipFlop:
+
+DFlipFlop
+=========
+
+Class ``bw.storage.DFlipFlop``
+------------------------------
+
+.. image:: images/schematics/storage/DFlipFlop.svg
+ :width: 360px
+
+Defined in `bitwise/storage/FLOP.py `_.
+
+Positive edge-triggered `D flip-flop `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ data,
+ clock,
+ output,
+ output_not
+ )
+
+Construct a new positive edge-triggered D flip-flop.
+
+Args:
+~~~~~
+* ``data``: An object of type ``Wire``. The data input to the flip-flop.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the flip-flop.
+* ``output``: An object of type ``Wire``. The output of the flip-flop. Takes on the value of ``data`` on the positive edges of ``clock``.
+* ``output_not``: An object of type ``Wire``. The complemented form of ``output``.
+
+
+.. _DFlipFlopPresetClear:
+
+DFlipFlopPresetClear
+====================
+
+Class ``bw.storage.DFlipFlopPresetClear``
+-----------------------------------------
+
+.. image:: images/schematics/storage/DFlipFlopPresetClear.svg
+ :width: 360px
+
+Defined in `bitwise/storage/FLOP.py `_.
+
+Positive edge-triggered `D flip-flop `_ with asynchronous active low preset and clear.
+
+__init__
+--------
+
+::
+
+ __init__(
+ data,
+ preset_n,
+ clear_n,
+ clock,
+ output,
+ output_not
+ )
+
+Construct a new positive edge-triggered D flip-flop with preset/clear capabilities.
+
+Args:
+~~~~~
+* ``data``: An object of type ``Wire``. The data input to the flip-flop.
+* ``preset_n``: An object of type ``Wire``. Presets ``output`` to 1 and ``output_not`` to 0 if its value is 0.
+* ``clear_n``: An object of type ``Wire``. Clears ``output`` to 0 and ``output_not`` to 1 if its value is 0.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the flip-flop.
+* ``output``: An object of type ``Wire``. The output of the flip-flop. Takes on the value of ``data`` on the positive edges of ``clock``.
+* ``output_not``: An object of type ``Wire``. The complemented form of ``output``.
+
+
+.. _GatedDLatch:
+
+GatedDLatch
+===========
+
+Class ``bw.storage.GatedDLatch``
+--------------------------------
+
+.. image:: images/schematics/storage/GatedDLatch.svg
+ :width: 360px
+
+Defined in `bitwise/storage/FLOP.py `_.
+
+`Gated D latch `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ data,
+ clock,
+ output,
+ output_not
+ )
+
+Construct a new gated D latch.
+
+Args:
+~~~~~
+* ``data``: An object of type ``Wire``. The data input to the latch.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the latch.
+* ``output``: An object of type ``Wire``. The output of the latch. Takes on the value of ``data`` if the value of ``clock`` is 1.
+* ``output_not``: An object of type ``Wire``. The complemented form of ``output``.
+
+
+.. _GatedSRLatch:
+
+GatedSRLatch
+============
+
+Class ``bw.storage.GatedSRLatch``
+---------------------------------
+
+.. image:: images/schematics/storage/GatedSRLatch.svg
+ :width: 360px
+
+Defined in `bitwise/storage/FLOP.py `_.
+
+`Gated SR latch `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ set_,
+ reset,
+ clock,
+ output,
+ output_not
+ )
+
+Construct a new gated SR latch.
+
+Args:
+~~~~~
+* ``set_``: An object of type ``Wire``. The set input to the latch.
+* ``reset``: An object of type ``Wire``. The reset input to the latch.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the latch.
+* ``output``: An object of type ``Wire``. The output of the latch. When the value of ``clock`` is 1, takes on the value of 1 if the value of ``set`` is 1 and the value of 0 if the value of ``reset`` is 1.
+* ``output_not``: An object of type ``Wire``. The complemented form of ``output``.
+
+
+.. _JKFlipFlop:
+
+JKFlipFlop
+==========
+
+Class ``bw.storage.JKFlipFlop``
+-------------------------------
+
+.. image:: images/schematics/storage/JKFlipFlop.svg
+ :width: 360px
+
+Defined in `bitwise/storage/FLOP.py `_.
+
+Positive edge-triggered `JK flip-flop `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ J,
+ K,
+ clock,
+ output,
+ output_not
+ )
+
+Construct a new positive edge-triggered JK flip-flop.
+
+Args:
+~~~~~
+* ``J``: An object of type ``Wire``. The J input to the flip-flop.
+* ``K``: An object of type ``Wire``. The K input to the flip-flop.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the flip-flop.
+* ``output``: An object of type ``Wire``. The output of the flip-flop. On the positive edges of ``clock``, takes on the value of 1 if the value of ``J`` is 1, takes on the value of 0 if the value of ``K`` is 1, and toggles its value if both ``J`` and ``K`` have value 1.
+* ``output_not``: An object of type ``Wire``. The complemented form of ``output``.
+
+
+.. _JKFlipFlopPresetClear:
+
+JKFlipFlopPresetClear
+=====================
+
+Class ``bw.storage.JKFlipFlopPresetClear``
+------------------------------------------
+
+.. image:: images/schematics/storage/JKFlipFlopPresetClear.svg
+ :width: 360px
+
+Defined in `bitwise/storage/FLOP.py `_.
+
+Positive edge-triggered `JK flip-flop `_ with asynchronous active low preset and clear.
+
+__init__
+--------
+
+::
+
+ __init__(
+ J,
+ K,
+ preset_n,
+ clear_n,
+ clock,
+ output,
+ output_not
+ )
+
+Construct a new positive edge-triggered JK flip-flop with preset/clear capabilities.
+
+Args:
+~~~~~
+* ``J``: An object of type ``Wire``. The J input to the flip-flop.
+* ``K``: An object of type ``Wire``. The K input to the flip-flop.
+* ``preset_n``: An object of type ``Wire``. Presets ``output`` to 1 and ``output_not`` to 0 if its value is 0.
+* ``clear_n``: An object of type ``Wire``. Clears ``output`` to 0 and ``output_not`` to 1 if its value is 0.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the flip-flop.
+* ``output``: An object of type ``Wire``. The output of the flip-flop. On the positive edges of ``clock``, takes on the value of 1 if the value of ``J`` is 1, takes on the value of 0 if the value of ``K`` is 1, and toggles its value if both ``J`` and ``K`` have value 1.
+* ``output_not``: An object of type ``Wire``. The complemented form of ``output``.
+
+
+.. _ParallelToSerialConverter4To1:
+
+ParallelToSerialConverter4To1
+=============================
+
+Class ``bw.signal.ParallelToSerialConverter4To1``
+-------------------------------------------------
+
+.. image:: images/schematics/storage/ParallelToSerialConverter4To1.svg
+ :width: 600px
+
+Defined in `bitwise/storage/PISO.py `_.
+
+`4-bit-parallel-to-serial converter `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ enable,
+ clear_n,
+ load_n,
+ data_bus,
+ clock,
+ output
+ )
+
+Construct a new 4-bit-parallel-to-serial converter.
+
+Args:
+~~~~~
+* ``enable``: An object of type ``Wire``. Enables the converter.
+* ``clear_n``: An object of type ``Wire``. Clears all 4 internal registers to 0 if its value is 0.
+* ``load_n``: An object of type ``Wire``. The mode select. A value of 0 indicates a parallel load operation, where the values of ``data_bus`` are loaded into the internal registers. A value of 1 indicates a shift-right operation.
+* ``data_bus``: An object of type ``Bus4``. The parallel data input.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input.
+* ``output``: An object of type ``Wire``. The serial output of the converter. ``data_bus[3]`` is outputted first, and ``data_bus[0]`` is outputted last.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If ``data_bus`` is not a bus of width 4.
+
+
+.. _ParallelToSerialConverter8To1:
+
+ParallelToSerialConverter8To1
+=============================
+
+Class ``bw.signal.ParallelToSerialConverter8To1``
+-------------------------------------------------
+
+.. image:: images/schematics/storage/ParallelToSerialConverter8To1.svg
+ :width: 600px
+
+Defined in `bitwise/storage/PISO.py `_.
+
+`8-bit-parallel-to-serial converter `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ enable,
+ clear_n,
+ load_n,
+ data_bus,
+ clock,
+ output
+ )
+
+Construct a new 8-bit-parallel-to-serial converter.
+
+Args:
+~~~~~
+* ``enable``: An object of type ``Wire``. Enables the converter.
+* ``clear_n``: An object of type ``Wire``. Clears all 8 internal registers to 0 if its value is 0.
+* ``load_n``: An object of type ``Wire``. The mode select. A value of 0 indicates a parallel load operation, where the values of ``data_bus`` are loaded into the internal registers. A value of 1 indicates a shift-right operation.
+* ``data_bus``: An object of type ``Bus8``. The parallel data input.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input.
+* ``output``: An object of type ``Wire``. The serial output of the converter. ``data_bus[7]`` is outputted first, and ``data_bus[0]`` is outputted last.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If ``data_bus`` is not a bus of width 8.
+
+
+.. _ParallelToSerialConverter16To1:
+
+ParallelToSerialConverter16To1
+==============================
+
+Class ``bw.signal.ParallelToSerialConverter16To1``
+--------------------------------------------------
+
+.. image:: images/schematics/storage/ParallelToSerialConverter16To1.svg
+ :width: 600px
+
+Defined in `bitwise/storage/PISO.py `_.
+
+`16-bit-parallel-to-serial converter `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ enable,
+ clear_n,
+ load_n,
+ data_bus,
+ clock,
+ output
+ )
+
+Construct a new 16-bit-parallel-to-serial converter.
+
+Args:
+~~~~~
+* ``enable``: An object of type ``Wire``. Enables the converter.
+* ``clear_n``: An object of type ``Wire``. Clears all 16 internal registers to 0 if its value is 0.
+* ``load_n``: An object of type ``Wire``. The mode select. A value of 0 indicates a parallel load operation, where the values of ``data_bus`` are loaded into the internal registers. A value of 1 indicates a shift-right operation.
+* ``data_bus``: An object of type ``Bus16``. The parallel data input.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input.
+* ``output``: An object of type ``Wire``. The serial output of the converter. ``data_bus[15]`` is outputted first, and ``data_bus[0]`` is outputted last.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If ``data_bus`` is not a bus of width 16.
+
+
+.. _Register4:
+
+Register4
+=========
+
+Class ``bw.storage.Register4``
+------------------------------
+
+.. image:: images/schematics/storage/Register4.svg
+ :width: 800px
+
+Defined in `bitwise/storage/REG.py `_.
+
+`4-bit storage register `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ data_bus,
+ clock,
+ output_bus
+ )
+
+Construct a new 4-bit storage register.
+
+Args:
+~~~~~
+* ``data_bus``: An object of type ``Bus4``. The data input to the register.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the register.
+* ``output_bus``: An object of type ``Bus4``. The output of the register. Takes on the value of ``data_bus`` on the positive edges of ``clock``.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If either ``data_bus`` or ``output_bus`` is not a bus of width 4.
+
+
+.. _Register8:
+
+Register8
+=========
+
+Class ``bw.storage.Register8``
+------------------------------
+
+.. image:: images/schematics/storage/Register8.svg
+ :width: 800px
+
+Defined in `bitwise/storage/REG.py `_.
+
+`8-bit storage register `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ data_bus,
+ clock,
+ output_bus
+ )
+
+Construct a new 8-bit storage register.
+
+Args:
+~~~~~
+* ``data_bus``: An object of type ``Bus8``. The data input to the register.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the register.
+* ``output_bus``: An object of type ``Bus8``. The output of the register. Takes on the value of ``data_bus`` on the positive edges of ``clock``.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If either ``data_bus`` or ``output_bus`` is not a bus of width 8.
+
+
+.. _Register16:
+
+Register16
+==========
+
+Class ``bw.storage.Register16``
+-------------------------------
+
+.. image:: images/schematics/storage/Register16.svg
+ :width: 800px
+
+Defined in `bitwise/storage/REG.py `_.
+
+`16-bit storage register `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ data_bus,
+ clock,
+ output_bus
+ )
+
+Construct a new 16-bit storage register.
+
+Args:
+~~~~~
+* ``data_bus``: An object of type ``Bus16``. The data input to the register.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the register.
+* ``output_bus``: An object of type ``Bus16``. The output of the register. Takes on the value of ``data_bus`` on the positive edges of ``clock``.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If either ``data_bus`` or ``output_bus`` is not a bus of width 16.
+
+
+.. _SerialToParallelConverter1To4:
+
+SerialToParallelConverter1To4
+=============================
+
+Class ``bw.storage.SerialToParallelConverter1To4``
+--------------------------------------------------
+
+.. image:: images/schematics/storage/SerialToParallelConverter1To4.svg
+ :width: 600px
+
+Defined in `bitwise/storage/SIPO.py `_.
+
+`Serial-to-4-bit-parallel converter `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ enable,
+ clear_n,
+ data,
+ clock,
+ output_bus
+ )
+
+Construct a new serial-to-4-bit-parallel converter.
+
+Args:
+~~~~~
+* ``enable``: An object of type ``Wire``. Enables the converter.
+* ``clear_n``: An object of type ``Wire``. Clears all 4 internal registers to 0 if its value is 0.
+* ``data``: An object of type ``Wire``. The serial data input.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input.
+* ``output_bus``: An object of type ``Bus4``. The parallel output of the converter. ``output[0]`` corresponds to the most recent serial data input.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If ``output_bus`` is not a bus of width 4.
+
+
+.. _SerialToParallelConverter1To8:
+
+SerialToParallelConverter1To8
+=============================
+
+Class ``bw.storage.SerialToParallelConverter1To8``
+--------------------------------------------------
+
+.. image:: images/schematics/storage/SerialToParallelConverter1To8.svg
+ :width: 600px
+
+Defined in `bitwise/storage/SIPO.py `_.
+
+`Serial-to-8-bit-parallel converter `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ enable,
+ clear_n,
+ data,
+ clock,
+ output_bus
+ )
+
+Construct a new serial-to-8-bit-parallel converter.
+
+Args:
+~~~~~
+* ``enable``: An object of type ``Wire``. Enables the converter.
+* ``clear_n``: An object of type ``Wire``. Clears all 8 internal registers to 0 if its value is 0.
+* ``data``: An object of type ``Wire``. The serial data input.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input.
+* ``output_bus``: An object of type ``Bus8``. The parallel output of the converter. ``output[0]`` corresponds to the most recent serial data input.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If ``output_bus`` is not a bus of width 8.
+
+
+.. _SerialToParallelConverter1To16:
+
+SerialToParallelConverter1To16
+==============================
+
+Class ``bw.storage.SerialToParallelConverter1To16``
+---------------------------------------------------
+
+.. image:: images/schematics/storage/SerialToParallelConverter1To16.svg
+ :width: 600px
+
+Defined in `bitwise/storage/SIPO.py `_.
+
+`Serial-to-16-bit-parallel converter `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ enable,
+ clear_n,
+ data,
+ clock,
+ output_bus
+ )
+
+Construct a new serial-to-16-bit-parallel converter.
+
+Args:
+~~~~~
+* ``enable``: An object of type ``Wire``. Enables the converter.
+* ``clear_n``: An object of type ``Wire``. Clears all 16 internal registers to 0 if its value is 0.
+* ``data``: An object of type ``Wire``. The serial data input.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input.
+* ``output_bus``: An object of type ``Bus16``. The parallel output of the converter. ``output[0]`` corresponds to the most recent serial data input.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If ``output_bus`` is not a bus of width 16.
+
+
+.. _ShiftRegister4:
+
+ShiftRegister4
+==============
+
+Class ``bw.storage.ShiftRegister4``
+-----------------------------------
+
+.. image:: images/schematics/storage/ShiftRegister4.svg
+ :width: 800px
+
+Defined in `bitwise/storage/SHIFT.py `_.
+
+`4-bit shift register `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ enable,
+ clear_n,
+ shift_load,
+ data_bus,
+ data_serial,
+ clock,
+ output_bus,
+ output_serial
+ )
+
+Construct a new 4-bit shift register.
+
+Args:
+~~~~~
+* ``enable``: An object of type ``Wire``. Enables the shift register.
+* ``clear_n``: An object of type ``Wire``. Clears ``output_bus`` and ``output_serial`` to 0 if its value is 1.
+* ``shift_load``: An object of type ``Wire``. The mode select. A value of 0 indicates a parallel load operation, where ``output_bus`` takes on the value of ``data_bus``. A value of 1 indicates a shift-right operation, where ``output_bus[3]`` takes on the value of ``output_bus[2]``, ``output_bus[2]`` takes on the value of ``output_bus[1]``, and so on; ``output_bus[0]`` takes on the value of ``data_serial``.
+* ``data_bus``: An object of type ``Bus4``. The parallel data input.
+* ``data_serial``. An object of type ``Wire``. The serial data input.
+* ``clock``. An object of type ``Wire`` or ``Clock``. The clock input to the shift register.
+* ``output_bus``. An object of type ``Bus4``. The parallel data output.
+* ``output_serial``. An object of type ``Wire``. The serial data output. Identical to ``output_bus[3]``.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If either ``data_bus`` or ``output_bus`` is not a bus of width 4.
+
+
+.. _ShiftRegister8:
+
+ShiftRegister8
+==============
+
+Class ``bw.storage.ShiftRegister8``
+-----------------------------------
+
+.. image:: images/schematics/storage/ShiftRegister8.svg
+ :width: 800px
+
+Defined in `bitwise/storage/SHIFT.py `_.
+
+`8-bit shift register `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ enable,
+ clear_n,
+ shift_load,
+ data_bus,
+ data_serial,
+ clock,
+ output_bus,
+ output_serial
+ )
+
+Construct a new 8-bit shift register.
+
+Args:
+~~~~~
+* ``enable``: An object of type ``Wire``. Enables the shift register.
+* ``clear_n``: An object of type ``Wire``. Clears ``output_bus`` and ``output_serial`` to 0 if its value is 1.
+* ``shift_load``: An object of type ``Wire``. The mode select. A value of 0 indicates a parallel load operation, where ``output_bus`` takes on the value of ``data_bus``. A value of 1 indicates a shift-right operation, where ``output_bus[7]`` takes on the value of ``output_bus[6]``, ``output_bus[6]`` takes on the value of ``output_bus[5]``, and so on; ``output_bus[0]`` takes on the value of ``data_serial``.
+* ``data_bus``: An object of type ``Bus8``. The parallel data input.
+* ``data_serial``. An object of type ``Wire``. The serial data input.
+* ``clock``. An object of type ``Wire`` or ``Clock``. The clock input to the shift register.
+* ``output_bus``. An object of type ``Bus8``. The parallel data output.
+* ``output_serial``. An object of type ``Wire``. The serial data output. Identical to ``output_bus[7]``.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If either ``data_bus`` or ``output_bus`` is not a bus of width 8.
+
+
+.. _ShiftRegister16:
+
+ShiftRegister16
+===============
+
+Class ``bw.storage.ShiftRegister16``
+------------------------------------
+
+.. image:: images/schematics/storage/ShiftRegister16.svg
+ :width: 800px
+
+Defined in `bitwise/storage/SHIFT.py `_.
+
+`16-bit shift register `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ enable,
+ clear_n,
+ shift_load,
+ data_bus,
+ data_serial,
+ clock,
+ output_bus,
+ output_serial
+ )
+
+Construct a new 16-bit shift register.
+
+Args:
+~~~~~
+* ``enable``: An object of type ``Wire``. Enables the shift register.
+* ``clear_n``: An object of type ``Wire``. Clears ``output_bus`` and ``output_serial`` to 0 if its value is 1.
+* ``shift_load``: An object of type ``Wire``. The mode select. A value of 0 indicates a parallel load operation, where ``output_bus`` takes on the value of ``data_bus``. A value of 1 indicates a shift-right operation, where ``output_bus[15]`` takes on the value of ``output_bus[14]``, ``output_bus[14]`` takes on the value of ``output_bus[13]``, and so on; ``output_bus[0]`` takes on the value of ``data_serial``.
+* ``data_bus``: An object of type ``Bus16``. The parallel data input.
+* ``data_serial``. An object of type ``Wire``. The serial data input.
+* ``clock``. An object of type ``Wire`` or ``Clock``. The clock input to the shift register.
+* ``output_bus``. An object of type ``Bus16``. The parallel data output.
+* ``output_serial``. An object of type ``Wire``. The serial data output. Identical to ``output_bus[15]``.
+
+Raises:
+~~~~~~~
+* ``TypeError``: If either ``data_bus`` or ``output_bus`` is not a bus of width 16.
+
+
+.. _SRLatch:
+
+SRLatch
+=======
+
+Class ``bw.storage.SRLatch``
+----------------------------
+
+.. image:: images/schematics/storage/SRLatch.svg
+ :width: 360px
+
+Defined in `bitwise/storage/FLOP.py `_.
+
+`SR latch `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ set_,
+ reset,
+ output,
+ output_not
+ )
+
+Construct a new SR latch.
+
+Args:
+~~~~~
+* ``set_``: An object of type ``Wire``. The set input to the latch.
+* ``reset``: An object of type ``Wire``. The reset input to the latch.
+* ``output``: An object of type ``Wire``. The output of the latch. Takes on the value of 1 if the value of ``set`` is 1 and the value of 0 if the value of ``reset`` is 1.
+* ``output_not``: An object of type ``Wire``. The complemented form of ``output``.
+
+
+.. _TFlipFlop:
+
+TFlipFlop
+=========
+
+Class ``bw.storage.TFlipFlop``
+------------------------------
+
+.. image:: images/schematics/storage/TFlipFlop.svg
+ :width: 360px
+
+Defined in `bitwise/storage/FLOP.py `_.
+
+Positive edge-triggered `T flip-flop `_.
+
+__init__
+--------
+
+::
+
+ __init__(
+ toggle,
+ clock,
+ output,
+ output_not
+ )
+
+Construct a new positive edge-triggered T flip-flop.
+
+Args:
+~~~~~
+* ``toggle``: An object of type ``Wire``. The toggle input to the flip-flop.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the flip-flop.
+* ``output``: An object of type ``Wire``. The output of the flip-flop. Toggles its value on the positive edges of ``clock`` if the value of ``toggle`` is 1.
+* ``output_not``: An object of type ``Wire``. The complemented form of ``output``.
+
+
+.. _TFlipFlopPresetClear:
+
+TFlipFlopPresetClear
+====================
+
+Class ``bw.storage.TFlipFlopPresetClear``
+-----------------------------------------
+
+.. image:: images/schematics/storage/TFlipFlopPresetClear.svg
+ :width: 360px
+
+Defined in `bitwise/storage/FLOP.py `_.
+
+Positive edge-triggered `T flip-flop `_ with asynchronous active low preset and clear.
+
+__init__
+--------
+
+::
+
+ __init__(
+ toggle,
+ preset_n,
+ clear_n,
+ clock,
+ output,
+ output_not
+ )
+
+Construct a new positive edge-triggered T flip-flop with preset/clear capabilities.
+
+Args:
+~~~~~
+* ``toggle``: An object of type ``Wire``. The toggle input to the flip-flop.
+* ``preset_n``: An object of type ``Wire``. Presets ``output`` to 1 and ``output_not`` to 0 if its value is 0.
+* ``clear_n``: An object of type ``Wire``. Clears ``output`` to 0 and ``output_not`` to 1 if its value is 0.
+* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the flip-flop.
+* ``output``: An object of type ``Wire``. The output of the flip-flop. Toggles its value on the positive edges of ``clock`` if the value of ``toggle`` is 1.
+* ``output_not``: An object of type ``Wire``. The complemented form of ``output``.
diff --git a/tests/signal/test_ParallelToSerialConverter16To1.py b/tests/storage/test_ParallelToSerialConverter16To1.py
similarity index 98%
rename from tests/signal/test_ParallelToSerialConverter16To1.py
rename to tests/storage/test_ParallelToSerialConverter16To1.py
index eccd3a7..a0d3e0b 100644
--- a/tests/signal/test_ParallelToSerialConverter16To1.py
+++ b/tests/storage/test_ParallelToSerialConverter16To1.py
@@ -43,7 +43,7 @@ def test_ParallelToSerialConverter16To1(self):
data_16
)
- bw.signal.ParallelToSerialConverter16To1(
+ bw.storage.ParallelToSerialConverter16To1(
enable,
reset_n,
parallel_load_n,
diff --git a/tests/signal/test_ParallelToSerialConverter4To1.py b/tests/storage/test_ParallelToSerialConverter4To1.py
similarity index 97%
rename from tests/signal/test_ParallelToSerialConverter4To1.py
rename to tests/storage/test_ParallelToSerialConverter4To1.py
index 96bec4f..c0941cd 100644
--- a/tests/signal/test_ParallelToSerialConverter4To1.py
+++ b/tests/storage/test_ParallelToSerialConverter4To1.py
@@ -14,7 +14,7 @@ def test_ParallelToSerialConverter4To1(self):
output = bw.wire.Wire()
data_bus = bw.wire.Bus4(data_1, data_2, data_3, data_4)
- bw.signal.ParallelToSerialConverter4To1(
+ bw.storage.ParallelToSerialConverter4To1(
enable,
reset_n,
parallel_load_n,
diff --git a/tests/signal/test_ParallelToSerialConverter8To1.py b/tests/storage/test_ParallelToSerialConverter8To1.py
similarity index 98%
rename from tests/signal/test_ParallelToSerialConverter8To1.py
rename to tests/storage/test_ParallelToSerialConverter8To1.py
index b6856e7..2a772f3 100644
--- a/tests/signal/test_ParallelToSerialConverter8To1.py
+++ b/tests/storage/test_ParallelToSerialConverter8To1.py
@@ -27,7 +27,7 @@ def test_ParallelToSerialConverter8To1(self):
data_8
)
- bw.signal.ParallelToSerialConverter8To1(
+ bw.storage.ParallelToSerialConverter8To1(
enable,
reset_n,
parallel_load_n,
diff --git a/tests/signal/test_SerialToParallelConverter1To16.py b/tests/storage/test_SerialToParallelConverter1To16.py
similarity index 99%
rename from tests/signal/test_SerialToParallelConverter1To16.py
rename to tests/storage/test_SerialToParallelConverter1To16.py
index 968e952..0b4a861 100644
--- a/tests/signal/test_SerialToParallelConverter1To16.py
+++ b/tests/storage/test_SerialToParallelConverter1To16.py
@@ -42,7 +42,7 @@ def test_SerialToParallelConverter1To16(self):
output_16
)
- bw.signal.SerialToParallelConverter1To16(
+ bw.storage.SerialToParallelConverter1To16(
enable,
reset_n,
data,
diff --git a/tests/signal/test_SerialToParallelConverter1To4.py b/tests/storage/test_SerialToParallelConverter1To4.py
similarity index 98%
rename from tests/signal/test_SerialToParallelConverter1To4.py
rename to tests/storage/test_SerialToParallelConverter1To4.py
index f80cad1..f1183d7 100644
--- a/tests/signal/test_SerialToParallelConverter1To4.py
+++ b/tests/storage/test_SerialToParallelConverter1To4.py
@@ -13,7 +13,7 @@ def test_SerialToParallelConverter1To4(self):
output_4 = bw.wire.Wire()
output_bus = bw.wire.Bus4(output_1, output_2, output_3, output_4)
- bw.signal.SerialToParallelConverter1To4(
+ bw.storage.SerialToParallelConverter1To4(
enable,
reset_n,
data,
diff --git a/tests/signal/test_SerialToParallelConverter1To8.py b/tests/storage/test_SerialToParallelConverter1To8.py
similarity index 98%
rename from tests/signal/test_SerialToParallelConverter1To8.py
rename to tests/storage/test_SerialToParallelConverter1To8.py
index e8d11ac..2d7c60f 100644
--- a/tests/signal/test_SerialToParallelConverter1To8.py
+++ b/tests/storage/test_SerialToParallelConverter1To8.py
@@ -26,7 +26,7 @@ def test_SerialToParallelConverter1To8(self):
output_8
)
- bw.signal.SerialToParallelConverter1To8(
+ bw.storage.SerialToParallelConverter1To8(
enable,
reset_n,
data,
+
+ 
