From 705c6e7c1ace1849e2504e2d79095a68b8433abc Mon Sep 17 00:00:00 2001 From: James Jiang Date: Tue, 23 Oct 2018 22:00:13 -0400 Subject: [PATCH] Documentation for storage subpackage (#20) * Finished schematics for storage classes * Finished documentation for flip-flops and registers * Finished docs for SIPO and PISO --- LICENSE | 2 +- README.rst | 6 +- bitwise/signal/__init__.py | 2 - bitwise/storage/FLOP.py | 231 ++--- bitwise/{signal => storage}/PISO.py | 69 +- bitwise/storage/REG.py | 177 ++-- bitwise/storage/SHIFT.py | 90 +- bitwise/{signal => storage}/SIPO.py | 60 +- bitwise/storage/__init__.py | 2 + docs/_build/doctrees/api.doctree | Bin 29117 -> 38154 bytes docs/_build/doctrees/changelog.doctree | Bin 0 -> 12983 bytes docs/_build/doctrees/environment.pickle | Bin 108335 -> 184014 bytes docs/_build/doctrees/index.doctree | Bin 5617 -> 6067 bytes docs/_build/doctrees/signal.doctree | Bin 205741 -> 205645 bytes docs/_build/doctrees/storage.doctree | Bin 2233 -> 213155 bytes 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docs/changelog.rst | 49 + docs/conf.py | 2 + docs/images/schematics/signal/signal.xml | 2 +- docs/images/schematics/storage/DFlipFlop.svg | 2 + .../storage/DFlipFlopPresetClear.svg | 2 + .../images/schematics/storage/GatedDLatch.svg | 2 + .../schematics/storage/GatedSRLatch.svg | 2 + docs/images/schematics/storage/JKFlipFlop.svg | 2 + .../storage/JKFlipFlopPresetClear.svg | 2 + .../ParallelToSerialConverter16To1.svg | 2 + .../storage/ParallelToSerialConverter4To1.svg | 2 + .../storage/ParallelToSerialConverter8To1.svg | 2 + docs/images/schematics/storage/Register16.svg | 2 + docs/images/schematics/storage/Register4.svg | 2 + docs/images/schematics/storage/Register8.svg | 2 + docs/images/schematics/storage/SRLatch.svg | 2 + .../SerialToParallelConverter1To16.svg | 2 + .../storage/SerialToParallelConverter1To4.svg | 2 + .../storage/SerialToParallelConverter1To8.svg | 2 + .../schematics/storage/ShiftRegister16.svg | 2 + .../schematics/storage/ShiftRegister4.svg | 2 + .../schematics/storage/ShiftRegister8.svg | 2 + docs/images/schematics/storage/TFlipFlop.svg | 2 + .../storage/TFlipFlopPresetClear.svg | 2 + docs/images/schematics/storage/storage.xml | 1 + docs/index.rst | 20 +- docs/signal.rst | 8 +- docs/storage.rst | 879 ++++++++++++++++++ .../test_ParallelToSerialConverter16To1.py | 2 +- .../test_ParallelToSerialConverter4To1.py | 2 +- .../test_ParallelToSerialConverter8To1.py | 2 +- .../test_SerialToParallelConverter1To16.py | 2 +- .../test_SerialToParallelConverter1To4.py | 2 +- .../test_SerialToParallelConverter1To8.py | 2 +- 94 files changed, 3480 insertions(+), 315 deletions(-) rename bitwise/{signal => storage}/PISO.py (52%) rename bitwise/{signal => storage}/SIPO.py (57%) create mode 100644 docs/_build/doctrees/changelog.doctree create mode 100644 docs/_build/html/_images/DFlipFlop.svg create mode 100644 docs/_build/html/_images/DFlipFlopPresetClear.svg create mode 100644 docs/_build/html/_images/GatedDLatch.svg create mode 100644 docs/_build/html/_images/GatedSRLatch.svg create mode 100644 docs/_build/html/_images/JKFlipFlop.svg create mode 100644 docs/_build/html/_images/JKFlipFlopPresetClear.svg create mode 100644 docs/_build/html/_images/ParallelToSerialConverter16To1.svg create mode 100644 docs/_build/html/_images/ParallelToSerialConverter4To1.svg create mode 100644 docs/_build/html/_images/ParallelToSerialConverter8To1.svg create mode 100644 docs/_build/html/_images/Register16.svg create mode 100644 docs/_build/html/_images/Register4.svg create mode 100644 docs/_build/html/_images/Register8.svg create mode 100644 docs/_build/html/_images/SRLatch.svg create mode 100644 docs/_build/html/_images/SerialToParallelConverter1To16.svg create mode 100644 docs/_build/html/_images/SerialToParallelConverter1To4.svg create mode 100644 docs/_build/html/_images/SerialToParallelConverter1To8.svg create mode 100644 docs/_build/html/_images/ShiftRegister16.svg create mode 100644 docs/_build/html/_images/ShiftRegister4.svg create mode 100644 docs/_build/html/_images/ShiftRegister8.svg create mode 100644 docs/_build/html/_images/TFlipFlop.svg create mode 100644 docs/_build/html/_images/TFlipFlopPresetClear.svg create mode 100644 docs/_build/html/_sources/changelog.rst.txt create mode 100644 docs/_build/html/changelog.html create mode 100644 docs/changelog.rst create mode 100644 docs/images/schematics/storage/DFlipFlop.svg create mode 100644 docs/images/schematics/storage/DFlipFlopPresetClear.svg create mode 100644 docs/images/schematics/storage/GatedDLatch.svg create mode 100644 docs/images/schematics/storage/GatedSRLatch.svg create mode 100644 docs/images/schematics/storage/JKFlipFlop.svg create mode 100644 docs/images/schematics/storage/JKFlipFlopPresetClear.svg create mode 100644 docs/images/schematics/storage/ParallelToSerialConverter16To1.svg create mode 100644 docs/images/schematics/storage/ParallelToSerialConverter4To1.svg create mode 100644 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tests/{signal => storage}/test_ParallelToSerialConverter16To1.py (98%) rename tests/{signal => storage}/test_ParallelToSerialConverter4To1.py (97%) rename tests/{signal => storage}/test_ParallelToSerialConverter8To1.py (98%) rename tests/{signal => storage}/test_SerialToParallelConverter1To16.py (99%) rename tests/{signal => storage}/test_SerialToParallelConverter1To4.py (98%) rename tests/{signal => storage}/test_SerialToParallelConverter1To8.py (98%) diff --git a/LICENSE b/LICENSE index 63b4b68..a46a1e0 100644 --- a/LICENSE +++ b/LICENSE @@ -1,6 +1,6 @@ MIT License -Copyright (c) [year] [fullname] +Copyright (c) 2018 James Jiang Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal diff --git a/README.rst b/README.rst index b1092da..838c6f3 100644 --- a/README.rst +++ b/README.rst @@ -46,7 +46,7 @@ Interacting with it in a Python session:: In [2]: b.value = 0 - In [3]: sum.value + In [3]: sum_.value Out[3]: 0 In [4]: carry_out.value @@ -54,7 +54,7 @@ Interacting with it in a Python session:: In [5]: a.value = 1 - In [6]: sum.value + In [6]: sum_.value Out[6]: 1 In [7]: carry_out.value @@ -62,7 +62,7 @@ Interacting with it in a Python session:: In [8]: b.value = 1 - In [9]: sum.value + In [9]: sum_.value Out[9]: 0 In [10]: carry_out.value diff --git a/bitwise/signal/__init__.py b/bitwise/signal/__init__.py index 7170fe7..140db94 100644 --- a/bitwise/signal/__init__.py +++ b/bitwise/signal/__init__.py @@ -3,6 +3,4 @@ from .ENC import * from .MUX import * from .INV_CTRL import * -from .PISO import * -from .SIPO import * from .SSD import * diff --git a/bitwise/storage/FLOP.py b/bitwise/storage/FLOP.py index 180d511..38a3567 100644 --- a/bitwise/storage/FLOP.py +++ b/bitwise/storage/FLOP.py @@ -1,9 +1,4 @@ """ -This module defines classes that simulate primitive storage elements, namely -1-bit latches and 1-bit flip-flops. Latches are level-sensitive, changing their -value according to the value of a clock input, while flip-flops are edge- -sensitive, changing their value according to edges of a clock input. - The following classes are defined: SRLatch GatedSRLatch @@ -24,16 +19,15 @@ class SRLatch: - """ - This class simulates an SR latch, which has two inputs and two outputs: - ________ - set ----| |---- output - reset ----|________|---- output_not - - If set is 1 and reset is 0, output and output_not are 1 and 0, - respectively. If set is 0 and reset is 1, output and output_not are 0 and - 1, respectively. If both set and reset are 0, output and output_not hold - their current values. The input where both set and reset are 1 is not used. + """Construct a new SR latch. + + Args: + set_: An object of type Wire. The set input to the latch. + reset: An object of type Wire. The reset input to the latch. + output: An object of type Wire. The output of the latch. Takes on the + value of 1 if the value of set is 1 and the value of 0 if the value + of reset is 1. + output_not: An object of type Wire. The complemented form of output. """ def __init__(self, set_, reset, output, output_not): gate.NORGate2(set_, output, output_not) @@ -41,21 +35,16 @@ def __init__(self, set_, reset, output, output_not): class GatedSRLatch: - """ - This class simulates a gated SR latch, which has three inputs, including a - clock, and two outputs: - ________ - set ----| |---- output - reset ----| |---- output_not - clock ----|________| - - If clock is 0, output and output_not hold their current values, regardless - of the set and reset inputs. If clock is 1 and set and reset are 1 and 0, - respectively, output and output_not are 1 and 0, respectively. If clock is - 1 and set and reset are 1 and 0, respectively, output and output_not are 0 - and 1, respectively. If clock is 1 and both set and reset are 0, output and - output_not hold their current values. The input where both set and reset - are 1 is not used. + """Construct a new gated SR latch. + + Args: + set_: An object of type Wire. The set input to the latch. + reset: An object of type Wire. The reset input to the latch. + clock: An object of type Wire. The clock input to the latch. + output: An object of type Wire. The output of the latch. When the value + of clock is 1, takes on the value of 1 if the value of set is 1 and + the value of 0 if the value of reset is 1. + output_not: An object of type Wire. The complemented form of output. """ def __init__(self, set_, reset, clock, output, output_not): wire_1 = Wire() @@ -67,16 +56,14 @@ def __init__(self, set_, reset, clock, output, output_not): class GatedDLatch: - """ - This class simulates a gated D latch, which has two inputs, including a - clock, and two outputs: - ________ - data ----| |---- output - clock ----|________|---- output_not - - If clock is 0, output and output_not hold their current values, regardless - of the data input. If clock is 1, output takes on the value of data and - output_not takes on the opposite value. + """Construct a new gated D latch. + + Args: + data: An object of type Wire. The data input to the latch. + clock: An object of type Wire. The clock input to the latch. + output: An object of type Wire. The output of the latch. Takes on the + value of data if the value of clock is 1. + output_not: An object of type Wire. The complemented form of output. """ def __init__(self, data, clock, output, output_not): wire_1 = Wire() @@ -86,17 +73,14 @@ def __init__(self, data, clock, output, output_not): class DFlipFlop: - """ - This class simulates a D flip-flop, which has two inputs, including a - clock, and two outputs: - ________ - data ----| |---- output - clock ----|________|---- output_not - - On the positive edge of clock (i.e. on the clock transition from a 0 value - to a 1 value), output takes on the value of data and output_not takes on - the opposite value. Otherwise, output and output_not hold their current - values. + """Construct a new positive edge-triggered D flip-flop. + + Args: + data: An object of type Wire. The data input to the flip-flop. + clock: An object of type Wire. The clock input to the flip-flop. + output: An object of type Wire. The output of the flip-flop. Takes on + the value of data on the positive edges of clock. + output_not: An object of type Wire. The complemented form of output. """ def __init__(self, data, clock, output, output_not): q_1 = Wire() @@ -109,24 +93,19 @@ def __init__(self, data, clock, output, output_not): class DFlipFlopPresetClear: - """ - This class simulates a D flip-flop, with additional inputs for presetting - and clearing the flip_flop. It has four inputs, including a clock, and two - outputs: - ________ - data ----| |---- output - preset_n ----| |---- output_not - clear_n ----| | - clock ----|________| - - On the positive edge of clock (i.e. on the clock transition from a 0 value - to a 1 value), output takes on the value of data and output_not takes on - the opposite value. Otherwise, output and output_not hold their current - values. - - Inputs preset_n and clear_n are, respectively, an active low - asynchronous preset (setting output to 1 and output_not to 0) and an active - low asynchronous clear (setting output to 0 and output_not to 1). + """Construct a new positive edge-triggered D flip-flop with preset/clear + capabilities. + + Args: + data: An object of type Wire. The data input to the flip-flop. + preset_n: An object of type Wire. Presets output to 1 and output_not to + 0 if its value is 0. + clear_n: An object of type Wire. Clears output to 0 and output_not to 1 + if its value is 0. + clock: An object of type Wire. The clock input to the flip-flop. + output: An object of type Wire. The output of the flip-flop. Takes on + the value of data on the positive edges of clock. + output_not: An object of type Wire. The complemented form of output. """ def __init__(self, data, preset_n, clear_n, clock, output, output_not): not_clock = Wire() @@ -151,17 +130,15 @@ def __init__(self, data, preset_n, clear_n, clock, output, output_not): class TFlipFlop: - """ - This class simulates a T flip-flop, which has two inputs, including a - clock, and two outputs: - ________ - toggle ----| |---- output - clock ----|________|---- output_not - - On the positive edge of clock (i.e. on the clock transition from a 0 value - to a 1 value), if toggle has the value 1, both output and output_not toggle - their current values. If toggle has the value 0, both output and output_not - are unchanged. + """Construct a new positive edge-triggered T flip-flop. + + Args: + toggle: An object of type Wire. The toggle input to the flip-flop. + clock: An object of type Wire. The clock input to the flip-flop. + output: An object of type Wire. The output of the flip-flop. Toggles + its value on the positive edges of clock if the value of toggle is + 1. + output_not: An object of type Wire. The complemented form of output. """ def __init__(self, toggle, clock, output, output_not): mux_output = Wire() @@ -173,24 +150,20 @@ def __init__(self, toggle, clock, output, output_not): class TFlipFlopPresetClear: - """ - This class simulates a T flip-flop, with additional inputs for presetting - and clearing the flip_flop. It has four inputs, including a clock, and two - outputs: - ________ - toggle ----| |---- output - preset_n ----| |---- output_not - clear_n ----| | - clock ----|________| - - On the positive edge of clock (i.e. on the clock transition from a 0 value - to a 1 value), if toggle has the value 1, both output and output_not toggle - their current values. If toggle has the value 0, both output and output_not - are unchanged. - - Inputs preset_n and clear_n are, respectively, an active low - asynchronous preset (setting output to 1 and output_not to 0) and an active - low asynchronous clear (setting output to 0 and output_not to 1). + """Construct a new positive edge-triggered T flip-flop with preset/clear + capabilities. + + Args: + toggle: An object of type Wire. The toggle input to the flip-flop. + preset_n: An object of type Wire. Presets output to 1 and output_not to + 0 if its value is 0. + clear_n: An object of type Wire. Clears output to 0 and output_not to 1 + if its value is 0. + clock: An object of type Wire. The clock input to the flip-flop. + output: An object of type Wire. The output of the flip-flop. Toggles + its value on the positive edges of clock if the value of toggle is + 1. + output_not: An object of type Wire. The complemented form of output. """ def __init__(self, toggle, preset_n, clear_n, clock, output, output_not): mux_output = Wire() @@ -209,20 +182,17 @@ def __init__(self, toggle, preset_n, clear_n, clock, output, output_not): class JKFlipFlop: - """ - This class simulates a JK flip-flop, which has three inputs, including a - clock, and two outputs: - ________ - J ----| |---- output - K ----| |---- output_not - clock ----|________| - - On the positive edge of clock (i.e. on the clock transition from a 0 value - to a 1 value), if J is 1 and K is 0, output and output_not are 1 and 0, - respectively. If J is 0 and K is 1, output and output_not are 0 and 1, - respectively. If J and K are both 0, both output and output_not hold their - current values. If J and K are both 1, both output and output_not toggle - their current values. + """Construct a new positive edge-triggered JK flip-flop. + + Args: + J: An object of type Wire. The J input to the flip-flop. + K: An object of type Wire. The K input to the flip-flop. + clock: An object of type Wire. The clock input to the flip-flop. + output: An object of type Wire. The output of the flip-flop. On the + positive edges of clock, takes on the value of 1 if the value of J + is 1, takes on the value of 0 if the value of K is 1, and toggles + its value if both J and K have value 1. + output_not: An object of type Wire. The complemented form of output. """ def __init__(self, j, k, clock, output, output_not): and_1 = Wire() @@ -238,27 +208,22 @@ def __init__(self, j, k, clock, output, output_not): class JKFlipFlopPresetClear: - """ - This class simulates a JK flip-flop, with additional inputs for presetting - and clearing the flip_flop. It has five inputs, including a clock, and two - outputs: - ________ - J ----| |---- output - K ----| |---- output_not - preset_n ----| | - clear_n ----| | - clock ----|________| - - On the positive edge of clock (i.e. on the clock transition from a 0 value - to a 1 value), if J is 1 and K is 0, output and output_not are 1 and 0, - respectively. If J is 0 and K is 1, output and output_not are 0 and 1, - respectively. If J and K are both 0, both output and output_not hold their - current values. If J and K are both 1, both output and output_not toggle - their current values. - - Inputs preset_n and clear_n are, respectively, an active low - asynchronous preset (setting output to 1 and output_not to 0) and an active - low asynchronous clear (setting output to 0 and output_not to 1). + """Construct a new positive edge-triggered JK flip-flop with preset/clear + capabilities. + + Args: + J: An object of type Wire. The J input to the flip-flop. + K: An object of type Wire. The K input to the flip-flop. + preset_n: An object of type Wire. Presets output to 1 and output_not to + 0 if its value is 0. + clear_n: An object of type Wire. Clears output to 0 and output_not to 1 + if its value is 0. + clock: An object of type Wire. The clock input to the flip-flop. + output: An object of type Wire. The output of the flip-flop. On the + positive edges of clock, takes on the value of 1 if the value of J + is 1, takes on the value of 0 if the value of K is 1, and toggles + its value if both J and K have value 1. + output_not: An object of type Wire. The complemented form of output. """ def __init__(self, j, k, preset_n, clear_n, clock, output, output_not): and_1 = Wire() diff --git a/bitwise/signal/PISO.py b/bitwise/storage/PISO.py similarity index 52% rename from bitwise/signal/PISO.py rename to bitwise/storage/PISO.py index 7702196..3ed651e 100644 --- a/bitwise/signal/PISO.py +++ b/bitwise/storage/PISO.py @@ -15,8 +15,23 @@ class ParallelToSerialConverter4To1: - """ - + """Construct a new 4-bit-parallel-to-serial converter. + + Args: + enable: An object of type Wire. Enables the converter. + clear_n: An object of type Wire. Clears all 4 internal registers to 0 + if its value is 0. + load_n: An object of type Wire. The mode select. A value of 0 indicates + a parallel load operation, where the values of data_bus are loaded + into the internal registers. A value of 1 indicates a shift-right + operation. + data_bus: An object of type Bus4. The parallel data input. + clock: An object of type Wire or Clock. The clock input. + output: An object of type Wire. The serial output of the converter. + data_bus[3] is outputted first, and data_bus[0] is outputted last. + + Raises: + TypeError: If data_bus is not a bus of width 4. """ def __init__( self, @@ -27,10 +42,10 @@ def __init__( clock, output ): - if len(data_bus.wires) != 4: + if len(data_bus) != 4: raise TypeError( "Expected bus of width 4, received bus of width {0}.".format( - len(data_bus.wires) + len(data_bus) ) ) @@ -59,8 +74,23 @@ def __init__( class ParallelToSerialConverter8To1: - """ - + """Construct a new 8-bit-parallel-to-serial converter. + + Args: + enable: An object of type Wire. Enables the converter. + clear_n: An object of type Wire. Clears all 8 internal registers to 0 + if its value is 0. + load_n: An object of type Wire. The mode select. A value of 0 indicates + a parallel load operation, where the values of data_bus are loaded + into the internal registers. A value of 1 indicates a shift-right + operation. + data_bus: An object of type Bus8. The parallel data input. + clock: An object of type Wire or Clock. The clock input. + output: An object of type Wire. The serial output of the converter. + data_bus[7] is outputted first, and data_bus[0] is outputted last. + + Raises: + TypeError: If data_bus is not a bus of width 8. """ def __init__( self, @@ -71,10 +101,10 @@ def __init__( clock, output ): - if len(data_bus.wires) != 8: + if len(data_bus) != 8: raise TypeError( "Expected bus of width 8, received bus of width {0}.".format( - len(data_bus.wires) + len(data_bus) ) ) @@ -107,8 +137,23 @@ def __init__( class ParallelToSerialConverter16To1: - """ - + """Construct a new 16-bit-parallel-to-serial converter. + + Args: + enable: An object of type Wire. Enables the converter. + clear_n: An object of type Wire. Clears all 16 internal registers to 0 + if its value is 0. + load_n: An object of type Wire. The mode select. A value of 0 indicates + a parallel load operation, where the values of data_bus are loaded + into the internal registers. A value of 1 indicates a shift-right + operation. + data_bus: An object of type Bus16. The parallel data input. + clock: An object of type Wire or Clock. The clock input. + output: An object of type Wire. The serial output of the converter. + data_bus[15] is outputted first, and data_bus[0] is outputted last. + + Raises: + TypeError: If data_bus is not a bus of width 16. """ def __init__( self, @@ -119,10 +164,10 @@ def __init__( clock, output ): - if len(data_bus.wires) != 16: + if len(data_bus) != 16: raise TypeError( "Expected bus of width 16, received bus of width {0}.".format( - len(data_bus.wires) + len(data_bus) ) ) diff --git a/bitwise/storage/REG.py b/bitwise/storage/REG.py index 4437693..8c80f93 100644 --- a/bitwise/storage/REG.py +++ b/bitwise/storage/REG.py @@ -1,8 +1,4 @@ """ -This module defines classes that simulate storage registers. These registers -are simply arrays of single-bit flip-flops, and they serve the same purpose as -flip-flops as well, being used for storing data. - The following classes are defined: Register4 Register8 @@ -16,33 +12,30 @@ class Register4: - """ - This register has four inputs in a single 4-bit bus, a clock input, and - four outputs in a single 4-bit bus: - ________ - input_1 ----| |---- output_1 - input_2 ----| |---- output_2 - input_3 ----| |---- output_3 - input_4 ----| |---- output_4 - clock ----|________| - - On the positive edge of clock (i.e. on the clock transition from a 0 value - to a 1 value), the outputs takes on the value of the inputs, with output_1 - corresponding to input_1, output_2, corresponding to input_2, and so on. - Otherwise, the outputs hold their current values. + """Construct a new 4-bit storage register. + + Args: + data_bus: An object of type Bus4. The data input to the register. + clock: An object of type Wire or Clock. The clock input to the + register. + output_bus: An object of type Bus4. The output of the register. Takes + on the value of data_bus on the positive edges of clock. + + Raises: + TypeError: If either data_bus or output_bus is not a bus of width 4. """ def __init__(self, input_bus, clock, output_bus): - if len(input_bus.wires) != 4: + if len(input_bus) != 4: raise TypeError( "Expected bus of width 4, received bus of width {0}.".format( - len(input_bus.wires) + len(input_bus) ) ) - if len(output_bus.wires) != 4: + if len(output_bus) != 4: raise TypeError( "Expected bus of width 4, received bus of width {0}.".format( - len(output_bus.wires) + len(output_bus) ) ) @@ -51,44 +44,37 @@ def __init__(self, input_bus, clock, output_bus): not_3 = Wire() not_4 = Wire() - FLOP.DFlipFlop(input_bus.wires[0], clock, output_bus.wires[0], not_1) - FLOP.DFlipFlop(input_bus.wires[1], clock, output_bus.wires[1], not_2) - FLOP.DFlipFlop(input_bus.wires[2], clock, output_bus.wires[2], not_3) - FLOP.DFlipFlop(input_bus.wires[3], clock, output_bus.wires[3], not_4) + FLOP.DFlipFlop(input_bus[0], clock, output_bus[0], not_1) + FLOP.DFlipFlop(input_bus[1], clock, output_bus[1], not_2) + FLOP.DFlipFlop(input_bus[2], clock, output_bus[2], not_3) + FLOP.DFlipFlop(input_bus[3], clock, output_bus[3], not_4) class Register8: - """ - This register has eight inputs in a single 8-bit bus, a clock input, and - eight outputs in a single 8-bit bus: - ________ - input_1 ----| |---- output_1 - input_2 ----| |---- output_2 - input_3 ----| |---- output_3 - input_4 ----| |---- output_4 - input_5 ----| |---- output_5 - input_6 ----| |---- output_6 - input_7 ----| |---- output_7 - input_8 ----| |---- output_8 - clock ----|________| - - On the positive edge of clock (i.e. on the clock transition from a 0 value - to a 1 value), the outputs takes on the value of the inputs, with output_1 - corresponding to input_1, output_2, corresponding to input_2, and so on. - Otherwise, the outputs hold their current values. + """Construct a new 8-bit storage register. + + Args: + data_bus: An object of type Bus8. The data input to the register. + clock: An object of type Wire or Clock. The clock input to the + register. + output_bus: An object of type Bus8. The output of the register. Takes + on the value of data_bus on the positive edges of clock. + + Raises: + TypeError: If either data_bus or output_bus is not a bus of width 8. """ def __init__(self, input_bus, clock, output_bus): - if len(input_bus.wires) != 8: + if len(input_bus) != 8: raise TypeError( "Expected bus of width 8, received bus of width {0}.".format( - len(input_bus.wires) + len(input_bus) ) ) - if len(output_bus.wires) != 8: + if len(output_bus) != 8: raise TypeError( "Expected bus of width 8, received bus of width {0}.".format( - len(output_bus.wires) + len(output_bus) ) ) @@ -101,56 +87,41 @@ def __init__(self, input_bus, clock, output_bus): not_7 = Wire() not_8 = Wire() - FLOP.DFlipFlop(input_bus.wires[0], clock, output_bus.wires[0], not_1) - FLOP.DFlipFlop(input_bus.wires[1], clock, output_bus.wires[1], not_2) - FLOP.DFlipFlop(input_bus.wires[2], clock, output_bus.wires[2], not_3) - FLOP.DFlipFlop(input_bus.wires[3], clock, output_bus.wires[3], not_4) - FLOP.DFlipFlop(input_bus.wires[4], clock, output_bus.wires[4], not_5) - FLOP.DFlipFlop(input_bus.wires[5], clock, output_bus.wires[5], not_6) - FLOP.DFlipFlop(input_bus.wires[6], clock, output_bus.wires[6], not_7) - FLOP.DFlipFlop(input_bus.wires[7], clock, output_bus.wires[7], not_8) + FLOP.DFlipFlop(input_bus[0], clock, output_bus[0], not_1) + FLOP.DFlipFlop(input_bus[1], clock, output_bus[1], not_2) + FLOP.DFlipFlop(input_bus[2], clock, output_bus[2], not_3) + FLOP.DFlipFlop(input_bus[3], clock, output_bus[3], not_4) + FLOP.DFlipFlop(input_bus[4], clock, output_bus[4], not_5) + FLOP.DFlipFlop(input_bus[5], clock, output_bus[5], not_6) + FLOP.DFlipFlop(input_bus[6], clock, output_bus[6], not_7) + FLOP.DFlipFlop(input_bus[7], clock, output_bus[7], not_8) class Register16: - """ - This register has sixteen inputs in a single 16-bit bus, a clock input, and - sixteen outputs in a single 16-bit bus: - ________ - input_1 ----| |---- output_1 - input_2 ----| |---- output_2 - input_3 ----| |---- output_3 - input_4 ----| |---- output_4 - input_5 ----| |---- output_5 - input_6 ----| |---- output_6 - input_7 ----| |---- output_7 - input_8 ----| |---- output_8 - input_9 ----| |---- output_9 - input_10 ----| |---- output_10 - input_11 ----| |---- output_11 - input_12 ----| |---- output_12 - input_13 ----| |---- output_13 - input_14 ----| |---- output_14 - input_15 ----| |---- output_15 - input_16 ----| |---- output_16 - clock ----|________| - - On the positive edge of clock (i.e. on the clock transition from a 0 value - to a 1 value), the outputs takes on the value of the inputs, with output_1 - corresponding to input_1, output_2, corresponding to input_2, and so on. - Otherwise, the outputs hold their current values. + """Construct a new 16-bit storage register. + + Args: + data_bus: An object of type Bus16. The data input to the register. + clock: An object of type Wire or Clock. The clock input to the + register. + output_bus: An object of type Bus16. The output of the register. Takes + on the value of data_bus on the positive edges of clock. + + Raises: + TypeError: If either data_bus or output_bus is not a bus of width 16. """ def __init__(self, input_bus, clock, output_bus): - if len(input_bus.wires) != 16: + if len(input_bus) != 16: raise TypeError( "Expected bus of width 16, received bus of width {0}.".format( - len(input_bus.wires) + len(input_bus) ) ) - if len(output_bus.wires) != 16: + if len(output_bus) != 16: raise TypeError( "Expected bus of width 16, received bus of width {0}.".format( - len(output_bus.wires) + len(output_bus) ) ) @@ -171,21 +142,19 @@ def __init__(self, input_bus, clock, output_bus): not_15 = Wire() not_16 = Wire() - output = output_bus.wires - - FLOP.DFlipFlop(input_bus.wires[0], clock, output[0], not_1) - FLOP.DFlipFlop(input_bus.wires[1], clock, output[1], not_2) - FLOP.DFlipFlop(input_bus.wires[2], clock, output[2], not_3) - FLOP.DFlipFlop(input_bus.wires[3], clock, output[3], not_4) - FLOP.DFlipFlop(input_bus.wires[4], clock, output[4], not_5) - FLOP.DFlipFlop(input_bus.wires[5], clock, output[5], not_6) - FLOP.DFlipFlop(input_bus.wires[6], clock, output[6], not_7) - FLOP.DFlipFlop(input_bus.wires[7], clock, output[7], not_8) - FLOP.DFlipFlop(input_bus.wires[8], clock, output[8], not_9) - FLOP.DFlipFlop(input_bus.wires[9], clock, output[9], not_10) - FLOP.DFlipFlop(input_bus.wires[10], clock, output[10], not_11) - FLOP.DFlipFlop(input_bus.wires[11], clock, output[11], not_12) - FLOP.DFlipFlop(input_bus.wires[12], clock, output[12], not_13) - FLOP.DFlipFlop(input_bus.wires[13], clock, output[13], not_14) - FLOP.DFlipFlop(input_bus.wires[14], clock, output[14], not_15) - FLOP.DFlipFlop(input_bus.wires[15], clock, output[15], not_16) + FLOP.DFlipFlop(input_bus[0], clock, output_bus[0], not_1) + FLOP.DFlipFlop(input_bus[1], clock, output_bus[1], not_2) + FLOP.DFlipFlop(input_bus[2], clock, output_bus[2], not_3) + FLOP.DFlipFlop(input_bus[3], clock, output_bus[3], not_4) + FLOP.DFlipFlop(input_bus[4], clock, output_bus[4], not_5) + FLOP.DFlipFlop(input_bus[5], clock, output_bus[5], not_6) + FLOP.DFlipFlop(input_bus[6], clock, output_bus[6], not_7) + FLOP.DFlipFlop(input_bus[7], clock, output_bus[7], not_8) + FLOP.DFlipFlop(input_bus[8], clock, output_bus[8], not_9) + FLOP.DFlipFlop(input_bus[9], clock, output_bus[9], not_10) + FLOP.DFlipFlop(input_bus[10], clock, output_bus[10], not_11) + FLOP.DFlipFlop(input_bus[11], clock, output_bus[11], not_12) + FLOP.DFlipFlop(input_bus[12], clock, output_bus[12], not_13) + FLOP.DFlipFlop(input_bus[13], clock, output_bus[13], not_14) + FLOP.DFlipFlop(input_bus[14], clock, output_bus[14], not_15) + FLOP.DFlipFlop(input_bus[15], clock, output_bus[15], not_16) diff --git a/bitwise/storage/SHIFT.py b/bitwise/storage/SHIFT.py index 0720e05..17dc9b2 100644 --- a/bitwise/storage/SHIFT.py +++ b/bitwise/storage/SHIFT.py @@ -17,8 +17,28 @@ class ShiftRegister4: - """ + """Construct a new 4-bit shift register. + + Args: + enable: An object of type Wire. Enables the shift register. + clear_n: An object of type Wire. Clears output_bus and output_serial to + 0 if its value is 1. + shift_load: An object of type Wire. The mode select. A value of 0 + indicates a parallel load operation, where output_bus takes on the + value of data_bus. A value of 1 indicates a shift-right operation, + where output_bus[3] takes on the value of output_bus[2], + output_bus[2] takes on the value of output_bus[1], and so on; + output_bus[0] takes on the value of data_serial. + data_bus: An object of type Bus4. The parallel data input. + data_serial. An object of type Wire. The serial data input. + clock. An object of type Wire or Clock. The clock input to the shift + register. + output_bus. An object of type Bus4. The parallel data output. + output_serial. An object of type Wire. The serial data output. + Identical to output_bus[3]. + Raises: + TypeError: If either data_bus or output_bus is not a bus of width 4. """ def __init__( self, @@ -31,17 +51,17 @@ def __init__( output_bus, output_s ): - if len(data_bus.wires) != 4: + if len(data_bus) != 4: raise TypeError( "Expected bus of width 4, received bus of width {0}.".format( - len(data_bus.wires) + len(data_bus) ) ) - if len(output_bus.wires) != 4: + if len(output_bus) != 4: raise TypeError( "Expected bus of width 4, received bus of width {0}.".format( - len(output_bus.wires) + len(output_bus) ) ) @@ -126,8 +146,28 @@ def __init__( class ShiftRegister8: - """ + """Construct a new 8-bit shift register. + Args: + enable: An object of type Wire. Enables the shift register. + clear_n: An object of type Wire. Clears output_bus and output_serial to + 0 if its value is 1. + shift_load: An object of type Wire. The mode select. A value of 0 + indicates a parallel load operation, where output_bus takes on the + value of data_bus. A value of 1 indicates a shift-right operation, + where output_bus[7] takes on the value of output_bus[6], + output_bus[6] takes on the value of output_bus[5], and so on; + output_bus[0] takes on the value of data_serial. + data_bus: An object of type Bus8. The parallel data input. + data_serial. An object of type Wire. The serial data input. + clock. An object of type Wire or Clock. The clock input to the shift + register. + output_bus. An object of type Bus8. The parallel data output. + output_serial. An object of type Wire. The serial data output. + Identical to output_bus[7]. + + Raises: + TypeError: If either data_bus or output_bus is not a bus of width 8. """ def __init__( self, @@ -140,17 +180,17 @@ def __init__( output_bus, output_s ): - if len(data_bus.wires) != 8: + if len(data_bus) != 8: raise TypeError( "Expected bus of width 8, received bus of width {0}.".format( - len(data_bus.wires) + len(data_bus) ) ) - if len(output_bus.wires) != 8: + if len(output_bus) != 8: raise TypeError( "Expected bus of width 8, received bus of width {0}.".format( - len(output_bus.wires) + len(output_bus) ) ) @@ -302,8 +342,28 @@ def __init__( class ShiftRegister16: - """ + """Construct a new 16-bit shift register. + + Args: + enable: An object of type Wire. Enables the shift register. + clear_n: An object of type Wire. Clears output_bus and output_serial to + 0 if its value is 1. + shift_load: An object of type Wire. The mode select. A value of 0 + indicates a parallel load operation, where output_bus takes on the + value of data_bus. A value of 1 indicates a shift-right operation, + where output_bus[15] takes on the value of output_bus[14], + output_bus[14] takes on the value of output_bus[13], and so on; + output_bus[0] takes on the value of data_serial. + data_bus: An object of type Bus16. The parallel data input. + data_serial. An object of type Wire. The serial data input. + clock. An object of type Wire or Clock. The clock input to the shift + register. + output_bus. An object of type Bus16. The parallel data output. + output_serial. An object of type Wire. The serial data output. + Identical to output_bus[15]. + Raises: + TypeError: If either data_bus or output_bus is not a bus of width 16. """ def __init__( self, @@ -316,17 +376,17 @@ def __init__( output_bus, output_s ): - if len(data_bus.wires) != 16: + if len(data_bus) != 16: raise TypeError( "Expected bus of width 16, received bus of width {0}.".format( - len(data_bus.wires) + len(data_bus) ) ) - if len(output_bus.wires) != 16: + if len(output_bus) != 16: raise TypeError( "Expected bus of width 16, received bus of width {0}.".format( - len(output_bus.wires) + len(output_bus) ) ) diff --git a/bitwise/signal/SIPO.py b/bitwise/storage/SIPO.py similarity index 57% rename from bitwise/signal/SIPO.py rename to bitwise/storage/SIPO.py index ff9d0e5..b0ba305 100644 --- a/bitwise/signal/SIPO.py +++ b/bitwise/storage/SIPO.py @@ -15,14 +15,26 @@ class SerialToParallelConverter1To4: - """ - + """Construct a new serial-to-4-bit-parallel converter. + + Args: + enable: An object of type Wire. Enables the converter. + clear_n: An object of type Wire. Clears all 4 internal registers to 0 + if its value is 0. + data: An object of type Wire. The serial data input. + clock: An object of type Wire or Clock. The clock input. + output_bus: An object of type Bus4. The parallel output of the + converter. output[0] corresponds to the most recent serial data + input. + + Raises: + TypeError: If output_bus is not a bus of width 4. """ def __init__(self, enable, reset_n, data, clock, output_bus): - if len(output_bus.wires) != 4: + if len(output_bus) != 4: raise TypeError( "Expected bus of width 4, received bus of width {0}.".format( - len(output_bus.wires) + len(output_bus) ) ) @@ -51,14 +63,26 @@ def __init__(self, enable, reset_n, data, clock, output_bus): class SerialToParallelConverter1To8: - """ - + """Construct a new serial-to-8-bit-parallel converter. + + Args: + enable: An object of type Wire. Enables the converter. + clear_n: An object of type Wire. Clears all 8 internal registers to 0 + if its value is 0. + data: An object of type Wire. The serial data input. + clock: An object of type Wire or Clock. The clock input. + output_bus: An object of type Bus8. The parallel output of the + converter. output[0] corresponds to the most recent serial data + input. + + Raises: + TypeError: If output_bus is not a bus of width 8. """ def __init__(self, enable, reset_n, data, clock, output_bus): - if len(output_bus.wires) != 8: + if len(output_bus) != 8: raise TypeError( "Expected bus of width 8, received bus of width {0}.".format( - len(output_bus.wires) + len(output_bus) ) ) @@ -91,14 +115,26 @@ def __init__(self, enable, reset_n, data, clock, output_bus): class SerialToParallelConverter1To16: - """ - + """Construct a new serial-to-16-bit-parallel converter. + + Args: + enable: An object of type Wire. Enables the converter. + clear_n: An object of type Wire. Clears all 16 internal registers to 0 + if its value is 0. + data: An object of type Wire. The serial data input. + clock: An object of type Wire or Clock. The clock input. + output_bus: An object of type Bus16. The parallel output of the + converter. output[0] corresponds to the most recent serial data + input. + + Raises: + TypeError: If output_bus is not a bus of width 16. """ def __init__(self, enable, reset_n, data, clock, output_bus): - if len(output_bus.wires) != 16: + if len(output_bus) != 16: raise TypeError( "Expected bus of width 16, received bus of width {0}.".format( - len(output_bus.wires) + len(output_bus) ) ) diff --git a/bitwise/storage/__init__.py b/bitwise/storage/__init__.py index dec80fd..79a024e 100644 --- a/bitwise/storage/__init__.py +++ b/bitwise/storage/__init__.py @@ -1,3 +1,5 @@ from .FLOP import * +from .PISO import * from .REG import * from .SHIFT import * +from .SIPO import * diff --git a/docs/_build/doctrees/api.doctree b/docs/_build/doctrees/api.doctree index b8330a22304dd69f138de7177993536ac5a3ccbb..2f76a4e02d565a028b82f8e29283a1885895630f 100644 GIT binary patch delta 4881 zcmaKwZERCj7{_VZZnv&$i|O5K+hqiB4u{Mvb8fuK++dq^Tk9LJt#{kq+ELf8?T8TA zSfXD@1Hze!F$N_uMi-or@rfwGX#8N5NMZ~jNF?GHVn7o=8G}COJncDm_pJLuPXD|2 zd49ippL=@Cm%mv~E?5gs6uk4_{H4O#LGrNPv2=QHyM>Hs-k7^JsgJdW+dE>>L`N*1 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[Not supported by viewer] \ No newline at end of file diff --git a/docs/_build/html/_sources/api.rst.txt b/docs/_build/html/_sources/api.rst.txt index 16bf3bc..024fc36 100644 --- a/docs/_build/html/_sources/api.rst.txt +++ b/docs/_build/html/_sources/api.rst.txt @@ -69,6 +69,27 @@ API Documentation :doc:`storage` ============== +* :ref:`DFlipFlop` +* :ref:`DFlipFlopPresetClear` +* :ref:`GatedDLatch` +* :ref:`GatedSRLatch` +* :ref:`JKFlipFlop` +* :ref:`JKFlipFlopPresetClear` +* :ref:`ParallelToSerialConverter4To1` +* :ref:`ParallelToSerialConverter8To1` +* :ref:`ParallelToSerialConverter16To1` +* :ref:`SerialToParallelConverter1To4` +* :ref:`SerialToParallelConverter1To8` +* :ref:`SerialToParallelConverter1To16` +* :ref:`Register4` +* :ref:`Register8` +* :ref:`Register16` +* :ref:`ShiftRegister4` +* :ref:`ShiftRegister8` +* :ref:`ShiftRegister16` +* :ref:`SRLatch` +* :ref:`TFlipFlop` +* :ref:`TFlipFlopPresetClear` :doc:`wire` =========== diff --git a/docs/_build/html/_sources/changelog.rst.txt b/docs/_build/html/_sources/changelog.rst.txt new file mode 100644 index 0000000..0281a3a --- /dev/null +++ b/docs/_build/html/_sources/changelog.rst.txt @@ -0,0 +1,49 @@ +:tocdepth: 2 + +========= +Changelog +========= + + +Unreleased +========== + +Added +----- +* Shift register classes to storage subpackage + * ``ShiftRegister4`` + * ``ShiftRegister8`` + * ``ShiftRegister16`` + +* Parallel-to-serial converter classes to signal subpackage + * ``ParallelToSerialConverter4To1`` + * ``ParallelToSerialConverter8To1`` + * ``ParallelToSerialConverter16To1`` + +* Serial-to-parallel converter classes to signal subpackage + * ``SerialToParallelConverter1To4`` + * ``SerialToParallelConverter1To8`` + * ``SerialToParallelConverter1To16`` + +* Buffer class to gate subpackage +* ``__getitem__()`` and ``__len__()`` methods to ``Bus4``, ``Bus8``, ``Bus16``, and ``BusSevenSegmentDisplay`` classes + +Changed +------- +* Rewrote docstrings for all classes +* Misc improvements + + +v0.1.1 - 2018-10-17 +=================== + +Added +----- +* Storage register classes to storage subpackage + * ``Register4`` + * ``Register8`` + * ``Register16`` + +Changed +------- +* Misc improvements diff --git a/docs/_build/html/_sources/index.rst.txt b/docs/_build/html/_sources/index.rst.txt index c377826..4d8ccee 100644 --- a/docs/_build/html/_sources/index.rst.txt +++ b/docs/_build/html/_sources/index.rst.txt @@ -1,3 +1,17 @@ +.. toctree:: + :hidden: + + api + arithmetic + changelog + gate + install + logic + signal + storage + wire + + ============= About Bitwise ============= @@ -40,7 +54,7 @@ Interacting with it in a Python session:: In [2]: b.value = 0 - In [3]: sum.value + In [3]: sum_.value Out[3]: 0 In [4]: carry_out.value @@ -48,7 +62,7 @@ Interacting with it in a Python session:: In [5]: a.value = 1 - In [6]: sum.value + In [6]: sum_.value Out[6]: 1 In [7]: carry_out.value @@ -56,7 +70,7 @@ Interacting with it in a Python session:: In [8]: b.value = 1 - In [9]: sum.value + In [9]: sum_.value Out[9]: 0 In [10]: carry_out.value diff --git a/docs/_build/html/_sources/signal.rst.txt b/docs/_build/html/_sources/signal.rst.txt index 7664be0..5184dde 100644 --- a/docs/_build/html/_sources/signal.rst.txt +++ b/docs/_build/html/_sources/signal.rst.txt @@ -578,7 +578,7 @@ Args: * ``select``: An object of type ``Wire``. The select input. * ``input_1``: An object of type ``Wire``. The first data input to the multiplexer. * ``input_2``: An object of type ``Wire``. The second data input to the multiplexer. -* ``output``: An object of type ``Wire``. The output of the multiplexer, which takes on the value of ``input_1`` for a 1 select and ``input_2`` for a 0 select. +* ``output``: An object of type ``Wire``. The output of the multiplexer. Takes on the value of ``input_1`` for a 1 select and ``input_2`` for a 0 select. .. _Multiplexer4To1: @@ -617,7 +617,7 @@ Args: * ``select_1``: An object of type ``Wire``. The most significant bit of the select input. * ``select_2``: An object of type ``Wire``. The least significant bit of the select input. * ``input_bus``: An object of type ``Bus4``. The data input to the multiplexer. -* ``output``: An object of type ``Wire``. The output of the multiplexer, which takes on the value of ``input_bus[0]`` for a (1, 1) select and ``input_bus[3]`` for a (0, 0) select. +* ``output``: An object of type ``Wire``. The output of the multiplexer. Takes on the value of ``input_bus[0]`` for a (1, 1) select and ``input_bus[3]`` for a (0, 0) select. Raises: ~~~~~~~ @@ -662,7 +662,7 @@ Args: * ``select_2``: An object of type ``Wire``. * ``select_3``: An object of type ``Wire``. The least significant bit of the select input. * ``input_bus``: An object of type ``Bus8``. The data input to the multiplexer. -* ``output``: An object of type ``Wire``. The output of the multiplexer, which takes on the value of ``input_bus[0]`` for a (1, 1, 1) select and ``input_bus[7]`` for a (0, 0, 0) select. +* ``output``: An object of type ``Wire``. The output of the multiplexer. Takes on the value of ``input_bus[0]`` for a (1, 1, 1) select and ``input_bus[7]`` for a (0, 0, 0) select. Raises: ~~~~~~~ @@ -703,7 +703,7 @@ Args: * ``enable``: An object of type ``Wire``. Enables the multiplexer. * ``select_bus``: An object of type ``Bus4``. ``select_bus[0]`` and ``select_bus[3]`` are the most and least significant bit, respectively. * ``input_bus``: An object of type ``Bus16``. The data input to the multiplexer. -* ``output``: An object of type ``Wire``. The output of the multiplexer, which takes on the value of ``input_bus[0]`` for a (1, 1, 1, 1) select and ``input_bus[15]`` for a (0, 0, 0, 0) select. +* ``output``: An object of type ``Wire``. The output of the multiplexer. Takes on the value of ``input_bus[0]`` for a (1, 1, 1, 1) select and ``input_bus[15]`` for a (0, 0, 0, 0) select. Raises: ~~~~~~~ diff --git a/docs/_build/html/_sources/storage.rst.txt b/docs/_build/html/_sources/storage.rst.txt index e318e4e..cdcb1ff 100644 --- a/docs/_build/html/_sources/storage.rst.txt +++ b/docs/_build/html/_sources/storage.rst.txt @@ -3,3 +3,882 @@ ======= Storage ======= + + +.. _DFlipFlop: + +DFlipFlop +========= + +Class ``bw.storage.DFlipFlop`` +------------------------------ + +.. image:: images/schematics/storage/DFlipFlop.svg + :width: 360px + +Defined in `bitwise/storage/FLOP.py `_. + +Positive edge-triggered `D flip-flop `_. + +__init__ +-------- + +:: + + __init__( + data, + clock, + output, + output_not + ) + +Construct a new positive edge-triggered D flip-flop. + +Args: +~~~~~ +* ``data``: An object of type ``Wire``. The data input to the flip-flop. +* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the flip-flop. +* ``output``: An object of type ``Wire``. The output of the flip-flop. Takes on the value of ``data`` on the positive edges of ``clock``. +* ``output_not``: An object of type ``Wire``. The complemented form of ``output``. + + +.. _DFlipFlopPresetClear: + +DFlipFlopPresetClear +==================== + +Class ``bw.storage.DFlipFlopPresetClear`` +----------------------------------------- + +.. image:: images/schematics/storage/DFlipFlopPresetClear.svg + :width: 360px + +Defined in `bitwise/storage/FLOP.py `_. + +Positive edge-triggered `D flip-flop `_ with asynchronous active low preset and clear. + +__init__ +-------- + +:: + + __init__( + data, + preset_n, + clear_n, + clock, + output, + output_not + ) + +Construct a new positive edge-triggered D flip-flop with preset/clear capabilities. + +Args: +~~~~~ +* ``data``: An object of type ``Wire``. The data input to the flip-flop. +* ``preset_n``: An object of type ``Wire``. Presets ``output`` to 1 and ``output_not`` to 0 if its value is 0. +* ``clear_n``: An object of type ``Wire``. Clears ``output`` to 0 and ``output_not`` to 1 if its value is 0. +* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the flip-flop. +* ``output``: An object of type ``Wire``. The output of the flip-flop. Takes on the value of ``data`` on the positive edges of ``clock``. +* ``output_not``: An object of type ``Wire``. The complemented form of ``output``. + + +.. _GatedDLatch: + +GatedDLatch +=========== + +Class ``bw.storage.GatedDLatch`` +-------------------------------- + +.. image:: images/schematics/storage/GatedDLatch.svg + :width: 360px + +Defined in `bitwise/storage/FLOP.py `_. + +`Gated D latch `_. + +__init__ +-------- + +:: + + __init__( + data, + clock, + output, + output_not + ) + +Construct a new gated D latch. + +Args: +~~~~~ +* ``data``: An object of type ``Wire``. The data input to the latch. +* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the latch. +* ``output``: An object of type ``Wire``. The output of the latch. Takes on the value of ``data`` if the value of ``clock`` is 1. +* ``output_not``: An object of type ``Wire``. The complemented form of ``output``. + + +.. _GatedSRLatch: + +GatedSRLatch +============ + +Class ``bw.storage.GatedSRLatch`` +--------------------------------- + +.. image:: images/schematics/storage/GatedSRLatch.svg + :width: 360px + +Defined in `bitwise/storage/FLOP.py `_. + +`Gated SR latch `_. + +__init__ +-------- + +:: + + __init__( + set_, + reset, + clock, + output, + output_not + ) + +Construct a new gated SR latch. + +Args: +~~~~~ +* ``set_``: An object of type ``Wire``. The set input to the latch. +* ``reset``: An object of type ``Wire``. The reset input to the latch. +* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the latch. +* ``output``: An object of type ``Wire``. The output of the latch. When the value of ``clock`` is 1, takes on the value of 1 if the value of ``set`` is 1 and the value of 0 if the value of ``reset`` is 1. +* ``output_not``: An object of type ``Wire``. The complemented form of ``output``. + + +.. _JKFlipFlop: + +JKFlipFlop +========== + +Class ``bw.storage.JKFlipFlop`` +------------------------------- + +.. image:: images/schematics/storage/JKFlipFlop.svg + :width: 360px + +Defined in `bitwise/storage/FLOP.py `_. + +Positive edge-triggered `JK flip-flop `_. + +__init__ +-------- + +:: + + __init__( + J, + K, + clock, + output, + output_not + ) + +Construct a new positive edge-triggered JK flip-flop. + +Args: +~~~~~ +* ``J``: An object of type ``Wire``. The J input to the flip-flop. +* ``K``: An object of type ``Wire``. The K input to the flip-flop. +* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the flip-flop. +* ``output``: An object of type ``Wire``. The output of the flip-flop. On the positive edges of ``clock``, takes on the value of 1 if the value of ``J`` is 1, takes on the value of 0 if the value of ``K`` is 1, and toggles its value if both ``J`` and ``K`` have value 1. +* ``output_not``: An object of type ``Wire``. The complemented form of ``output``. + + +.. _JKFlipFlopPresetClear: + +JKFlipFlopPresetClear +===================== + +Class ``bw.storage.JKFlipFlopPresetClear`` +------------------------------------------ + +.. image:: images/schematics/storage/JKFlipFlopPresetClear.svg + :width: 360px + +Defined in `bitwise/storage/FLOP.py `_. + +Positive edge-triggered `JK flip-flop `_ with asynchronous active low preset and clear. + +__init__ +-------- + +:: + + __init__( + J, + K, + preset_n, + clear_n, + clock, + output, + output_not + ) + +Construct a new positive edge-triggered JK flip-flop with preset/clear capabilities. + +Args: +~~~~~ +* ``J``: An object of type ``Wire``. The J input to the flip-flop. +* ``K``: An object of type ``Wire``. The K input to the flip-flop. +* ``preset_n``: An object of type ``Wire``. Presets ``output`` to 1 and ``output_not`` to 0 if its value is 0. +* ``clear_n``: An object of type ``Wire``. Clears ``output`` to 0 and ``output_not`` to 1 if its value is 0. +* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the flip-flop. +* ``output``: An object of type ``Wire``. The output of the flip-flop. On the positive edges of ``clock``, takes on the value of 1 if the value of ``J`` is 1, takes on the value of 0 if the value of ``K`` is 1, and toggles its value if both ``J`` and ``K`` have value 1. +* ``output_not``: An object of type ``Wire``. The complemented form of ``output``. + + +.. _ParallelToSerialConverter4To1: + +ParallelToSerialConverter4To1 +============================= + +Class ``bw.signal.ParallelToSerialConverter4To1`` +------------------------------------------------- + +.. image:: images/schematics/storage/ParallelToSerialConverter4To1.svg + :width: 600px + +Defined in `bitwise/storage/PISO.py `_. + +`4-bit-parallel-to-serial converter `_. + +__init__ +-------- + +:: + + __init__( + enable, + clear_n, + load_n, + data_bus, + clock, + output + ) + +Construct a new 4-bit-parallel-to-serial converter. + +Args: +~~~~~ +* ``enable``: An object of type ``Wire``. Enables the converter. +* ``clear_n``: An object of type ``Wire``. Clears all 4 internal registers to 0 if its value is 0. +* ``load_n``: An object of type ``Wire``. The mode select. A value of 0 indicates a parallel load operation, where the values of ``data_bus`` are loaded into the internal registers. A value of 1 indicates a shift-right operation. +* ``data_bus``: An object of type ``Bus4``. The parallel data input. +* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input. +* ``output``: An object of type ``Wire``. The serial output of the converter. ``data_bus[3]`` is outputted first, and ``data_bus[0]`` is outputted last. + +Raises: +~~~~~~~ +* ``TypeError``: If ``data_bus`` is not a bus of width 4. + + +.. _ParallelToSerialConverter8To1: + +ParallelToSerialConverter8To1 +============================= + +Class ``bw.signal.ParallelToSerialConverter8To1`` +------------------------------------------------- + +.. image:: images/schematics/storage/ParallelToSerialConverter8To1.svg + :width: 600px + +Defined in `bitwise/storage/PISO.py `_. + +`8-bit-parallel-to-serial converter `_. + +__init__ +-------- + +:: + + __init__( + enable, + clear_n, + load_n, + data_bus, + clock, + output + ) + +Construct a new 8-bit-parallel-to-serial converter. + +Args: +~~~~~ +* ``enable``: An object of type ``Wire``. Enables the converter. +* ``clear_n``: An object of type ``Wire``. Clears all 8 internal registers to 0 if its value is 0. +* ``load_n``: An object of type ``Wire``. The mode select. A value of 0 indicates a parallel load operation, where the values of ``data_bus`` are loaded into the internal registers. A value of 1 indicates a shift-right operation. +* ``data_bus``: An object of type ``Bus8``. The parallel data input. +* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input. +* ``output``: An object of type ``Wire``. The serial output of the converter. ``data_bus[7]`` is outputted first, and ``data_bus[0]`` is outputted last. + +Raises: +~~~~~~~ +* ``TypeError``: If ``data_bus`` is not a bus of width 8. + + +.. _ParallelToSerialConverter16To1: + +ParallelToSerialConverter16To1 +============================== + +Class ``bw.signal.ParallelToSerialConverter16To1`` +-------------------------------------------------- + +.. image:: images/schematics/storage/ParallelToSerialConverter16To1.svg + :width: 600px + +Defined in `bitwise/storage/PISO.py `_. + +`16-bit-parallel-to-serial converter `_. + +__init__ +-------- + +:: + + __init__( + enable, + clear_n, + load_n, + data_bus, + clock, + output + ) + +Construct a new 16-bit-parallel-to-serial converter. + +Args: +~~~~~ +* ``enable``: An object of type ``Wire``. Enables the converter. +* ``clear_n``: An object of type ``Wire``. Clears all 16 internal registers to 0 if its value is 0. +* ``load_n``: An object of type ``Wire``. The mode select. A value of 0 indicates a parallel load operation, where the values of ``data_bus`` are loaded into the internal registers. A value of 1 indicates a shift-right operation. +* ``data_bus``: An object of type ``Bus16``. The parallel data input. +* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input. +* ``output``: An object of type ``Wire``. The serial output of the converter. ``data_bus[15]`` is outputted first, and ``data_bus[0]`` is outputted last. + +Raises: +~~~~~~~ +* ``TypeError``: If ``data_bus`` is not a bus of width 16. + + +.. _Register4: + +Register4 +========= + +Class ``bw.storage.Register4`` +------------------------------ + +.. image:: images/schematics/storage/Register4.svg + :width: 800px + +Defined in `bitwise/storage/REG.py `_. + +`4-bit storage register `_. + +__init__ +-------- + +:: + + __init__( + data_bus, + clock, + output_bus + ) + +Construct a new 4-bit storage register. + +Args: +~~~~~ +* ``data_bus``: An object of type ``Bus4``. The data input to the register. +* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the register. +* ``output_bus``: An object of type ``Bus4``. The output of the register. Takes on the value of ``data_bus`` on the positive edges of ``clock``. + +Raises: +~~~~~~~ +* ``TypeError``: If either ``data_bus`` or ``output_bus`` is not a bus of width 4. + + +.. _Register8: + +Register8 +========= + +Class ``bw.storage.Register8`` +------------------------------ + +.. image:: images/schematics/storage/Register8.svg + :width: 800px + +Defined in `bitwise/storage/REG.py `_. + +`8-bit storage register `_. + +__init__ +-------- + +:: + + __init__( + data_bus, + clock, + output_bus + ) + +Construct a new 8-bit storage register. + +Args: +~~~~~ +* ``data_bus``: An object of type ``Bus8``. The data input to the register. +* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the register. +* ``output_bus``: An object of type ``Bus8``. The output of the register. Takes on the value of ``data_bus`` on the positive edges of ``clock``. + +Raises: +~~~~~~~ +* ``TypeError``: If either ``data_bus`` or ``output_bus`` is not a bus of width 8. + + +.. _Register16: + +Register16 +========== + +Class ``bw.storage.Register16`` +------------------------------- + +.. image:: images/schematics/storage/Register16.svg + :width: 800px + +Defined in `bitwise/storage/REG.py `_. + +`16-bit storage register `_. + +__init__ +-------- + +:: + + __init__( + data_bus, + clock, + output_bus + ) + +Construct a new 16-bit storage register. + +Args: +~~~~~ +* ``data_bus``: An object of type ``Bus16``. The data input to the register. +* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the register. +* ``output_bus``: An object of type ``Bus16``. The output of the register. Takes on the value of ``data_bus`` on the positive edges of ``clock``. + +Raises: +~~~~~~~ +* ``TypeError``: If either ``data_bus`` or ``output_bus`` is not a bus of width 16. + + +.. _SerialToParallelConverter1To4: + +SerialToParallelConverter1To4 +============================= + +Class ``bw.storage.SerialToParallelConverter1To4`` +-------------------------------------------------- + +.. image:: images/schematics/storage/SerialToParallelConverter1To4.svg + :width: 600px + +Defined in `bitwise/storage/SIPO.py `_. + +`Serial-to-4-bit-parallel converter `_. + +__init__ +-------- + +:: + + __init__( + enable, + clear_n, + data, + clock, + output_bus + ) + +Construct a new serial-to-4-bit-parallel converter. + +Args: +~~~~~ +* ``enable``: An object of type ``Wire``. Enables the converter. +* ``clear_n``: An object of type ``Wire``. Clears all 4 internal registers to 0 if its value is 0. +* ``data``: An object of type ``Wire``. The serial data input. +* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input. +* ``output_bus``: An object of type ``Bus4``. The parallel output of the converter. ``output[0]`` corresponds to the most recent serial data input. + +Raises: +~~~~~~~ +* ``TypeError``: If ``output_bus`` is not a bus of width 4. + + +.. _SerialToParallelConverter1To8: + +SerialToParallelConverter1To8 +============================= + +Class ``bw.storage.SerialToParallelConverter1To8`` +-------------------------------------------------- + +.. image:: images/schematics/storage/SerialToParallelConverter1To8.svg + :width: 600px + +Defined in `bitwise/storage/SIPO.py `_. + +`Serial-to-8-bit-parallel converter `_. + +__init__ +-------- + +:: + + __init__( + enable, + clear_n, + data, + clock, + output_bus + ) + +Construct a new serial-to-8-bit-parallel converter. + +Args: +~~~~~ +* ``enable``: An object of type ``Wire``. Enables the converter. +* ``clear_n``: An object of type ``Wire``. Clears all 8 internal registers to 0 if its value is 0. +* ``data``: An object of type ``Wire``. The serial data input. +* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input. +* ``output_bus``: An object of type ``Bus8``. The parallel output of the converter. ``output[0]`` corresponds to the most recent serial data input. + +Raises: +~~~~~~~ +* ``TypeError``: If ``output_bus`` is not a bus of width 8. + + +.. _SerialToParallelConverter1To16: + +SerialToParallelConverter1To16 +============================== + +Class ``bw.storage.SerialToParallelConverter1To16`` +--------------------------------------------------- + +.. image:: images/schematics/storage/SerialToParallelConverter1To16.svg + :width: 600px + +Defined in `bitwise/storage/SIPO.py `_. + +`Serial-to-16-bit-parallel converter `_. + +__init__ +-------- + +:: + + __init__( + enable, + clear_n, + data, + clock, + output_bus + ) + +Construct a new serial-to-16-bit-parallel converter. + +Args: +~~~~~ +* ``enable``: An object of type ``Wire``. Enables the converter. +* ``clear_n``: An object of type ``Wire``. Clears all 16 internal registers to 0 if its value is 0. +* ``data``: An object of type ``Wire``. The serial data input. +* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input. +* ``output_bus``: An object of type ``Bus16``. The parallel output of the converter. ``output[0]`` corresponds to the most recent serial data input. + +Raises: +~~~~~~~ +* ``TypeError``: If ``output_bus`` is not a bus of width 16. + + +.. _ShiftRegister4: + +ShiftRegister4 +============== + +Class ``bw.storage.ShiftRegister4`` +----------------------------------- + +.. image:: images/schematics/storage/ShiftRegister4.svg + :width: 800px + +Defined in `bitwise/storage/SHIFT.py `_. + +`4-bit shift register `_. + +__init__ +-------- + +:: + + __init__( + enable, + clear_n, + shift_load, + data_bus, + data_serial, + clock, + output_bus, + output_serial + ) + +Construct a new 4-bit shift register. + +Args: +~~~~~ +* ``enable``: An object of type ``Wire``. Enables the shift register. +* ``clear_n``: An object of type ``Wire``. Clears ``output_bus`` and ``output_serial`` to 0 if its value is 1. +* ``shift_load``: An object of type ``Wire``. The mode select. A value of 0 indicates a parallel load operation, where ``output_bus`` takes on the value of ``data_bus``. A value of 1 indicates a shift-right operation, where ``output_bus[3]`` takes on the value of ``output_bus[2]``, ``output_bus[2]`` takes on the value of ``output_bus[1]``, and so on; ``output_bus[0]`` takes on the value of ``data_serial``. +* ``data_bus``: An object of type ``Bus4``. The parallel data input. +* ``data_serial``. An object of type ``Wire``. The serial data input. +* ``clock``. An object of type ``Wire`` or ``Clock``. The clock input to the shift register. +* ``output_bus``. An object of type ``Bus4``. The parallel data output. +* ``output_serial``. An object of type ``Wire``. The serial data output. Identical to ``output_bus[3]``. + +Raises: +~~~~~~~ +* ``TypeError``: If either ``data_bus`` or ``output_bus`` is not a bus of width 4. + + +.. _ShiftRegister8: + +ShiftRegister8 +============== + +Class ``bw.storage.ShiftRegister8`` +----------------------------------- + +.. image:: images/schematics/storage/ShiftRegister8.svg + :width: 800px + +Defined in `bitwise/storage/SHIFT.py `_. + +`8-bit shift register `_. + +__init__ +-------- + +:: + + __init__( + enable, + clear_n, + shift_load, + data_bus, + data_serial, + clock, + output_bus, + output_serial + ) + +Construct a new 8-bit shift register. + +Args: +~~~~~ +* ``enable``: An object of type ``Wire``. Enables the shift register. +* ``clear_n``: An object of type ``Wire``. Clears ``output_bus`` and ``output_serial`` to 0 if its value is 1. +* ``shift_load``: An object of type ``Wire``. The mode select. A value of 0 indicates a parallel load operation, where ``output_bus`` takes on the value of ``data_bus``. A value of 1 indicates a shift-right operation, where ``output_bus[7]`` takes on the value of ``output_bus[6]``, ``output_bus[6]`` takes on the value of ``output_bus[5]``, and so on; ``output_bus[0]`` takes on the value of ``data_serial``. +* ``data_bus``: An object of type ``Bus8``. The parallel data input. +* ``data_serial``. An object of type ``Wire``. The serial data input. +* ``clock``. An object of type ``Wire`` or ``Clock``. The clock input to the shift register. +* ``output_bus``. An object of type ``Bus8``. The parallel data output. +* ``output_serial``. An object of type ``Wire``. The serial data output. Identical to ``output_bus[7]``. + +Raises: +~~~~~~~ +* ``TypeError``: If either ``data_bus`` or ``output_bus`` is not a bus of width 8. + + +.. _ShiftRegister16: + +ShiftRegister16 +=============== + +Class ``bw.storage.ShiftRegister16`` +------------------------------------ + +.. image:: images/schematics/storage/ShiftRegister16.svg + :width: 800px + +Defined in `bitwise/storage/SHIFT.py `_. + +`16-bit shift register `_. + +__init__ +-------- + +:: + + __init__( + enable, + clear_n, + shift_load, + data_bus, + data_serial, + clock, + output_bus, + output_serial + ) + +Construct a new 16-bit shift register. + +Args: +~~~~~ +* ``enable``: An object of type ``Wire``. Enables the shift register. +* ``clear_n``: An object of type ``Wire``. Clears ``output_bus`` and ``output_serial`` to 0 if its value is 1. +* ``shift_load``: An object of type ``Wire``. The mode select. A value of 0 indicates a parallel load operation, where ``output_bus`` takes on the value of ``data_bus``. A value of 1 indicates a shift-right operation, where ``output_bus[15]`` takes on the value of ``output_bus[14]``, ``output_bus[14]`` takes on the value of ``output_bus[13]``, and so on; ``output_bus[0]`` takes on the value of ``data_serial``. +* ``data_bus``: An object of type ``Bus16``. The parallel data input. +* ``data_serial``. An object of type ``Wire``. The serial data input. +* ``clock``. An object of type ``Wire`` or ``Clock``. The clock input to the shift register. +* ``output_bus``. An object of type ``Bus16``. The parallel data output. +* ``output_serial``. An object of type ``Wire``. The serial data output. Identical to ``output_bus[15]``. + +Raises: +~~~~~~~ +* ``TypeError``: If either ``data_bus`` or ``output_bus`` is not a bus of width 16. + + +.. _SRLatch: + +SRLatch +======= + +Class ``bw.storage.SRLatch`` +---------------------------- + +.. image:: images/schematics/storage/SRLatch.svg + :width: 360px + +Defined in `bitwise/storage/FLOP.py `_. + +`SR latch `_. + +__init__ +-------- + +:: + + __init__( + set_, + reset, + output, + output_not + ) + +Construct a new SR latch. + +Args: +~~~~~ +* ``set_``: An object of type ``Wire``. The set input to the latch. +* ``reset``: An object of type ``Wire``. The reset input to the latch. +* ``output``: An object of type ``Wire``. The output of the latch. Takes on the value of 1 if the value of ``set`` is 1 and the value of 0 if the value of ``reset`` is 1. +* ``output_not``: An object of type ``Wire``. The complemented form of ``output``. + + +.. _TFlipFlop: + +TFlipFlop +========= + +Class ``bw.storage.TFlipFlop`` +------------------------------ + +.. image:: images/schematics/storage/TFlipFlop.svg + :width: 360px + +Defined in `bitwise/storage/FLOP.py `_. + +Positive edge-triggered `T flip-flop `_. + +__init__ +-------- + +:: + + __init__( + toggle, + clock, + output, + output_not + ) + +Construct a new positive edge-triggered T flip-flop. + +Args: +~~~~~ +* ``toggle``: An object of type ``Wire``. The toggle input to the flip-flop. +* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the flip-flop. +* ``output``: An object of type ``Wire``. The output of the flip-flop. Toggles its value on the positive edges of ``clock`` if the value of ``toggle`` is 1. +* ``output_not``: An object of type ``Wire``. The complemented form of ``output``. + + +.. _TFlipFlopPresetClear: + +TFlipFlopPresetClear +==================== + +Class ``bw.storage.TFlipFlopPresetClear`` +----------------------------------------- + +.. image:: images/schematics/storage/TFlipFlopPresetClear.svg + :width: 360px + +Defined in `bitwise/storage/FLOP.py `_. + +Positive edge-triggered `T flip-flop `_ with asynchronous active low preset and clear. + +__init__ +-------- + +:: + + __init__( + toggle, + preset_n, + clear_n, + clock, + output, + output_not + ) + +Construct a new positive edge-triggered T flip-flop with preset/clear capabilities. + +Args: +~~~~~ +* ``toggle``: An object of type ``Wire``. The toggle input to the flip-flop. +* ``preset_n``: An object of type ``Wire``. Presets ``output`` to 1 and ``output_not`` to 0 if its value is 0. +* ``clear_n``: An object of type ``Wire``. Clears ``output`` to 0 and ``output_not`` to 1 if its value is 0. +* ``clock``: An object of type ``Wire`` or ``Clock``. The clock input to the flip-flop. +* ``output``: An object of type ``Wire``. The output of the flip-flop. Toggles its value on the positive edges of ``clock`` if the value of ``toggle`` is 1. +* ``output_not``: An object of type ``Wire``. The complemented form of ``output``. diff --git a/docs/_build/html/_static/alabaster.css b/docs/_build/html/_static/alabaster.css index 4966909..900083d 100644 --- a/docs/_build/html/_static/alabaster.css +++ b/docs/_build/html/_static/alabaster.css @@ -75,11 +75,11 @@ div.documentwrapper { } div.bodywrapper { - margin: 0 0 0 220px; + margin: 0 0 0 240px; } div.sphinxsidebar { - width: 220px; + width: 240px; font-size: 14px; line-height: 1.5; } diff --git a/docs/_build/html/_static/custom.css b/docs/_build/html/_static/custom.css index 3a79c64..1a0230e 100644 --- a/docs/_build/html/_static/custom.css +++ b/docs/_build/html/_static/custom.css @@ -1,10 +1,40 @@ @import url('https://fonts.googleapis.com/css?family=Sorts+Mill+Goudy'); +@import url('https://fonts.googleapis.com/css?family=EB+Garamond'); body { font-family: 'Sorts Mill Goudy', serif; } +/* +div.sphinxsidebar { + width: 240px; + font-size: 14px; + line-height: 1.5; + overflow-y: scroll; + top: 40px; + bottom: 0; +} + +div.sphinxsidebarwrapper { + padding: 18px 10px; +} +*/ +div.sphinxsidebar input { + font-family: 'Sorts Mill Goudy', serif; +} a:hover, a:visited, a:link, a:active { /* text-decoration: none !important; */ border-bottom: none !important; } + +div.body h1, +div.body h2, +div.body h3, +div.body h4, +div.body h5, +div.body h6 { + font-family: 'Garamond', 'Georgia', serif; + font-weight: normal; + margin: 30px 0px 10px 0px; + padding: 0; +} diff --git a/docs/_build/html/api.html b/docs/_build/html/api.html index ed7d68d..f617b91 100644 --- a/docs/_build/html/api.html +++ b/docs/_build/html/api.html @@ -24,6 +24,8 @@ + + @@ -64,6 +66,8 @@

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    Changelog

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    + ©2018, James Jiang. + + | + Page source +
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    diff --git a/docs/_build/html/genindex.html b/docs/_build/html/genindex.html index 3902390..b655296 100644 --- a/docs/_build/html/genindex.html +++ b/docs/_build/html/genindex.html @@ -65,6 +65,8 @@

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