diff --git a/bitwise/arithmetic/ADD.py b/bitwise/arithmetic/ADD.py index 944e638..0f86572 100644 --- a/bitwise/arithmetic/ADD.py +++ b/bitwise/arithmetic/ADD.py @@ -1,3 +1,12 @@ +""" +The following classes are defined: + Adder4 + Adder8 + Adder16 + FullAdder + HalfAdder +""" + from .. import wire from .. import gate @@ -8,12 +17,29 @@ class HalfAdder: + """Construct a new half adder. + + Args: + a: An object of type Wire. The first addend. + b: An object of type Wire. The second addend. + carry_out: An object of type Wire. The carry-out of the adder. + sum_: An object of type Wire. The sum of the two addends. + """ def __init__(self, input_1, input_2, carry_out, sum_): gate.ANDGate2(input_1, input_2, carry_out) gate.XORGate2(input_1, input_2, sum_) class FullAdder: + """Construct a new full adder. + + Args: + carry_in: An object of type Wire. The carry-in to the adder. + a: An object of type Wire. The first addend. + b: An object of type Wire. The second addend. + carry_out: An object of type Wire. The carry-out of the adder. + sum_: An object of type Wire. The sum of the two addends. + """ def __init__(self, carry_in, input_1, input_2, carry_out, sum_): wire_1 = Wire() wire_2 = Wire() @@ -26,7 +52,38 @@ def __init__(self, carry_in, input_1, input_2, carry_out, sum_): gate.ORGate2(wire_2, wire_3, carry_out) -class LookaheadCarryUnit4: +class _LookaheadCarryUnit4: + """ + This class simulates a lookahead carry unit for a 4-bit adder. Though an + LCU is not used in the 4-bit adder itself, it is useful for fast operations + with chained 4-bit adders. An LCU takes the binary numbers being added + together and determines if a carry is generated, without waiting for all + the carries to "ripple" through the chain. + + This LCU has eight inputs in two 4-bit buses, a carry_in input, and three + outputs: + ________ + carry_in ----| |---- carry_out + input_1 ----| |---- group_propagate + input_2 ----| |---- group_generate + input_3 ----| | + input_4 ----| | + input_5 ----| | + input_6 ----| | + input_7 ----| | + input_8 ----|________| + + Inputs input_1 and input_4 correspond to the MSB and LSB, respectively, + of the first addend, and inputs input_5 and input_8 correspond to the MSB + and LSB, respectively, of the second addend. The carry-in input is usually + 0 for an adder, but can be 1 if multiple adders are chained together. + + The carry_out output denotes whether or not the two 4-bit binary numbers + will have a carry-out. The group_propagate and group_generate outputs are + used in higher-order LCU's and denote, respectively, whether the binary + numbers will propagate an input carry-in to carry-out, and whether the + binary numbers will themselves generate a carry-out. + """ def __init__( self, carry_in, @@ -84,7 +141,50 @@ def __init__( gate.ORGate2(wire_4, group_generate, carry_out) -class LookaheadCarryUnit16: +class _LookaheadCarryUnit16: + """ + This class simulates a lookahead carry unit for a 16-bit adder. It is + useful for fast operations, since it takes the binary numbers being added + together and determines if a carry is generated, without waiting for all + the carries to "ripple" through the chain of adders. + + This LCU has thirty-two inputs in two 16-bit buses, a carry_in input, and + six outputs: + ________ + carry_in ----| |---- internal_carry_1 + input_1 ----| |---- internal_carry_2 + input_2 ----| |---- internal_carry_3 + input_3 ----| |---- carry_out + input_4 ----| |---- group_propagate + ... | |---- group_generate + input_13 ----| | + input_14 ----| | + input_15 ----| | + input_16 ----| | + input_17 ----| | + input_18 ----| | + input_19 ----| | + input_20 ----| | + ... + input_29 ----| | + input_30 ----| | + input_31 ----| | + input_32 ----|________| + + Inputs input_1 and input_16 correspond to the MSB and LSB, respectively, + of the first addend, and inputs input_17 and input_32 correspond to the MSB + and LSB, respectively, of the second addend. The carry-in input is usually + 0 for an adder, but can be 1 if multiple adders are chained together. + + The carry_out output denotes whether or not the two 16-bit binary numbers + will have a carry-out. The internal_carry outputs are used in the 16-bit + adder to speed up operations, with internal_carry_1 corresponding to the + carry from the LSB to the second-LSB. The group_propagate and + group_generate outputs are used in higher-order LCU's and denote, + respectively, whether the binary numbers will propagate an input carry-in + to carry-out, and whether the binary numbers will themselves generate a + carry-out. + """ def __init__( self, carry_in, @@ -131,7 +231,7 @@ def __init__( wire_2 = Wire() wire_3 = Wire() - LookaheadCarryUnit4( + _LookaheadCarryUnit4( carry_in, input_1_bus_1, input_2_bus_1, @@ -139,7 +239,7 @@ def __init__( lcu_1_pg, lcu_1_gg ) - LookaheadCarryUnit4( + _LookaheadCarryUnit4( internal_carry_1, input_1_bus_2, input_2_bus_2, @@ -147,7 +247,7 @@ def __init__( lcu_2_pg, lcu_2_gg ) - LookaheadCarryUnit4( + _LookaheadCarryUnit4( internal_carry_2, input_1_bus_3, input_2_bus_3, @@ -155,7 +255,7 @@ def __init__( lcu_3_pg, lcu_3_gg ) - LookaheadCarryUnit4( + _LookaheadCarryUnit4( internal_carry_3, input_1_bus_4, input_2_bus_4, @@ -172,14 +272,30 @@ def __init__( class Adder4: + """Construct a new 4-bit adder. + + Args: + carry_in: An object of type Wire. The carry-in to the adder. + a_bus: An object of type Bus4. The first addend. a_bus[0] and a_bus[3] + are the most and least significant bit, respectively. + b_bus: An object of type Bus4. The second addend. b_bus[0] and b_bus[3] + are the most and least significant bit, respectively. + carry_out: An object of type Wire. The carry-out of the adder. + sum_bus: An object of type Bus4. The sum of the two addends. sum_bus[0] + and sum_bus[3] are the most and least significant bit, + respectively. + + Raises: + TypeError: If either a_bus, b_bus, or sum_bus is not a bus of width 4. + """ def __init__( - self, - carry_in, - input_bus_1, - input_bus_2, - carry_out, - output_bus - ): + self, + carry_in, + input_bus_1, + input_bus_2, + carry_out, + output_bus + ): if len(input_bus_1.wires) != 4: raise TypeError( "Expected bus of width 4, received bus of width {0}.".format( @@ -216,14 +332,30 @@ def __init__( class Adder8: + """Construct a new 8-bit adder. + + Args: + carry_in: An object of type Wire. The carry-in to the adder. + a_bus: An object of type Bus8. The first addend. a_bus[0] and a_bus[7] + are the most and least significant bit, respectively. + b_bus: An object of type Bus8. The second addend. b_bus[0] and b_bus[7] + are the most and least significant bit, respectively. + carry_out: An object of type Wire. The carry-out of the adder. + sum_bus: An object of type Bus8. The sum of the two addends. sum_bus[0] + and sum_bus[7] are the most and least significant bit, + respectively. + + Raises: + TypeError: If either a_bus, b_bus, or sum_bus is not a bus of width 8. + """ def __init__( - self, - carry_in, - input_bus_1, - input_bus_2, - carry_out, - output_bus - ): + self, + carry_in, + input_bus_1, + input_bus_2, + carry_out, + output_bus + ): if len(input_bus_1.wires) != 8: raise TypeError( "Expected bus of width 8, received bus of width {0}.".format( @@ -259,7 +391,7 @@ def __init__( lcu_pg = Wire() lcu_gg = Wire() - LookaheadCarryUnit4( + _LookaheadCarryUnit4( carry_in, input_1_2, input_2_2, @@ -272,14 +404,30 @@ def __init__( class Adder16: + """Construct a new 16-bit adder. + + Args: + carry_in: An object of type Wire. The carry-in to the adder. + a_bus: An object of type Bus16. The first addend. a_bus[0] and + a_bus[15] are the most and least significant bit, respectively. + b_bus: An object of type Bus16. The second addend. b_bus[0] and + b_bus[15] are the most and least significant bit, respectively. + carry_out: An object of type Wire. The carry-out of the adder. + sum_bus: An object of type Bus16. The sum of the two addends. + sum_bus[0] and sum_bus[15] are the most and least significant bit, + respectively. + + Raises: + TypeError: If either a_bus, b_bus, or sum_bus is not a bus of width 16. + """ def __init__( - self, - carry_in, - input_bus_1, - input_bus_2, - carry_out, - output_bus - ): + self, + carry_in, + input_bus_1, + input_bus_2, + carry_out, + output_bus + ): if len(input_bus_1.wires) != 16: raise TypeError( "Expected bus of width 16, received bus of width {0}.".format( @@ -293,7 +441,7 @@ def __init__( len(input_bus_2.wires) ) ) - + if len(output_bus.wires) != 16: raise TypeError( "Expected bus of width 16, received bus of width {0}.".format( @@ -323,7 +471,7 @@ def __init__( lcu_pg = Wire() lcu_gg = Wire() - LookaheadCarryUnit16( + _LookaheadCarryUnit16( carry_in, input_bus_1, input_bus_2, diff --git a/bitwise/arithmetic/ADD_SUB.py b/bitwise/arithmetic/ADD_SUB.py index f0784ad..4d089d8 100644 --- a/bitwise/arithmetic/ADD_SUB.py +++ b/bitwise/arithmetic/ADD_SUB.py @@ -1,3 +1,10 @@ +""" +The following classes are defined: + AdderSubtractor4 + AdderSubtractor8 + AdderSubtractor16 +""" + from .. import wire from .. import gate from .. import signal @@ -10,15 +17,37 @@ class AdderSubtractor4: + """Construct a new 4-bit adder-subtractor. + + Args: + add_subtract: An object of type Wire. Indicates the operation to carry + out - 0 for addition, 1 for subtraction. + a_bus: An object of type Bus4. The first addend, or the minuend. + a_bus[0] and a_bus[3] are the most and least significant bit, + respectively. a_bus[0] is the sign bit in subtraction operations. + b_bus: An object of type Bus4. The second addend, or the subtrahend. + b_bus[0] and b_bus[3] are the most and least significant bit, + respectively. b_bus[0] is the sign bit in subtraction operations. + overflow: An object of type Wire. The overflow indicator of the + subtractor. + carry_out: An object of type Wire. The carry-out of the adder. + sum_bus: An object of type Bus4. The sum of the two addends, or the + difference between the minuend and the subtrahend. sum_bus[0] and + sum_bus[3] are the most and least significant bit, respectively. + sum_bus[0] is the sign bit in subtraction operations. + + Raises: + TypeError: If either a_bus, b_bus, or sum_bus is not a bus of width 4. + """ def __init__( - self, - add_subtract, - input_bus_1, - input_bus_2, - overflow, - carry_out, - output_bus - ): + self, + add_subtract, + input_bus_1, + input_bus_2, + overflow, + carry_out, + output_bus + ): if len(input_bus_1.wires) != 4: raise TypeError( "Expected bus of width 4, received bus of width {0}.".format( @@ -66,15 +95,37 @@ def __init__( class AdderSubtractor8: + """Construct a new 8-bit adder-subtractor. + + Args: + add_subtract: An object of type Wire. Indicates the operation to carry + out - 0 for addition, 1 for subtraction. + a_bus: An object of type Bus8. The first addend, or the minuend. + a_bus[0] and a_bus[7] are the most and least significant bit, + respectively. a_bus[0] is the sign bit in subtraction operations. + b_bus: An object of type Bus8. The second addend, or the subtrahend. + b_bus[0] and b_bus[7] are the most and least significant bit, + respectively. b_bus[0] is the sign bit in subtraction operations. + overflow: An object of type Wire. The overflow indicator of the + subtractor. + carry_out: An object of type Wire. The carry-out of the adder. + sum_bus: An object of type Bus8. The sum of the two addends, or the + difference between the minuend and the subtrahend. sum_bus[0] and + sum_bus[7] are the most and least significant bit, respectively. + sum_bus[0] is the sign bit in subtraction operations. + + Raises: + TypeError: If either a_bus, b_bus, or sum_bus is not a bus of width 8. + """ def __init__( - self, - add_subtract, - input_bus_1, - input_bus_2, - overflow, - carry_out, - output_bus - ): + self, + add_subtract, + input_bus_1, + input_bus_2, + overflow, + carry_out, + output_bus + ): if len(input_bus_1.wires) != 8: raise TypeError( "Expected bus of width 8, received bus of width {0}.".format( @@ -135,15 +186,37 @@ def __init__( class AdderSubtractor16: + """Construct a new 16-bit adder-subtractor. + + Args: + add_subtract: An object of type Wire. Indicates the operation to carry + out - 0 for addition, 1 for subtraction. + a_bus: An object of type Bus16. The first addend, or the minuend. + a_bus[0] and a_bus[15] are the most and least significant bit, + respectively. a_bus[0] is the sign bit in subtraction operations. + b_bus: An object of type Bus16. The second addend, or the subtrahend. + b_bus[0] and b_bus[15] are the most and least significant bit, + respectively. b_bus[0] is the sign bit in subtraction operations. + overflow: An object of type Wire. The overflow indicator of the + subtractor. + carry_out: An object of type Wire. The carry-out of the adder. + sum_bus: An object of type Bus16. The sum of the two addends, or the + difference between the minuend and the subtrahend. sum_bus[0] and + sum_bus[15] are the most and least significant bit, respectively. + sum_bus[0] is the sign bit in subtraction operations. + + Raises: + TypeError: If either a_bus, b_bus, or sum_bus is not a bus of width 16. + """ def __init__( - self, - add_subtract, - input_bus_1, - input_bus_2, - overflow, - carry_out, - output_bus - ): + self, + add_subtract, + input_bus_1, + input_bus_2, + overflow, + carry_out, + output_bus + ): if len(input_bus_1.wires) != 16: raise TypeError( "Expected bus of width 16, received bus of width {0}.".format( diff --git a/bitwise/gate/AND.py b/bitwise/gate/AND.py index b3a4297..4722b6e 100644 --- a/bitwise/gate/AND.py +++ b/bitwise/gate/AND.py @@ -1,9 +1,23 @@ +""" +The following classes are defined: + ANDGate2 + ANDGate3 + ANDGate4 +""" + from .. import wire Wire = wire.Wire class ANDGate2: + """Construct a new two-input AND gate. + + Args: + input_1: An object of type Wire. The first input to the AND gate. + input_2: An object of type Wire. The second input to the AND gate. + output: An object of type Wire. The output of the AND gate. + """ def __init__(self, input_1, input_2, output): self.input_1 = input_1 self.input_2 = input_2 @@ -32,6 +46,14 @@ def _update_input_2(self, value): class ANDGate3: + """Construct a new three-input AND gate. + + Args: + input_1: An object of type Wire. The first input to the AND gate. + input_2: An object of type Wire. The second input to the AND gate. + input_3: An object of type Wire. The third input to the AND gate. + output: An object of type Wire. The output of the AND gate. + """ def __init__(self, input_1, input_2, input_3, output): wire_1 = Wire() ANDGate2(input_1, input_2, wire_1) @@ -39,6 +61,15 @@ def __init__(self, input_1, input_2, input_3, output): class ANDGate4: + """Construct a new four-input AND gate. + + Args: + input_1: An object of type Wire. The first input to the AND gate. + input_2: An object of type Wire. The second input to the AND gate. + input_3: An object of type Wire. The third input to the AND gate. + input_4: An object of type Wire. The fourth input to the AND gate. + output: An object of type Wire. The output of the AND gate. + """ def __init__(self, input_1, input_2, input_3, input_4, output): wire_1 = Wire() wire_2 = Wire() diff --git a/bitwise/gate/NAND.py b/bitwise/gate/NAND.py index f39306e..a6090c3 100644 --- a/bitwise/gate/NAND.py +++ b/bitwise/gate/NAND.py @@ -1,3 +1,10 @@ +""" +The following classes are defined: + NANDGate2 + NANDGate3 + NANDGate4 +""" + from .. import wire from . import AND from . import NOT @@ -6,6 +13,13 @@ class NANDGate2: + """Construct a new two-input NAND gate. + + Args: + input_1: An object of type Wire. The first input to the NAND gate. + input_2: An object of type Wire. The second input to the NAND gate. + output: An object of type Wire. The output of the NAND gate. + """ def __init__(self, input_1, input_2, output): wire_1 = Wire() AND.ANDGate2(input_1, input_2, wire_1) @@ -13,6 +27,14 @@ def __init__(self, input_1, input_2, output): class NANDGate3: + """Construct a new three-input NAND gate. + + Args: + input_1: An object of type Wire. The first input to the NAND gate. + input_2: An object of type Wire. The second input to the NAND gate. + input_3: An object of type Wire. The third input to the NAND gate. + output: An object of type Wire. The output of the NAND gate. + """ def __init__(self, input_1, input_2, input_3, output): wire_1 = Wire() AND.ANDGate3(input_1, input_2, input_3, wire_1) @@ -20,6 +42,15 @@ def __init__(self, input_1, input_2, input_3, output): class NANDGate4: + """Construct a new four-input NAND gate. + + Args: + input_1: An object of type Wire. The first input to the NAND gate. + input_2: An object of type Wire. The second input to the NAND gate. + input_3: An object of type Wire. The third input to the NAND gate. + input_4: An object of type Wire. The fourth input to the NAND gate. + output: An object of type Wire. The output of the NAND gate. + """ def __init__(self, input_1, input_2, input_3, input_4, output): wire_1 = Wire() AND.ANDGate4(input_1, input_2, input_3, input_4, wire_1) diff --git a/bitwise/gate/NOR.py b/bitwise/gate/NOR.py index 247b092..0661594 100644 --- a/bitwise/gate/NOR.py +++ b/bitwise/gate/NOR.py @@ -1,3 +1,10 @@ +""" +The following classes are defined: + NORGate2 + NORGate3 + NORGate4 +""" + from .. import wire from . import OR from . import NOT @@ -6,6 +13,13 @@ class NORGate2: + """Construct a new two-input NOR gate. + + Args: + input_1: An object of type Wire. The first input to the NOR gate. + input_2: An object of type Wire. The second input to the NOR gate. + output: An object of type Wire. The output of the NOR gate. + """ def __init__(self, input_1, input_2, output): wire_1 = Wire() OR.ORGate2(input_1, input_2, wire_1) @@ -13,6 +27,14 @@ def __init__(self, input_1, input_2, output): class NORGate3: + """Construct a new three-input NOR gate. + + Args: + input_1: An object of type Wire. The first input to the NOR gate. + input_2: An object of type Wire. The second input to the NOR gate. + input_3: An object of type Wire. The third input to the NOR gate. + output: An object of type Wire. The output of the NOR gate. + """ def __init__(self, input_1, input_2, input_3, output): wire_1 = Wire() OR.ORGate3(input_1, input_2, input_3, wire_1) @@ -20,6 +42,15 @@ def __init__(self, input_1, input_2, input_3, output): class NORGate4: + """Construct a new four-input NOR gate. + + Args: + input_1: An object of type Wire. The first input to the NOR gate. + input_2: An object of type Wire. The second input to the NOR gate. + input_3: An object of type Wire. The third input to the NOR gate. + input_4: An object of type Wire. The fourth input to the NOR gate. + output: An object of type Wire. The output of the NOR gate. + """ def __init__(self, input_1, input_2, input_3, input_4, output): wire_1 = Wire() OR.ORGate4(input_1, input_2, input_3, input_4, wire_1) diff --git a/bitwise/gate/NOT.py b/bitwise/gate/NOT.py index 97ac684..fb7cbb1 100644 --- a/bitwise/gate/NOT.py +++ b/bitwise/gate/NOT.py @@ -1,4 +1,20 @@ +""" +The following classes are defined: + NOTGate +""" + +from .. import wire + +Wire = wire.Wire + + class NOTGate: + """Construct a new NOT gate. + + Args: + input_1: An object of type Wire. The input to the NOT gate. + output: An object of type Wire. The output of the NOT gate. + """ def __init__(self, input_1, output): self.input_1 = input_1 self.output = output diff --git a/bitwise/gate/OR.py b/bitwise/gate/OR.py index 6ea4d75..2648605 100644 --- a/bitwise/gate/OR.py +++ b/bitwise/gate/OR.py @@ -1,9 +1,23 @@ +""" +The following classes are defined: + ORGate2 + ORGate3 + ORGate4 +""" + from .. import wire Wire = wire.Wire class ORGate2: + """Construct a new two-input OR gate. + + Args: + input_1: An object of type Wire. The first input to the OR gate. + input_2: An object of type Wire. The second input to the OR gate. + output: An object of type Wire. The output of the OR gate. + """ def __init__(self, input_1, input_2, output): self.input_1 = input_1 self.input_2 = input_2 @@ -32,6 +46,14 @@ def _update_input_2(self, value): class ORGate3: + """Construct a new three-input OR gate. + + Args: + input_1: An object of type Wire. The first input to the OR gate. + input_2: An object of type Wire. The second input to the OR gate. + input_3: An object of type Wire. The third input to the OR gate. + output: An object of type Wire. The output of the OR gate. + """ def __init__(self, input_1, input_2, input_3, output): wire_1 = Wire() ORGate2(input_1, input_2, wire_1) @@ -39,6 +61,15 @@ def __init__(self, input_1, input_2, input_3, output): class ORGate4: + """Construct a new four-input OR gate. + + Args: + input_1: An object of type Wire. The first input to the OR gate. + input_2: An object of type Wire. The second input to the OR gate. + input_3: An object of type Wire. The third input to the OR gate. + input_4: An object of type Wire. The fourth input to the OR gate. + output: An object of type Wire. The output of the OR gate. + """ def __init__(self, input_1, input_2, input_3, input_4, output): wire_1 = Wire() wire_2 = Wire() diff --git a/bitwise/gate/XNOR.py b/bitwise/gate/XNOR.py index dfd97bf..910a3b5 100644 --- a/bitwise/gate/XNOR.py +++ b/bitwise/gate/XNOR.py @@ -1,3 +1,8 @@ +""" +The following classes are defined: + XNORGate2 +""" + from .. import wire from . import AND from . import OR @@ -7,6 +12,13 @@ class XNORGate2: + """Construct a new two-input XNOR gate. + + Args: + input_1: An object of type Wire. The first input to the XNOR gate. + input_2: An object of type Wire. The second input to the XNOR gate. + output: An object of type Wire. The output of the XNOR gate. + """ def __init__(self, input_1, input_2, output): wire_1 = Wire() wire_2 = Wire() diff --git a/bitwise/gate/XOR.py b/bitwise/gate/XOR.py index 01506fb..dd0a5bb 100644 --- a/bitwise/gate/XOR.py +++ b/bitwise/gate/XOR.py @@ -1,3 +1,8 @@ +""" +The following classes are defined: + XORGate2 +""" + from .. import wire from . import AND from . import OR @@ -7,6 +12,13 @@ class XORGate2: + """Construct a new two-input XOR gate. + + Args: + input_1: An object of type Wire. The first input to the XOR gate. + input_2: An object of type Wire. The second input to the XOR gate. + output: An object of type Wire. The output of the XOR gate. + """ def __init__(self, input_1, input_2, output): wire_1 = Wire() wire_2 = Wire() diff --git a/bitwise/logic/COMP.py b/bitwise/logic/COMP.py index d8e1e6d..fd3e556 100644 --- a/bitwise/logic/COMP.py +++ b/bitwise/logic/COMP.py @@ -1,9 +1,4 @@ """ -This module defines classes that simulate logical comparators. While there are -many different forms of comparators, the ones in this module simply receive two -signed binary numbers in two's complement form and determine if the first is -greater than, equal to, or less than the second. - The following classes are defined: Comparator3 Comparator7 @@ -21,25 +16,21 @@ class Comparator3: - """ - This logical comparator has eight inputs in two 4-bit buses and three - outputs: - ________ - input_1 ----| |---- greater_than - input_2 ----| |---- equal_to - input_3 ----| |---- less_than - input_4 ----| | - input_5 ----| | - input_6 ----| | - input_7 ----| | - input_8 ----|________| - - The comparator compares two signed 3-bit binary numbers. The first number - has input_1, input_2, and input_4 as the sign bit, MSB, and LSB, - respectively (input_bus_1). The second number has input_5, input_6, and - input_8 as the sign bit, MSB, and LSB, respectively (input_bus_2). If the - first number is greater than the second, the greater_than output will be 1, - with all other outputs 0. The other outputs work analogously. + """Construct a new 3-bit logical comparator. + + Args: + a_bus: An object of type Bus4. The number to be compared. a_bus[1] and + a_bus[3] are the most and least significant bit, respectively. + a_bus[0] is the sign bit. + b_bus: An object of type Bus4. The number to be compared against. + b_bus[1] and b_bus[3] are the most and least significant bit, + respectively. b_bus[0] is the sign bit. + greater_than: An object of type Wire. The greater-than indicator. + equal_to: An object of type Wire. The equal-to indicator. + less_than: An object of type Wire. The less-than indicator. + + Raises: + TypeError: If either a_bus or b_bus is not a bus of width 4. """ def __init__(self, input_bus_1, input_bus_2, gt, z, lt): if len(input_bus_1.wires) != 4: @@ -83,33 +74,21 @@ def __init__(self, input_bus_1, input_bus_2, gt, z, lt): class Comparator7: - """ - This logical comparator has sixteen inputs in two 8-bit buses and three - outputs: - ________ - input_1 ----| |---- greater_than - input_2 ----| |---- equal_to - input_3 ----| |---- less_than - input_4 ----| | - input_5 ----| | - input_6 ----| | - input_7 ----| | - input_8 ----| | - input_9 ----| | - input_10 ----| | - input_11 ----| | - input_12 ----| | - input_13 ----| | - input_14 ----| | - input_15 ----| | - input_16 ----|________| - - The comparator compares two signed 7-bit binary numbers. The first number - has input_1, input_2, and input_8 as the sign bit, MSB, and LSB, - respectively (input_bus_1). The second number has input_9, input_10, and - input_16 as the sign bit, MSB, and LSB, respectively (input_bus_2). If the - first number is greater than the second, the greater_than output will be 1, - with all other outputs 0. The other outputs work analogously. + """Construct a new 7-bit logical comparator. + + Args: + a_bus: An object of type Bus8. The number to be compared. a_bus[1] and + a_bus[7] are the most and least significant bit, respectively. + a_bus[0] is the sign bit. + b_bus: An object of type Bus8. The number to be compared against. + b_bus[1] and b_bus[7] are the most and least significant bit, + respectively. b_bus[0] is the sign bit. + greater_than: An object of type Wire. The greater-than indicator. + equal_to: An object of type Wire. The equal-to indicator. + less_than: An object of type Wire. The less-than indicator. + + Raises: + TypeError: If either a_bus or b_bus is not a bus of width 8. """ def __init__(self, input_bus_1, input_bus_2, gt, z, lt): if len(input_bus_1.wires) != 8: @@ -170,35 +149,21 @@ def __init__(self, input_bus_1, input_bus_2, gt, z, lt): class Comparator15: - """ - This logical comparator has thirty-two inputs in two 16-bit buses and three - outputs: - ________ - input_1 ----| |---- greater_than - input_2 ----| |---- equal_to - input_3 ----| |---- less_than - input_4 ----| | - ... | | - input_13 ----| | - input_14 ----| | - input_15 ----| | - input_16 ----| | - input_17 ----| | - input_18 ----| | - input_19 ----| | - input_20 ----| | - ... | | - input_29 ----| | - input_30 ----| | - input_31 ----| | - input_32 ----|________| - - The comparator compares two signed 15-bit binary numbers. The first number - has input_1, input_2, and input_16 as the sign bit, MSB, and LSB, - respectively (input_bus_1). The second number has input_17, input_18, and - input_32 as the sign bit, MSB, and LSB, respectively (input_bus_2). If the - first number is greater than the second, the greater_than output will be 1, - with all other outputs 0. The other outputs work analogously. + """Construct a new 15-bit logical comparator. + + Args: + a_bus: An object of type Bus16. The number to be compared. a_bus[1] and + a_bus[15] are the most and least significant bit, respectively. + a_bus[0] is the sign bit. + b_bus: An object of type Bus16. The number to be compared against. + b_bus[1] and b_bus[15] are the most and least significant bit, + respectively. b_bus[0] is the sign bit. + greater_than: An object of type Wire. The greater-than indicator. + equal_to: An object of type Wire. The equal-to indicator. + less_than: An object of type Wire. The less-than indicator. + + Raises: + TypeError: If either a_bus or b_bus is not a bus of width 16. """ def __init__(self, input_bus_1, input_bus_2, gt, z, lt): if len(input_bus_1.wires) != 16: diff --git a/bitwise/logic/PAR.py b/bitwise/logic/PAR.py index b5e8ad1..cb4e45f 100644 --- a/bitwise/logic/PAR.py +++ b/bitwise/logic/PAR.py @@ -1,19 +1,4 @@ """ -This module defines classes that simulate parity generators and parity -checkers. These two circuits have essentially the same structure, but perform -different functions. A parity generator transmits a single output, called a -parity bit, based on its inputs. A parity checker transmits a single output -that denotes an error if it has value 1. - -All the parity generators in this module are even. If the input carries an even -number of 1's, the parity bit is 0. If the input carries an odd number of 1's, -the parity bit is 1. This ensures that the total number of 1's in the input and -the parity bit is even, which is the premise for a parity checker. - -The parity checkers in this module are even. If the input carries an even -number of 1's, there is no error and the output is 0. If the input carries an -odd number of 1's, there has been an error in transmission and the output is 1. - The following classes are defined: ParityGenerator4 ParityChecker4 @@ -33,17 +18,14 @@ class ParityGenerator4: - """ - This parity generator has four inputs in a single 4-bit bus and a single - output: - ________ - input_1 ----| |---- parity_bit - input_2 ----| | - input_3 ----| | - input_4 ----|________| - - If the number of 1's in the input is even, parity_bit is 0. If the number - of 1's in the input is odd, parity_bit is 1. + """Construct a new 4-bit even parity generator. + + Args: + input_bus: An object of type Bus4. The input to the parity generator. + parity_bit: An object of type Wire. The parity bit. + + Raises: + TypeError: If input_bus is not a bus of width 4. """ def __init__(self, input_bus, parity_bit): if len(input_bus.wires) != 4: @@ -62,19 +44,15 @@ def __init__(self, input_bus, parity_bit): class ParityChecker4: - """ - This parity checker has four inputs in a single 4-bit bus, a parity_bit - input, and a single output, denoting if an error has occurred: - ________ - input_1 ----| |---- error - input_2 ----| | - input_3 ----| | - input_4 ----| | - parity_bit ----|________| - - If the number of 1's in the input, including parity_bit, is even, no error - has occurred and the output is 0. If the number of 1's in the input, - including parity_bit, is odd, an error has occurred and the output is 1. + """Construct a new 4-bit even parity checker. + + Args: + input_bus: An object of type Bus4. The input to the parity checker. + parity_bit: An object of type Wire. The parity bit. + error: An object of type Wire. The error indicator. + + Raises: + TypeError: If input_bus is not a bus of width 4. """ def __init__(self, input_bus, parity_bit, error): if len(input_bus.wires) != 4: @@ -90,21 +68,14 @@ def __init__(self, input_bus, parity_bit, error): class ParityGenerator8: - """ - This parity generator has eight inputs in a single 8-bit bus and a single - output: - ________ - input_1 ----| |---- parity_bit - input_2 ----| | - input_3 ----| | - input_4 ----| | - input_5 ----| | - input_6 ----| | - input_7 ----| | - input_8 ----|________| - - If the number of 1's in the input is even, parity_bit is 0. If the number - of 1's in the input is odd, parity_bit is 1. + """Construct a new 8-bit even parity generator. + + Args: + input_bus: An object of type Bus8. The input to the parity generator. + parity_bit: An object of type Wire. The parity bit. + + Raises: + TypeError: If input_bus is not a bus of width 8. """ def __init__(self, input_bus, parity_bit): if len(input_bus.wires) != 8: @@ -125,23 +96,15 @@ def __init__(self, input_bus, parity_bit): class ParityChecker8: - """ - This parity checker has eight inputs in a single 8-bit bus, a parity_bit - input, and a single output, denoting if an error has occurred: - ________ - input_1 ----| |---- error - input_2 ----| | - input_3 ----| | - input_4 ----| | - input_5 ----| | - input_6 ----| | - input_7 ----| | - input_8 ----| | - parity_bit ----|________| - - If the number of 1's in the input, including parity_bit, is even, no error - has occurred and the output is 0. If the number of 1's in the input, - including parity_bit, is odd, an error has occurred and the output is 1. + """Construct a new 8-bit even parity checker. + + Args: + input_bus: An object of type Bus8. The input to the parity checker. + parity_bit: An object of type Wire. The parity bit. + error: An object of type Wire. The error indicator. + + Raises: + TypeError: If input_bus is not a bus of width 8. """ def __init__(self, input_bus, parity_bit, error): if len(input_bus.wires) != 8: @@ -157,29 +120,14 @@ def __init__(self, input_bus, parity_bit, error): class ParityGenerator16: - """ - This parity generator has sixteen inputs in a single 16-bit bus and a - single output: - ________ - input_1 ----| |---- parity_bit - input_2 ----| | - input_3 ----| | - input_4 ----| | - input_5 ----| | - input_6 ----| | - input_7 ----| | - input_8 ----| | - input_9 ----| | - input_10 ----| | - input_11 ----| | - input_12 ----| | - input_13 ----| | - input_14 ----| | - input_15 ----| | - input_16 ----|________| - - If the number of 1's in the input is even, parity_bit is 0. If the number - of 1's in the input is odd, parity_bit is 1. + """Construct a new 16-bit even parity generator. + + Args: + input_bus: An object of type Bus16. The input to the parity generator. + parity_bit: An object of type Wire. The parity bit. + + Raises: + TypeError: If input_bus is not a bus of width 16. """ def __init__(self, input_bus, parity_bit): if len(input_bus.wires) != 16: @@ -200,31 +148,15 @@ def __init__(self, input_bus, parity_bit): class ParityChecker16: - """ - This parity checker has sixteen inputs in a single 16-bit bus, a parity_bit - input, and a single output, denoting if an error has occurred: - ________ - input_1 ----| |---- error - input_2 ----| | - input_3 ----| | - input_4 ----| | - input_5 ----| | - input_6 ----| | - input_7 ----| | - input_8 ----| | - input_9 ----| | - input_10 ----| | - input_11 ----| | - input_12 ----| | - input_13 ----| | - input_14 ----| | - input_15 ----| | - input_16 ----| | - parity_bit ----|________| - - If the number of 1's in the input, including parity_bit, is even, no error - has occurred and the output is 0. If the number of 1's in the input, - including parity_bit, is odd, an error has occurred and the output is 1. + """Construct a new 16-bit even parity checker. + + Args: + input_bus: An object of type Bus16. The input to the parity checker. + parity_bit: An object of type Wire. The parity bit. + error: An object of type Wire. The error indicator. + + Raises: + TypeError: If input_bus is not a bus of width 16. """ def __init__(self, input_bus, parity_bit, error): if len(input_bus.wires) != 16: diff --git a/bitwise/signal/DEC.py b/bitwise/signal/DEC.py index e3bf29d..2e26281 100644 --- a/bitwise/signal/DEC.py +++ b/bitwise/signal/DEC.py @@ -1,10 +1,4 @@ """ -This module defines classes that simulate decoders. A decoder receives an -encoded value, such as a binary value, and transmits a one-hot output -corresponding to the decoded value. The decoders in this module have an -additional enable input; if this input is 0, all the output values are 0, -regardless of the other inputs. - The following classes are defined: Decoder1Of4 Decoder1Of8 @@ -21,19 +15,20 @@ class Decoder1Of4: - """ - This decoder has two data inputs, an enable input, and four outputs in a - single 4-bit bus: - ________ - enable ----| |---- output_1 - input_1 ----| |---- output_2 - input_2 ----| |---- output_3 - |________|---- output_4 - - The inputs have input_1 and input_2 as the MSB and LSB, respectively. The - outputs have output_1 corresponding to the (1, 1) input and output_4 - corresponding to the (0, 0) input. If the enable is 0, the outputs are - all 0, regardless of input. + """Construct a new 1-of-4 decoder. + + Args: + enable: An object of type Wire. Enables the decoder. + input_1: An object of type Wire. The most significant bit of the data + input. + input_2: An object of type Wire. The least significant bit of the data + input. + output_bus: An object of type Bus4. A one-hot encoded value of the + input, with output_bus[0] corresponding to a (1, 1) input and + output_bus[3] corresponding to a (0, 0) input. + + Raises: + TypeError: If output_bus is not a bus of width 4. """ def __init__(self, enable, input_1, input_2, output_bus): if len(output_bus.wires) != 4: @@ -56,23 +51,21 @@ def __init__(self, enable, input_1, input_2, output_bus): class Decoder1Of8: - """ - This decoder has three data inputs, an enable input, and eight outputs in a - single 8-bit bus: - ________ - enable ----| |---- output_1 - input_1 ----| |---- output_2 - input_2 ----| |---- output_3 - input_3 ----| |---- output_4 - | |---- output_5 - | |---- output_6 - | |---- output_7 - |________|---- output_8 - - The inputs have input_1 and input_3 as the MSB and LSB, respectively. The - outputs have output_1 corresponding to the (1, 1, 1) input and output_8 - corresponding to the (0, 0, 0) input. If the enable is 0, the outputs are - all 0, regardless of input. + """Construct a new 1-of-8 decoder. + + Args: + enable: An object of type Wire. Enables the decoder. + input_1: An object of type Wire. The most significant bit of the data + input. + input_2: An object of type Wire. + input_3: An object of type Wire. The least significant bit of the data + input. + output_bus: An object of type Bus8. A one-hot encoded value of the data + input, with output[0] corresponding to a (1, 1, 1) input and + output[7] corresponding to a (0, 0, 0) input. + + Raises: + TypeError: If output_bus is not a bus of width 8. """ def __init__(self, enable, input_1, input_2, input_3, output_bus): if len(output_bus.wires) != 8: @@ -97,30 +90,20 @@ def __init__(self, enable, input_1, input_2, input_3, output_bus): class Decoder1Of16: """ - This decoder has four data inputs in a single 4-bit bus, an enable input, - and sixteen outputs in a single 16-bit bus: - ________ - enable ----| |---- output_1 - input_1 ----| |---- output_2 - input_2 ----| |---- output_3 - input_3 ----| |---- output_4 - input_4 ----| |---- output_5 - | |---- output_6 - | |---- output_7 - | |---- output_8 - | |---- output_9 - | |---- output_10 - | |---- output_11 - | |---- output_12 - | |---- output_13 - | |---- output_14 - | |---- output_15 - |________|---- output_16 - - The inputs have input_1 and input_4 as the MSB and LSB, respectively. The - outputs have output_1 corresponding to the (1, 1, 1, 1) input and - output_16 corresponding to the (0, 0, 0, 0) input. If the enable is 0, the - outputs are all 0, regardless of input. + Construct a new 1-of-16 decoder. + + Args: + enable: An object of type Wire. Enables the decoder. + input_bus: An object of type Bus4. The data input to the decoder. + input_1 and input_4 are the most and least significant bit, + respectively. + output_bus: An object of type Bus16. A one-hot encoded value of the + input, with output[0] corresponding to a (1, 1, 1, 1) input and + output[15] corresponding to a (0, 0, 0, 0) input. + + Raises: + TypeError: If input_bus is not a bus of width 4, or if output_bus is + not a bus of width 16. """ def __init__(self, enable, input_bus, output_bus): if len(input_bus.wires) != 4: diff --git a/bitwise/signal/DEMUX.py b/bitwise/signal/DEMUX.py index 4c52282..3b18be4 100644 --- a/bitwise/signal/DEMUX.py +++ b/bitwise/signal/DEMUX.py @@ -1,11 +1,4 @@ """ -This module defines classes that simulate demultiplexers. A demultiplexer -receives a single input and selects one output to transmit the input to. This -selection is done by one or more select inputs. The other outputs that are not -selected will have the value 0. The demultiplexers in this module have an -additional enable input; if this input is 0, all the output values are 0, -regardless of the other inputs. - The following classes are defined: Demultiplexer1To2 Demultiplexer1To4 @@ -24,16 +17,16 @@ class Demultiplexer1To2: - """ - This demultiplexer has a data input, a single select input, an enable - input, and two outputs: - ________ - enable ----| |---- output_1 - select ----| |---- output_2 - input ----|________| - - The input is transmitted to output_1 for a (1) select and output_2 for a - (0) select. If the enable is 0, the outputs are all 0, regardless of input. + """Construct a new 1-to-2 demultiplexer. + + Args: + enable: An object of type Wire. Enables the demultiplexer. + select: An object of type Wire. The select input. + input_: An object of type Wire. The data input to the demultiplexer. + output_1: An object of type Wire. Transmits the value of input_ if the + value of select is 1. + output_2: An object of type Wire. Transmits the value of input_ if the + value of select is 0. """ def __init__(self, enable, select, input_1, output_1, output_2): wire_1 = Wire() @@ -44,19 +37,21 @@ def __init__(self, enable, select, input_1, output_1, output_2): class Demultiplexer1To4: - """ - This demultiplexer has a data input, two select inputs, an enable input, - and four outputs in a single 4-bit bus: - ________ - enable ----| |---- output_1 - select_1 ----| |---- output_2 - select_2 ----| |---- output_3 - input ----|________|---- output_4 - - The selects have select_1 and select_2 as the MSB and LSB, respectively. - The input is transmitted to output_1 for a (1, 1) select and output_4 for a - (0, 0) select. If the enable is 0, the outputs are all 0, regardless of - input. + """Construct a new 1-to-4 demultiplexer. + + Args: + enable: An object of type Wire. Enables the demultiplexer. + select_1: An object of type Wire. The most significant bit of the + select input. + select_2: An object of type Wire. The least significant bit of the + select input. + input_: An object of type Wire. The data input to the demultiplexer. + output_bus: An object of type Bus4. output[0] transmits the value of + input_ for a (1, 1) select, and output[3] transmits the value of + input_ for a (0, 0) select. + + Raises: + TypeError: If output_bus is not a bus of width 4. """ def __init__(self, enable, select_1, select_2, input_1, output_bus): if len(output_bus.wires) != 4: @@ -81,22 +76,22 @@ def __init__(self, enable, select_1, select_2, input_1, output_bus): class Demultiplexer1To8: """ - This demultiplexer has a data input, three select inputs, an enable input, - and eight outputs in a single 8-bit bus: - ________ - enable ----| |---- output_1 - select_1 ----| |---- output_2 - select_2 ----| |---- output_3 - select_3 ----| |---- output_4 - input ----| |---- output_5 - | |---- output_6 - | |---- output_7 - |________|---- output_8 - - The selects have select_1 and select_3 as the MSB and LSB, respectively. - The input is transmitted to output_1 for a (1, 1, 1) select and output_8 - for a (0, 0, 0) select. If the enable is 0, the outputs are all 0, - regardless of input. + Construct a new 1-to-8 demultiplexer. + + Args: + enable: An object of type Wire. Enables the demultiplexer. + select_1: An object of type Wire. The most significant bit of the + select input. + select_2: An object of type Wire. + select_3: An object of type Wire. The least significant bit of the + select input. + input_: An object of type Wire. The data input to the demultiplexer. + output_bus: An object of type Bus8. output[0] transmits the value of + input_ for a (1, 1, 1) select, and output[7] transmits the value of + input_ for a (0, 0, 0) select. + + Raises: + TypeError: If output_bus is not a bus of width 8. """ def __init__( self, @@ -145,31 +140,21 @@ def __init__( class Demultiplexer1To16: - """ - This demultiplexer has a data input, four select inputs in a single 4-bit - bus, an enable input, and sixteen outputs in a single 16-bit bus: - ________ - enable ----| |---- output_1 - select_1 ----| |---- output_2 - select_2 ----| |---- output_3 - select_3 ----| |---- output_4 - select_4 ----| |---- output_5 - input ----| |---- output_6 - | |---- output_7 - | |---- output_8 - | |---- output_9 - | |---- output_10 - | |---- output_11 - | |---- output_12 - | |---- output_13 - | |---- output_14 - | |---- output_15 - |________|---- output_16 - - The selects have select_1 and select_4 as the MSB and LSB, respectively. - The input is transmitted to output_1 for a (1, 1, 1, 1) select and - output_16 for a (0, 0, 0, 0) select. If the enable is 0, the outputs are - all 0, regardless of input. + """Construct a new 1-to-16 demultiplexer. + + Args: + enable: An object of type Wire. Enables the demultiplexer. + select_bus: An object of type Bus4. The select input to the + demultiplexer. select[0] and select[3] are the most and least + significant bit, respectively. + input_: An object of type Wire. The data input to the demultiplexer. + output_bus: An object of type Bus16. output[0] transmits the value of + input_ for a (1, 1, 1, 1) select, and output[15] transmits the + value of input_ for a (0, 0, 0, 0) select. + + Raises: + TypeError: If select_bus is not a bus of width 4, or if output_bus is + not a bus of width 16. """ def __init__(self, enable, select_bus, input_1, output_bus): if len(select_bus.wires) != 4: diff --git a/bitwise/wire/BUS.py b/bitwise/wire/BUS.py index b518d0c..3b9131c 100644 --- a/bitwise/wire/BUS.py +++ b/bitwise/wire/BUS.py @@ -1,4 +1,26 @@ +""" +The following classes are defined: + Bus4 + Bus8 + Bus16 + BusSevenSegmentDisplay +""" + +from . import WIRE + +Wire = WIRE.Wire + + class Bus4: + """Initialize a new 4-bit bus. + + Args: + wire_1, wire_2, ... , wire_4: Objects of type Wire. + + Accessors: + bus.wires: A tuple of the wires in the bus. + bus.wire_values: A tuple of values of the wires in the bus. + """ def __init__(self, wire_1, wire_2, wire_3, wire_4): self._wires = (wire_1, wire_2, wire_3, wire_4) @@ -9,9 +31,26 @@ def wires(self): @property def wire_values(self): return tuple([wire.value for wire in self._wires]) + + def __getitem__(self, key): + if (key >= 0) and (key < 4): + return self._wires[key] + elif (key < 0) and (key >= -4): + return self._wires[4 + key] + else: + raise IndexError("Bus width exceeded.") class Bus8: + """Initialize a new 8-bit bus. + + Args: + wire_1, wire_2, ... , wire_8: Objects of type Wire. + + Accessors: + bus.wires: A tuple of the wires in the bus. + bus.wire_values: A tuple of values of the wires in the bus. + """ def __init__( self, wire_1, @@ -41,9 +80,26 @@ def wires(self): @property def wire_values(self): return tuple([wire.value for wire in self._wires]) + + def __getitem__(self, key): + if (key >= 0) and (key < 8): + return self._wires[key] + elif (key < 0) and (key >= -8): + return self._wires[8 + key] + else: + raise IndexError("Bus width exceeded.") class Bus16: + """Initialize a new 16-bit bus. + + Args: + wire_1, wire_2, ... , wire_16: Objects of type Wire. + + Accessors: + bus.wires: A tuple of the wires in the bus. + bus.wire_values: A tuple of values of the wires in the bus. + """ def __init__( self, wire_1, @@ -89,9 +145,26 @@ def wires(self): @property def wire_values(self): return tuple([wire.value for wire in self._wires]) + + def __getitem__(self, key): + if (key >= 0) and (key < 16): + return self._wires[key] + elif (key < 0) and (key >= -16): + return self._wires[16 + key] + else: + raise IndexError("Bus width exceeded.") class BusSevenSegmentDisplay: + """Initialize a new seven-segment display bus. + + Args: + wire_1, wire_2, ... , wire_7: Objects of type Wire. + + Accessors: + bus.wires: A tuple of the wires in the bus. + bus.wire_values: A tuple of values of the wires in the bus. + """ def __init__( self, wire_1, @@ -100,7 +173,7 @@ def __init__( wire_4, wire_5, wire_6, - wire_7, + wire_7 ): self._wires = ( wire_1, @@ -119,3 +192,11 @@ def wires(self): @property def wire_values(self): return tuple([wire.value for wire in self._wires]) + + def __getitem__(self, key): + if (key >= 0) and (key < 7): + return self._wires[key] + elif (key < 0) and (key >= -7): + return self._wires[7 + key] + else: + raise IndexError("Bus width exceeded.") diff --git a/bitwise/wire/CLK.py b/bitwise/wire/CLK.py index 26768d5..b34e681 100644 --- a/bitwise/wire/CLK.py +++ b/bitwise/wire/CLK.py @@ -1,3 +1,8 @@ +""" +The following classes are defined: + Clock +""" + import _thread diff --git a/bitwise/wire/WIRE.py b/bitwise/wire/WIRE.py index 073f57b..8d5ee45 100644 --- a/bitwise/wire/WIRE.py +++ b/bitwise/wire/WIRE.py @@ -1,4 +1,16 @@ +""" +The following classes are defined: + Wire +""" + + class Wire: + """Initialize a new wire with value 0. After initialization, the value of the wire can be both + accessed and mutated using wire.value. + + Raises: + ValueError: If value assigned to wire is not 0 or 1. + """ def __init__(self): self._value = 0 self.connections = [] diff --git a/bitwise/wire/__init__.py b/bitwise/wire/__init__.py index 38e8d95..84a2d0f 100644 --- a/bitwise/wire/__init__.py +++ b/bitwise/wire/__init__.py @@ -1,7 +1,3 @@ -import os -import sys -sys.path.insert(0, os.path.dirname(os.path.realpath(__file__))) - -from CLK import * -from BUS import * -from WIRE import * +from .CLK import * +from .BUS import * +from .WIRE import * diff --git a/tests/wire/test_Bus16.py b/tests/wire/test_Bus16.py index 4277fdf..7f1974d 100644 --- a/tests/wire/test_Bus16.py +++ b/tests/wire/test_Bus16.py @@ -73,6 +73,39 @@ def test_Bus16(self): wire_8.value = 1 assert bus_1.wire_values == ( 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0) + + assert bus_1[0].value == 1 + assert bus_1[1].value == 1 + assert bus_1[2].value == 1 + assert bus_1[3].value == 1 + assert bus_1[4].value == 1 + assert bus_1[5].value == 1 + assert bus_1[6].value == 1 + assert bus_1[7].value == 1 + assert bus_1[8].value == 0 + assert bus_1[9].value == 0 + assert bus_1[10].value == 0 + assert bus_1[11].value == 0 + assert bus_1[12].value == 0 + assert bus_1[13].value == 0 + assert bus_1[14].value == 0 + assert bus_1[15].value == 0 + assert bus_1[-16].value == 1 + assert bus_1[-15].value == 1 + assert bus_1[-14].value == 1 + assert bus_1[-13].value == 1 + assert bus_1[-12].value == 1 + assert bus_1[-11].value == 1 + assert bus_1[-10].value == 1 + assert bus_1[-9].value == 1 + assert bus_1[-8].value == 0 + assert bus_1[-7].value == 0 + assert bus_1[-6].value == 0 + assert bus_1[-5].value == 0 + assert bus_1[-4].value == 0 + assert bus_1[-3].value == 0 + assert bus_1[-2].value == 0 + assert bus_1[-1].value == 0 wire_9.value = 1 assert bus_1.wire_values == ( diff --git a/tests/wire/test_Bus4.py b/tests/wire/test_Bus4.py index 01388f8..2d58475 100644 --- a/tests/wire/test_Bus4.py +++ b/tests/wire/test_Bus4.py @@ -22,6 +22,15 @@ def test_Bus4(self): wire_2.value = 1 assert bus_1.wire_values == (1, 1, 0, 0) + + assert bus_1[0].value == 1 + assert bus_1[1].value == 1 + assert bus_1[2].value == 0 + assert bus_1[3].value == 0 + assert bus_1[-4].value == 1 + assert bus_1[-3].value == 1 + assert bus_1[-2].value == 0 + assert bus_1[-1].value == 0 wire_3.value = 1 assert bus_1.wire_values == (1, 1, 1, 0) diff --git a/tests/wire/test_Bus8.py b/tests/wire/test_Bus8.py index 4a6113f..9ed44eb 100644 --- a/tests/wire/test_Bus8.py +++ b/tests/wire/test_Bus8.py @@ -36,6 +36,23 @@ def test_Bus8(self): wire_4.value = 1 assert bus_1.wire_values == (1, 1, 1, 1, 0, 0, 0, 0) + + assert bus_1[0].value == 1 + assert bus_1[1].value == 1 + assert bus_1[2].value == 1 + assert bus_1[3].value == 1 + assert bus_1[4].value == 0 + assert bus_1[5].value == 0 + assert bus_1[6].value == 0 + assert bus_1[7].value == 0 + assert bus_1[-8].value == 1 + assert bus_1[-7].value == 1 + assert bus_1[-6].value == 1 + assert bus_1[-5].value == 1 + assert bus_1[-4].value == 0 + assert bus_1[-3].value == 0 + assert bus_1[-2].value == 0 + assert bus_1[-1].value == 0 wire_5.value = 1 assert bus_1.wire_values == (1, 1, 1, 1, 1, 0, 0, 0) diff --git a/tests/wire/test_BusSevenSegmentDisplay.py b/tests/wire/test_BusSevenSegmentDisplay.py index 75f94e1..d011f40 100644 --- a/tests/wire/test_BusSevenSegmentDisplay.py +++ b/tests/wire/test_BusSevenSegmentDisplay.py @@ -34,6 +34,21 @@ def test_BusSevenSegmentDisplay(self): wire_4.value = 1 assert bus_1.wire_values == (1, 1, 1, 1, 0, 0, 0) + + assert bus_1[0].value == 1 + assert bus_1[1].value == 1 + assert bus_1[2].value == 1 + assert bus_1[3].value == 1 + assert bus_1[4].value == 0 + assert bus_1[5].value == 0 + assert bus_1[6].value == 0 + assert bus_1[-7].value == 1 + assert bus_1[-6].value == 1 + assert bus_1[-5].value == 1 + assert bus_1[-4].value == 1 + assert bus_1[-3].value == 0 + assert bus_1[-2].value == 0 + assert bus_1[-1].value == 0 wire_5.value = 1 assert bus_1.wire_values == (1, 1, 1, 1, 1, 0, 0)