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verilog
vhdl
README.md
convert.py
gray_code.py
gray_counter.py
test_gray_counter.py

README.md

gray_counter

This is the code from this essay.

It illustrates how to design at the RTL level by starting from an algorithm. The design problem is a gray counter. The algorithm goes as follows:

Given an n-bit Gray code word G = { g[n-1] g[n-2] g[n-3] ... g[0] }, with g[k] representing the individual bits of the word:

  • Construct a new word W = { 1 g[n-3] ... g[0] p }, with p being the even parity bit of G.
  • Starting from the LSB at position 0, look for the first 1 in W
  • Toggle the bit in G at the corresponding position.