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v0.13-preview.121.04+149

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xclerc committed Sep 19, 2019
1 parent 936328a commit a495dc92e819524a94836fa8f5487b30af345333
Showing with 66 additions and 4 deletions.
  1. +7 −4 src/rtl.ml
  2. +59 −0 test/lib/test_circuit.ml
@@ -1072,6 +1072,9 @@ end
module Make (R : Rtl_internal) = struct
let write blackbox io circ =
let inputs, outputs = Circuit.inputs circ, Circuit.outputs circ in
let phantom_inputs =
List.map ~f:(fun (a, b) -> a, b, []) (Circuit.phantom_inputs circ)
in
let signal_graph = Circuit.signal_graph circ in
(* write signal declarations *)
let is_internal s =
@@ -1081,7 +1084,10 @@ module Make (R : Rtl_internal) = struct
in
let internal_signals = Signal_graph.filter signal_graph ~f:is_internal in
(* initialize the mangler *)
let nm = R.Names.init R.Names.reserved in
let nm =
(* reserved words and the names of phantom inputs. *)
R.Names.init (R.Names.reserved @ List.map phantom_inputs ~f:(fun (n, _, _) -> n))
in
let add f nm x = List.fold x ~init:nm ~f:(fun nm x -> f x nm) in
let nm = add R.Names.add_port nm inputs in
let nm = add R.Names.add_port nm outputs in
@@ -1096,9 +1102,6 @@ module Make (R : Rtl_internal) = struct
Array.to_list n)
in
let primary s = primary_name s, width s, attributes s in
let phantom_inputs =
List.map ~f:(fun (a, b) -> a, b, []) (Circuit.phantom_inputs circ)
in
List.iter internal_signals ~f:(fun s -> R.check_signal s);
R.header_and_ports
~io
@@ -329,6 +329,65 @@ let%expect_test "phantom inputs" =
(output_ports (b))))) |}]
;;

let%expect_test "phantom input aliases an internal name" =
let f () =
let a = input "a" 1 in
let b = ~:a -- "b" in
output "c" b
in
let circuit = Circuit.create_exn ~name:"test" [ f () ] in
Rtl.print Verilog circuit;
[%expect
{|
module test (
a,
c
);

input a;
output c;

/* signal declarations */
wire b;

/* logic */
assign b = ~ a;

/* aliases */

/* output assignments */
assign c = b;

endmodule |}];
(* Note that the internal name [b] is now mangled correctly *)
let circuit = Circuit.set_phantom_inputs circuit [ "b", 1 ] in
Rtl.print Verilog circuit;
[%expect
{|
module test (
a,
b,
c
);

input a;
input b;
output c;

/* signal declarations */
wire b_0;

/* logic */
assign b_0 = ~ a;

/* aliases */

/* output assignments */
assign c = b_0;

endmodule |}]
;;

let%expect_test "verify_clock_pins" =
let circuit =
let foo = input "foo" 1 in

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