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Opcode tester now tests AJMP at least in one page.

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commit 54473bfc172f94dd3d82ee0436e825421d09cc27 1 parent 3b7d5e0
authored October 04, 2012
63  test/cpu_test/bin/TB51_CPU.HEX
@@ -484,37 +484,38 @@
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 :101E500075993F756E01907FCD743373021E6E00CD
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 :101E6000007400740074007400759963800675999D
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-:0720600075990A800001657B
  487
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  497
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+:101F8000FF007F01901FC578007909E80893F5F0FC
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  511
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  512
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+:0E2070004975994C75990D75990A8000017C8F
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 :10800000021E61021E6E021E7C021E83E581B453B5
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 :108010000DE552B44808E553B41E03021E4A021E81
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 :01802000500F
1,533  test/cpu_test/lst/TB51_CPU.LST
@@ -10636,7 +10636,7 @@ ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. H
10636 10636
  9440+ 1  1DA4			??0813:
10637 10637
  9441:
10638 10638
  9442:				        ; d.- <MOVX A, @Ri>
10639  
- 9443:	  1DA4	74 79		        mov     a,#79h              ; change A and DPTR so we can catch fails
  10639
+ 9443:	  1DA4	74 79		        mov     a,#79h              ; Let [0013h] = 79h and [0014h] = 97h
10640 10640
  9444:	  1DA6	90 00 13	        mov     dptr,#0013h
10641 10641
  9445:	  1DA9	78 13		        mov     r0,#13h
10642 10642
  9446:	  1DAB	79 14		        mov     r1,#14h
@@ -10782,58 +10782,58 @@ ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. H
10782 10782
  9565:
10783 10783
  9566:
10784 10784
  9567:				        ;-- Test series R ------------------------------------------------------
10785  
- 9568:				        ; ACALL, LCALL, JMP @A+DPTR, LJMP instructions
  10785
+ 9568:				        ; ACALL, LCALL, JMP @A+DPTR, LJMP, AJMP instructions
10786 10786
  9569:				        ; a.- <ACALL addr8>     <-- uses LJMP too
10787 10787
  9570:				        ; b.- <LCALL addr16>    <-- uses LJMP too
10788 10788
  9571:				        ; c.- <JMP @A+DPTR>
10789 10789
  9572:				        ; d.- <LJMP addr16>
10790  
- 9573:				        ;
10791  
- 9574:				        ; Biggest limitations:
10792  
- 9575:				        ; .- Only long jumps; jumps to same page (== H addr byte) untested.
10793  
- 9576:				        ;
10794  
- 9577:				        ; Note RET is NOT tested here! we don't return from these calls, just
10795  
- 9578:				        ; use them as jumps.
10796  
- 9579:				        ;
10797  
- 9580:
10798  
- 9581:				        putc    #'R'                ; start of test series
10799  
- 9582+ 1  1E15			??0830:
10800  
- 9583+ 1			        ;jnb     SCON.1,putc_loop
10801  
- 9584+ 1			        ;clr     SCON.1
10802  
- 9585+ 1  1E15	75 99 52	        mov     SBUF,#'R'
10803  
- 9586:
10804  
- 9587:	  1E18	75 81 4F	        mov     SP,#4fh             ; Initialize SP...
10805  
- 9588:	  1E1B	75 50 00	        mov     50h,#00h            ; ...and clear stack area
10806  
- 9589:	  1E1E	75 51 00	        mov     51h,#00h
10807  
- 9590:	  1E21	75 52 00	        mov     52h,#00h
10808  
- 9591:	  1E24	75 53 00	        mov     53h,#00h
10809  
- 9592:
10810  
- 9593:				        ; a.- <ACALL addr8>
10811  
- 9594:				        ; We should test all code pages eventually...
10812  
- 9595:	  1E27	D1 2B		        acall   tr_sub0             ; Do the call...
10813  
- 9596:	  1E29	80 14		tr_rv0: sjmp    tr_a0
10814  
- 9597:	  1E2B			tr_sub0:
10815  
- 9598:	  1E2B	E5 81		        mov     A,SP
10816  
- 9599:	  1E2D	B4 51 0F	        cjne    A,#51h,tr_a0       ; ...verify the SP value...
10817  
- 9600:	  1E30	E5 50		        mov     A,50h
10818  
- 9601:	  1E32	B4 29 0A	        cjne    A,#LOW(tr_rv0),tr_a0 ; ...and verify the pushed ret address
10819  
- 9602:	  1E35	E5 51		        mov     A,51h
10820  
- 9603:	  1E37	B4 1E 05	        cjne    A,#HIGH(tr_rv0),tr_a0
10821  
- 9604:
10822  
- 9605:				        eot     'a',tr_a0
10823  
- 9606+ 1			        putc    #'a'
10824  
- 9607+ 2  1E3A			??0832:
10825  
- 9608+ 2			        ;jnb     SCON.1,putc_loop
10826  
- 9609+ 2			        ;clr     SCON.1
10827  
- 9610+ 2  1E3A	75 99 61	        mov     SBUF,#'a'
10828  
- 9611+ 1  1E3D	80 06		        sjmp    ??0831
10829  
- 9612+ 1  1E3F			tr_a0:  putc    #'?'
10830  
- 9613+ 2  1E3F			??0833:
10831  
- 9614+ 2			        ;jnb     SCON.1,putc_loop
10832  
- 9615+ 2			        ;clr     SCON.1
10833  
- 9616+ 2  1E3F	75 99 3F	        mov     SBUF,#'?'
10834  
- 9617+ 1  1E42	75 6E 01	        mov     fail,#001h
10835  
- 9618+ 1  1E45			??0831:
10836  
- 9619:
  10790
+ 9573:				        ; e.- <AJMP addr8>
  10791
+ 9574:				        ;
  10792
+ 9575:				        ; Biggest limitations:
  10793
+ 9576:				        ; .- Jumps to same page (== H addr byte) tested only at one page.
  10794
+ 9577:				        ;
  10795
+ 9578:				        ; Note RET is NOT tested here! we don't return from these calls, just
  10796
+ 9579:				        ; use them as jumps.
  10797
+ 9580:				        ;
  10798
+ 9581:
  10799
+ 9582:				        putc    #'R'                ; start of test series
  10800
+ 9583+ 1  1E15			??0830:
  10801
+ 9584+ 1			        ;jnb     SCON.1,putc_loop
  10802
+ 9585+ 1			        ;clr     SCON.1
  10803
+ 9586+ 1  1E15	75 99 52	        mov     SBUF,#'R'
  10804
+ 9587:
  10805
+ 9588:	  1E18	75 81 4F	        mov     SP,#4fh             ; Initialize SP...
  10806
+ 9589:	  1E1B	75 50 00	        mov     50h,#00h            ; ...and clear stack area
  10807
+ 9590:	  1E1E	75 51 00	        mov     51h,#00h
  10808
+ 9591:	  1E21	75 52 00	        mov     52h,#00h
  10809
+ 9592:	  1E24	75 53 00	        mov     53h,#00h
  10810
+ 9593:
  10811
+ 9594:				        ; a.- <ACALL addr8>
  10812
+ 9595:				        ; We should test all code pages eventually...
  10813
+ 9596:	  1E27	D1 2B		        acall   tr_sub0             ; Do the call...
  10814
+ 9597:	  1E29	80 14		tr_rv0: sjmp    tr_a0
  10815
+ 9598:	  1E2B			tr_sub0:
  10816
+ 9599:	  1E2B	E5 81		        mov     A,SP
  10817
+ 9600:	  1E2D	B4 51 0F	        cjne    A,#51h,tr_a0       ; ...verify the SP value...
  10818
+ 9601:	  1E30	E5 50		        mov     A,50h
  10819
+ 9602:	  1E32	B4 29 0A	        cjne    A,#LOW(tr_rv0),tr_a0 ; ...and verify the pushed ret address
  10820
+ 9603:	  1E35	E5 51		        mov     A,51h
  10821
+ 9604:	  1E37	B4 1E 05	        cjne    A,#HIGH(tr_rv0),tr_a0
  10822
+ 9605:
  10823
+ 9606:				        eot     'a',tr_a0
  10824
+ 9607+ 1			        putc    #'a'
  10825
+ 9608+ 2  1E3A			??0832:
  10826
+ 9609+ 2			        ;jnb     SCON.1,putc_loop
  10827
+ 9610+ 2			        ;clr     SCON.1
  10828
+ 9611+ 2  1E3A	75 99 61	        mov     SBUF,#'a'
  10829
+ 9612+ 1  1E3D	80 06		        sjmp    ??0831
  10830
+ 9613+ 1  1E3F			tr_a0:  putc    #'?'
  10831
+ 9614+ 2  1E3F			??0833:
  10832
+ 9615+ 2			        ;jnb     SCON.1,putc_loop
  10833
+ 9616+ 2			        ;clr     SCON.1
  10834
+ 9617+ 2  1E3F	75 99 3F	        mov     SBUF,#'?'
  10835
+ 9618+ 1  1E42	75 6E 01	        mov     fail,#001h
  10836
+ 9619+ 1  1E45			??0831:
10837 10837
 
10838 10838
 ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. Heinz                                        PAGE 173
10839 10839
 
@@ -10841,62 +10841,62 @@ ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. H
10841 10841
 
10842 10842
  Line  I  Addr  Code            Source
10843 10843
 
10844  
- 9620:				        ; b.- <LCALL addr16>
10845  
- 9621:	  1E45	12 80 0C	        lcall   tr_sub1             ; Do the call...
10846  
- 9622:	  1E48	80 06		tr_rv1: sjmp    tr_b0
10847  
- 9623:	  1E4A	00		tr_rv2: nop
10848  
- 9624:				        eot     'b',tr_b0
10849  
- 9625+ 1			        putc    #'b'
10850  
- 9626+ 2  1E4B			??0835:
10851  
- 9627+ 2			        ;jnb     SCON.1,putc_loop
10852  
- 9628+ 2			        ;clr     SCON.1
10853  
- 9629+ 2  1E4B	75 99 62	        mov     SBUF,#'b'
10854  
- 9630+ 1  1E4E	80 06		        sjmp    ??0834
10855  
- 9631+ 1  1E50			tr_b0:  putc    #'?'
10856  
- 9632+ 2  1E50			??0836:
10857  
- 9633+ 2			        ;jnb     SCON.1,putc_loop
10858  
- 9634+ 2			        ;clr     SCON.1
10859  
- 9635+ 2  1E50	75 99 3F	        mov     SBUF,#'?'
10860  
- 9636+ 1  1E53	75 6E 01	        mov     fail,#001h
10861  
- 9637+ 1  1E56			??0834:
10862  
- 9638:
  10844
+ 9620:
  10845
+ 9621:				        ; b.- <LCALL addr16>
  10846
+ 9622:	  1E45	12 80 0C	        lcall   tr_sub1             ; Do the call...
  10847
+ 9623:	  1E48	80 06		tr_rv1: sjmp    tr_b0
  10848
+ 9624:	  1E4A	00		tr_rv2: nop
  10849
+ 9625:				        eot     'b',tr_b0
  10850
+ 9626+ 1			        putc    #'b'
  10851
+ 9627+ 2  1E4B			??0835:
  10852
+ 9628+ 2			        ;jnb     SCON.1,putc_loop
  10853
+ 9629+ 2			        ;clr     SCON.1
  10854
+ 9630+ 2  1E4B	75 99 62	        mov     SBUF,#'b'
  10855
+ 9631+ 1  1E4E	80 06		        sjmp    ??0834
  10856
+ 9632+ 1  1E50			tr_b0:  putc    #'?'
  10857
+ 9633+ 2  1E50			??0836:
  10858
+ 9634+ 2			        ;jnb     SCON.1,putc_loop
  10859
+ 9635+ 2			        ;clr     SCON.1
  10860
+ 9636+ 2  1E50	75 99 3F	        mov     SBUF,#'?'
  10861
+ 9637+ 1  1E53	75 6E 01	        mov     fail,#001h
  10862
+ 9638+ 1  1E56			??0834:
10863 10863
  9639:
10864  
- 9640:				        ; c.- <JMP @A+DPTR>
10865  
- 9641:				        ; Note that tr_sub2 is at 8000h so that we test the A+DPTR carry
10866  
- 9642:				        ; propagation. Any address xx00h would do.
10867  
- 9643:	  1E56	90 7F CD	        mov     DPTR,#(tr_sub2-33h) ; Prepare DPTR and A so that their sum
10868  
- 9644:	  1E59	74 33		        mov     a,#33h              ; gives the target address.
10869  
- 9645:	  1E5B	73		        jmp     @a+DPTR
10870  
- 9646:	  1E5C	02 1E 6E	        jmp     tr_c0
10871  
- 9647:	  1E5F	00		        nop
10872  
- 9648:	  1E60	00		        nop
10873  
- 9649:	  1E61	74 00		tr_rv3: mov     a,#00h
10874  
- 9650:	  1E63	74 00		        mov     a,#00h
10875  
- 9651:	  1E65	74 00		        mov     a,#00h
10876  
- 9652:	  1E67	74 00		        mov     a,#00h
10877  
- 9653:
10878  
- 9654:				        eot     'c',tr_c0
10879  
- 9655+ 1			        putc    #'c'
10880  
- 9656+ 2  1E69			??0838:
10881  
- 9657+ 2			        ;jnb     SCON.1,putc_loop
10882  
- 9658+ 2			        ;clr     SCON.1
10883  
- 9659+ 2  1E69	75 99 63	        mov     SBUF,#'c'
10884  
- 9660+ 1  1E6C	80 06		        sjmp    ??0837
10885  
- 9661+ 1  1E6E			tr_c0:  putc    #'?'
10886  
- 9662+ 2  1E6E			??0839:
10887  
- 9663+ 2			        ;jnb     SCON.1,putc_loop
10888  
- 9664+ 2			        ;clr     SCON.1
10889  
- 9665+ 2  1E6E	75 99 3F	        mov     SBUF,#'?'
10890  
- 9666+ 1  1E71	75 6E 01	        mov     fail,#001h
10891  
- 9667+ 1  1E74			??0837:
10892  
- 9668:
10893  
- 9669:				        ; c.- <LJMP addr16>
10894  
- 9670:	  1E74	02 80 06	        ljmp    tr_sub3
10895  
- 9671:	  1E77	02 1E 83	        jmp     tr_d0
10896  
- 9672:	  1E7A	00		        nop
10897  
- 9673:	  1E7B	00		        nop
10898  
- 9674:	  1E7C	00		tr_rv4: nop
10899  
- 9675:	  1E7D	00		        nop
  10864
+ 9640:
  10865
+ 9641:				        ; c.- <JMP @A+DPTR>
  10866
+ 9642:				        ; Note that tr_sub2 is at 8000h so that we test the A+DPTR carry
  10867
+ 9643:				        ; propagation. Any address xx00h would do.
  10868
+ 9644:	  1E56	90 7F CD	        mov     DPTR,#(tr_sub2-33h) ; Prepare DPTR and A so that their sum
  10869
+ 9645:	  1E59	74 33		        mov     a,#33h              ; gives the target address.
  10870
+ 9646:	  1E5B	73		        jmp     @a+DPTR
  10871
+ 9647:	  1E5C	02 1E 6E	        jmp     tr_c0
  10872
+ 9648:	  1E5F	00		        nop
  10873
+ 9649:	  1E60	00		        nop
  10874
+ 9650:	  1E61	74 00		tr_rv3: mov     a,#00h
  10875
+ 9651:	  1E63	74 00		        mov     a,#00h
  10876
+ 9652:	  1E65	74 00		        mov     a,#00h
  10877
+ 9653:	  1E67	74 00		        mov     a,#00h
  10878
+ 9654:
  10879
+ 9655:				        eot     'c',tr_c0
  10880
+ 9656+ 1			        putc    #'c'
  10881
+ 9657+ 2  1E69			??0838:
  10882
+ 9658+ 2			        ;jnb     SCON.1,putc_loop
  10883
+ 9659+ 2			        ;clr     SCON.1
  10884
+ 9660+ 2  1E69	75 99 63	        mov     SBUF,#'c'
  10885
+ 9661+ 1  1E6C	80 06		        sjmp    ??0837
  10886
+ 9662+ 1  1E6E			tr_c0:  putc    #'?'
  10887
+ 9663+ 2  1E6E			??0839:
  10888
+ 9664+ 2			        ;jnb     SCON.1,putc_loop
  10889
+ 9665+ 2			        ;clr     SCON.1
  10890
+ 9666+ 2  1E6E	75 99 3F	        mov     SBUF,#'?'
  10891
+ 9667+ 1  1E71	75 6E 01	        mov     fail,#001h
  10892
+ 9668+ 1  1E74			??0837:
  10893
+ 9669:
  10894
+ 9670:				        ; d.- <LJMP addr16>
  10895
+ 9671:	  1E74	02 80 06	        ljmp    tr_sub3
  10896
+ 9672:	  1E77	02 1E 83	        jmp     tr_d0
  10897
+ 9673:	  1E7A	00		        nop
  10898
+ 9674:	  1E7B	00		        nop
  10899
+ 9675:	  1E7C	00		tr_rv4: nop
10900 10900
 
10901 10901
 ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. Heinz                                        PAGE 174
10902 10902
 
@@ -10904,62 +10904,62 @@ ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. H
10904 10904
 
10905 10905
  Line  I  Addr  Code            Source
10906 10906
 
10907  
- 9676:				        eot     'd',tr_d0
10908  
- 9677+ 1			        putc    #'d'
10909  
- 9678+ 2  1E7E			??0841:
10910  
- 9679+ 2			        ;jnb     SCON.1,putc_loop
10911  
- 9680+ 2			        ;clr     SCON.1
10912  
- 9681+ 2  1E7E	75 99 64	        mov     SBUF,#'d'
10913  
- 9682+ 1  1E81	80 06		        sjmp    ??0840
10914  
- 9683+ 1  1E83			tr_d0:  putc    #'?'
10915  
- 9684+ 2  1E83			??0842:
10916  
- 9685+ 2			        ;jnb     SCON.1,putc_loop
10917  
- 9686+ 2			        ;clr     SCON.1
10918  
- 9687+ 2  1E83	75 99 3F	        mov     SBUF,#'?'
10919  
- 9688+ 1  1E86	75 6E 01	        mov     fail,#001h
10920  
- 9689+ 1  1E89			??0840:
10921  
- 9690:
10922  
- 9691:				        put_crlf                    ; end of test series
10923  
- 9692+ 1			        putc    #13
10924  
- 9693+ 2  1E89			??0843:
10925  
- 9694+ 2			        ;jnb     SCON.1,putc_loop
10926  
- 9695+ 2			        ;clr     SCON.1
10927  
- 9696+ 2  1E89	75 99 0D	        mov     SBUF,#13
10928  
- 9697+ 1			        putc    #10
10929  
- 9698+ 2  1E8C			??0844:
10930  
- 9699+ 2			        ;jnb     SCON.1,putc_loop
10931  
- 9700+ 2			        ;clr     SCON.1
10932  
- 9701+ 2  1E8C	75 99 0A	        mov     SBUF,#10
  10907
+ 9676:	  1E7D	00		        nop
  10908
+ 9677:				        eot     'd',tr_d0
  10909
+ 9678+ 1			        putc    #'d'
  10910
+ 9679+ 2  1E7E			??0841:
  10911
+ 9680+ 2			        ;jnb     SCON.1,putc_loop
  10912
+ 9681+ 2			        ;clr     SCON.1
  10913
+ 9682+ 2  1E7E	75 99 64	        mov     SBUF,#'d'
  10914
+ 9683+ 1  1E81	80 06		        sjmp    ??0840
  10915
+ 9684+ 1  1E83			tr_d0:  putc    #'?'
  10916
+ 9685+ 2  1E83			??0842:
  10917
+ 9686+ 2			        ;jnb     SCON.1,putc_loop
  10918
+ 9687+ 2			        ;clr     SCON.1
  10919
+ 9688+ 2  1E83	75 99 3F	        mov     SBUF,#'?'
  10920
+ 9689+ 1  1E86	75 6E 01	        mov     fail,#001h
  10921
+ 9690+ 1  1E89			??0840:
  10922
+ 9691:
  10923
+ 9692:				        ; e.- <AJMP addr8>
  10924
+ 9693:				        ; We should test all code pages eventually...
  10925
+ 9694:	  1E89	74 00		        mov     a,#00h
  10926
+ 9695:	  1E8B	C1 8F		        ajmp    tr_ajmp0            ; Do the jump...
  10927
+ 9696:	  1E8D	80 02		        sjmp    tr_rv5
  10928
+ 9697:	  1E8F			tr_ajmp0:
  10929
+ 9698:	  1E8F	74 42		        mov     a,#042h
  10930
+ 9699:	  1E91			tr_rv5:
  10931
+ 9700:	  1E91	B4 42 06	        cjne    A,#42h,tr_e0       ; ...and make sure we've actually been there
  10932
+ 9701:	  1E94	00		        nop
10933 10933
  9702:
10934  
- 9703:
10935  
- 9704:				        ;-- Test series S ------------------------------------------------------
10936  
- 9705:				        ; RET, RETI instructions
10937  
- 9706:				        ; a.- <RET>
10938  
- 9707:				        ; b.- <RETI>
10939  
- 9708:				        ;
10940  
- 9709:				        ; RETs to different code pages (!= H addr byte) not tested!
10941  
- 9710:				        ; Interrupt flag stuff not tested, only RET functionality
10942  
- 9711:
10943  
- 9712:				        putc    #'S'                ; start of test series
10944  
- 9713+ 1  1E8F			??0845:
10945  
- 9714+ 1			        ;jnb     SCON.1,putc_loop
10946  
- 9715+ 1			        ;clr     SCON.1
10947  
- 9716+ 1  1E8F	75 99 53	        mov     SBUF,#'S'
  10934
+ 9703:				        eot     'e',tr_e0
  10935
+ 9704+ 1			        putc    #'e'
  10936
+ 9705+ 2  1E95			??0844:
  10937
+ 9706+ 2			        ;jnb     SCON.1,putc_loop
  10938
+ 9707+ 2			        ;clr     SCON.1
  10939
+ 9708+ 2  1E95	75 99 65	        mov     SBUF,#'e'
  10940
+ 9709+ 1  1E98	80 06		        sjmp    ??0843
  10941
+ 9710+ 1  1E9A			tr_e0:  putc    #'?'
  10942
+ 9711+ 2  1E9A			??0845:
  10943
+ 9712+ 2			        ;jnb     SCON.1,putc_loop
  10944
+ 9713+ 2			        ;clr     SCON.1
  10945
+ 9714+ 2  1E9A	75 99 3F	        mov     SBUF,#'?'
  10946
+ 9715+ 1  1E9D	75 6E 01	        mov     fail,#001h
  10947
+ 9716+ 1  1EA0			??0843:
10948 10948
  9717:
10949  
- 9718:
10950  
- 9719:				        ; a.- <RET>
10951  
- 9720:	  1E92	75 81 4F	        mov     SP,#4fh             ; Initialize SP...
10952  
- 9721:	  1E95	75 4F 1E	        mov     4fh,#HIGH(s_sub0)   ; ...and load stack area with return
10953  
- 9722:	  1E98	75 4E A6	        mov     4eh,#LOW(s_sub0)    ; addresses to be tested
10954  
- 9723:	  1E9B	75 4D 1E	        mov     4dh,#HIGH(s_sub1)
10955  
- 9724:	  1E9E	75 4C B0	        mov     4ch,#LOW(s_sub1)
10956  
- 9725:
10957  
- 9726:	  1EA1	22		        ret                         ; Do the ret...
10958  
- 9727:	  1EA2	80 16		        sjmp    ts_a0
10959  
- 9728:	  1EA4	74 00		        mov     A,#00h
10960  
- 9729:	  1EA6	E5 81		s_sub0: mov     A,SP
10961  
- 9730:	  1EA8	B4 4D 0F	        cjne    A,#4dh,ts_a0       ; ... and verify the SP value
10962  
- 9731:
  10949
+ 9718:				        put_crlf                    ; end of test series
  10950
+ 9719+ 1			        putc    #13
  10951
+ 9720+ 2  1EA0			??0846:
  10952
+ 9721+ 2			        ;jnb     SCON.1,putc_loop
  10953
+ 9722+ 2			        ;clr     SCON.1
  10954
+ 9723+ 2  1EA0	75 99 0D	        mov     SBUF,#13
  10955
+ 9724+ 1			        putc    #10
  10956
+ 9725+ 2  1EA3			??0847:
  10957
+ 9726+ 2			        ;jnb     SCON.1,putc_loop
  10958
+ 9727+ 2			        ;clr     SCON.1
  10959
+ 9728+ 2  1EA3	75 99 0A	        mov     SBUF,#10
  10960
+ 9729:
  10961
+ 9730:
  10962
+ 9731:				        ;-- Test series S ------------------------------------------------------
10963 10963
 
10964 10964
 ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. Heinz                                        PAGE 175
10965 10965
 
@@ -10967,61 +10967,61 @@ ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. H
10967 10967
 
10968 10968
  Line  I  Addr  Code            Source
10969 10969
 
10970  
- 9732:	  1EAB	22		        ret                         ; Do another ret...
10971  
- 9733:	  1EAC	80 0C		        sjmp    ts_a0
10972  
- 9734:	  1EAE	74 00		        mov     A,#00h
10973  
- 9735:	  1EB0	E5 81		s_sub1: mov     A,SP
10974  
- 9736:	  1EB2	B4 4B 05	        cjne    A,#4bh,ts_a0       ; ... and verify the SP value
10975  
- 9737:
10976  
- 9738:				        eot     'a',ts_a0
10977  
- 9739+ 1			        putc    #'a'
10978  
- 9740+ 2  1EB5			??0847:
10979  
- 9741+ 2			        ;jnb     SCON.1,putc_loop
10980  
- 9742+ 2			        ;clr     SCON.1
10981  
- 9743+ 2  1EB5	75 99 61	        mov     SBUF,#'a'
10982  
- 9744+ 1  1EB8	80 06		        sjmp    ??0846
10983  
- 9745+ 1  1EBA			ts_a0:  putc    #'?'
10984  
- 9746+ 2  1EBA			??0848:
10985  
- 9747+ 2			        ;jnb     SCON.1,putc_loop
10986  
- 9748+ 2			        ;clr     SCON.1
10987  
- 9749+ 2  1EBA	75 99 3F	        mov     SBUF,#'?'
10988  
- 9750+ 1  1EBD	75 6E 01	        mov     fail,#001h
10989  
- 9751+ 1  1EC0			??0846:
  10970
+ 9732:				        ; RET, RETI instructions
  10971
+ 9733:				        ; a.- <RET>
  10972
+ 9734:				        ; b.- <RETI>
  10973
+ 9735:				        ;
  10974
+ 9736:				        ; RETs to different code pages (!= H addr byte) not tested!
  10975
+ 9737:				        ; Interrupt flag stuff not tested, only RET functionality
  10976
+ 9738:
  10977
+ 9739:				        putc    #'S'                ; start of test series
  10978
+ 9740+ 1  1EA6			??0848:
  10979
+ 9741+ 1			        ;jnb     SCON.1,putc_loop
  10980
+ 9742+ 1			        ;clr     SCON.1
  10981
+ 9743+ 1  1EA6	75 99 53	        mov     SBUF,#'S'
  10982
+ 9744:
  10983
+ 9745:
  10984
+ 9746:				        ; a.- <RET>
  10985
+ 9747:	  1EA9	75 81 4F	        mov     SP,#4fh             ; Initialize SP...
  10986
+ 9748:	  1EAC	75 4F 1E	        mov     4fh,#HIGH(s_sub0)   ; ...and load stack area with return
  10987
+ 9749:	  1EAF	75 4E BD	        mov     4eh,#LOW(s_sub0)    ; addresses to be tested
  10988
+ 9750:	  1EB2	75 4D 1E	        mov     4dh,#HIGH(s_sub1)
  10989
+ 9751:	  1EB5	75 4C C7	        mov     4ch,#LOW(s_sub1)
10990 10990
  9752:
10991  
- 9753:
10992  
- 9754:				        ; a.- <RETI>
10993  
- 9755:	  1EC0	75 81 4F	        mov     SP,#4fh             ; Initialize SP...
10994  
- 9756:	  1EC3	75 4F 1E	        mov     4fh,#HIGH(s_sub2)   ; ...and load stack area with return
10995  
- 9757:	  1EC6	75 4E D4	        mov     4eh,#LOW(s_sub2)    ; addresses to be tested
10996  
- 9758:	  1EC9	75 4D 1E	        mov     4dh,#HIGH(s_sub3)
10997  
- 9759:	  1ECC	75 4C DE	        mov     4ch,#LOW(s_sub3)
10998  
- 9760:
10999  
- 9761:	  1ECF	22		        ret                         ; Do the ret...
11000  
- 9762:	  1ED0	80 E8		        sjmp    ts_a0
11001  
- 9763:	  1ED2	74 00		        mov     A,#00h
11002  
- 9764:	  1ED4	E5 81		s_sub2: mov     A,SP
11003  
- 9765:	  1ED6	B4 4D 0F	        cjne    A,#4dh,ts_b0       ; ... and verify the SP value
11004  
- 9766:
11005  
- 9767:	  1ED9	22		        ret                         ; Do another ret...
11006  
- 9768:	  1EDA	80 DE		        sjmp    ts_a0
11007  
- 9769:	  1EDC	74 00		        mov     A,#00h
11008  
- 9770:	  1EDE	E5 81		s_sub3: mov     A,SP
11009  
- 9771:	  1EE0	B4 4B 05	        cjne    A,#4bh,ts_b0       ; ... and verify the SP value
11010  
- 9772:
11011  
- 9773:				        eot     'b',ts_b0
11012  
- 9774+ 1			        putc    #'b'
11013  
- 9775+ 2  1EE3			??0850:
11014  
- 9776+ 2			        ;jnb     SCON.1,putc_loop
11015  
- 9777+ 2			        ;clr     SCON.1
11016  
- 9778+ 2  1EE3	75 99 62	        mov     SBUF,#'b'
11017  
- 9779+ 1  1EE6	80 06		        sjmp    ??0849
11018  
- 9780+ 1  1EE8			ts_b0:  putc    #'?'
11019  
- 9781+ 2  1EE8			??0851:
11020  
- 9782+ 2			        ;jnb     SCON.1,putc_loop
11021  
- 9783+ 2			        ;clr     SCON.1
11022  
- 9784+ 2  1EE8	75 99 3F	        mov     SBUF,#'?'
11023  
- 9785+ 1  1EEB	75 6E 01	        mov     fail,#001h
11024  
- 9786+ 1  1EEE			??0849:
  10991
+ 9753:	  1EB8	22		        ret                         ; Do the ret...
  10992
+ 9754:	  1EB9	80 16		        sjmp    ts_a0
  10993
+ 9755:	  1EBB	74 00		        mov     A,#00h
  10994
+ 9756:	  1EBD	E5 81		s_sub0: mov     A,SP
  10995
+ 9757:	  1EBF	B4 4D 0F	        cjne    A,#4dh,ts_a0       ; ... and verify the SP value
  10996
+ 9758:
  10997
+ 9759:	  1EC2	22		        ret                         ; Do another ret...
  10998
+ 9760:	  1EC3	80 0C		        sjmp    ts_a0
  10999
+ 9761:	  1EC5	74 00		        mov     A,#00h
  11000
+ 9762:	  1EC7	E5 81		s_sub1: mov     A,SP
  11001
+ 9763:	  1EC9	B4 4B 05	        cjne    A,#4bh,ts_a0       ; ... and verify the SP value
  11002
+ 9764:
  11003
+ 9765:				        eot     'a',ts_a0
  11004
+ 9766+ 1			        putc    #'a'
  11005
+ 9767+ 2  1ECC			??0850:
  11006
+ 9768+ 2			        ;jnb     SCON.1,putc_loop
  11007
+ 9769+ 2			        ;clr     SCON.1
  11008
+ 9770+ 2  1ECC	75 99 61	        mov     SBUF,#'a'
  11009
+ 9771+ 1  1ECF	80 06		        sjmp    ??0849
  11010
+ 9772+ 1  1ED1			ts_a0:  putc    #'?'
  11011
+ 9773+ 2  1ED1			??0851:
  11012
+ 9774+ 2			        ;jnb     SCON.1,putc_loop
  11013
+ 9775+ 2			        ;clr     SCON.1
  11014
+ 9776+ 2  1ED1	75 99 3F	        mov     SBUF,#'?'
  11015
+ 9777+ 1  1ED4	75 6E 01	        mov     fail,#001h
  11016
+ 9778+ 1  1ED7			??0849:
  11017
+ 9779:
  11018
+ 9780:
  11019
+ 9781:				        ; a.- <RETI>
  11020
+ 9782:	  1ED7	75 81 4F	        mov     SP,#4fh             ; Initialize SP...
  11021
+ 9783:	  1EDA	75 4F 1E	        mov     4fh,#HIGH(s_sub2)   ; ...and load stack area with return
  11022
+ 9784:	  1EDD	75 4E EB	        mov     4eh,#LOW(s_sub2)    ; addresses to be tested
  11023
+ 9785:	  1EE0	75 4D 1E	        mov     4dh,#HIGH(s_sub3)
  11024
+ 9786:	  1EE3	75 4C F5	        mov     4ch,#LOW(s_sub3)
11025 11025
  9787:
11026 11026
 
11027 11027
 ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. Heinz                                        PAGE 176
@@ -11030,62 +11030,62 @@ ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. H
11030 11030
 
11031 11031
  Line  I  Addr  Code            Source
11032 11032
 
11033  
- 9788:				        ; Lots of things can go badly and we wouldn't know with this test...
11034  
- 9789:				        put_crlf                    ; end of test series
11035  
- 9790+ 1			        putc    #13
11036  
- 9791+ 2  1EEE			??0852:
11037  
- 9792+ 2			        ;jnb     SCON.1,putc_loop
11038  
- 9793+ 2			        ;clr     SCON.1
11039  
- 9794+ 2  1EEE	75 99 0D	        mov     SBUF,#13
11040  
- 9795+ 1			        putc    #10
11041  
- 9796+ 2  1EF1			??0853:
11042  
- 9797+ 2			        ;jnb     SCON.1,putc_loop
11043  
- 9798+ 2			        ;clr     SCON.1
11044  
- 9799+ 2  1EF1	75 99 0A	        mov     SBUF,#10
11045  
- 9800:
11046  
- 9801:				        ;-- Test series T ------------------------------------------------------
11047  
- 9802:				        ; MUL, DIV instructions
11048  
- 9803:				        ; a.- <DIV>
11049  
- 9804:				        ; b.- <MUL>
11050  
- 9805:				        ;
11051  
- 9806:
11052  
- 9807:				        putc    #'T'                ; start of test series
11053  
- 9808+ 1  1EF4			??0854:
11054  
- 9809+ 1			        ;jnb     SCON.1,putc_loop
11055  
- 9810+ 1			        ;clr     SCON.1
11056  
- 9811+ 1  1EF4	75 99 54	        mov     SBUF,#'T'
11057  
- 9812:
11058  
- 9813:				        ; a.- <DIV>
11059  
- 9814:	  1EF7	75 F0 07	        mov     B,#07h              ; First of all, make sure B can be read back
11060  
- 9815:	  1EFA	74 13		        mov     A,#13h
11061  
- 9816:	  1EFC	E5 F0		        mov     A,B
11062  
- 9817:	  1EFE	B4 07 37	        cjne    A,#07h,tt_a0
11063  
- 9818:
11064  
- 9819:				        ; Now do a few representative DIVs using a table. The table has the
11065  
- 9820:				        ; following format:
11066  
- 9821:				        ; denominator, numerator, overflow, quotient, remainder
11067  
- 9822:				        ; Where 'overflow' is 00h or 04h.
11068  
- 9823:
11069  
- 9824:				        ; DPTR will point to the start of the table, r0 will be the current data
11070  
- 9825:				        ; byte offset and r1 the number of test cases remaiining.
11071  
- 9826:	  1F01	90 1F 40	        mov     DPTR,#tt_a_tab
11072  
- 9827:	  1F04	78 00		        mov     r0,#00h
11073  
- 9828:	  1F06	79 09		        mov     r1,#((tt_a_tab_end-tt_a_tab)/5)
11074  
- 9829:
11075  
- 9830:	  1F08			tt_a_loop:
11076  
- 9831:	  1F08	E8		        mov     a,r0
11077  
- 9832:	  1F09	08		        inc     r0
11078  
- 9833:	  1F0A	93		        movc    a,@a+DPTR
11079  
- 9834:	  1F0B	F5 F0		        mov     B,a
11080  
- 9835:	  1F0D	E8		        mov     a,r0
11081  
- 9836:	  1F0E	08		        inc     r0
11082  
- 9837:	  1F0F	93		        movc    a,@a+DPTR
11083  
- 9838:	  1F10	84		        div     ab
11084  
- 9839:	  1F11	F5 60		        mov     dir0,a
11085  
- 9840:
11086  
- 9841:	  1F13	E8		        mov     a,r0                ; Get expected OV flag
11087  
- 9842:	  1F14	08		        inc     r0
11088  
- 9843:	  1F15	93		        movc    a,@a+DPTR
  11033
+ 9788:	  1EE6	22		        ret                         ; Do the ret...
  11034
+ 9789:	  1EE7	80 E8		        sjmp    ts_a0
  11035
+ 9790:	  1EE9	74 00		        mov     A,#00h
  11036
+ 9791:	  1EEB	E5 81		s_sub2: mov     A,SP
  11037
+ 9792:	  1EED	B4 4D 0F	        cjne    A,#4dh,ts_b0       ; ... and verify the SP value
  11038
+ 9793:
  11039
+ 9794:	  1EF0	22		        ret                         ; Do another ret...
  11040
+ 9795:	  1EF1	80 DE		        sjmp    ts_a0
  11041
+ 9796:	  1EF3	74 00		        mov     A,#00h
  11042
+ 9797:	  1EF5	E5 81		s_sub3: mov     A,SP
  11043
+ 9798:	  1EF7	B4 4B 05	        cjne    A,#4bh,ts_b0       ; ... and verify the SP value
  11044
+ 9799:
  11045
+ 9800:				        eot     'b',ts_b0
  11046
+ 9801+ 1			        putc    #'b'
  11047
+ 9802+ 2  1EFA			??0853:
  11048
+ 9803+ 2			        ;jnb     SCON.1,putc_loop
  11049
+ 9804+ 2			        ;clr     SCON.1
  11050
+ 9805+ 2  1EFA	75 99 62	        mov     SBUF,#'b'
  11051
+ 9806+ 1  1EFD	80 06		        sjmp    ??0852
  11052
+ 9807+ 1  1EFF			ts_b0:  putc    #'?'
  11053
+ 9808+ 2  1EFF			??0854:
  11054
+ 9809+ 2			        ;jnb     SCON.1,putc_loop
  11055
+ 9810+ 2			        ;clr     SCON.1
  11056
+ 9811+ 2  1EFF	75 99 3F	        mov     SBUF,#'?'
  11057
+ 9812+ 1  1F02	75 6E 01	        mov     fail,#001h
  11058
+ 9813+ 1  1F05			??0852:
  11059
+ 9814:
  11060
+ 9815:				        ; Lots of things can go badly and we wouldn't know with this test...
  11061
+ 9816:				        put_crlf                    ; end of test series
  11062
+ 9817+ 1			        putc    #13
  11063
+ 9818+ 2  1F05			??0855:
  11064
+ 9819+ 2			        ;jnb     SCON.1,putc_loop
  11065
+ 9820+ 2			        ;clr     SCON.1
  11066
+ 9821+ 2  1F05	75 99 0D	        mov     SBUF,#13
  11067
+ 9822+ 1			        putc    #10
  11068
+ 9823+ 2  1F08			??0856:
  11069
+ 9824+ 2			        ;jnb     SCON.1,putc_loop
  11070
+ 9825+ 2			        ;clr     SCON.1
  11071
+ 9826+ 2  1F08	75 99 0A	        mov     SBUF,#10
  11072
+ 9827:
  11073
+ 9828:				        ;-- Test series T ------------------------------------------------------
  11074
+ 9829:				        ; MUL, DIV instructions
  11075
+ 9830:				        ; a.- <DIV>
  11076
+ 9831:				        ; b.- <MUL>
  11077
+ 9832:				        ;
  11078
+ 9833:
  11079
+ 9834:				        putc    #'T'                ; start of test series
  11080
+ 9835+ 1  1F0B			??0857:
  11081
+ 9836+ 1			        ;jnb     SCON.1,putc_loop
  11082
+ 9837+ 1			        ;clr     SCON.1
  11083
+ 9838+ 1  1F0B	75 99 54	        mov     SBUF,#'T'
  11084
+ 9839:
  11085
+ 9840:				        ; a.- <DIV>
  11086
+ 9841:	  1F0E	75 F0 07	        mov     B,#07h              ; First of all, make sure B can be read back
  11087
+ 9842:	  1F11	74 13		        mov     A,#13h
  11088
+ 9843:	  1F13	E5 F0		        mov     A,B
11089 11089
 
11090 11090
 ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. Heinz                                        PAGE 177
11091 11091
 
@@ -11093,62 +11093,62 @@ ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. H
11093 11093
 
11094 11094
  Line  I  Addr  Code            Source
11095 11095
 
11096  
- 9844:	  1F16	70 15		        jnz     tt_a_divzero        ; If OV expected, skip verification of
11097  
- 9845:	  1F18	E5 D0		        mov     a,PSW               ; quotient and remainder
11098  
- 9846:	  1F1A	54 04		        anl     a,#04h
11099  
- 9847:	  1F1C	70 1A		        jnz     tt_a0
11100  
- 9848:
11101  
- 9849:	  1F1E	E8		        mov     a,r0                ; Verify quotient...
11102  
- 9850:	  1F1F	08		        inc     r0
11103  
- 9851:	  1F20	93		        movc    a,@a+DPTR
11104  
- 9852:	  1F21	B5 60 14	        cjne    a,dir0,tt_a0
11105  
- 9853:	  1F24	E8		        mov     a,r0                ; ...and verify remainder
11106  
- 9854:	  1F25	08		        inc     r0
11107  
- 9855:	  1F26	93		        movc    a,@a+DPTR
11108  
- 9856:	  1F27	B5 F0 0E	        cjne    a,B,tt_a0
11109  
- 9857:	  1F2A	02 1F 2F	        jmp     tt_a_next
11110  
- 9858:
11111  
- 9859:	  1F2D			tt_a_divzero:
11112  
- 9860:	  1F2D	08		        inc     r0
11113  
- 9861:	  1F2E	08		        inc     r0
11114  
- 9862:	  1F2F			tt_a_next:
11115  
- 9863:	  1F2F	19		        dec     r1                  ; go for next test vector, if any
11116  
- 9864:	  1F30	E9		        mov     a,r1
11117  
- 9865:	  1F31	70 D5		        jnz     tt_a_loop
11118  
- 9866:
11119  
- 9867:				        eot     'a',tt_a0
11120  
- 9868+ 1			        putc    #'a'
11121  
- 9869+ 2  1F33			??0856:
11122  
- 9870+ 2			        ;jnb     SCON.1,putc_loop
11123  
- 9871+ 2			        ;clr     SCON.1
11124  
- 9872+ 2  1F33	75 99 61	        mov     SBUF,#'a'
11125  
- 9873+ 1  1F36	80 06		        sjmp    ??0855
11126  
- 9874+ 1  1F38			tt_a0:  putc    #'?'
11127  
- 9875+ 2  1F38			??0857:
11128  
- 9876+ 2			        ;jnb     SCON.1,putc_loop
11129  
- 9877+ 2			        ;clr     SCON.1
11130  
- 9878+ 2  1F38	75 99 3F	        mov     SBUF,#'?'
11131  
- 9879+ 1  1F3B	75 6E 01	        mov     fail,#001h
11132  
- 9880+ 1  1F3E			??0855:
11133  
- 9881:	  1F3E	80 2D		        sjmp    tt_a_tab_end
11134  
- 9882:
11135  
- 9883:	  1F40			tt_a_tab:
11136  
- 9884:	  1F40	07 13 00 02	        db      7,19,0,2,5
11137  
-	  1F44	05
11138  
- 9885:	  1F45	07 11 00 02	        db      7,17,0,2,3
11139  
-	  1F49	03
11140  
- 9886:	  1F4A	07 0D 00 01	        db      7,13,0,1,6
11141  
-	  1F4E	06
11142  
- 9887:	  1F4F	0D 11 00 01	        db      13,17,0,1,4
11143  
-	  1F53	04
11144  
- 9888:	  1F54	11 0D 00 00	        db      17,13,0,0,13
11145  
-	  1F58	0D
11146  
- 9889:	  1F59	00 0D 04 00	        db      0,13,4,0,13
11147  
-	  1F5D	0D
11148  
- 9890:	  1F5E	80 87 00 01	        db      80h,87h,0,1,7
11149  
-	  1F62	07
11150  
- 9891:	  1F63	01 FF 00 FF	        db      1,255,0,255,0
11151  
-	  1F67	00
  11096
+ 9844:	  1F15	B4 07 37	        cjne    A,#07h,tt_a0
  11097
+ 9845:
  11098
+ 9846:				        ; Now do a few representative DIVs using a table. The table has the
  11099
+ 9847:				        ; following format:
  11100
+ 9848:				        ; denominator, numerator, overflow, quotient, remainder
  11101
+ 9849:				        ; Where 'overflow' is 00h or 04h.
  11102
+ 9850:
  11103
+ 9851:				        ; DPTR will point to the start of the table, r0 will be the current data
  11104
+ 9852:				        ; byte offset and r1 the number of test cases remaiining.
  11105
+ 9853:	  1F18	90 1F 57	        mov     DPTR,#tt_a_tab
  11106
+ 9854:	  1F1B	78 00		        mov     r0,#00h
  11107
+ 9855:	  1F1D	79 09		        mov     r1,#((tt_a_tab_end-tt_a_tab)/5)
  11108
+ 9856:
  11109
+ 9857:	  1F1F			tt_a_loop:
  11110
+ 9858:	  1F1F	E8		        mov     a,r0
  11111
+ 9859:	  1F20	08		        inc     r0
  11112
+ 9860:	  1F21	93		        movc    a,@a+DPTR
  11113
+ 9861:	  1F22	F5 F0		        mov     B,a
  11114
+ 9862:	  1F24	E8		        mov     a,r0
  11115
+ 9863:	  1F25	08		        inc     r0
  11116
+ 9864:	  1F26	93		        movc    a,@a+DPTR
  11117
+ 9865:	  1F27	84		        div     ab
  11118
+ 9866:	  1F28	F5 60		        mov     dir0,a
  11119
+ 9867:
  11120
+ 9868:	  1F2A	E8		        mov     a,r0                ; Get expected OV flag
  11121
+ 9869:	  1F2B	08		        inc     r0
  11122
+ 9870:	  1F2C	93		        movc    a,@a+DPTR
  11123
+ 9871:	  1F2D	70 15		        jnz     tt_a_divzero        ; If OV expected, skip verification of
  11124
+ 9872:	  1F2F	E5 D0		        mov     a,PSW               ; quotient and remainder
  11125
+ 9873:	  1F31	54 04		        anl     a,#04h
  11126
+ 9874:	  1F33	70 1A		        jnz     tt_a0
  11127
+ 9875:
  11128
+ 9876:	  1F35	E8		        mov     a,r0                ; Verify quotient...
  11129
+ 9877:	  1F36	08		        inc     r0
  11130
+ 9878:	  1F37	93		        movc    a,@a+DPTR
  11131
+ 9879:	  1F38	B5 60 14	        cjne    a,dir0,tt_a0
  11132
+ 9880:	  1F3B	E8		        mov     a,r0                ; ...and verify remainder
  11133
+ 9881:	  1F3C	08		        inc     r0
  11134
+ 9882:	  1F3D	93		        movc    a,@a+DPTR
  11135
+ 9883:	  1F3E	B5 F0 0E	        cjne    a,B,tt_a0
  11136
+ 9884:	  1F41	02 1F 46	        jmp     tt_a_next
  11137
+ 9885:
  11138
+ 9886:	  1F44			tt_a_divzero:
  11139
+ 9887:	  1F44	08		        inc     r0
  11140
+ 9888:	  1F45	08		        inc     r0
  11141
+ 9889:	  1F46			tt_a_next:
  11142
+ 9890:	  1F46	19		        dec     r1                  ; go for next test vector, if any
  11143
+ 9891:	  1F47	E9		        mov     a,r1
  11144
+ 9892:	  1F48	70 D5		        jnz     tt_a_loop
  11145
+ 9893:
  11146
+ 9894:				        eot     'a',tt_a0
  11147
+ 9895+ 1			        putc    #'a'
  11148
+ 9896+ 2  1F4A			??0859:
  11149
+ 9897+ 2			        ;jnb     SCON.1,putc_loop
  11150
+ 9898+ 2			        ;clr     SCON.1
  11151
+ 9899+ 2  1F4A	75 99 61	        mov     SBUF,#'a'
11152 11152
 
11153 11153
 ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. Heinz                                        PAGE 178
11154 11154
 
@@ -11156,62 +11156,62 @@ ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. H
11156 11156
 
11157 11157
  Line  I  Addr  Code            Source
11158 11158
 
11159  
- 9892:	  1F68	02 FF 00 7F	        db      2,255,0,127,1
11160  
-	  1F6C	01
11161  
- 9893:	  1F6D			tt_a_tab_end:
11162  
- 9894:
11163  
- 9895:				        ; b.- <MUL>
11164  
- 9896:
11165  
- 9897:				        ; Do with MUL the same we just did with DIV. The test data table has
11166  
- 9898:				        ; the following format:
11167  
- 9899:				        ; denominator, numerator, product high byte, product low byte.
11168  
- 9900:
11169  
- 9901:				        ; DPTR will point to the start of the table, r0 will be the current data
11170  
- 9902:				        ; byte offset and r1 the number of test cases remaiining.
11171  
- 9903:	  1F6D	90 1F AE	        mov     DPTR,#tt_b_tab
11172  
- 9904:	  1F70	78 00		        mov     r0,#00h
11173  
- 9905:	  1F72	79 09		        mov     r1,#((tt_b_tab_end-tt_b_tab)/4)
11174  
- 9906:
11175  
- 9907:	  1F74			tt_b_loop:
11176  
- 9908:	  1F74	E8		        mov     a,r0                ; Load B with test data...
11177  
- 9909:	  1F75	08		        inc     r0
11178  
- 9910:	  1F76	93		        movc    a,@a+DPTR
11179  
- 9911:	  1F77	F5 F0		        mov     B,a
11180  
- 9912:	  1F79	E8		        mov     a,r0                ; ...then load A with test data...
11181  
- 9913:	  1F7A	08		        inc     r0
11182  
- 9914:	  1F7B	93		        movc    a,@a+DPTR
11183  
- 9915:	  1F7C	A4		        mul     ab                  ; and do the MUL
11184  
- 9916:	  1F7D	F5 60		        mov     dir0,a              ; Save A for later checks
11185  
- 9917:
11186  
- 9918:	  1F7F	E8		        mov     a,r0                ; Verify product high byte
11187  
- 9919:				        ;inc     r0
11188  
- 9920:	  1F80	93		        movc    a,@a+DPTR
11189  
- 9921:	  1F81	60 08		        jz      tt_b_noovf
11190  
- 9922:
11191  
- 9923:	  1F83	E5 D0		        mov     a,PSW               ; overflow expected
11192  
- 9924:	  1F85	54 04		        anl     a,#04h
11193  
- 9925:	  1F87	60 1D		        jz      tt_b0
11194  
- 9926:	  1F89	80 06		        sjmp    tt_b_0
  11159
+ 9900+ 1  1F4D	80 06		        sjmp    ??0858
  11160
+ 9901+ 1  1F4F			tt_a0:  putc    #'?'
  11161
+ 9902+ 2  1F4F			??0860:
  11162
+ 9903+ 2			        ;jnb     SCON.1,putc_loop
  11163
+ 9904+ 2			        ;clr     SCON.1
  11164
+ 9905+ 2  1F4F	75 99 3F	        mov     SBUF,#'?'
  11165
+ 9906+ 1  1F52	75 6E 01	        mov     fail,#001h
  11166
+ 9907+ 1  1F55			??0858:
  11167
+ 9908:	  1F55	80 2D		        sjmp    tt_a_tab_end
  11168
+ 9909:
  11169
+ 9910:	  1F57			tt_a_tab:
  11170
+ 9911:	  1F57	07 13 00 02	        db      7,19,0,2,5
  11171
+	  1F5B	05
  11172
+ 9912:	  1F5C	07 11 00 02	        db      7,17,0,2,3
  11173
+	  1F60	03
  11174
+ 9913:	  1F61	07 0D 00 01	        db      7,13,0,1,6
  11175
+	  1F65	06
  11176
+ 9914:	  1F66	0D 11 00 01	        db      13,17,0,1,4
  11177
+	  1F6A	04
  11178
+ 9915:	  1F6B	11 0D 00 00	        db      17,13,0,0,13
  11179
+	  1F6F	0D
  11180
+ 9916:	  1F70	00 0D 04 00	        db      0,13,4,0,13
  11181
+	  1F74	0D
  11182
+ 9917:	  1F75	80 87 00 01	        db      80h,87h,0,1,7
  11183
+	  1F79	07
  11184
+ 9918:	  1F7A	01 FF 00 FF	        db      1,255,0,255,0
  11185
+	  1F7E	00
  11186
+ 9919:	  1F7F	02 FF 00 7F	        db      2,255,0,127,1
  11187
+	  1F83	01
  11188
+ 9920:	  1F84			tt_a_tab_end:
  11189
+ 9921:
  11190
+ 9922:				        ; b.- <MUL>
  11191
+ 9923:
  11192
+ 9924:				        ; Do with MUL the same we just did with DIV. The test data table has
  11193
+ 9925:				        ; the following format:
  11194
+ 9926:				        ; denominator, numerator, product high byte, product low byte.
11195 11195
  9927:
11196  
- 9928:	  1F8B			tt_b_noovf:
11197  
- 9929:	  1F8B	E5 D0		        mov     a,PSW               ; no overflow expected
11198  
- 9930:	  1F8D	54 04		        anl     a,#04h
11199  
- 9931:	  1F8F	70 15		        jnz     tt_b0
11200  
- 9932:
11201  
- 9933:	  1F91			tt_b_0:
11202  
- 9934:	  1F91	E8		        mov     a,r0                ; Verify product high byte
11203  
- 9935:	  1F92	08		        inc     r0
11204  
- 9936:	  1F93	93		        movc    a,@a+DPTR
11205  
- 9937:	  1F94	B5 F0 0F	        cjne    a,B,tt_b0
11206  
- 9938:	  1F97	E8		        mov     a,r0                ; ...and verify low byte
11207  
- 9939:	  1F98	08		        inc     r0
11208  
- 9940:	  1F99	93		        movc    a,@a+DPTR
11209  
- 9941:	  1F9A	B5 60 09	        cjne    a,dir0,tt_b0
11210  
- 9942:
11211  
- 9943:	  1F9D	19		        dec     r1                  ; go for next test vector, if any
11212  
- 9944:	  1F9E	E9		        mov     a,r1
11213  
- 9945:	  1F9F	70 D3		        jnz     tt_b_loop
11214  
- 9946:
  11196
+ 9928:				        ; DPTR will point to the start of the table, r0 will be the current data
  11197
+ 9929:				        ; byte offset and r1 the number of test cases remaiining.
  11198
+ 9930:	  1F84	90 1F C5	        mov     DPTR,#tt_b_tab
  11199
+ 9931:	  1F87	78 00		        mov     r0,#00h
  11200
+ 9932:	  1F89	79 09		        mov     r1,#((tt_b_tab_end-tt_b_tab)/4)
  11201
+ 9933:
  11202
+ 9934:	  1F8B			tt_b_loop:
  11203
+ 9935:	  1F8B	E8		        mov     a,r0                ; Load B with test data...
  11204
+ 9936:	  1F8C	08		        inc     r0
  11205
+ 9937:	  1F8D	93		        movc    a,@a+DPTR
  11206
+ 9938:	  1F8E	F5 F0		        mov     B,a
  11207
+ 9939:	  1F90	E8		        mov     a,r0                ; ...then load A with test data...
  11208
+ 9940:	  1F91	08		        inc     r0
  11209
+ 9941:	  1F92	93		        movc    a,@a+DPTR
  11210
+ 9942:	  1F93	A4		        mul     ab                  ; and do the MUL
  11211
+ 9943:	  1F94	F5 60		        mov     dir0,a              ; Save A for later checks
  11212
+ 9944:
  11213
+ 9945:	  1F96	E8		        mov     a,r0                ; Verify product high byte
  11214
+ 9946:				        ;inc     r0
11215 11215
 
11216 11216
 ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. Heinz                                        PAGE 179
11217 11217
 
@@ -11219,62 +11219,62 @@ ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. H
11219 11219
 
11220 11220
  Line  I  Addr  Code            Source
11221 11221
 
11222  
- 9947:				        eot     'b',tt_b0
11223  
- 9948+ 1			        putc    #'b'
11224  
- 9949+ 2  1FA1			??0859:
11225  
- 9950+ 2			        ;jnb     SCON.1,putc_loop
11226  
- 9951+ 2			        ;clr     SCON.1
11227  
- 9952+ 2  1FA1	75 99 62	        mov     SBUF,#'b'
11228  
- 9953+ 1  1FA4	80 06		        sjmp    ??0858
11229  
- 9954+ 1  1FA6			tt_b0:  putc    #'?'
11230  
- 9955+ 2  1FA6			??0860:
11231  
- 9956+ 2			        ;jnb     SCON.1,putc_loop
11232  
- 9957+ 2			        ;clr     SCON.1
11233  
- 9958+ 2  1FA6	75 99 3F	        mov     SBUF,#'?'
11234  
- 9959+ 1  1FA9	75 6E 01	        mov     fail,#001h
11235  
- 9960+ 1  1FAC			??0858:
11236  
- 9961:	  1FAC	80 24		        sjmp    tt_b_tab_end
11237  
- 9962:
11238  
- 9963:	  1FAE			tt_b_tab:
11239  
- 9964:	  1FAE	07 13 00 85	        db      7,19,0,133
11240  
- 9965:	  1FB2	07 11 00 77	        db      7,17,0,119
11241  
- 9966:	  1FB6	07 0D 00 5B	        db      7,13,0,91
11242  
- 9967:	  1FBA	0D 11 00 DD	        db      13,17,0,221
11243  
- 9968:	  1FBE	11 0D 00 DD	        db      17,13,0,221
11244  
- 9969:	  1FC2	00 0D 00 00	        db      0,13,0,0
11245  
- 9970:	  1FC6	80 87 43 80	        db      80h,87h,43h,80h
11246  
- 9971:	  1FCA	01 FF 00 FF	        db      1,255,0,255
11247  
- 9972:	  1FCE	02 FF 01 FE	        db      2,255,01h,0feh
11248  
- 9973:	  1FD2			tt_b_tab_end:
11249  
- 9974:
11250  
- 9975:				        put_crlf                    ; end of test series
11251  
- 9976+ 1			        putc    #13
11252  
- 9977+ 2  1FD2			??0861:
11253  
- 9978+ 2			        ;jnb     SCON.1,putc_loop
11254  
- 9979+ 2			        ;clr     SCON.1
11255  
- 9980+ 2  1FD2	75 99 0D	        mov     SBUF,#13
11256  
- 9981+ 1			        putc    #10
11257  
- 9982+ 2  1FD5			??0862:
  11222
+ 9947:	  1F97	93		        movc    a,@a+DPTR
  11223
+ 9948:	  1F98	60 08		        jz      tt_b_noovf
  11224
+ 9949:
  11225
+ 9950:	  1F9A	E5 D0		        mov     a,PSW               ; overflow expected
  11226
+ 9951:	  1F9C	54 04		        anl     a,#04h
  11227
+ 9952:	  1F9E	60 1D		        jz      tt_b0
  11228
+ 9953:	  1FA0	80 06		        sjmp    tt_b_0
  11229
+ 9954:
  11230
+ 9955:	  1FA2			tt_b_noovf:
  11231
+ 9956:	  1FA2	E5 D0		        mov     a,PSW               ; no overflow expected
  11232
+ 9957:	  1FA4	54 04		        anl     a,#04h
  11233
+ 9958:	  1FA6	70 15		        jnz     tt_b0
  11234
+ 9959:
  11235
+ 9960:	  1FA8			tt_b_0:
  11236
+ 9961:	  1FA8	E8		        mov     a,r0                ; Verify product high byte
  11237
+ 9962:	  1FA9	08		        inc     r0
  11238
+ 9963:	  1FAA	93		        movc    a,@a+DPTR
  11239
+ 9964:	  1FAB	B5 F0 0F	        cjne    a,B,tt_b0
  11240
+ 9965:	  1FAE	E8		        mov     a,r0                ; ...and verify low byte
  11241
+ 9966:	  1FAF	08		        inc     r0
  11242
+ 9967:	  1FB0	93		        movc    a,@a+DPTR
  11243
+ 9968:	  1FB1	B5 60 09	        cjne    a,dir0,tt_b0
  11244
+ 9969:
  11245
+ 9970:	  1FB4	19		        dec     r1                  ; go for next test vector, if any
  11246
+ 9971:	  1FB5	E9		        mov     a,r1
  11247
+ 9972:	  1FB6	70 D3		        jnz     tt_b_loop
  11248
+ 9973:
  11249
+ 9974:				        eot     'b',tt_b0
  11250
+ 9975+ 1			        putc    #'b'
  11251
+ 9976+ 2  1FB8			??0862:
  11252
+ 9977+ 2			        ;jnb     SCON.1,putc_loop
  11253
+ 9978+ 2			        ;clr     SCON.1
  11254
+ 9979+ 2  1FB8	75 99 62	        mov     SBUF,#'b'
  11255
+ 9980+ 1  1FBB	80 06		        sjmp    ??0861
  11256
+ 9981+ 1  1FBD			tt_b0:  putc    #'?'
  11257
+ 9982+ 2  1FBD			??0863:
11258 11258
  9983+ 2			        ;jnb     SCON.1,putc_loop
11259 11259
  9984+ 2			        ;clr     SCON.1
11260  
- 9985+ 2  1FD5	75 99 0A	        mov     SBUF,#10
11261  
- 9986:
11262  
- 9987:
11263  
- 9988:
11264  
- 9989:				        ;-- Test series U ------------------------------------------------------
11265  
- 9990:				        ; Register banks
11266  
- 9991:				        ; a.- Write to register, read from indirect address.
11267  
- 9992:				        ; a.- Write to indirect address, read from register.
11268  
- 9993:				        ;
11269  
- 9994:
11270  
- 9995:				        putc    #'U'                ; start of test series
11271  
- 9996+ 1  1FD8			??0863:
11272  
- 9997+ 1			        ;jnb     SCON.1,putc_loop
11273  
- 9998+ 1			        ;clr     SCON.1
11274  
- 9999+ 1  1FD8	75 99 55	        mov     SBUF,#'U'
11275  
-10000:
  11260
+ 9985+ 2  1FBD	75 99 3F	        mov     SBUF,#'?'
  11261
+ 9986+ 1  1FC0	75 6E 01	        mov     fail,#001h
  11262
+ 9987+ 1  1FC3			??0861:
  11263
+ 9988:	  1FC3	80 24		        sjmp    tt_b_tab_end
  11264
+ 9989:
  11265
+ 9990:	  1FC5			tt_b_tab:
  11266
+ 9991:	  1FC5	07 13 00 85	        db      7,19,0,133
  11267
+ 9992:	  1FC9	07 11 00 77	        db      7,17,0,119
  11268
+ 9993:	  1FCD	07 0D 00 5B	        db      7,13,0,91
  11269
+ 9994:	  1FD1	0D 11 00 DD	        db      13,17,0,221
  11270
+ 9995:	  1FD5	11 0D 00 DD	        db      17,13,0,221
  11271
+ 9996:	  1FD9	00 0D 00 00	        db      0,13,0,0
  11272
+ 9997:	  1FDD	80 87 43 80	        db      80h,87h,43h,80h
  11273
+ 9998:	  1FE1	01 FF 00 FF	        db      1,255,0,255
  11274
+ 9999:	  1FE5	02 FF 01 FE	        db      2,255,01h,0feh
  11275
+10000:	  1FE9			tt_b_tab_end:
11276 11276
 10001:
11277  
-10002:	  1FDB	75 D0 00	        mov     PSW,#00h            ; Test bank 0
  11277
+10002:				        put_crlf                    ; end of test series
11278 11278
 
11279 11279
 ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. Heinz                                        PAGE 180
11280 11280
 
@@ -11282,62 +11282,62 @@ ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. H
11282 11282
 
11283 11283
  Line  I  Addr  Code            Source
11284 11284
 
11285  
-10003:	  1FDE	74 01		        mov     a,#00h + 1
11286  
-10004:	  1FE0	12 1F FD	        call    tu_a_test
11287  
-10005:
11288  
-10006:	  1FE3	75 D0 08	        mov     PSW,#08h            ; Test bank 1
11289  
-10007:	  1FE6	74 09		        mov     a,#08h + 1
11290  
-10008:	  1FE8	12 1F FD	        call    tu_a_test
11291  
-10009:
11292  
-10010:	  1FEB	75 D0 10	        mov     PSW,#10h            ; Test bank 2
11293  
-10011:	  1FEE	74 11		        mov     a,#10h + 1
11294  
-10012:	  1FF0	12 1F FD	        call    tu_a_test
  11285
+10003+ 1			        putc    #13
  11286
+10004+ 2  1FE9			??0864:
  11287
+10005+ 2			        ;jnb     SCON.1,putc_loop
  11288
+10006+ 2			        ;clr     SCON.1
  11289
+10007+ 2  1FE9	75 99 0D	        mov     SBUF,#13
  11290
+10008+ 1			        putc    #10
  11291
+10009+ 2  1FEC			??0865:
  11292
+10010+ 2			        ;jnb     SCON.1,putc_loop
  11293
+10011+ 2			        ;clr     SCON.1
  11294
+10012+ 2  1FEC	75 99 0A	        mov     SBUF,#10
11295 11295
 10013:
11296  
-10014:	  1FF3	75 D0 18	        mov     PSW,#18h            ; Test bank 3
11297  
-10015:	  1FF6	74 19		        mov     a,#18h + 1
11298  
-10016:	  1FF8	12 1F FD	        call    tu_a_test
11299  
-10017:
11300  
-10018:	  1FFB	80 1E		        sjmp    tu_a_done
11301  
-10019:
11302  
-10020:	  1FFD			tu_a_test:
11303  
-10021:	  1FFD	F8		        mov     r0,a                ; R0 points to R1 in the selected bank.
11304  
-10022:
11305  
-10023:	  1FFE	79 12		        mov     r1,#12h             ; Write to registers R1 and R7
11306  
-10024:	  2000	7F 34		        mov     r7,#34h
11307  
-10025:
11308  
-10026:	  2002	E6		        mov     a,@r0               ; Check R1
11309  
-10027:	  2003	B4 12 1B	        cjne    a,#12h,tu_a0
11310  
-10028:	  2006	74 56		        mov     a,#56h              ; Ok, now write to R1 with reg addressing...
11311  
-10029:	  2008	F6		        mov     @r0,a               ; ...and check by reading in indirect.
11312  
-10030:	  2009	B9 56 15	        cjne    r1,#56h,tu_a0
11313  
-10031:
11314  
-10032:	  200C	E8		        mov     a,r0                ; Set R0 to point to R7 in selected bank
11315  
-10033:	  200D	24 06		        add     a,#06h
11316  
-10034:	  200F	F8		        mov     r0,a
11317  
-10035:	  2010	E6		        mov     a,@r0               ; Check R7
11318  
-10036:	  2011	B4 34 0D	        cjne    a,#34h,tu_a0
11319  
-10037:
11320  
-10038:	  2014	74 78		        mov     a,#78h              ; Ok, now write to R7 with reg addressing...
11321  
-10039:	  2016	F6		        mov     @r0,a               ; ...and check by reading in indirect.
11322  
-10040:	  2017	B4 78 07	        cjne    a,#78h,tu_a0
11323  
-10041:
11324  
-10042:	  201A	22		        ret
11325  
-10043:
11326  
-10044:	  201B			tu_a_done:
11327  
-10045:	  201B	00		        nop
11328  
-10046:				        eot     'a',tu_a0
11329  
-10047+ 1			        putc    #'a'
11330  
-10048+ 2  201C			??0865:
11331  
-10049+ 2			        ;jnb     SCON.1,putc_loop
11332  
-10050+ 2			        ;clr     SCON.1
11333  
-10051+ 2  201C	75 99 61	        mov     SBUF,#'a'
11334  
-10052+ 1  201F	80 06		        sjmp    ??0864
11335  
-10053+ 1  2021			tu_a0:  putc    #'?'
11336  
-10054+ 2  2021			??0866:
11337  
-10055+ 2			        ;jnb     SCON.1,putc_loop
11338  
-10056+ 2			        ;clr     SCON.1
11339  
-10057+ 2  2021	75 99 3F	        mov     SBUF,#'?'
11340  
-10058+ 1  2024	75 6E 01	        mov     fail,#001h
  11296
+10014:
  11297
+10015:
  11298
+10016:				        ;-- Test series U ------------------------------------------------------
  11299
+10017:				        ; Register banks
  11300
+10018:				        ; a.- Write to register, read from indirect address.
  11301
+10019:				        ; a.- Write to indirect address, read from register.
  11302
+10020:				        ;
  11303
+10021:
  11304
+10022:				        putc    #'U'                ; start of test series
  11305
+10023+ 1  1FEF			??0866:
  11306
+10024+ 1			        ;jnb     SCON.1,putc_loop
  11307
+10025+ 1			        ;clr     SCON.1
  11308
+10026+ 1  1FEF	75 99 55	        mov     SBUF,#'U'
  11309
+10027:
  11310
+10028:
  11311
+10029:	  1FF2	75 D0 00	        mov     PSW,#00h            ; Test bank 0
  11312
+10030:	  1FF5	74 01		        mov     a,#00h + 1
  11313
+10031:	  1FF7	12 20 14	        call    tu_a_test
  11314
+10032:
  11315
+10033:	  1FFA	75 D0 08	        mov     PSW,#08h            ; Test bank 1
  11316
+10034:	  1FFD	74 09		        mov     a,#08h + 1
  11317
+10035:	  1FFF	12 20 14	        call    tu_a_test
  11318
+10036:
  11319
+10037:	  2002	75 D0 10	        mov     PSW,#10h            ; Test bank 2
  11320
+10038:	  2005	74 11		        mov     a,#10h + 1
  11321
+10039:	  2007	12 20 14	        call    tu_a_test
  11322
+10040:
  11323
+10041:	  200A	75 D0 18	        mov     PSW,#18h            ; Test bank 3
  11324
+10042:	  200D	74 19		        mov     a,#18h + 1
  11325
+10043:	  200F	12 20 14	        call    tu_a_test
  11326
+10044:
  11327
+10045:	  2012	80 1E		        sjmp    tu_a_done
  11328
+10046:
  11329
+10047:	  2014			tu_a_test:
  11330
+10048:	  2014	F8		        mov     r0,a                ; R0 points to R1 in the selected bank.
  11331
+10049:
  11332
+10050:	  2015	79 12		        mov     r1,#12h             ; Write to registers R1 and R7
  11333
+10051:	  2017	7F 34		        mov     r7,#34h
  11334
+10052:
  11335
+10053:	  2019	E6		        mov     a,@r0               ; Check R1
  11336
+10054:	  201A	B4 12 1B	        cjne    a,#12h,tu_a0
  11337
+10055:	  201D	74 56		        mov     a,#56h              ; Ok, now write to R1 with reg addressing...
  11338
+10056:	  201F	F6		        mov     @r0,a               ; ...and check by reading in indirect.
  11339
+10057:	  2020	B9 56 15	        cjne    r1,#56h,tu_a0
  11340
+10058:
11341 11341
 
11342 11342
 ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. Heinz                                        PAGE 181
11343 11343
 
@@ -11345,62 +11345,62 @@ ASEM-51 V1.3                                        Copyright (c) 2002 by W.W. H
11345 11345