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fix last bit in write mode

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1 parent 4fc1da2 commit 1cfa8e22ff649c9a65672b01ed8f62c13c209027 jctemkin committed
Showing with 46,809 additions and 45 deletions.
  1. +0 −3 _xmsgs/pn_parser.xmsgs
  2. +24 −0 fuse.log
  3. +12 −0 fuse.xmsgs
  4. +1 −0 fuseRelaunch.cmd
  5. +4 −4 iseconfig/quad_fpga.projectmgr
  6. +2 −0 isim.cmd
  7. +20 −0 isim.log
  8. +16 −0 isim/isim_usage_statistics.html
  9. 0 isim/lockfile
  10. +1 −0 isim/pn_info
  11. +34,667 −0 isim/precompiled.exe.sim/ieee/p_1242562249.c
  12. BIN isim/precompiled.exe.sim/ieee/p_1242562249.didat
  13. BIN isim/precompiled.exe.sim/ieee/p_1242562249.lin64.o
  14. +8,819 −0 isim/precompiled.exe.sim/ieee/p_2592010699.c
  15. BIN isim/precompiled.exe.sim/ieee/p_2592010699.didat
  16. BIN isim/precompiled.exe.sim/ieee/p_2592010699.lin64.o
  17. BIN isim/spi_tb_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
  18. 0 isim/spi_tb_isim_beh.exe.sim/isimcrash.log
  19. +29 −0 isim/spi_tb_isim_beh.exe.sim/isimkernel.log
  20. BIN isim/spi_tb_isim_beh.exe.sim/netId.dat
  21. BIN isim/spi_tb_isim_beh.exe.sim/spi_tb_isim_beh.exe
  22. BIN isim/spi_tb_isim_beh.exe.sim/tmp_save/_1
  23. +1,921 −0 isim/spi_tb_isim_beh.exe.sim/work/a_1797001535_2372691052.c
  24. BIN isim/spi_tb_isim_beh.exe.sim/work/a_1797001535_2372691052.didat
  25. BIN isim/spi_tb_isim_beh.exe.sim/work/a_1797001535_2372691052.lin64.o
  26. +993 −0 isim/spi_tb_isim_beh.exe.sim/work/a_3415757621_3212880686.c
  27. BIN isim/spi_tb_isim_beh.exe.sim/work/a_3415757621_3212880686.didat
  28. BIN isim/spi_tb_isim_beh.exe.sim/work/a_3415757621_3212880686.lin64.o
  29. +43 −0 isim/spi_tb_isim_beh.exe.sim/work/spi_tb_isim_beh.exe_main.c
  30. BIN isim/spi_tb_isim_beh.exe.sim/work/spi_tb_isim_beh.exe_main.lin64.o
  31. BIN isim/work/spi_module.vdb
  32. BIN isim/work/spi_tb.vdb
  33. +1 −0 pepExtractor.prj
  34. +66 −2 quad_fpga.gise
  35. +8 −7 quad_fpga.xise
  36. +106 −0 sdfs.wcfg
  37. +20 −8 spi_module.vhd
  38. BIN spi_module_isim_beh.exe
  39. +1 −0 spi_module_stx_beh.prj
  40. +52 −21 spi_tb.vhd
  41. +2 −0 spi_tb_beh.prj
  42. BIN spi_tb_isim_beh.exe
  43. BIN spi_tb_isim_beh.wdb
  44. BIN spi_tb_isim_beh1.wdb
  45. +1 −0 xilinxsim.ini
View
3 _xmsgs/pn_parser.xmsgs
@@ -8,9 +8,6 @@
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<messages>
-<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/jenn/quad/quad_fpga/pcm_gen.vhd&quot; into library work</arg>
-</msg>
-
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/jenn/quad/quad_fpga/spi_module.vhd&quot; into library work</arg>
</msg>
View
24 fuse.log
@@ -0,0 +1,24 @@
+Running: /opt/Xilinx/13.2/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/jenn/quad/quad_fpga/spi_tb_isim_beh.exe -prj /home/jenn/quad/quad_fpga/spi_tb_beh.prj work.spi_tb
+ISim O.61xd (signature 0xb4d1ced7)
+Number of CPUs detected in this system: 4
+Turning on mult-threading, number of parallel sub-compilation jobs: 8
+Determining compilation order of HDL files
+Parsing VHDL file "/home/jenn/quad/quad_fpga/spi_module.vhd" into library work
+Parsing VHDL file "/home/jenn/quad/quad_fpga/spi_tb.vhd" into library work
+Starting static elaboration
+WARNING:HDLCompiler:960 - "/home/jenn/quad/quad_fpga/spi_module.vhd" Line 73: Expression has incompatible type
+Completed static elaboration
+Fuse Memory Usage: 73808 KB
+Fuse CPU Usage: 80 ms
+Compiling package standard
+Compiling package std_logic_1164
+Compiling package numeric_std
+Compiling architecture behavioral of entity spi_module [spi_module_default]
+Compiling architecture behavior of entity spi_tb
+Time Resolution for simulation is 1ps.
+Waiting for 1 sub-compilation(s) to finish...
+Compiled 6 VHDL Units
+Built simulation executable /home/jenn/quad/quad_fpga/spi_tb_isim_beh.exe
+Fuse Memory Usage: 645636 KB
+Fuse CPU Usage: 190 ms
+GCC CPU Usage: 380 ms
View
12 fuse.xmsgs
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="HDLCompiler" num="960" delta="unknown" >"/home/jenn/quad/quad_fpga/spi_module.vhd" Line 73: Expression has incompatible type
+</msg>
+
+</messages>
+
View
1 fuseRelaunch.cmd
@@ -0,0 +1 @@
+-intstyle "ise" -incremental -lib "secureip" -o "/home/jenn/quad/quad_fpga/spi_tb_isim_beh.exe" -prj "/home/jenn/quad/quad_fpga/spi_tb_beh.prj" "work.spi_tb"
View
8 iseconfig/quad_fpga.projectmgr
@@ -92,13 +92,13 @@
<ClosedNodesVersion>2</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
- <SelectedItem>uut - spi_module - Behavioral (/home/jenn/quad/quad_fpga/spi_module.vhd)</SelectedItem>
+ <SelectedItem>spi_tb - behavior (/home/jenn/quad/quad_fpga/spi_tb.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000185000000020000000000000000000000000200000064ffffffff000000810000000300000002000001850000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
- <CurrentItem>uut - spi_module - Behavioral (/home/jenn/quad/quad_fpga/spi_module.vhd)</CurrentItem>
+ <CurrentItem>spi_tb - behavior (/home/jenn/quad/quad_fpga/spi_tb.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
<ClosedNodes>
@@ -119,12 +119,12 @@
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
- <SelectedItem>Behavioral Check Syntax</SelectedItem>
+ <SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000111000000010000000100000000000000000000000064ffffffff000000810000000000000001000001110000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
- <CurrentItem>Behavioral Check Syntax</CurrentItem>
+ <CurrentItem></CurrentItem>
</ItemView>
</Project>
View
2 isim.cmd
@@ -0,0 +1,2 @@
+onerror {resume}
+run 5us;
View
20 isim.log
@@ -0,0 +1,20 @@
+ISim log file
+Running: /home/jenn/quad/quad_fpga/spi_tb_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -view /home/jenn/quad/quad_fpga/sdfs.wcfg -wdb /home/jenn/quad/quad_fpga/spi_tb_isim_beh.wdb
+ISim O.61xd (signature 0xb4d1ced7)
+WARNING: A WEBPACK license was found.
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
+This is a Lite version of ISim.
+Time resolution is 1 ps
+# onerror resume
+# run 5us
+Simulator is doing circuit initialization process.
+at 0 ps, Instance /spi_tb/uut/ : Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+at 0 ps, Instance /spi_tb/uut/ : Warning: NUMERIC_STD.">": metavalue detected, returning FALSE
+at 0 ps, Instance /spi_tb/uut/ : Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+at 0 ps, Instance /spi_tb/uut/ : Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+Finished circuit initialization process.
+at 100 ns(1), Instance /spi_tb/uut/ : Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+at 100 ns(1), Instance /spi_tb/uut/ : Warning: NUMERIC_STD.">": metavalue detected, returning FALSE
+at 100 ns(1), Instance /spi_tb/uut/ : Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# exit 0
View
16 isim/isim_usage_statistics.html
@@ -0,0 +1,16 @@
+<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<xtag-section name="ISimStatistics">
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
+<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
+<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>190 ms, 645636 KB</xtag-isim-property-value></TD></TR>
+
+<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>35</xtag-isim-property-value></TD></TR>
+<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>81</xtag-isim-property-value></TD></TR>
+<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>4</xtag-isim-property-value></TD></TR>
+<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>13</xtag-isim-property-value></TD></TR>
+<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>5 us</xtag-isim-property-value></TD></TR>
+<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.08 sec, 232558 KB</xtag-isim-property-value></TD></TR>
+<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
+<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
+</xtag-section>
+</TABLE>
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0 isim/lockfile
No changes.
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1 isim/pn_info
@@ -0,0 +1 @@
+13.2
View
34,667 isim/precompiled.exe.sim/ieee/p_1242562249.c
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BIN isim/precompiled.exe.sim/ieee/p_1242562249.didat
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BIN isim/precompiled.exe.sim/ieee/p_1242562249.lin64.o
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8,819 isim/precompiled.exe.sim/ieee/p_2592010699.c
8,819 additions, 0 deletions not shown because the diff is too large. Please use a local Git client to view these changes.
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BIN isim/precompiled.exe.sim/ieee/p_2592010699.didat
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BIN isim/precompiled.exe.sim/ieee/p_2592010699.lin64.o
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BIN isim/spi_tb_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
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0 isim/spi_tb_isim_beh.exe.sim/isimcrash.log
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29 isim/spi_tb_isim_beh.exe.sim/isimkernel.log
@@ -0,0 +1,29 @@
+Command line:
+ spi_tb_isim_beh.exe
+ -simmode gui
+ -simrunnum 0
+ -socket 39602
+
+Thu Oct 11 00:36:05 2012
+
+
+ Elaboration Time: 0.01 sec
+
+ Current Memory Usage: 158.11 Meg
+
+ Total Signals : 35
+ Total Nets : 81
+ Total Signal Drivers : 23
+ Total Blocks : 4
+ Total Primitive Blocks : 3
+ Total Processes : 13
+ Total Traceable Variables : 15
+ Total Scalar Nets and Variables : 566
+Total Line Count : 81
+
+ Total Simulation Time: 0.08 sec
+
+ Current Memory Usage: 233.611 Meg
+
+Thu Oct 11 00:37:35 2012
+
View
BIN isim/spi_tb_isim_beh.exe.sim/netId.dat
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BIN isim/spi_tb_isim_beh.exe.sim/spi_tb_isim_beh.exe
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BIN isim/spi_tb_isim_beh.exe.sim/tmp_save/_1
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1,921 isim/spi_tb_isim_beh.exe.sim/work/a_1797001535_2372691052.c
1,921 additions, 0 deletions not shown because the diff is too large. Please use a local Git client to view these changes.
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BIN isim/spi_tb_isim_beh.exe.sim/work/a_1797001535_2372691052.didat
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BIN isim/spi_tb_isim_beh.exe.sim/work/a_1797001535_2372691052.lin64.o
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993 isim/spi_tb_isim_beh.exe.sim/work/a_3415757621_3212880686.c
@@ -0,0 +1,993 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/***********************************************************************/
+
+/* This file is designed for use with ISim build 0xb4d1ced7 */
+
+#define XSI_HIDE_SYMBOL_SPEC true
+#include "xsi.h"
+#include <memory.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+static const char *ng0 = "/home/jenn/quad/quad_fpga/spi_module.vhd";
+extern char *IEEE_P_2592010699;
+extern char *IEEE_P_1242562249;
+
+char *ieee_p_1242562249_sub_1006216973935652998_1035706684(char *, char *, char *, char *, int );
+unsigned char ieee_p_1242562249_sub_3307759752501467860_1035706684(char *, char *, char *, int );
+unsigned char ieee_p_1242562249_sub_3307759752501503797_1035706684(char *, char *, char *, int );
+unsigned char ieee_p_1242562249_sub_3307759752501539734_1035706684(char *, char *, char *, int );
+unsigned char ieee_p_2592010699_sub_13554554585326073636_503743352(char *, char *, unsigned int , unsigned int );
+unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int );
+unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
+unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
+
+
+static void work_a_3415757621_3212880686_p_0(char *t0)
+{
+ char t17[16];
+ char t19[16];
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ unsigned char t4;
+ unsigned char t5;
+ char *t6;
+ char *t7;
+ unsigned char t8;
+ unsigned char t9;
+ char *t10;
+ unsigned int t11;
+ unsigned int t12;
+ unsigned int t13;
+ char *t14;
+ char *t15;
+ unsigned char t16;
+ char *t18;
+ char *t20;
+ char *t21;
+ int t22;
+ unsigned int t23;
+ unsigned char t24;
+ char *t25;
+ char *t26;
+ char *t27;
+ char *t28;
+
+LAB0: xsi_set_current_line(52, ng0);
+ t1 = (t0 + 1192U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t4 = (t3 == (unsigned char)2);
+ if (t4 != 0)
+ goto LAB2;
+
+LAB4: xsi_set_current_line(87, ng0);
+ t1 = xsi_get_transient_memory(8U);
+ memset(t1, 0, 8U);
+ t2 = t1;
+ memset(t2, (unsigned char)2, 8U);
+ t6 = (t0 + 9160);
+ t7 = (t6 + 56U);
+ t10 = *((char **)t7);
+ t14 = (t10 + 56U);
+ t15 = *((char **)t14);
+ memcpy(t15, t1, 8U);
+ xsi_driver_first_trans_fast(t6);
+ xsi_set_current_line(88, ng0);
+ t1 = (t0 + 9096);
+ t2 = (t1 + 56U);
+ t6 = *((char **)t2);
+ t7 = (t6 + 56U);
+ t10 = *((char **)t7);
+ *((unsigned char *)t10) = (unsigned char)2;
+ xsi_driver_first_trans_fast(t1);
+ xsi_set_current_line(89, ng0);
+ t1 = xsi_get_transient_memory(8U);
+ memset(t1, 0, 8U);
+ t2 = t1;
+ memset(t2, (unsigned char)2, 8U);
+ t6 = (t0 + 8904);
+ t7 = (t6 + 56U);
+ t10 = *((char **)t7);
+ t14 = (t10 + 56U);
+ t15 = *((char **)t14);
+ memcpy(t15, t1, 8U);
+ xsi_driver_first_trans_fast(t6);
+ xsi_set_current_line(90, ng0);
+ t1 = xsi_get_transient_memory(8U);
+ memset(t1, 0, 8U);
+ t2 = t1;
+ memset(t2, (unsigned char)2, 8U);
+ t6 = (t0 + 9288);
+ t7 = (t6 + 56U);
+ t10 = *((char **)t7);
+ t14 = (t10 + 56U);
+ t15 = *((char **)t14);
+ memcpy(t15, t1, 8U);
+ xsi_driver_first_trans_fast(t6);
+ xsi_set_current_line(91, ng0);
+ t1 = (t0 + 8968);
+ t2 = (t1 + 56U);
+ t6 = *((char **)t2);
+ t7 = (t6 + 56U);
+ t10 = *((char **)t7);
+ *((unsigned char *)t10) = (unsigned char)2;
+ xsi_driver_first_trans_fast(t1);
+
+LAB3: t1 = (t0 + 8664);
+ *((int *)t1) = 1;
+
+LAB1: return;
+LAB2: xsi_set_current_line(53, ng0);
+ t1 = (t0 + 992U);
+ t5 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t1, 0U, 0U);
+ if (t5 != 0)
+ goto LAB5;
+
+LAB7:
+LAB6: xsi_set_current_line(70, ng0);
+ t1 = (t0 + 992U);
+ t3 = ieee_p_2592010699_sub_13554554585326073636_503743352(IEEE_P_2592010699, t1, 0U, 0U);
+ if (t3 != 0)
+ goto LAB33;
+
+LAB35:
+LAB34: goto LAB3;
+
+LAB5: xsi_set_current_line(55, ng0);
+ t6 = (t0 + 2952U);
+ t7 = *((char **)t6);
+ t8 = *((unsigned char *)t7);
+ t9 = (t8 == (unsigned char)3);
+ if (t9 != 0)
+ goto LAB8;
+
+LAB10:
+LAB9: xsi_set_current_line(59, ng0);
+ t1 = (t0 + 3912U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 13371);
+ t4 = 1;
+ if (8U == 8U)
+ goto LAB19;
+
+LAB20: t4 = 0;
+
+LAB21: if (t4 == 1)
+ goto LAB16;
+
+LAB17: t3 = (unsigned char)0;
+
+LAB18: if (t3 != 0)
+ goto LAB13;
+
+LAB15: t1 = (t0 + 3912U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 13379);
+ t3 = 1;
+ if (8U == 8U)
+ goto LAB27;
+
+LAB28: t3 = 0;
+
+LAB29: if (t3 != 0)
+ goto LAB25;
+
+LAB26:
+LAB14: xsi_set_current_line(66, ng0);
+ t1 = (t0 + 3912U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 13272U);
+ t6 = ieee_p_1242562249_sub_1006216973935652998_1035706684(IEEE_P_1242562249, t17, t2, t1, 1);
+ t7 = (t0 + 9160);
+ t10 = (t7 + 56U);
+ t14 = *((char **)t10);
+ t15 = (t14 + 56U);
+ t18 = *((char **)t15);
+ memcpy(t18, t6, 8U);
+ xsi_driver_first_trans_fast(t7);
+ goto LAB6;
+
+LAB8: xsi_set_current_line(56, ng0);
+ t6 = (t0 + 3592U);
+ t10 = *((char **)t6);
+ t11 = (7 - 6);
+ t12 = (t11 * 1U);
+ t13 = (0 + t12);
+ t6 = (t10 + t13);
+ t14 = (t0 + 1352U);
+ t15 = *((char **)t14);
+ t16 = *((unsigned char *)t15);
+ t18 = ((IEEE_P_2592010699) + 4000);
+ t20 = (t19 + 0U);
+ t21 = (t20 + 0U);
+ *((int *)t21) = 6;
+ t21 = (t20 + 4U);
+ *((int *)t21) = 0;
+ t21 = (t20 + 8U);
+ *((int *)t21) = -1;
+ t22 = (0 - 6);
+ t23 = (t22 * -1);
+ t23 = (t23 + 1);
+ t21 = (t20 + 12U);
+ *((unsigned int *)t21) = t23;
+ t14 = xsi_base_array_concat(t14, t17, t18, (char)97, t6, t19, (char)99, t16, (char)101);
+ t23 = (7U + 1U);
+ t24 = (8U != t23);
+ if (t24 == 1)
+ goto LAB11;
+
+LAB12: t21 = (t0 + 8904);
+ t25 = (t21 + 56U);
+ t26 = *((char **)t25);
+ t27 = (t26 + 56U);
+ t28 = *((char **)t27);
+ memcpy(t28, t14, 8U);
+ xsi_driver_first_trans_fast(t21);
+ goto LAB9;
+
+LAB11: xsi_size_not_matching(8U, t23, 0);
+ goto LAB12;
+
+LAB13: xsi_set_current_line(60, ng0);
+ t14 = (t0 + 4232U);
+ t18 = *((char **)t14);
+ t9 = *((unsigned char *)t18);
+ t16 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t9);
+ t14 = (t0 + 8968);
+ t20 = (t14 + 56U);
+ t21 = *((char **)t20);
+ t25 = (t21 + 56U);
+ t26 = *((char **)t25);
+ *((unsigned char *)t26) = t16;
+ xsi_driver_first_trans_fast(t14);
+ xsi_set_current_line(61, ng0);
+ t1 = (t0 + 3592U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 9032);
+ t6 = (t1 + 56U);
+ t7 = *((char **)t6);
+ t10 = (t7 + 56U);
+ t14 = *((char **)t10);
+ memcpy(t14, t2, 8U);
+ xsi_driver_first_trans_fast(t1);
+ goto LAB14;
+
+LAB16: t14 = (t0 + 4712U);
+ t15 = *((char **)t14);
+ t5 = *((unsigned char *)t15);
+ t8 = (t5 == (unsigned char)3);
+ t3 = t8;
+ goto LAB18;
+
+LAB19: t11 = 0;
+
+LAB22: if (t11 < 8U)
+ goto LAB23;
+ else
+ goto LAB21;
+
+LAB23: t7 = (t2 + t11);
+ t10 = (t1 + t11);
+ if (*((unsigned char *)t7) != *((unsigned char *)t10))
+ goto LAB20;
+
+LAB24: t11 = (t11 + 1);
+ goto LAB22;
+
+LAB25: xsi_set_current_line(63, ng0);
+ t14 = (t0 + 3592U);
+ t15 = *((char **)t14);
+ t22 = (6 - 7);
+ t12 = (t22 * -1);
+ t13 = (1U * t12);
+ t23 = (0 + t13);
+ t14 = (t15 + t23);
+ t4 = *((unsigned char *)t14);
+ t5 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t4);
+ t18 = (t0 + 9096);
+ t20 = (t18 + 56U);
+ t21 = *((char **)t20);
+ t25 = (t21 + 56U);
+ t26 = *((char **)t25);
+ *((unsigned char *)t26) = t5;
+ xsi_driver_first_trans_fast(t18);
+ goto LAB14;
+
+LAB27: t11 = 0;
+
+LAB30: if (t11 < 8U)
+ goto LAB31;
+ else
+ goto LAB29;
+
+LAB31: t7 = (t2 + t11);
+ t10 = (t1 + t11);
+ if (*((unsigned char *)t7) != *((unsigned char *)t10))
+ goto LAB28;
+
+LAB32: t11 = (t11 + 1);
+ goto LAB30;
+
+LAB33: xsi_set_current_line(72, ng0);
+ t2 = (t0 + 2792U);
+ t6 = *((char **)t2);
+ t4 = *((unsigned char *)t6);
+ t5 = (t4 == (unsigned char)3);
+ if (t5 != 0)
+ goto LAB36;
+
+LAB38:
+LAB37: xsi_set_current_line(76, ng0);
+ t1 = (t0 + 3112U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t4 = (t3 == (unsigned char)3);
+ if (t4 != 0)
+ goto LAB39;
+
+LAB41:
+LAB40: xsi_set_current_line(80, ng0);
+ t1 = (t0 + 3272U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t4 = (t3 == (unsigned char)3);
+ if (t4 != 0)
+ goto LAB44;
+
+LAB46:
+LAB45: goto LAB34;
+
+LAB36: xsi_set_current_line(73, ng0);
+ t2 = (t0 + 3592U);
+ t7 = *((char **)t2);
+ t2 = (t0 + 9224);
+ t10 = (t2 + 56U);
+ t14 = *((char **)t10);
+ t15 = (t14 + 56U);
+ t18 = *((char **)t15);
+ memcpy(t18, t7, 6U);
+ xsi_driver_first_trans_fast(t2);
+ goto LAB37;
+
+LAB39: xsi_set_current_line(77, ng0);
+ t1 = (t0 + 3752U);
+ t6 = *((char **)t1);
+ t11 = (7 - 6);
+ t12 = (t11 * 1U);
+ t13 = (0 + t12);
+ t1 = (t6 + t13);
+ t10 = ((IEEE_P_2592010699) + 4000);
+ t14 = (t19 + 0U);
+ t15 = (t14 + 0U);
+ *((int *)t15) = 6;
+ t15 = (t14 + 4U);
+ *((int *)t15) = 0;
+ t15 = (t14 + 8U);
+ *((int *)t15) = -1;
+ t22 = (0 - 6);
+ t23 = (t22 * -1);
+ t23 = (t23 + 1);
+ t15 = (t14 + 12U);
+ *((unsigned int *)t15) = t23;
+ t7 = xsi_base_array_concat(t7, t17, t10, (char)97, t1, t19, (char)99, (unsigned char)2, (char)101);
+ t23 = (7U + 1U);
+ t5 = (8U != t23);
+ if (t5 == 1)
+ goto LAB42;
+
+LAB43: t15 = (t0 + 9288);
+ t18 = (t15 + 56U);
+ t20 = *((char **)t18);
+ t21 = (t20 + 56U);
+ t25 = *((char **)t21);
+ memcpy(t25, t7, 8U);
+ xsi_driver_first_trans_fast(t15);
+ goto LAB40;
+
+LAB42: xsi_size_not_matching(8U, t23, 0);
+ goto LAB43;
+
+LAB44: xsi_set_current_line(81, ng0);
+ t1 = (t0 + 2152U);
+ t6 = *((char **)t1);
+ t1 = (t0 + 9288);
+ t7 = (t1 + 56U);
+ t10 = *((char **)t7);
+ t14 = (t10 + 56U);
+ t15 = *((char **)t14);
+ memcpy(t15, t6, 8U);
+ xsi_driver_first_trans_fast(t1);
+ goto LAB45;
+
+}
+
+static void work_a_3415757621_3212880686_p_1(char *t0)
+{
+ char *t1;
+ unsigned char t2;
+ char *t3;
+ char *t4;
+ unsigned char t5;
+ char *t6;
+ char *t7;
+ char *t8;
+ char *t9;
+
+LAB0: xsi_set_current_line(100, ng0);
+ t1 = (t0 + 1792U);
+ t2 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t1, 0U, 0U);
+ if (t2 != 0)
+ goto LAB2;
+
+LAB4:
+LAB3: t1 = (t0 + 8680);
+ *((int *)t1) = 1;
+
+LAB1: return;
+LAB2: xsi_set_current_line(101, ng0);
+ t3 = (t0 + 4392U);
+ t4 = *((char **)t3);
+ t5 = *((unsigned char *)t4);
+ t3 = (t0 + 9352);
+ t6 = (t3 + 56U);
+ t7 = *((char **)t6);
+ t8 = (t7 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = t5;
+ xsi_driver_first_trans_fast(t3);
+ xsi_set_current_line(102, ng0);
+ t1 = (t0 + 4232U);
+ t3 = *((char **)t1);
+ t2 = *((unsigned char *)t3);
+ t1 = (t0 + 9416);
+ t4 = (t1 + 56U);
+ t6 = *((char **)t4);
+ t7 = (t6 + 56U);
+ t8 = *((char **)t7);
+ *((unsigned char *)t8) = t2;
+ xsi_driver_first_trans_fast(t1);
+ goto LAB3;
+
+}
+
+static void work_a_3415757621_3212880686_p_2(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ unsigned char t5;
+ unsigned char t6;
+ unsigned char t7;
+ char *t8;
+ char *t9;
+ char *t10;
+ char *t11;
+ char *t12;
+
+LAB0: xsi_set_current_line(106, ng0);
+
+LAB3: t1 = (t0 + 4552U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 4392U);
+ t4 = *((char **)t1);
+ t5 = *((unsigned char *)t4);
+ t6 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t5);
+ t7 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t3, t6);
+ t1 = (t0 + 9480);
+ t8 = (t1 + 56U);
+ t9 = *((char **)t8);
+ t10 = (t9 + 56U);
+ t11 = *((char **)t10);
+ *((unsigned char *)t11) = t7;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t12 = (t0 + 8696);
+ *((int *)t12) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void work_a_3415757621_3212880686_p_3(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ unsigned char t6;
+ unsigned char t7;
+ char *t8;
+ unsigned char t9;
+ unsigned char t10;
+ unsigned char t11;
+ char *t12;
+ char *t13;
+ char *t14;
+ char *t15;
+ char *t16;
+ char *t17;
+ char *t18;
+ char *t19;
+ char *t20;
+ char *t21;
+
+LAB0: xsi_set_current_line(114, ng0);
+ t1 = (t0 + 3912U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 13272U);
+ t3 = ieee_p_1242562249_sub_3307759752501503797_1035706684(IEEE_P_1242562249, t2, t1, 8);
+ if (t3 != 0)
+ goto LAB3;
+
+LAB4:
+LAB5: t16 = (t0 + 9544);
+ t17 = (t16 + 56U);
+ t18 = *((char **)t17);
+ t19 = (t18 + 56U);
+ t20 = *((char **)t19);
+ *((unsigned char *)t20) = (unsigned char)2;
+ xsi_driver_first_trans_fast(t16);
+
+LAB2: t21 = (t0 + 8712);
+ *((int *)t21) = 1;
+
+LAB1: return;
+LAB3: t4 = (t0 + 1192U);
+ t5 = *((char **)t4);
+ t6 = *((unsigned char *)t5);
+ t7 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t6);
+ t4 = (t0 + 4712U);
+ t8 = *((char **)t4);
+ t9 = *((unsigned char *)t8);
+ t10 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t9);
+ t11 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t7, t10);
+ t4 = (t0 + 9544);
+ t12 = (t4 + 56U);
+ t13 = *((char **)t12);
+ t14 = (t13 + 56U);
+ t15 = *((char **)t14);
+ *((unsigned char *)t15) = t11;
+ xsi_driver_first_trans_fast(t4);
+ goto LAB2;
+
+LAB6: goto LAB2;
+
+}
+
+static void work_a_3415757621_3212880686_p_4(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ unsigned char t6;
+ unsigned char t7;
+ char *t8;
+ unsigned char t9;
+ unsigned char t10;
+ unsigned char t11;
+ char *t12;
+ char *t13;
+ char *t14;
+ char *t15;
+ char *t16;
+ char *t17;
+ char *t18;
+ char *t19;
+ char *t20;
+ char *t21;
+
+LAB0: xsi_set_current_line(117, ng0);
+ t1 = (t0 + 3912U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 13272U);
+ t3 = ieee_p_1242562249_sub_3307759752501539734_1035706684(IEEE_P_1242562249, t2, t1, 8);
+ if (t3 != 0)
+ goto LAB3;
+
+LAB4:
+LAB5: t16 = (t0 + 9608);
+ t17 = (t16 + 56U);
+ t18 = *((char **)t17);
+ t19 = (t18 + 56U);
+ t20 = *((char **)t19);
+ *((unsigned char *)t20) = (unsigned char)2;
+ xsi_driver_first_trans_fast(t16);
+
+LAB2: t21 = (t0 + 8728);
+ *((int *)t21) = 1;
+
+LAB1: return;
+LAB3: t4 = (t0 + 1192U);
+ t5 = *((char **)t4);
+ t6 = *((unsigned char *)t5);
+ t7 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t6);
+ t4 = (t0 + 4712U);
+ t8 = *((char **)t4);
+ t9 = *((unsigned char *)t8);
+ t10 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t9);
+ t11 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t7, t10);
+ t4 = (t0 + 9608);
+ t12 = (t4 + 56U);
+ t13 = *((char **)t12);
+ t14 = (t13 + 56U);
+ t15 = *((char **)t14);
+ *((unsigned char *)t15) = t11;
+ xsi_driver_first_trans_fast(t4);
+ goto LAB2;
+
+LAB6: goto LAB2;
+
+}
+
+static void work_a_3415757621_3212880686_p_5(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ unsigned char t6;
+ unsigned char t7;
+ char *t8;
+ char *t9;
+ char *t10;
+ char *t11;
+ char *t12;
+ char *t13;
+ unsigned char t14;
+ char *t15;
+ char *t16;
+ char *t17;
+ char *t18;
+ char *t19;
+
+LAB0: xsi_set_current_line(118, ng0);
+ t1 = (t0 + 3912U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 13272U);
+ t3 = ieee_p_1242562249_sub_3307759752501467860_1035706684(IEEE_P_1242562249, t2, t1, 8);
+ if (t3 != 0)
+ goto LAB3;
+
+LAB4:
+LAB5: t12 = (t0 + 4712U);
+ t13 = *((char **)t12);
+ t14 = *((unsigned char *)t13);
+ t12 = (t0 + 9672);
+ t15 = (t12 + 56U);
+ t16 = *((char **)t15);
+ t17 = (t16 + 56U);
+ t18 = *((char **)t17);
+ *((unsigned char *)t18) = t14;
+ xsi_driver_first_trans_fast(t12);
+
+LAB2: t19 = (t0 + 8744);
+ *((int *)t19) = 1;
+
+LAB1: return;
+LAB3: t4 = (t0 + 1192U);
+ t5 = *((char **)t4);
+ t6 = *((unsigned char *)t5);
+ t7 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t6);
+ t4 = (t0 + 9672);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ t10 = (t9 + 56U);
+ t11 = *((char **)t10);
+ *((unsigned char *)t11) = t7;
+ xsi_driver_first_trans_fast(t4);
+ goto LAB2;
+
+LAB6: goto LAB2;
+
+}
+
+static void work_a_3415757621_3212880686_p_6(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ int t6;
+ unsigned int t7;
+ unsigned int t8;
+ unsigned int t9;
+ unsigned char t10;
+ unsigned char t11;
+ char *t12;
+ char *t13;
+ char *t14;
+ char *t15;
+ char *t16;
+ char *t17;
+ char *t18;
+ char *t19;
+ char *t20;
+ char *t21;
+ char *t22;
+
+LAB0: xsi_set_current_line(121, ng0);
+ t1 = (t0 + 3912U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 13272U);
+ t3 = ieee_p_1242562249_sub_3307759752501503797_1035706684(IEEE_P_1242562249, t2, t1, 8);
+ if (t3 != 0)
+ goto LAB3;
+
+LAB4:
+LAB5: t17 = (t0 + 9736);
+ t18 = (t17 + 56U);
+ t19 = *((char **)t18);
+ t20 = (t19 + 56U);
+ t21 = *((char **)t20);
+ *((unsigned char *)t21) = (unsigned char)2;
+ xsi_driver_first_trans_fast(t17);
+
+LAB2: t22 = (t0 + 8760);
+ *((int *)t22) = 1;
+
+LAB1: return;
+LAB3: t4 = (t0 + 3592U);
+ t5 = *((char **)t4);
+ t6 = (7 - 7);
+ t7 = (t6 * -1);
+ t8 = (1U * t7);
+ t9 = (0 + t8);
+ t4 = (t5 + t9);
+ t10 = *((unsigned char *)t4);
+ t11 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t10);
+ t12 = (t0 + 9736);
+ t13 = (t12 + 56U);
+ t14 = *((char **)t13);
+ t15 = (t14 + 56U);
+ t16 = *((char **)t15);
+ *((unsigned char *)t16) = t11;
+ xsi_driver_first_trans_fast(t12);
+ goto LAB2;
+
+LAB6: goto LAB2;
+
+}
+
+static void work_a_3415757621_3212880686_p_7(char *t0)
+{
+ unsigned char t1;
+ unsigned char t2;
+ char *t3;
+ char *t4;
+ unsigned char t5;
+ unsigned char t6;
+ unsigned char t7;
+ char *t8;
+ unsigned char t9;
+ unsigned char t10;
+ char *t11;
+ unsigned char t12;
+ unsigned char t13;
+ unsigned char t14;
+ char *t15;
+ unsigned char t16;
+ unsigned char t17;
+ char *t18;
+ char *t19;
+ char *t20;
+ char *t21;
+ char *t22;
+ char *t23;
+ int t24;
+ unsigned int t25;
+ unsigned int t26;
+ unsigned int t27;
+ unsigned char t28;
+ char *t29;
+ char *t30;
+ char *t31;
+ char *t32;
+ char *t33;
+ char *t34;
+
+LAB0: xsi_set_current_line(123, ng0);
+ t3 = (t0 + 3112U);
+ t4 = *((char **)t3);
+ t5 = *((unsigned char *)t4);
+ t6 = (t5 == (unsigned char)3);
+ if (t6 == 1)
+ goto LAB8;
+
+LAB9: t3 = (t0 + 3272U);
+ t8 = *((char **)t3);
+ t9 = *((unsigned char *)t8);
+ t10 = (t9 == (unsigned char)3);
+ if (t10 == 1)
+ goto LAB11;
+
+LAB12: t7 = (unsigned char)0;
+
+LAB13: t2 = t7;
+
+LAB10: t14 = (!(t2));
+ if (t14 == 1)
+ goto LAB5;
+
+LAB6: t3 = (t0 + 4712U);
+ t15 = *((char **)t3);
+ t16 = *((unsigned char *)t15);
+ t17 = (t16 == (unsigned char)3);
+ t1 = t17;
+
+LAB7: if (t1 != 0)
+ goto LAB3;
+
+LAB4:
+LAB14: t22 = (t0 + 3752U);
+ t23 = *((char **)t22);
+ t24 = (7 - 7);
+ t25 = (t24 * -1);
+ t26 = (1U * t25);
+ t27 = (0 + t26);
+ t22 = (t23 + t27);
+ t28 = *((unsigned char *)t22);
+ t29 = (t0 + 9800);
+ t30 = (t29 + 56U);
+ t31 = *((char **)t30);
+ t32 = (t31 + 56U);
+ t33 = *((char **)t32);
+ *((unsigned char *)t33) = t28;
+ xsi_driver_first_trans_fast_port(t29);
+
+LAB2: t34 = (t0 + 8776);
+ *((int *)t34) = 1;
+
+LAB1: return;
+LAB3: t3 = (t0 + 9800);
+ t18 = (t3 + 56U);
+ t19 = *((char **)t18);
+ t20 = (t19 + 56U);
+ t21 = *((char **)t20);
+ *((unsigned char *)t21) = (unsigned char)4;
+ xsi_driver_first_trans_fast_port(t3);
+ goto LAB2;
+
+LAB5: t1 = (unsigned char)1;
+ goto LAB7;
+
+LAB8: t2 = (unsigned char)1;
+ goto LAB10;
+
+LAB11: t3 = (t0 + 1032U);
+ t11 = *((char **)t3);
+ t12 = *((unsigned char *)t11);
+ t13 = (t12 == (unsigned char)2);
+ t7 = t13;
+ goto LAB13;
+
+LAB15: goto LAB2;
+
+}
+
+static void work_a_3415757621_3212880686_p_8(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned int t3;
+ unsigned int t4;
+ unsigned int t5;
+ char *t6;
+ char *t7;
+ char *t8;
+ char *t9;
+ char *t10;
+ char *t11;
+
+LAB0: xsi_set_current_line(126, ng0);
+
+LAB3: t1 = (t0 + 3592U);
+ t2 = *((char **)t1);
+ t3 = (7 - 5);
+ t4 = (t3 * 1U);
+ t5 = (0 + t4);
+ t1 = (t2 + t5);
+ t6 = (t0 + 9864);
+ t7 = (t6 + 56U);
+ t8 = *((char **)t7);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ memcpy(t10, t1, 6U);
+ xsi_driver_first_trans_fast_port(t6);
+
+LAB2: t11 = (t0 + 8792);
+ *((int *)t11) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void work_a_3415757621_3212880686_p_9(char *t0)
+{
+ char *t1;
+ char *t2;
+ char *t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+
+LAB0: xsi_set_current_line(127, ng0);
+
+LAB3: t1 = (t0 + 4072U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 9928);
+ t3 = (t1 + 56U);
+ t4 = *((char **)t3);
+ t5 = (t4 + 56U);
+ t6 = *((char **)t5);
+ memcpy(t6, t2, 8U);
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t7 = (t0 + 8808);
+ *((int *)t7) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void work_a_3415757621_3212880686_p_10(char *t0)
+{
+ char *t1;
+ char *t2;
+ char *t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+
+LAB0: xsi_set_current_line(128, ng0);
+
+LAB3: t1 = (t0 + 3432U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 9992);
+ t3 = (t1 + 56U);
+ t4 = *((char **)t3);
+ t5 = (t4 + 56U);
+ t6 = *((char **)t5);
+ memcpy(t6, t2, 6U);
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t7 = (t0 + 8824);
+ *((int *)t7) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+
+extern void work_a_3415757621_3212880686_init()
+{
+ static char *pe[] = {(void *)work_a_3415757621_3212880686_p_0,(void *)work_a_3415757621_3212880686_p_1,(void *)work_a_3415757621_3212880686_p_2,(void *)work_a_3415757621_3212880686_p_3,(void *)work_a_3415757621_3212880686_p_4,(void *)work_a_3415757621_3212880686_p_5,(void *)work_a_3415757621_3212880686_p_6,(void *)work_a_3415757621_3212880686_p_7,(void *)work_a_3415757621_3212880686_p_8,(void *)work_a_3415757621_3212880686_p_9,(void *)work_a_3415757621_3212880686_p_10};
+ xsi_register_didat("work_a_3415757621_3212880686", "isim/spi_tb_isim_beh.exe.sim/work/a_3415757621_3212880686.didat");
+ xsi_register_executes(pe);
+}
View
BIN isim/spi_tb_isim_beh.exe.sim/work/a_3415757621_3212880686.didat
Binary file not shown.
View
BIN isim/spi_tb_isim_beh.exe.sim/work/a_3415757621_3212880686.lin64.o
Binary file not shown.
View
43 isim/spi_tb_isim_beh.exe.sim/work/spi_tb_isim_beh.exe_main.c
@@ -0,0 +1,43 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/***********************************************************************/
+
+#include "xsi.h"
+
+struct XSI_INFO xsi_info;
+
+char *IEEE_P_2592010699;
+char *STD_STANDARD;
+char *IEEE_P_1242562249;
+
+
+int main(int argc, char **argv)
+{
+ xsi_init_design(argc, argv);
+ xsi_register_info(&xsi_info);
+
+ xsi_register_min_prec_unit(-12);
+ ieee_p_2592010699_init();
+ ieee_p_1242562249_init();
+ work_a_3415757621_3212880686_init();
+ work_a_1797001535_2372691052_init();
+
+
+ xsi_register_tops("work_a_1797001535_2372691052");
+
+ IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
+ xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
+ STD_STANDARD = xsi_get_engine_memory("std_standard");
+ IEEE_P_1242562249 = xsi_get_engine_memory("ieee_p_1242562249");
+
+ return xsi_run_simulation(argc, argv);
+
+}
View
BIN isim/spi_tb_isim_beh.exe.sim/work/spi_tb_isim_beh.exe_main.lin64.o
Binary file not shown.
View
BIN isim/work/spi_module.vdb
Binary file not shown.
View
BIN isim/work/spi_tb.vdb
Binary file not shown.
View
1 pepExtractor.prj
@@ -0,0 +1 @@
+work "spi_module.vhd"
View
68 quad_fpga.gise
@@ -22,19 +22,83 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="quad_fpga.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="spi_module_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="spi_module_stx_beh.prj"/>
- <file xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
+ <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="spi_tb_beh.prj"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="spi_tb_isim_beh.exe"/>
+ <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="spi_tb_isim_beh.wdb"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
- <transform xil_pn:end_ts="1349916826" xil_pn:in_ck="3835236939522292507" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1349916826">
+ <transform xil_pn:end_ts="1349924788" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1349924788">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1349930164" xil_pn:in_ck="3835236939522292507" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1349930164">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="InputChanged"/>
+ <status xil_pn:value="OutputChanged"/>
+ <outfile xil_pn:name="pcm_gen.vhd"/>
+ <outfile xil_pn:name="spi_module.vhd"/>
+ <outfile xil_pn:name="spi_tb.vhd"/>
+ </transform>
+ <transform xil_pn:end_ts="1349924810" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-5581984638585281129" xil_pn:start_ts="1349924810">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1349924810" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="1818631572989642773" xil_pn:start_ts="1349924810">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1349924788" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="3751239105336241745" xil_pn:start_ts="1349924788">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1349930164" xil_pn:in_ck="3835236939522292507" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1349930164">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="InputChanged"/>
+ <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="pcm_gen.vhd"/>
<outfile xil_pn:name="spi_module.vhd"/>
<outfile xil_pn:name="spi_tb.vhd"/>
</transform>
+ <transform xil_pn:end_ts="1349930164" xil_pn:in_ck="3835236939522292507" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-4852070346826095538" xil_pn:start_ts="1349930164">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="InputChanged"/>
+ <status xil_pn:value="OutputChanged"/>
+ <outfile xil_pn:name="fuse.log"/>
+ <outfile xil_pn:name="isim"/>
+ <outfile xil_pn:name="isim.log"/>
+ <outfile xil_pn:name="spi_tb_beh.prj"/>
+ <outfile xil_pn:name="spi_tb_isim_beh.exe"/>
+ <outfile xil_pn:name="xilinxsim.ini"/>
+ </transform>
+ <transform xil_pn:end_ts="1349930164" xil_pn:in_ck="-7868406126363437584" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-6987686293618254160" xil_pn:start_ts="1349930164">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="OutputChanged"/>
+ <outfile xil_pn:name="isim.cmd"/>
+ <outfile xil_pn:name="isim.log"/>
+ <outfile xil_pn:name="spi_tb_isim_beh.wdb"/>
+ </transform>
</transforms>
</generated_project>
View
15 quad_fpga.xise
@@ -24,7 +24,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="spi_tb.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
@@ -74,6 +74,7 @@
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="sdfs.wcfg" xil_pn:valueState="non-default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx25" xil_pn:valueState="non-default"/>
@@ -262,8 +263,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/spi_tb/uut" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spi_module" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/spi_tb" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spi_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -274,14 +275,14 @@
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="5us" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.spi_module" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.spi_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -306,7 +307,7 @@
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -331,7 +332,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
- <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|spi_module|Behavioral" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|spi_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="quad_fpga" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
View
106 sdfs.wcfg
@@ -0,0 +1,106 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+ <wave_state>
+ </wave_state>
+ <db_ref_list>
+ <db_ref path="/home/jenn/quad/quad_fpga/spi_tb_isim_beh.wdb" id="1" type="auto">
+ <top_modules>
+ <top_module name="numeric_std" />
+ <top_module name="spi_tb" />
+ <top_module name="std_logic_1164" />
+ </top_modules>
+ </db_ref>
+ </db_ref_list>
+ <WVObjectSize size="22" />
+ <wvobject fp_name="/spi_tb/sck" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">sck</obj_property>
+ <obj_property name="ObjectShortName">sck</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/cs" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">cs</obj_property>
+ <obj_property name="ObjectShortName">cs</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/mosi" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">mosi</obj_property>
+ <obj_property name="ObjectShortName">mosi</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/miso" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">miso</obj_property>
+ <obj_property name="ObjectShortName">miso</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/uut/bits_received" type="array" db_ref_id="1">
+ <obj_property name="ElementShortName">bits_received[7:0]</obj_property>
+ <obj_property name="ObjectShortName">bits_received[7:0]</obj_property>
+ <obj_property name="Radix">HEXRADIX</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/rst" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">rst</obj_property>
+ <obj_property name="ObjectShortName">rst</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/clk" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">clk</obj_property>
+ <obj_property name="ObjectShortName">clk</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/read_data" type="array" db_ref_id="1">
+ <obj_property name="ElementShortName">read_data[7:0]</obj_property>
+ <obj_property name="ObjectShortName">read_data[7:0]</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/uut/rx_shift_reg" type="array" db_ref_id="1">
+ <obj_property name="ElementShortName">rx_shift_reg[7:0]</obj_property>
+ <obj_property name="ObjectShortName">rx_shift_reg[7:0]</obj_property>
+ <obj_property name="Radix">HEXRADIX</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/uut/tx_shift_reg" type="array" db_ref_id="1">
+ <obj_property name="ElementShortName">tx_shift_reg[7:0]</obj_property>
+ <obj_property name="ObjectShortName">tx_shift_reg[7:0]</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/write_addr" type="array" db_ref_id="1">
+ <obj_property name="ElementShortName">write_addr[5:0]</obj_property>
+ <obj_property name="ObjectShortName">write_addr[5:0]</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/write_data" type="array" db_ref_id="1">
+ <obj_property name="ElementShortName">write_data[7:0]</obj_property>
+ <obj_property name="ObjectShortName">write_data[7:0]</obj_property>
+ <obj_property name="Radix">HEXRADIX</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/uut/save_wr_addr" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">save_wr_addr</obj_property>
+ <obj_property name="ObjectShortName">save_wr_addr</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/write_enable" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">write_enable</obj_property>
+ <obj_property name="ObjectShortName">write_enable</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/uut/wr_flag_sck" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">wr_flag_sck</obj_property>
+ <obj_property name="ObjectShortName">wr_flag_sck</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/uut/wr_flag_clk" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">wr_flag_clk</obj_property>
+ <obj_property name="ObjectShortName">wr_flag_clk</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/uut/wr_flag_clk_sync" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">wr_flag_clk_sync</obj_property>
+ <obj_property name="ObjectShortName">wr_flag_clk_sync</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/uut/rx_shift" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">rx_shift</obj_property>
+ <obj_property name="ObjectShortName">rx_shift</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/uut/tx_shift" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">tx_shift</obj_property>
+ <obj_property name="ObjectShortName">tx_shift</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/uut/tx_load" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">tx_load</obj_property>
+ <obj_property name="ObjectShortName">tx_load</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/uut/read_mode" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">read_mode</obj_property>
+ <obj_property name="ObjectShortName">read_mode</obj_property>
+ </wvobject>
+ <wvobject fp_name="/spi_tb/read_addr" type="array" db_ref_id="1">
+ <obj_property name="ElementShortName">read_addr[5:0]</obj_property>
+ <obj_property name="ObjectShortName">read_addr[5:0]</obj_property>
+ </wvobject>
+</wave_config>
View
28 spi_module.vhd
@@ -40,21 +40,27 @@ architecture Behavioral of spi_module is
signal wr_flag_sck: std_logic;
signal wr_flag_clk: std_logic;
signal wr_flag_clk_sync: std_logic;
+
+ signal read_mode: std_logic;
+
+
begin
-- SPI process
process(cs, sck)
begin
- if cs = '1' then
+ if cs = '0' then
if rising_edge(sck) then
if rx_shift = '1' then
rx_shift_reg <= rx_shift_reg(6 downto 0) & mosi;
end if;
- if (bits_received = x"0F") then
+ if (bits_received = x"0F") and (read_mode = '1') then
wr_flag_sck <= NOT wr_flag_sck;
write_data_reg <= rx_shift_reg;
+ elsif (bits_received = x"07") then
+ read_mode <= NOT rx_shift_reg(6);
end if;
bits_received <= std_logic_vector(unsigned(bits_received) + 1);
@@ -79,6 +85,10 @@ begin
else
bits_received <= (others => '0');
+ read_mode <= '0';
+ rx_shift_reg <= (others => '0');
+ tx_shift_reg <= (others => '0');
+ wr_flag_sck <= '0';
end if;
end process;
@@ -93,7 +103,7 @@ begin
end if;
end process;
- write_enable <= wr_flag_clk XOR wr_flag_clk_sync;
+ write_enable <= wr_flag_clk_sync AND NOT wr_flag_clk;
-- Control signals
@@ -101,19 +111,21 @@ begin
--tx_load <= '0' when bits_received = x"00" else '1';
- tx_load <= (not cs) when (unsigned(bits_received) = 8);
+ tx_load <= (not cs and not read_mode) when (unsigned(bits_received) = 8) else '0';
- tx_shift <= NOT cs when (unsigned(bits_received) > 8) else '0';
- rx_shift <= NOT cs when (unsigned(bits_received) < 8) else '0';
+ tx_shift <= ((NOT cs) AND NOT read_mode) when (unsigned(bits_received) > 8) else '0';
+ rx_shift <= NOT cs when (unsigned(bits_received) < 8) else read_mode;
save_wr_addr <= NOT rx_shift_reg(7) when (unsigned(bits_received) = 8) else '0';
- miso <= 'Z' when NOT (tx_shift = '1' OR tx_load = '1') else
+ miso <= 'Z' when NOT (tx_shift = '1' OR (tx_load = '1' AND sck = '0')) OR (read_mode = '1') else
tx_shift_reg(7);
-
+ read_addr <= rx_shift_reg(5 downto 0);
+ write_data <= write_data_reg;
+ write_addr <= wr_addr_reg;
end Behavioral;
View
BIN spi_module_isim_beh.exe
Binary file not shown.
View
1 spi_module_stx_beh.prj
@@ -0,0 +1 @@
+vhdl isim_temp "spi_module.vhd"
View
73 spi_tb.vhd
@@ -80,31 +80,62 @@ BEGIN
sck <= '1';
cs <= '1';
mosi <= '1';
- read_data <= 0x"AC";
+ read_data <= x"AC";
wait for 2*sckp;
- cs <= '0'; wait for 50 ns;
-
- sck <= '0';
- mosi <= '1'; wait for sckp; sck <= '1'; wait for sckp; sck <= '0';
- mosi <= '1'; wait for sckp; sck <= '1'; wait for sckp; sck <= '0';
- mosi <= '0'; wait for sckp; sck <= '1'; wait for sckp; sck <= '0';
- mosi <= '1'; wait for sckp; sck <= '1'; wait for sckp; sck <= '0';
- mosi <= '0'; wait for sckp; sck <= '1'; wait for sckp; sck <= '0';
- mosi <= '0'; wait for sckp; sck <= '1'; wait for sckp; sck <= '0';
- mosi <= '1'; wait for sckp; sck <= '1'; wait for sckp; sck <= '0';
- mosi <= '1'; wait for sckp; sck <= '1'; wait for sckp; sck <= '0';
-
- wait for sckp; sck <= '1'; wait for sckp; sck <= '0';
- wait for sckp; sck <= '1'; wait for sckp; sck <= '0';
- wait for sckp; sck <= '1'; wait for sckp; sck <= '0';
- wait for sckp; sck <= '1'; wait for sckp; sck <= '0';
- wait for sckp; sck <= '1'; wait for sckp; sck <= '0';
- wait for sckp; sck <= '1'; wait for sckp; sck <= '0';
- wait for sckp; sck <= '1'; wait for sckp; sck <= '0';
- wait for sckp; sck <= '1'; wait for sckp;
+
+ -- begin read operation
+ cs <= '0'; wait for 50 ns; sck <= '0';
+
+ mosi <= '1'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '1'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '0'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '1'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '0'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '0'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '1'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '1'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+
+ wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ wait for sckp/2; sck <= '1';
+
+ wait for 50 ns; cs <= '1';
+
+
+ wait for 200 ns;
+
+ -- begin write operation
+ cs <= '0'; wait for 50 ns; sck <= '0';
+
+ mosi <= '0'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '1'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '0'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '1'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '0'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '1'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '0'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '1'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+
+ mosi <= '0'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '1'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '1'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '1'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '0'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '1'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '1'; wait for sckp/2; sck <= '1'; wait for sckp/2; sck <= '0';
+ mosi <= '1'; wait for sckp/2; sck <= '1';
wait for 50 ns; cs <= '1';
+
+
+
+
wait;
end process;
View
2 spi_tb_beh.prj
@@ -0,0 +1,2 @@
+vhdl work "spi_module.vhd"
+vhdl work "spi_tb.vhd"
View
BIN spi_tb_isim_beh.exe
Binary file not shown.
View
BIN spi_tb_isim_beh.wdb
Binary file not shown.
View
BIN spi_tb_isim_beh1.wdb
Binary file not shown.
View
1 xilinxsim.ini
@@ -0,0 +1 @@
+work=isim/work

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