One scanline takes 6 + 167.5 cycles to generate, in the simplest case. According to the above reference, the pixels are clocked out on the falling edge of the master clock. This implies that the repeat read done in the first 6 pixels is used to "prime" the renderer, and that the 8 2-bit pixels are shifted out to the LCD during the read of the next 8 pixels, and the extra time on the end is to shift out the last few pixels. This would not be consistent with the statement that the first memory location is read twice, however, so what occurs during the B01 read, and do pixels only start going to the LCD after the first B01s read?
We have a video source non-synchronous with the video sink (display driver). A framebuffer is therefore required between the two. For efficiency, DRAM will be used, so an input and output FIFO is needed.
Sizing the FIFOs
In the worst case scenario, the input FIFO contains a full scan line just as the framebuffer starts a read burst. Writing the input is therefore delayed by the time of one full read burst plus the setup time of a write burst.
A read burst must occur before the output FIFO is emptied of it's scanline. If the expected empty time of the output FIFO is t_o, a read burst should be scheduled at t_o - (t_r + t_w), t_r and t_w being the time required for a read and write burst respectively.
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