TIS-100 CPU in VHDL
VHDL C++ xBase
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InstructionDecoderTruthTable.xls
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README.md
alu.vhd
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ben.vhd
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cpu_1x3.vhd
cpu_1x3_tb.vhd
instruction_decoder.vhd
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instruction_memory.vhd
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mux2.vhd
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next_pc.vhd
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node_port_readdec.vhd
node_port_readmux.vhd
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reg.vhd
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README.md

TIS-100 CPU in VHDL

Work in progress.

Check the Wiki for details (mostly thoughts of a possible implementation atm).

I use Xilinx ISE Webpack for development and testing. I try to keep testbench files up to date, but don't count on it. Hopefully the end result will be synthesizable on a small/cheap FPGA. Currently, I don't have an FPGA, so don't count on that either :)