TIS-100 CPU in VHDL
Work in progress.
Check the Wiki for details (mostly thoughts of a possible implementation atm).
I use Xilinx ISE Webpack for development and testing. I try to keep testbench files up to date, but don't count on it. Hopefully the end result will be synthesizable on a small/cheap FPGA. Currently, I don't have an FPGA, so don't count on that either :)