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hw: Update bootrom and synthesized hardware.

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commit 1a1ca4a9ab4b2f34437e9bdb1456a7e19fc2707a 1 parent f5cd0a0
@jeuneS2 authored
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2  README
@@ -15,7 +15,7 @@ caches have been designed to reduce the overestimation for worst-case
execution time analysis as much as possible.
The processor runs at 66 MHz in an Altera DE2-70 board, where it
-consumes about 46K logic cells and 60KB of on-chip memory, including
+consumes about 54K logic cells and 61KB of on-chip memory, including
the floating-point unit and caches.
Along with the hardware implementation come an assembler, a back-end
View
358 hw/bootrom/bootrom.s
@@ -7,17 +7,11 @@ _main: ; @main
_main_start:
; BB#0: ; %entry
#0: ldiu 48 -> r3
-#2: wb.s r15, 12
-#1: ldx $rb, 0 -> r1.31
-#3: ldga _printstr -> r0
+#1: wb.s r15, 12
+#2: ldga _printstr -> r0
+#3: ldga ._.str -> r1
;;
#0: sub r15, r3 -> r15
-#2: ldx $ro, 0 -> r2.31
-#1: ldga ._.str -> r1
- ;;
-#1: stm.s r1.31, r15, 0
- ;;
-#2: stm.s r2.31, r15, 1
;;
#0: stm.s r10, r15, 7
#1: ldiu 0 -> r10
@@ -29,37 +23,54 @@ _main_start:
#1: add r0, r10 -> r2
#2: add r1, r10 -> r0
;;
-#0: stm.s r0.23, r15, 4
+#0: stm.s r13, r15, 4
+#1: ldx $rb, 0 -> r13
+ ;;
+#0: stm.s r13, r15, 3
+#1: ldx $ro, 0 -> r13
+ ;;
+#0: stm.s r13, r15, 2
;;
-#3: stm.s r3.23, r15, 3
+#0: jop call r2
;;
-#0: call r2
+ nop 0
+ ;;
+ nop 0
;;
- nop 3
+ nop 0
;;
#0: ldga _readint -> r0
+#1: ldi 0 -> r11
;;
-#0: add r0, r10 -> r0.23
-#3: ldi 0 -> r3.23
+#0: add r0, r10 -> r10
;;
-#0: call r0.23
+#0: jop call r10
;;
- nop 3
+ nop 0
;;
-#0: or r0, 0 -> r10
+ nop 0
;;
-#0: call r0.23
+ nop 0
;;
- nop 3
+#0: or r0, 0 -> r12
;;
-#1: br .BB0_5
-#0: or r0, 0 -> r0.23
-#3: or r3.23, 0 -> r11
+#0: jop call r10
;;
- nop 2
+ nop 0
+ ;;
+ nop 0
;;
-.BB0_1: ; %bb
- ; Parent Loop BB0_5 Depth=1
+ nop 0
+ ;;
+#0: br @ .BB0_6
+#1: or r0, 0 -> r10
+#2: or r11, 0 -> r13
+ ;;
+.BB0_1: ; in Loop: Header=BB0_6 Depth=1
+#0: add r13, 1 -> r0
+ ;;
+.BB0_2: ; %bb
+ ; Parent Loop BB0_6 Depth=1
; => This Inner Loop Header: Depth=2
#0: ldi -120 -> r1
;;
@@ -69,59 +80,45 @@ _main_start:
;;
#0: btest r1, 1 -> c1
;;
-#0: if !c1 br .BB0_1
+#0: if !c1 br @ .BB0_2
;;
- nop 2
- ;;
-.BB0_2: ; %bb2
- ; in Loop: Header=BB0_5 Depth=1
+.BB0_3: ; %bb2
+ ; in Loop: Header=BB0_6 Depth=1
#0: ldi -116 -> r1
-#1: and r11, 3 -> r2
+#1: and r13, 3 -> r2
;;
#0: ldm.b r1, 0
#1: cmpne r2, 3 -> c1
;;
-#0: if c1 br .BB0_4
+#0: if c1 br .BB0_5
#1: ldx $membu, r1 -> r1
;;
#0: sl r1, 24 -> r3
-#1: stmb.a r1, r11, 0
- ;;
-#3: or r3, r3.23 -> r12
+#1: stmb.a r1, r13, 0
;;
- nop 0
+#0: or r3, r11 -> r11
;;
-.BB0_3: ; %bb3
- ; in Loop: Header=BB0_5 Depth=1
-#0: ldm.f r11, -3
+.BB0_4: ; %bb3
+ ; in Loop: Header=BB0_6 Depth=1
+#0: ldm.f r13, -3
;;
#0: ldx $mem, 0 -> r1
;;
-#0: cmpne r12, r1 -> c1
+#0: cmpne r11, r1 -> c1
;;
-#0: if c1 br .BB0_9
+#0: if c1 br @ .BB0_9
;;
- nop 2
+.BB0_5: ; %bb4
+ ; in Loop: Header=BB0_6 Depth=1
+#0: sr r11, 8 -> r11
+#1: or r0, 0 -> r13
;;
-.BB0_4: ; %bb4
- ; in Loop: Header=BB0_5 Depth=1
-#3: sr r12, 8 -> r3.23
-#0: or r0, 0 -> r11
- ;;
-.BB0_5: ; %bb5
+.BB0_6: ; %bb5
; =>This Loop Header: Depth=1
- ; Child Loop BB0_1 Depth 2
-#0: cmpult r11, r10 -> c1
- ;;
-#0: if !c1 br .BB0_7
- ;;
- nop 2
- ;;
-.BB0_6: ; in Loop: Header=BB0_5 Depth=1
-#0: add r11, 1 -> r0
-#1: br .BB0_1
+ ; Child Loop BB0_2 Depth 2
+#0: cmpult r13, r12 -> c1
;;
- nop 2
+#0: if c1 br @ .BB0_1
;;
.BB0_7: ; %bb6
#0: ldiu 0 -> r11
@@ -130,45 +127,59 @@ _main_start:
;;
#0: ldim 1024 -> r11
;;
-#0: add r0, r11 -> r12
+#0: add r0, r11 -> r13
#1: add r1, r11 -> r0
;;
-#0: call r12
+#0: jop call r13
;;
- nop 3
+ nop 0
;;
-#0: call r0.23
+ nop 0
;;
- nop 3
+ nop 0
;;
-#0: or r0, 0 -> r11
+#0: jop call r10
+ ;;
+ nop 0
+ ;;
+ nop 0
+ ;;
+ nop 0
+ ;;
+#0: or r0, 0 -> r13
;;
.BB0_8: ; %exit
-#0: ldiu 0 -> r12
+#0: ldiu 0 -> r11
#1: ldga _printstr -> r0
#2: ldga ._.str2 -> r1
;;
-#0: ldim 1024 -> r12
+#0: ldim 1024 -> r11
+ ;;
+#0: add r0, r11 -> r2
+#1: add r1, r11 -> r0
;;
-#0: add r0, r12 -> r2
-#1: add r1, r12 -> r0
+#0: jop call r2
;;
-#0: call r2
+ nop 0
+ ;;
+ nop 0
;;
- nop 3
+ nop 0
;;
#0: ldga _printint -> r0
;;
-#0: add r0, r12 -> r12
-#1: or r11, 0 -> r0
+#0: add r0, r11 -> r11
+#1: or r13, 0 -> r0
;;
-#0: call r12
+#0: jop call r11
;;
- nop 3
+ nop 0
;;
-#0: br .BB0_10
+ nop 0
;;
- nop 2
+ nop 0
+ ;;
+#0: br @ .BB0_10
;;
.BB0_9: ; %fail
#0: ldiu 0 -> r10
@@ -180,33 +191,49 @@ _main_start:
#0: add r0, r10 -> r2
#1: add r1, r10 -> r0
;;
-#0: call r2
+#0: jop call r2
+ ;;
+ nop 0
+ ;;
+ nop 0
;;
- nop 3
+ nop 0
;;
#0: ldga _printint -> r0
;;
-#3: add r0, r10 -> r3.23
-#0: add r11, 1 -> r0
+#0: add r0, r10 -> r10
+#1: add r13, 1 -> r0
;;
-#3: call r3.23
+#0: jop call r10
;;
- nop 3
+ nop 0
;;
-#0: ldm.f r11, -3
-#1: ldi 0 -> r11
+ nop 0
+ ;;
+ nop 0
+ ;;
+#0: ldm.f r13, -3
+#1: ldi 0 -> r13
;;
#0: ldx $mem, 0 -> r0
;;
-#3: call r3.23
+#0: jop call r10
+ ;;
+ nop 0
+ ;;
+ nop 0
;;
- nop 3
+ nop 0
;;
-#0: or r12, 0 -> r0
+#0: or r11, 0 -> r0
;;
-#3: call r3.23
+#0: jop call r10
;;
- nop 3
+ nop 0
+ ;;
+ nop 0
+ ;;
+ nop 0
;;
.BB0_10: ; %restart
; =>This Inner Loop Header: Depth=1
@@ -218,9 +245,7 @@ _main_start:
;;
#0: btest r0, 0 -> c1
;;
-#0: if !c1 br .BB0_10
- ;;
- nop 2
+#0: if !c1 br @ .BB0_10
;;
.BB0_11: ; %bb7
#0: ldiu 0 -> r0
@@ -232,13 +257,15 @@ _main_start:
;;
#0: add r1, r0 -> r0
;;
-#0: call r0
+#0: jop call r0
;;
- nop 3
+ nop 0
;;
-#0: br .BB0_8
+ nop 0
;;
- nop 2
+ nop 0
+ ;;
+#0: br @ .BB0_8
;;
.align 4
_main_end:
@@ -255,12 +282,7 @@ _printstr_start:
;;
#0: ldx $membu, r0 -> r1
;;
-#0: cmpeq r1, 0 -> c1
- ;;
-#0: if c1 ret
-#1: if c1 add r15, 24 -> r15
- ;;
- nop 3
+#0: brz eq @ r1, .BB1_5
;;
.BB1_1: ; %bb.preheader.preheader
#0: add r0, 1 -> r0
@@ -275,9 +297,7 @@ _printstr_start:
;;
#0: btest r2, 0 -> c1
;;
-#0: if !c1 br .BB1_2
- ;;
- nop 2
+#0: if !c1 br @ .BB1_2
;;
.BB1_3: ; %bb1
; in Loop: Header=BB1_2 Depth=1
@@ -290,17 +310,21 @@ _printstr_start:
#0: ldx $membu, r0 -> r1
#1: add r0, 1 -> r0
;;
-#0: cmpeq r1, 0 -> c1
- ;;
-#0: if !c1 br .BB1_2
+#0: brz eq @ r1, .BB1_5
;;
- nop 2
+.BB1_4: ; %bb.preheader
+ ; in Loop: Header=BB1_2 Depth=1
+#0: br @ .BB1_2
;;
-.BB1_4: ; %return
+.BB1_5: ; %return
#0: add r15, 24 -> r15
-#1: ret
+#1: jop ret
;;
- nop 3
+ nop 0
+ ;;
+ nop 0
+ ;;
+ nop 0
;;
.align 4
_printstr_end:
@@ -325,33 +349,35 @@ _readint_start:
;;
#0: btest r2, 1 -> c1
;;
-#0: if !c1 br .BB2_1
- ;;
- nop 2
+#0: if !c1 br @ .BB2_1
;;
.BB2_2: ; %bb2
; in Loop: Header=BB2_1 Depth=1
#0: ldi -116 -> r2
-#1: sub r1, 1 -> r1
-#2: sl r0, 8 -> r0
+#1: sl r0, 8 -> r0
+#2: sub r1, 1 -> r1
;;
-#0: ldm.b r2, 0
-#1: cmpeq r1, 0 -> c1
+#0: brz eq r1, .BB2_4
+#1: ldm.b r2, 0
;;
-#0: if c1 add r15, 24 -> r15
- ;;
-#0: if c1 ret
-#1: ldx $membu, r2 -> r2
+#0: ldx $membu, r2 -> r2
;;
#0: or r2, r0 -> r0
;;
- nop 2
+.BB2_3: ; %bb.preheader
+ ; in Loop: Header=BB2_1 Depth=1
+#0: br @ .BB2_1
+ ;;
+.BB2_4: ; %bb4
+#0: add r15, 24 -> r15
+#1: jop ret
+ ;;
+ nop 0
;;
-#0: br .BB2_1
+ nop 0
;;
- nop 2
+ nop 0
;;
-.BB2_3: ; %bb4
.align 4
_readint_end:
@@ -361,59 +387,56 @@ _printint: ; @printint
_printint_start:
; BB#0: ; %bb.nph
#0: ldi 28 -> r1
-#1: wb.s r15, 6
-#2: sub r15, 24 -> r15
+#1: ldi 87 -> r5
+#2: wb.s r15, 6
+#3: sub r15, 24 -> r15
;;
.BB3_1: ; %bb
; =>This Loop Header: Depth=1
; Child Loop BB3_2 Depth 2
-#0: sr r0, r1 -> r2
-#1: ldi 48 -> r3
+#0: or r1, 0 -> r2
;;
-#0: and r2, 15 -> r2
+#0: sr r0, r2 -> r1
;;
-#0: or r2, r3 -> r3
+#0: and r1, 15 -> r3
+#1: ldi 48 -> r1
+ ;;
+#0: or r3, r1 -> r4
;;
.BB3_2: ; %bb3
; Parent Loop BB3_1 Depth=1
; => This Inner Loop Header: Depth=2
-#1: ldi -120 -> r1.16
- ;;
-#1: ldm.b r1.16, 0
+#0: ldi -120 -> r1
;;
-#1: ldx $membu, r1.16 -> r4
+#0: ldm.b r1, 0
;;
-#0: btest r4, 0 -> c1
+#0: ldx $membu, r1 -> r1
;;
-#0: if !c1 br .BB3_2
+#0: btest r1, 0 -> c1
;;
- nop 2
+#0: if !c1 br @ .BB3_2
;;
.BB3_3: ; %bb4
; in Loop: Header=BB3_1 Depth=1
-#1: ldi 87 -> r1.16
-#2: cmpult r2, 10 -> c1
-#0: sub r1, 4 -> r0.16
+#0: cmpult r3, 10 -> c1
+#1: brz ne r2, .BB3_1
+#2: sub r2, 4 -> r1
;;
-#1: add r2, r1.16 -> r2
+#0: if !c1 add r3, r5 -> r4
+#1: ldi -116 -> r3
;;
-#1: if c1 or r3, 0 -> r2
-#2: cmpne r1, 0 -> c1
-#3: ldi -116 -> r3
-#0: or r0.16, 0 -> r1
+#0: stmb.a r4, r3, 0
;;
-#0: stmb.a r2, r3, 0
-#1: if !c1 add r15, 24 -> r15
- ;;
-#0: if !c1 ret
+.BB3_4: ; %return
+#0: add r15, 24 -> r15
+#1: jop ret
;;
- nop 3
+ nop 0
;;
-#0: br .BB3_1
+ nop 0
;;
- nop 2
+ nop 0
;;
-.BB3_4: ; %return
.align 4
_printint_end:
@@ -427,9 +450,8 @@ _reset_start:
#2: ldiu 2047 -> r1
;;
#0: add r15, 4 -> r0
-#1: ldim 15 -> r1
- ;;
-#0: stm.a 0, r0, 0
+#1: stm.a 0, r15, 1
+#2: ldim 15 -> r1
;;
#0: ldm.b r0, 0
;;
@@ -437,9 +459,7 @@ _reset_start:
;;
#0: cmpult r1, r2 -> c1
;;
-#0: if c1 br .BB4_3
- ;;
- nop 2
+#0: if c1 br @ .BB4_3
;;
.BB4_1:
#0: ldga 32768 -> r2
@@ -452,7 +472,7 @@ _reset_start:
;;
#0: add r1, 1 -> r1
;;
-#0: stm.a r1, r0, 0
+#0: stm.a r1, r15, 1
;;
#0: ldm.b r0, 0
;;
@@ -460,9 +480,7 @@ _reset_start:
;;
#0: cmpult r1, r2 -> c1
;;
-#0: if c1 br .BB4_2
- ;;
- nop 2
+#0: if c1 br @ .BB4_2
;;
.BB4_3: ; %bb2
#0: ldi -4 -> r0
@@ -471,9 +489,7 @@ _reset_start:
;;
.BB4_4: ; %bb3
; =>This Inner Loop Header: Depth=1
-#0: br .BB4_4
- ;;
- nop 2
+#0: br @ .BB4_4
;;
.align 4
_reset_end:
View
361 hw/bootrom/bootrom.vhd
@@ -16,130 +16,130 @@ architecture rtl of bootrom is
begin
process(a) begin
case a is
- when X"00" => d <= X"00000194";
- when X"01" => d <= X"f6460c25";
- when X"02" => d <= X"8a07f267";
- when X"03" => d <= X"80c98000";
- when X"04" => d <= X"65705e37";
- when X"05" => d <= X"a62002fa";
- when X"06" => d <= X"c583f828";
- when X"07" => d <= X"dff02048";
- when X"08" => d <= X"dff0a038";
- when X"09" => d <= X"dea3a32a";
- when X"0a" => d <= X"001038de";
- when X"0b" => d <= X"b3234a80";
- when X"0c" => d <= X"1078dec2";
- when X"0d" => d <= X"a0005090";
- when X"0e" => d <= X"00a80818";
- when X"0f" => d <= X"df722088";
- when X"10" => d <= X"df71a017";
- when X"11" => d <= X"44202003";
- when X"12" => d <= X"1c0003e0";
- when X"13" => d <= X"9000aba3";
- when X"14" => d <= X"17001017";
- when X"15" => d <= X"6f702003";
- when X"16" => d <= X"11000560";
- when X"17" => d <= X"176f7020";
- when X"18" => d <= X"03b1000b";
- when X"19" => d <= X"e38013f0";
- when X"1a" => d <= X"4b817802";
- when X"1b" => d <= X"1603e220";
- when X"1c" => d <= X"19c20020";
- when X"1d" => d <= X"1b0e10a0";
- when X"1e" => d <= X"158210e0";
- when X"1f" => d <= X"173ff648";
- when X"20" => d <= X"023603e3";
- when X"21" => d <= X"206b18b0";
- when X"22" => d <= X"39c20022";
- when X"23" => d <= X"22187037";
- when X"24" => d <= X"000eed87";
- when X"25" => d <= X"08503183";
- when X"26" => d <= X"81e44b08";
- when X"27" => d <= X"10810776";
- when X"28" => d <= X"20001a57";
- when X"29" => d <= X"ff601b08";
- when X"2a" => d <= X"00e01458";
- when X"2b" => d <= X"10a01700";
- when X"2c" => d <= X"35e80291";
- when X"2d" => d <= X"0005e0ec";
- when X"2e" => d <= X"45f01516";
- when X"2f" => d <= X"a0a01700";
- when X"30" => d <= X"04c80230";
- when X"31" => d <= X"1610639f";
- when X"32" => d <= X"e8b00276";
- when X"33" => d <= X"56002600";
- when X"34" => d <= X"01971001";
- when X"35" => d <= X"80169700";
- when X"36" => d <= X"203000b6";
- when X"37" => d <= X"20015810";
- when X"38" => d <= X"1758c020";
- when X"39" => d <= X"03176f70";
- when X"3a" => d <= X"20031100";
- when X"3b" => d <= X"05e07658";
- when X"3c" => d <= X"00260001";
- when X"3d" => d <= X"97100184";
- when X"3e" => d <= X"16990020";
- when X"3f" => d <= X"3000c120";
- when X"40" => d <= X"01601017";
- when X"41" => d <= X"44202003";
- when X"42" => d <= X"1c000478";
- when X"43" => d <= X"3000c620";
- when X"44" => d <= X"8b003017";
- when X"45" => d <= X"58c02003";
- when X"46" => d <= X"17002260";
- when X"47" => d <= X"02765400";
- when X"48" => d <= X"26000197";
- when X"49" => d <= X"10018816";
+ when X"00" => d <= X"0000019c";
+ when X"01" => d <= X"f6460c24";
+ when X"02" => d <= X"cf019300";
+ when X"03" => d <= X"00cf8800";
+ when X"04" => d <= X"bb105e37";
+ when X"05" => d <= X"a038dea3";
+ when X"06" => d <= X"a32a0010";
+ when X"07" => d <= X"38deb323";
+ when X"08" => d <= X"4a801078";
+ when X"09" => d <= X"dec2a000";
+ when X"0a" => d <= X"509000a8";
+ when X"0b" => d <= X"0838ded2";
+ when X"0c" => d <= X"258b0370";
+ when X"0d" => d <= X"38ded1a5";
+ when X"0e" => d <= X"8c037018";
+ when X"0f" => d <= X"ded12017";
+ when X"10" => d <= X"84102000";
+ when X"11" => d <= X"00003c00";
+ when X"12" => d <= X"03e30b00";
+ when X"13" => d <= X"101000a5";
+ when X"14" => d <= X"20179410";
+ when X"15" => d <= X"20000000";
+ when X"16" => d <= X"11000660";
+ when X"17" => d <= X"17941020";
+ when X"18" => d <= X"00000077";
+ when X"19" => d <= X"0027a080";
+ when X"1a" => d <= X"02b04581";
+ when X"1b" => d <= X"b8101a10";
+ when X"1c" => d <= X"601603e2";
+ when X"1d" => d <= X"2019c200";
+ when X"1e" => d <= X"201b0e10";
+ when X"1f" => d <= X"a0158210";
+ when X"20" => d <= X"e0173ff6";
+ when X"21" => d <= X"083603e3";
+ when X"22" => d <= X"206d18b0";
+ when X"23" => d <= X"39c20022";
+ when X"24" => d <= X"22187037";
+ when X"25" => d <= X"000ded87";
+ when X"26" => d <= X"08503183";
+ when X"27" => d <= X"81e44d08";
+ when X"28" => d <= X"101106b5";
+ when X"29" => d <= X"a01a5bff";
+ when X"2a" => d <= X"601b0800";
+ when X"2b" => d <= X"e0145610";
+ when X"2c" => d <= X"a0170034";
+ when X"2d" => d <= X"2831d685";
+ when X"2e" => d <= X"e0800370";
+ when X"2f" => d <= X"151ac0a0";
+ when X"30" => d <= X"173fd4a8";
+ when X"31" => d <= X"76560026";
+ when X"32" => d <= X"00019f10";
+ when X"33" => d <= X"017a1697";
+ when X"34" => d <= X"00203000";
+ when X"35" => d <= X"b6a00158";
+ when X"36" => d <= X"10179a10";
+ when X"37" => d <= X"20000000";
+ when X"38" => d <= X"17941020";
+ when X"39" => d <= X"00000011";
+ when X"3a" => d <= X"0006e076";
+ when X"3b" => d <= X"56002600";
+ when X"3c" => d <= X"019f1001";
+ when X"3d" => d <= X"7e169700";
+ when X"3e" => d <= X"203000b1";
+ when X"3f" => d <= X"20015810";
+ when X"40" => d <= X"17841020";
+ when X"41" => d <= X"0000001c";
+ when X"42" => d <= X"00047830";
+ when X"43" => d <= X"00b5a08d";
+ when X"44" => d <= X"00301796";
+ when X"45" => d <= X"10200000";
+ when X"46" => d <= X"00170025";
+ when X"47" => d <= X"a0765400";
+ when X"48" => d <= X"2600019f";
+ when X"49" => d <= X"10018216";
when X"4a" => d <= X"95002030";
when X"4b" => d <= X"00a12001";
- when X"4c" => d <= X"50101744";
- when X"4d" => d <= X"2020031c";
- when X"4e" => d <= X"00047890";
- when X"4f" => d <= X"16106000";
- when X"50" => d <= X"55d0876f";
- when X"51" => d <= X"7020033a";
- when X"52" => d <= X"57ff630b";
- when X"53" => d <= X"00101b08";
- when X"54" => d <= X"0060876f";
- when X"55" => d <= X"70200311";
- when X"56" => d <= X"18006087";
- when X"57" => d <= X"6f702003";
- when X"58" => d <= X"1601e220";
- when X"59" => d <= X"19c00020";
- when X"5a" => d <= X"1b0e0020";
- when X"5b" => d <= X"158000e0";
- when X"5c" => d <= X"173ff648";
- when X"5d" => d <= X"02364000";
- when X"5e" => d <= X"2301f190";
- when X"5f" => d <= X"7882a066";
- when X"60" => d <= X"20029da0";
- when X"61" => d <= X"40081002";
- when X"62" => d <= X"00201740";
- when X"63" => d <= X"00200317";
- when X"64" => d <= X"3fade002";
- when X"65" => d <= X"0000005c";
- when X"66" => d <= X"399e01a0";
- when X"67" => d <= X"2fc3f01a";
- when X"68" => d <= X"4000201b";
- when X"69" => d <= X"0e00a014";
- when X"6a" => d <= X"0200e037";
- when X"6b" => d <= X"c000280f";
- when X"6c" => d <= X"c3f40310";
+ when X"4c" => d <= X"50101784";
+ when X"4d" => d <= X"10200000";
+ when X"4e" => d <= X"001c0004";
+ when X"4f" => d <= X"783000a5";
+ when X"50" => d <= X"200d0830";
+ when X"51" => d <= X"17941020";
+ when X"52" => d <= X"0000003a";
+ when X"53" => d <= X"5bff630d";
+ when X"54" => d <= X"00101b08";
+ when X"55" => d <= X"00601794";
+ when X"56" => d <= X"10200000";
+ when X"57" => d <= X"00111600";
+ when X"58" => d <= X"60179410";
+ when X"59" => d <= X"20000000";
+ when X"5a" => d <= X"1601e220";
+ when X"5b" => d <= X"19c00020";
+ when X"5c" => d <= X"1b0e0020";
+ when X"5d" => d <= X"158000e0";
+ when X"5e" => d <= X"173ff608";
+ when X"5f" => d <= X"36400023";
+ when X"60" => d <= X"01f19078";
+ when X"61" => d <= X"82a06620";
+ when X"62" => d <= X"0295a040";
+ when X"63" => d <= X"08100200";
+ when X"64" => d <= X"20178010";
+ when X"65" => d <= X"20000000";
+ when X"66" => d <= X"173fa7a0";
+ when X"67" => d <= X"00000054";
+ when X"68" => d <= X"399e01a0";
+ when X"69" => d <= X"2fc3f01a";
+ when X"6a" => d <= X"4000201b";
+ when X"6b" => d <= X"0e00a017";
+ when X"6c" => d <= X"42198010";
when X"6d" => d <= X"00106016";
when X"6e" => d <= X"05e22019";
when X"6f" => d <= X"c400201b";
when X"70" => d <= X"0e212015";
when X"71" => d <= X"8400e017";
- when X"72" => d <= X"3ff64802";
- when X"73" => d <= X"1605e320";
- when X"74" => d <= X"18841020";
- when X"75" => d <= X"1a400020";
- when X"76" => d <= X"3b0e00a0";
- when X"77" => d <= X"00083014";
- when X"78" => d <= X"0200e017";
- when X"79" => d <= X"3fe84802";
- when X"7a" => d <= X"301f87e3";
- when X"7b" => d <= X"e0001003";
+ when X"72" => d <= X"3ff60816";
+ when X"73" => d <= X"05e32018";
+ when X"74" => d <= X"8410201a";
+ when X"75" => d <= X"4000203b";
+ when X"76" => d <= X"0e00a000";
+ when X"77" => d <= X"08301742";
+ when X"78" => d <= X"0200173f";
+ when X"79" => d <= X"e8a0301f";
+ when X"7a" => d <= X"87e3c010";
+ when X"7b" => d <= X"10000000";
when X"7c" => d <= X"0000004c";
when X"7d" => d <= X"f6020123";
when X"7e" => d <= X"00001267";
@@ -149,71 +149,68 @@ process(a) begin
when X"82" => d <= X"201b0e21";
when X"83" => d <= X"20158410";
when X"84" => d <= X"e0173ff6";
- when X"85" => d <= X"48027605";
- when X"86" => d <= X"e3202108";
- when X"87" => d <= X"70602018";
- when X"88" => d <= X"39c40022";
- when X"89" => d <= X"01007010";
- when X"8a" => d <= X"1f87e837";
- when X"8b" => d <= X"c0002d87";
- when X"8c" => d <= X"10901104";
- when X"8d" => d <= X"00200217";
- when X"8e" => d <= X"3fe36002";
- when X"8f" => d <= X"00000060";
- when X"90" => d <= X"76020724";
- when X"91" => d <= X"cf00d017";
- when X"92" => d <= X"e1f831c0";
- when X"93" => d <= X"11230306";
- when X"94" => d <= X"1010c4f1";
- when X"95" => d <= X"60110431";
- when X"96" => d <= X"a02621e2";
- when X"97" => d <= X"2029e000";
- when X"98" => d <= X"202b0f02";
- when X"99" => d <= X"20158800";
- when X"9a" => d <= X"e0173ff6";
- when X"9b" => d <= X"48027042";
- when X"9c" => d <= X"4863100a";
- when X"9d" => d <= X"f1412838";
- when X"9e" => d <= X"20050120";
- when X"9f" => d <= X"f12000e0";
- when X"a0" => d <= X"8300b510";
- when X"a1" => d <= X"8038c0fc";
- when X"a2" => d <= X"64388620";
- when X"a3" => d <= X"200fc3e4";
- when X"a4" => d <= X"17c00008";
- when X"a5" => d <= X"03173fd8";
- when X"a6" => d <= X"e0020000";
- when X"a7" => d <= X"0000005c";
- when X"a8" => d <= X"799e01a0";
- when X"a9" => d <= X"2fc3f190";
- when X"aa" => d <= X"fff8301e";
- when X"ab" => d <= X"40634101";
- when X"ac" => d <= X"f0180000";
- when X"ad" => d <= X"6019c000";
- when X"ae" => d <= X"201b0801";
- when X"af" => d <= X"60150220";
- when X"b0" => d <= X"a0170013";
- when X"b1" => d <= X"68021c81";
- when X"b2" => d <= X"000019c0";
- when X"b3" => d <= X"00201b08";
- when X"b4" => d <= X"00e01002";
- when X"b5" => d <= X"10e01800";
- when X"b6" => d <= X"102019c0";
- when X"b7" => d <= X"00201b08";
- when X"b8" => d <= X"00e01502";
- when X"b9" => d <= X"20a0173f";
- when X"ba" => d <= X"f0680216";
- when X"bb" => d <= X"01ff2018";
- when X"bc" => d <= X"00006017";
- when X"bd" => d <= X"3ffe6002";
- when X"be" => d <= X"414f4c0a";
- when X"bf" => d <= X"00000a44";
- when X"c0" => d <= X"544f4f42";
- when X"c1" => d <= X"0000000a";
- when X"c2" => d <= X"4958450a";
- when X"c3" => d <= X"00002054";
- when X"c4" => d <= X"4c494146";
- when X"c5" => d <= X"00004020";
+ when X"85" => d <= X"087605e3";
+ when X"86" => d <= X"20c04030";
+ when X"87" => d <= X"10843837";
+ when X"88" => d <= X"420644e2";
+ when X"89" => d <= X"00101b0e";
+ when X"8a" => d <= X"21201104";
+ when X"8b" => d <= X"0020173f";
+ when X"8c" => d <= X"e7a0301f";
+ when X"8d" => d <= X"87e3c010";
+ when X"8e" => d <= X"10000000";
+ when X"8f" => d <= X"00000058";
+ when X"90" => d <= X"f6020723";
+ when X"91" => d <= X"050af267";
+ when X"92" => d <= X"80680bf0";
+ when X"93" => d <= X"fc110201";
+ when X"94" => d <= X"6011c020";
+ when X"95" => d <= X"a030c2f1";
+ when X"96" => d <= X"e3010610";
+ when X"97" => d <= X"11061220";
+ when X"98" => d <= X"1603e220";
+ when X"99" => d <= X"19c20020";
+ when X"9a" => d <= X"1b0e10a0";
+ when X"9b" => d <= X"158200e0";
+ when X"9c" => d <= X"173ff608";
+ when X"9d" => d <= X"7506a0e3";
+ when X"9e" => d <= X"a2f3e411";
+ when X"9f" => d <= X"10383006";
+ when X"a0" => d <= X"520b03f1";
+ when X"a1" => d <= X"90188640";
+ when X"a2" => d <= X"20301f87";
+ when X"a3" => d <= X"e3c01010";
+ when X"a4" => d <= X"00000000";
+ when X"a5" => d <= X"00000058";
+ when X"a6" => d <= X"799e01a0";
+ when X"a7" => d <= X"2fc3f190";
+ when X"a8" => d <= X"fff8701e";
+ when X"a9" => d <= X"40640f00";
+ when X"aa" => d <= X"71a080f8";
+ when X"ab" => d <= X"19c00020";
+ when X"ac" => d <= X"1b080160";
+ when X"ad" => d <= X"150220a0";
+ when X"ae" => d <= X"17001228";
+ when X"af" => d <= X"1c810000";
+ when X"b0" => d <= X"19c00020";
+ when X"b1" => d <= X"1b0800e0";
+ when X"b2" => d <= X"100210e0";
+ when X"b3" => d <= X"181e10a0";
+ when X"b4" => d <= X"19c00020";
+ when X"b5" => d <= X"1b0800e0";
+ when X"b6" => d <= X"150220a0";
+ when X"b7" => d <= X"173ff028";
+ when X"b8" => d <= X"1601ff20";
+ when X"b9" => d <= X"18000060";
+ when X"ba" => d <= X"173ffe20";
+ when X"bb" => d <= X"414f4c0a";
+ when X"bc" => d <= X"00000a44";
+ when X"bd" => d <= X"544f4f42";
+ when X"be" => d <= X"0000000a";
+ when X"bf" => d <= X"4958450a";
+ when X"c0" => d <= X"00002054";
+ when X"c1" => d <= X"4c494146";
+ when X"c2" => d <= X"00004020";
when others => d <= (others => '0');
end case;
end process;
View
6 hw/bootrom/sim_bootrom.s
@@ -2,7 +2,11 @@
bootrom_start:
#0: callg 0
;;
- nop 3
+ nop 0
+ ;;
+ nop 0
+ ;;
+ nop 0
;;
exit:
#0: ldi -4 -> r0
View
10 hw/bootrom/sim_bootrom.vhd
@@ -17,11 +17,11 @@ begin
process(a) begin
case a is
when X"00" => d <= X"00000014";
- when X"01" => d <= X"17800000";
- when X"02" => d <= X"031601ff";
- when X"03" => d <= X"2019c000";
- when X"04" => d <= X"201b0800";
- when X"05" => d <= X"600f0000";
+ when X"01" => d <= X"17c00000";
+ when X"02" => d <= X"00000016";
+ when X"03" => d <= X"01ff2019";
+ when X"04" => d <= X"c000201b";
+ when X"05" => d <= X"0800600f";
when others => d <= (others => '0');
end case;
end process;
View
4 hw/quartus/lemberg.qpf
@@ -18,12 +18,12 @@
#
# Quartus II
# Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version
-# Date created = 11:32:07 May 19, 2011
+# Date created = 22:29:00 February 14, 2012
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "10.1"
-DATE = "11:32:07 May 19, 2011"
+DATE = "22:29:00 February 14, 2012"
# Revisions
View
7 hw/quartus/lemberg.qsf
@@ -46,7 +46,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name MUX_RESTRUCTURE ON
+set_global_assignment -name MUX_RESTRUCTURE OFF
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
@@ -113,7 +113,7 @@ set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
set_global_assignment -name ENABLE_DA_RULE "C101, C102, C103, C104, C105, C106, R101, R102, R103, R104, R105, T101, T102, A101, A102, A103, A104, A105, A106, A107, A108, A109, A110, S101, S102, S103, S104, D101, D102, D103, M101, M102, M103, M104, M105"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name STATE_MACHINE_PROCESSING AUTO
-set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
set_global_assignment -name POWER_USE_INPUT_FILES ON
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
@@ -284,4 +284,7 @@ set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/conversions.vhd -section_
set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/sim_ssram_512x36.vhd -section_id cpu_rtl_tb
set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/cpu_tb.vhd -section_id cpu_rtl_tb
set_global_assignment -name IGNORE_MODE_FOR_MERGE OFF
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION ON
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to sram_pin_inout.*
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sram_pin_inout.*
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
View
BIN  hw/quartus/lemberg.sof
Binary file not shown
View
23,754 hw/quartus/lemberg.svf
11,877 additions, 11,877 deletions not shown
View
2  hw/src/core_pack.vhd
@@ -22,7 +22,7 @@ use ieee.std_logic_1164.all;
package core_pack is
-- version number
- constant VERSION : std_logic_vector(31 downto 0) := X"20120126";
+ constant VERSION : std_logic_vector(31 downto 0) := X"20120312";
-- speed
constant CLOCK_FREQ : integer := 66666667;
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