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hw: Minor tweaks in fetch stage.

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commit d3e192d97581ae1edd32ff75bd289166f29261d5 1 parent 80d111d
@jeuneS2 authored
View
31 hw/src/fetch.vhd
@@ -135,37 +135,28 @@ begin -- behavior
pcvec(i) := pc_reg + to_unsigned((MAX_CLUSTERS+i*SYLLABLE_WIDTH+BYTE_WIDTH-1)/BYTE_WIDTH, FETCHBUF_BITS);
end loop; -- i
- for i in 0 to FETCHBUF_BYTES-1 loop
- maskvec(i) := raw_next(i*BYTE_WIDTH+MAX_CLUSTERS-CLUSTERS
- to i*BYTE_WIDTH+MAX_CLUSTERS-1);
- opcntvec(i) := count_bits(maskvec(i));
- end loop; -- i
- opcnt := opcntvec(to_integer(start_pos));
+ opcnt := count_bits(raw_next(to_integer(start_pos)*BYTE_WIDTH+MAX_CLUSTERS-CLUSTERS
+ to to_integer(start_pos)*BYTE_WIDTH+MAX_CLUSTERS-1));
start_next <= startvec(opcnt);
pc_next <= pcvec(opcnt);
spec_tag <= std_logic_vector(pcvec(opcnt));
pc_out <= std_logic_vector(pcvec(opcnt));
-
+
wrap_next <= '0';
- raw_next <= raw_reg;
fetch_next <= start_pos;
- if start_pos = fetch_pos or wrap_reg='1' then
- raw_next <= raw_in;
- fetch_next <= fetch_pos;
- vpc0_next <= vpc0_reg+FETCHBUF_BYTES;
- vpc1_next <= vpc1_reg+FETCHBUF_BYTES;
- vpc0_inc_next <= vpc0_reg+FETCHBUF_BYTES+startvec(opcnt);
- vpc1_inc_next <= vpc1_reg+FETCHBUF_BYTES+startvec(opcnt);
- vpc0_out <= std_logic_vector(vpc0_inc+FETCHBUF_BYTES);
- vpc1_out <= std_logic_vector(vpc1_inc+FETCHBUF_BYTES);
- elsif fetch_pos > start_pos then
+ if fetch_pos >= start_pos or wrap_reg = '1' then
for i in 0 to FETCHBUF_WIDTH-1 loop
- if i >= to_integer(fetch_pos*BYTE_WIDTH) or i < to_integer(start_pos*BYTE_WIDTH)then
+ if i >= to_integer(fetch_pos*BYTE_WIDTH) or i < to_integer(start_pos*BYTE_WIDTH) then
raw_next(i) <= raw_in(i);
+ else
+ raw_next(i) <= raw_reg(i);
end if;
end loop; -- i
+ if wrap_reg = '1' then
+ fetch_next <= fetch_pos;
+ end if;
vpc0_next <= vpc0_reg+FETCHBUF_BYTES;
vpc1_next <= vpc1_reg+FETCHBUF_BYTES;
vpc0_inc_next <= vpc0_reg+FETCHBUF_BYTES+startvec(opcnt);
@@ -176,6 +167,8 @@ begin -- behavior
for i in 0 to FETCHBUF_WIDTH-1 loop
if i >= to_integer(fetch_pos*BYTE_WIDTH) and i < to_integer(start_pos*BYTE_WIDTH) then
raw_next(i) <= raw_in(i);
+ else
+ raw_next(i) <= raw_reg(i);
end if;
end loop; -- i
vpc0_next <= vpc0_reg;
View
6 hw/src/imem.vhd
@@ -76,10 +76,6 @@ begin
wraddr1 <= write.wraddr(PC_WIDTH-3 downto 3) & write.wraddr(1 downto 0);
end process wr;
- rd: process(q0, q1)
- begin
- rddata <= q0(31 downto 0) & q0(63 downto 32) & q0(95 downto 64) & q0(127 downto 96)
- & q1(31 downto 0) & q1(63 downto 32) & q1(95 downto 64) & q1(127 downto 96);
- end process;
+ rddata <= q0 & q1;
end rtl;
View
8 hw/src/imem_block.vhd
@@ -93,10 +93,10 @@ begin
asynrd: process (rdaddress_reg, block0, block1, block2, block3)
begin -- process asynrd
- q(wrwidth-1 downto 0) <= block0(to_integer(unsigned(rdaddress_reg)));
- q(2*wrwidth-1 downto wrwidth) <= block1(to_integer(unsigned(rdaddress_reg)));
- q(3*wrwidth-1 downto 2*wrwidth) <= block2(to_integer(unsigned(rdaddress_reg)));
- q(4*wrwidth-1 downto 3*wrwidth) <= block3(to_integer(unsigned(rdaddress_reg)));
+ q(wrwidth-1 downto 0) <= block3(to_integer(unsigned(rdaddress_reg)));
+ q(2*wrwidth-1 downto wrwidth) <= block2(to_integer(unsigned(rdaddress_reg)));
+ q(3*wrwidth-1 downto 2*wrwidth) <= block1(to_integer(unsigned(rdaddress_reg)));
+ q(4*wrwidth-1 downto 3*wrwidth) <= block0(to_integer(unsigned(rdaddress_reg)));
end process asynrd;
end rtl;
View
19 hw/src/inflate.vhd
@@ -40,8 +40,6 @@ end inflate;
architecture behavior of inflate is
- signal raw_reg : std_logic_vector(0 to FETCH_WIDTH-1);
-
--pragma synthesis off
signal nop_cnt : integer := 0;
signal ena_cnt : integer := 0;
@@ -51,21 +49,26 @@ architecture behavior of inflate is
begin -- behavior
- raw_reg <= raw;
pc_out <= pc_in;
-- this needs to be adapted when changing the number of clusters
- inflate: process (raw_reg)
+ inflate: process (raw)
variable syll : bundle_type;
begin -- process inflate
- bundle <= BUNDLE_NOP;
+ for i in 0 to CLUSTERS-1 loop
+ syll(i) := to_syllable(raw(MAX_CLUSTERS+i*SYLLABLE_WIDTH
+ to MAX_CLUSTERS+(i+1)*SYLLABLE_WIDTH-1));
+ end loop; -- i
for i in 0 to CLUSTERS-1 loop
- syll(i) := to_syllable(raw_reg(MAX_CLUSTERS+i*SYLLABLE_WIDTH
- to MAX_CLUSTERS+(i+1)*SYLLABLE_WIDTH-1));
+ bundle(i) <= syll(0);
+ -- use "if !c0 or ..." as NOP
+ bundle(i).op <= "000110";
+ bundle(i).cond <= COND_FALSE;
+ bundle(i).flag <= (others => '0');
end loop; -- i
- case raw_reg(0 to MAX_CLUSTERS-1) is
+ case raw(0 to MAX_CLUSTERS-1) is
when "0000" => null;
when "0001" =>
bundle(0) <= syll(0);
View
4 hw/src/op_pack.vhd
@@ -46,7 +46,7 @@ package op_pack is
constant COND_FALSE : std_logic := '0';
constant SYLLABLE_NOP : syllable_type :=
- ( "000110", (others => '1'), (others => '1'), (others => '1'),
+ ( "000110", (others => '0'), (others => '0'), (others => '0'),
'0', COND_FALSE, (others => '0'));
function to_syllable (
@@ -60,7 +60,7 @@ package op_pack is
-- TODO: define constants for ISA-level operation encoding
- -- use OR and read from local register as NOP to minimize power
+ -- use "if !c0 or r0, r0 -> r0" as NOP
constant BUNDLE_NOP : bundle_type := (others => SYLLABLE_NOP);
---------------------------------------------------------------------------
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