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Table of Contents generated with DocToc
- 1 Overview
- 2 Quadlet Transfer
- 3 Block Transfer
4 Data Fields Description
- 4.1 Status (Read)
- 4.2 Status (Write)
- 4.3 Hardware Version
- 4.4 Firmware Version
- 4.5 Temperature
- 4.6 Digital Input/Output Value
- 4.7 ADC: Motor Current Feedback
- 4.8 ADC Analog Input (e.g. Potentiometer) Feedback
- 4.9 Encoder Counts
- 4.10 Encoder Preload
- 4.11 Encoder Velocity
- 4.12 DAC Motor Currents
- 4.13 Watchdog
- 4.14 Timestamp
- 4.15 Physical Layer Chip Read and Write
- 5 PROM 25AA128 (QLA)
- 6 Ethernet KSZ8851
The FPGA supports two types of data transfer: Quadlet Transfer and Block Transfer. For quadlet transfers, a quadlet packet with address field is sent to the FGPA and the FGPA will either send the requested data back for the read case or have the write request executed. The quadlet transfer is often used for debugging or initialization of the FPGA connection. Because only one 32-bit register of the specified channel can be read or written, the quadlet transfer is not appropriate for reading and sending data in the robot servo control thread for performance reasons. In contrast, the block transfer supports reads and writes to a few key registers for all channels at one time.
2 Quadlet Transfer
All of the I/O resources are directly accessible by software via quadlet transfers, with the desired device specified by an appropriate value in the address field of the packet header. In all cases, the FPGA checks the destination ID field in the packet header and only acts if the value matches the local node ID, which is automatically assigned by the physical layer. Furthermore, it only acts if the specified transaction code is supported. Otherwise packets are considered inapplicable to the node and are silently ignored. When active, the FPGA reads data from or writes data to intermediate buffers.
The address field for quadlet transfers is interpreted as follows: bits 7-4 address a channel, while bits 0-4 address a device on that channel. The address map is listed in Table 1. One detail of note is that channel devices begin at channel address 1, as channel address 0 specifies the global I/O module, whose address map is also shown in the table. Although the Quad Linear Amplifier (QLA) has only 4 channels, this interface specification has been defined to accommodate up to 8 channels. Detailed description of each register is available below.
|Bits 7-4||Bits 3-0||Description (Read)||Description (Write)|
|0(Global Register)||0||Status Register||Power and relay control|
|1||IEEE 1394 Physical Layer Chip Control Register||IEEE 1394 Physical Layer Chip Control Register|
|2||IEEE 1394 Physical Layer Chip Data Register||IEEE 1394 Physical Layer Chip Data Register|
|3||Watchdog Timeout Period Register||Watchdog Timeout Period Register|
|4||FPGA Hardware Version|
|6||DOUT (digital output) status||DOUT (digital output)|
|7||FPGA Firmware Version|
|10||Digital inputs (and output state)|
|15||DEBUG Register||DEBUG Register|
|1-4(Channel Select)||0||ADC Data Register|
|1||DAC Control Register||DAC Control Register|
|4||Quadrature Encoder Preload Register|
|5||Quadrature Encoder Data Register|
|6||Encoder Period Data Register (DT)|
|7||Encoder Frequency Data Register (DP)|
|8||Digital OUT High/Low period|
|5-8||X||Reserved for 8-axis systems||Reserved for 8-axis systems|
|12 (1100)||X||Reserved for PROM||Reserved for PROM|
Table 1: Device map of quadlet transaction address field
3 Block Transfer
The devices involved in block reads and writes are fixed according to their positions in the data block. Also, only certain devices are accessible through block transfers, i.e. those necessary for real-time operation. Table 2 depicts the respective packet formats expected by the FPGA, as well as how it interprets the data fields. The FPGA firmware is meant to handle write blocks of a fixed size due to the simplicity and reliability of such an approach. Thus the MSB of each Motor Current data quadlet is interpreted as a valid bit, which is set by software to indicate to the FPGA whether or not the corresponding device is to be written.
Please note that the N is chosen to be 4, but can be changed to support other hardware. The block read data should have 4N+4 quadlets and the block write data should have N+1 quadlets. Note that the FPGA estimates the motor velocity from the encoder feedback using two methods (see also 4.10 Encoder Velocity):
- DT: FPGA measures the time between two rising edges on the encoder A channel; this works well for slow speeds (assuming that the counter does not overflow)
- DP: FPGA counts the number of quadrature pulses that occur over a given time period; this works well for high speeds (assuming that the counter does not overflow) [''NOTE: this method is likely to be eliminated in the next firmware revision'']
|Read Packet||Write Packet|
|Timestamp||Motor Current 1|
|Digital I/O||Motor Current N|
|Temperature||Power / Relay Control|
|Pot / Cur 1|
|Pot / Cur N|
|Encoder Vel (DT) 1|
|Encoder Vel (DT) N|
|Encoder Vel (DP) 1|
|Encoder Vel (DP) N|
Table 2: Block data format
4 Data Fields Description
4.1 Status (Read)
This 32-bit status register provides motor and board status information. The meaning for each bit is shown in the following table.
|31-28||Number of channels (4)|
|22||eth1394 mode (Rev 5+ firmware, 0 in prior versions)|
|21||QLA digital output config valid (Rev 5+ firmware, 0 in prior versions)|
|20||QLA digital output config, 0=MOSFET, 1=Bidirectional (Rev 5+ firmware, 0 in prior versions)|
|19||Motor voltage good|
|18||Power enable control|
|17||Safety relay status|
|16||Safety relay control|
|15||Motor power fault (Rev 6+ firmware, with QLA 1.4+)|
|11-8||Amplifiers enabled (1) or fault (0)|
|7-4||Amplifiers disabled due to feedback current check (1)|
|3-0||Amplifier enable control|
The QLA digital output configuration is auto-detected by the firmware (Rev 5+), and distinguishes between the bidirectional transceiver design (QLA Rev 1.4+) and the MOSFET open drain design (prior QLA versions). Note that an FPGA with firmware version less than 5 cannot control the digital outputs for QLA Rev 1.4+ because they are configured as inputs on power-up and the firmware must explicitly configure them as outputs.
4.1.2 Rotary Switch
A rotary switch is available on each FPGA controller board. Its value can be used as the identifier for each board set, when multiple board sets are daisy-chained to control more than 4 motors. This is important because the computer program needs to specify the destination ID in the packet header, which is automatically assigned by the IEEE-1394 physical layer. The rotary switch value is bits 24-27 in the Status data. In the example Status read, the rotary switch is set to 5.
~@: ./quad1394 0 0x45000000
4.2 Status (Write)
The status register can be written to enable/disable power and relays. The bits definitions are as follows:
|23||Mask for eth1394 mode, Rev 5+ firmware|
|22||Set eth1394 mode, Rev 5+ firmware|
|21||Mask for software reset|
|19||Mask for power enable|
|18||Power enable control|
|17||Mask for safety relay|
|16||Safety relay control|
|11-8||Masks for amplifier enable|
|3-0||Amplifier enable control|
4.2.1 Enable / Disable Motor Power
The Quad-Linear-Amplifier boards have two level power control. The FPGA can control the amplifier board’s motor voltage regulator chip to turn on/off the motor voltage power for the entire board. Also, a control pin is connected to each Op-Amp’s E/S pin, thus providing amplifier enable/disable control for each individual axis. The board level power is set by the power enable control bit, and the axis level power enable can be controlled by changing the amplifier enable bits. The indicator LED will be turned on if the corresponding axis is enabled.
Example 1: Enable board level power (bit_19 = 1 bit_18 = 1) ~@: ./quad1394 0 0xC0000 Example 2: Disable board level power (bit_19 = 1 bit_18 = 0) ~@: ./quad1394 0 0x80000 Example 3: Enable motor power for Axis 3 ~@: ./quad1394 0 0404 Example 4: Disable motor power for Axis 3 ~@: ./quad1394 0 0400
4.2.2: Enable / Disable RELAY
One relay is built in each QLA boards as a safety feature, which can be controlled by RELAY_ON signal from FPGA chip. The following examples show how to enable, disable and check relay. Let's assume, there is only one FPGA_QLA board set connected and has default node id (0).
Example 1: Enable RELAY (Mask bit_17 = 1, Control bit_16 = 1) ~@: ./quad1394 0 0x30000 Example 2: Disable RELAY (Mask bit_17 = 1, Control bit_16 = 0) ~@: ./quad1394 0 0x20000 Example 3: Read RELAY status (Status bit_17 = 1, Control bit_16 = 1) ~@: ./quad1394 0 0x45030000
4.3 Hardware Version
~@: ./quad1394 4 0x514C4131
Quadlet read from 0x04 will return FPGA_QLA hardware version. Right now the hardware verison is 1, so the return value 0x514C4131 = "QLA1" (ASCII).
4.4 Firmware Version
~@: ./quad1394 7 0x00000001
Quadlet read from 0x07 will return the FPGA_QLA firmware version. Right now the firmware version is 1.
The quadlet transfer with address 0x05 will read the two MAX6576 temperature sensors that are located on the motor power amplifier heat sink. Bits 0-7 and 8-15 give the readings from sensors one and two, respectively. Dividing each reading by 2 gives the temperature in degrees Celsius.
Example: Quadlet temperature read, T1 = 0x3F/2 = 31.5 deg T2 = 0x3D/2 = 30.5 deg
~@: ./quad1394 5 0x003D3F
4.6 Digital Input/Output Value
Read current digital input/output from address 0x0A. Note this data is also available in block transfer. The return value includes v-fault, enc-a, enc-b, enc-i, dout, nlim, plim, home values as detailed in the following table. Note, high bit number always maps to high axis number. For example, data is home for axis 4.
# read digital input/output value ~@: ./quad1394 0x0A
|31||V-Fault (short in encoder circuit)|
|27-24||Encoder Channel A|
|23-20||Encoder Channel B|
4.7 ADC: Motor Current Feedback
Motor current can be read from a 16-bit analog-to-digital converter (ADC) LTC1864. ADC counts reading 0x0000, 0x8000 and 0xFFFF correspond to motor currents -6.25 A, 0.00 A and +6.25 A, respectively, and Eq. (1) converts ADC counts to mA.
Im = 6250 * 2 / (0xFFFF - 0x0000)Icnt - 6250 = 0.190737Icnt - 6250
Example: Sample motor current quadlet read for Axis 3
~@: ./quad1394 30 Pot: 0x047F Cur: 0x7FBD
The motor current for Axis 3 is Im = 0x7FBD × 0.190737 − 6250 = −12.71 mA.
4.8 ADC Analog Input (e.g. Potentiometer) Feedback
The analog input feedback uses a reference voltage of 4.5 V and its reading can be obtained from ADC LTC1864. The following equation converts ADC counts to Volts:
Vang = (4.5 - 0.0) / (0xFFFF - 0x0000)Vcnt = 0.00006866559Vcnt
Example: Sample potentiometer voltage quadlet read for Axis 3
~@: ./quad1394 30 Pot: 0x047F Cur: 0x7FBD
The analog input for Axis 3 is Vang = 0x047F × 0.00006866559 = 0.079 V. If the analog input is a potentiometer voltage, you will also need hardware specific information to convert the POT voltage into either translation or rotation units.
4.9 Encoder Counts
The FPGA1394 QLA controller board supports quadrature encoder input and gives incremental position measurements in counts. The 24-bit encoder counter will overflow when the count drops below 0 or increases beyond 0xFFFFFF, so it is important to either preload the counter with the midpoint value (0x7FFFFF) during initialization or manage the underflow/overflow in software. The unit conversion equation is
ENCsi = EncoderCountsPerTurn x GearRatio x Pitch x (ENCcnt - ENCpreload),
where ''EncoderCountsPerTurn'' is encoder counts per motor revolution, ''GearRatio'' is gear box ratio and ''Pitch'' is translational movement per turn for prismatic joint and 1 for revolute joint.
Example: Read encoder counts for Axis 3 using quadlet read
~@: ./quad1394 35 0x007FFFFF
4.10 Encoder Preload
Preload encoder counts into the encoder register in the FPGA.
Example: Preload 0x7FFFF to encoder register for Axis 3
~@: ./quad1394 34 0x7FFFFF 0x007FFFFF
This command changes the axis 3 encoder preload to 0x7FFFFF.
4.11 Encoder Velocity
The board has two built-in methods to compute velocity based on optical encoder inputs. Using hardware to compute velocity ensures a higher degree of accuracy as compared to difference formulas. Velocity Register 1 measures the time between transitions of the pulses (1/∆Time method, also called DT) and Velocity Register 2 gives an estimate of velocity in terms of encoder pulses in a given time interval (∆Position/∆Sample method, also called DP) . Each of these methods has limitations, however. The DT method works well at low encoder frequencies, but has poor resolution at high frequencies because the time between pulses is short. Conversely, the DP method works well at high frequencies, but has poor resolution at low frequencies because the number of pulses in a given time period is small. In terms of practical implementation, it is also important to consider that the DT method will overflow at very low encoder frequencies and the DP method will overflow at very high frequencies. The software can determine the most accurate velocity estimate at any given time using either method or by using a weighted sum of both estimates.
Example 1: Read velocity (DT) for Axis 3 using quadlet read
~@: ./quad1394 36 0xFFFFFFF
Example 2: Read velocity (DP) for Axis 3 using quadlet read
~@: ./quad1394 37 0xFFFFFFF
4.12 DAC Motor Currents
For each axis, a 16-bit LTC2601 digital-to-analog (DAC) is used to output the commanded motor current. The relationship between DAC counts and commanded motor current is shown in following table.
|DAC Counts||Motor Current|
Table 2: DAC Cnts to Currents
Example: Set Axis 3 motor current to +254 mA
~@: ./quad1394 31 8500
A 16-bit watchdog is built in each FPGA board. Watchdog counter will be reset when a write packet is received. When a watchdog timeout occurs, all four amplifiers will be disabled. The maximum watchdog period is 340 ms. If the watchdog period is set to 0x0000, then the watchdog will be disabled. The watchdog period can be read and write via quadlet read/write command.
Example 1: Write watchdog period to 0x1FFF (About 42 ms) ~@: ./quad1394 03 0x1FFF Example 2: Read watchdog period ~@: ./quad1394 03 0x00001FFF
A 32-bit counter records the time interval between each block read in counts (clock = 49.152 MHz).
Example: Sample block read ~@: ./block1394 0 20 0x01492252 (timestamp) 0x46830000 ...... ......
In this sample block read, the timestamp field is 0x01492252, which is 0.439 second.
4.15 Physical Layer Chip Read and Write
Send command through Control Register and Read from Data Register
# 0x01: phy ctrl 0x02: phy data # phy ctrl data format # bit 12: 1 write 0 read # bit 11-4: 8 bit data # bit 3-0: 4 bit addr # phy register format # 0x0 | 6: phycial ID | 1:R | 1:PS | Example 2: Read phy register located at 0x0 ~@: ./quad1394 0x01 0x0000 0x00000004 # Phy data = 0b00000100, so physical id = 0b000001, R = 0 PS = 0
Reference: Book Chapter 11/22
5 PROM 25AA128 (QLA)
The 25AA128 is a 128 kb PROM installed on the QLA with a page size of 64 bytes. It supports a list of standard commands:
|8'h05||Read STATUS register|
|8'h01||Write STATUS register|
Also to support block read and write, we extended the commands
5.2 Sending Commands
To send a command to the PROM, write data to 0x3000. See following examples:
# Write Enable, high 8-bit is command ./quad1394 0x3000 0x06000000 # Write Disable, high 8-bit is command ./quad1394 0x3000 0x04000000 # Read Staus, high 8-bit is command ./quad1394 0x3000 0x05000000 # send command ./quad1394 0x3002 # read result back # Write Status ./quad1394 0x3000 0x06000000 # enable write ./quad1394 0x3000 0x01800000 # 0x01 command 0x80 status # Read byte, 0x03 command 0x0010 address ./quad1394 0x3000 0x03001000 # Write byte ./quad1394 0x3000 0x06000000 # enable write ./quad1394 0x3000 0x020010AA # write 0xAA to address 0x0010
5.3 Block Read & Write
A 16 quadlets (64 bytes) buffer is allocated in the FPGA and can be accessed at address 0x3100-0x310F. To program a block of data for example a page (64-byte) into the PROM, you need to do the following things:
# 1 Block write data from the data ./block1394 0x3100 16 0x0100 0x0200 ..... 0x1000 # 2 Trigger block write ./quad1394 0x3100 0xFF0000F # last 8-bit is NumOfQuad - 1
To read a block of data from the PROM:
# 1 Trigger block read ./quad1394 0x3000 0xFE00000F # last 8-bit is NumOfQuad - 1 # 2 Block read data from the data ./block1394 0x3100 16
5.4 Sample C++ Code
// Address AmpIO_UInt16 addr = 0x0000; // Write Test data AmpIO_UInt8 wdata = 0xA3; // test Board.PromWriteByte25AA128(addr,wdata); // Read Back AmpIO_UInt8 rdata; Board.PromReadByte25AA128(addr, rdata);
6 Ethernet KSZ8851 (FPGA1394 Rev 1.5+)
KSZ8851 is a 10/100 Mbps Ethernet controller chip that exists on FPGA V2.0+. Here we document using the FireWire interface to access the KSZ8851 chip, including chip register read and write.
Write to the FPGA register located at 0x0C (12) to issue a Read/Write to an Ethernet chip register. Then, read back the result from 0x0C.
|25||R/W Read(0) or Write(1)|
|24||W/B Word(1) or Byte(0)|
# 1 Quadlet write to select KSZ8851 Chip ID and Enable Register (0xC0) ./quad1394 0x0C 0x01C00000 # 2 Read the result ./quad1394 0x0C # Returns 0xA01C8872 # Last 16-bits 0x8872 are the returned register value # (Upper 16 bits are status/debug information)
Firewire System Architecture Second Edition IEEE 1394a